Pvt-insensitive high-bandwidth variable gain amplifier and receiver analog front-end circuit

Abstract

The application provides a PVT-insensitive high-bandwidth variable gain amplifier and a receiver analog front-end circuit, which comprises a transistor amplification circuit for amplifying and outputting a differential mode signal in a gate input signal; a source degeneration resistor for providing an equivalent impedance for the first transistor circuit; a PVT following circuit for collecting source common mode voltages of the first transistor and the second transistor, and providing an adjustable voltage to the transistor amplification circuit according to the source common mode voltages, so that the equivalent impedance of the gain amplifier can be adjusted to work in a linear region; the PVT following circuit adopts an adjustable current source, and the adjustable current source generates an adjustable voltage through the following circuit, so that the equivalent impedance is only related to the adjustable current source and the device characteristic constant, and is not related to PVT. The application utilizes a structure of controlling the on-resistance of a transistor or a transistor array by a gate voltage to design a source degeneration structure VGA, and adds a PVT following circuit to reduce the change of the VGA gain with PVT, so as to achieve the effects of PVT insensitivity, high bandwidth and high precision of the VGA.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, in particular to a PVT-insensitive high-bandwidth variable gain amplifier and a receiver analog front-end circuit. BACKGROUND

[0002] With the increasing demand for high-speed communication in data centers, the requirements for the optical module receiver analog front-end applied therein are also increasing. Among them, the variable gain amplifier (VGA) is the core component of the optical module receiver analog front-end, which is an amplifier with adjustable gain characteristics. The VGA needs to amplify the received data signal with high quality and transmit it to the subsequent data processing circuit under the requirements of linearity and noise. In addition, according to the application under different insertion losses, the VGA needs to meet a certain range of gain conditions, and in many application scenarios, the VGA is also required to realize a quasi-continuous calibration process, so the VGA needs to meet a small enough adjustment step.

[0003] The existing VGA is mainly divided into two structural designs of closed loop and open loop. On the one hand, the closed loop structure usually uses a metal resistance array to realize gain adjustment. The closed loop structure VGA has strong anti-interference ability based on the negative feedback mechanism, but the metal resistance array used for adjusting the gain will introduce large parasitic parameters, which is not conducive to the optimization of bandwidth and linearity under high frequency application. At the same time, its gain adjustment depends on the fixed resistance ratio, so it is difficult to realize the quasi-continuous fine step adjustment, and it cannot meet the demand of accurate calibration for high-end applications. On the other hand, the open loop structure has structures such as pseudo-differential pair, source degeneration, and diode load, which usually use metal resistance arrays and load current arrays to realize gain adjustment. Although its structure is relatively simple and more easily realizes high frequency operation and high bandwidth, the same problems exist when using a metal resistance array. If the load current array scheme is used, it will be difficult to cover the large dynamic range required by high-speed optical modules due to the limited adjustment range of the load current array itself. Moreover, the open loop structure inherently lacks the correction effect of negative feedback, and its linearity and gain accuracy are generally poor, and it is more susceptible to PVT (Process Voltage Temperature: process, voltage, temperature) factors.

[0004] In summary, the existing design of the optical module receiver analog front-end cannot meet the high-performance and high-precision gain adjustment under low power consumption, therefore, it is urgent to design a PVT-insensitive variable gain amplifier and a receiver analog front-end circuit that can realize high bandwidth and high gain under low power consumption. SUMMARY

[0005] In order to solve the problems existing in the prior art, the present application aims to provide a PVT-insensitive high-bandwidth variable gain amplifier and a receiver analog front-end circuit, which uses a structure of controlling the on-resistance of a transistor or a transistor array by a gate voltage to design a source degeneration structure VGA, and adds a PVT following circuit to reduce the change of the VGA gain with PVT, so as to achieve the effects of PVT insensitivity, high bandwidth and high precision of the VGA.

[0006] The present application achieves the above-mentioned purposes by the following technical solutions:

[0007] The PVT-insensitive high-bandwidth variable gain amplifier comprises a transistor amplification circuit, a source degeneration resistor and a bias circuit, the source degeneration resistor is connected in series with the source of a transistor in the transistor amplification circuit, and the bias circuit is used to provide a bias for the transistor amplification circuit to make it work in a linear region; the transistor amplification circuit comprises a first transistor and a second transistor, the first transistor and the second transistor constitute a differential input pair tube, which is used to amplify and output the differential mode signal in the gate input signal.

[0008] The first transistor circuit is further provided, and the source degeneration resistor provides an equivalent impedance for the first transistor circuit The first transistor circuit at least comprises a fifth transistor, and the drain and source of the fifth transistor are connected with the source of the first transistor and the second transistor respectively.

[0009] The PVT following circuit is further provided, which is used to collect the common-mode voltage of the sources of the first transistor and the second transistor, and provide an adjustable voltage to the gate of the fifth transistor according to the common-mode voltage, so that the equivalent impedance of the gain amplifier working in the linear region is adjustable.

[0010] According to the PVT-insensitive high-bandwidth variable gain amplifier provided by the present application, the input end of the transistor amplification circuit is taken from the gate of the first transistor and the second transistor, the output end is taken from the drain of the first transistor and the second transistor, and is used to provide an amplification gain from the input signal to the output differential mode signal; wherein the input signal is a differential mode signal and / or a common mode signal, the differential mode signal in the input signal is amplified and outputted, and the common mode signal is suppressed.

[0011] According to the PVT-insensitive high-bandwidth variable gain amplifier provided by the present application, the bias circuit comprises a third transistor and a fourth transistor, the gates of the third transistor and the fourth transistor are connected and connected with a bias voltage, and the drains are connected with the sources of the first transistor and the second transistor respectively, so as to constitute a current mirror with the differential input pair tube, and are used to provide a bias current to stabilize the working state of the transistor amplification circuit.​

[0012] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application further comprises a series peaking circuit, the series peaking circuit comprising a first inductor and a second inductor, the first inductor and the second inductor being connected in series at the drain of the first transistor and the drain of the second transistor respectively, so as to form an LC resonant circuit with the parasitic capacitance of the first transistor and the second transistor, for compensating the high-frequency gain roll-off caused by the parasitic capacitance.

[0013] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application, the PVT follower circuit adopts an adjustable current source, the adjustable current source generates the adjustable voltage through the PVT follower circuit, and the equivalent impedance is related to the adjustable current source and the device characteristic constant, and is not related to PVT.

[0014] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application, the PVT follower circuit further comprises a voltage follower circuit and a second transistor circuit, the second transistor circuit comprising at least a sixth transistor, the input end of the voltage follower circuit inputting the source common-mode voltage, the output end of the voltage follower circuit being connected with the source of the sixth transistor, the gate of the sixth transistor being connected with the drain, the drain being connected with the adjustable current source, and the adjustable voltage being output to the gate of the fifth transistor.

[0015] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application, the transistors in the first transistor circuit and the second transistor circuit have the same conduction threshold voltage, and the equivalent impedance is:

[0016]

[0017] wherein, the aspect ratio of the fifth transistor, the width-length ratio of the sixth transistor, the gm constant current provided by the adjustable current source, the device characteristic constant related to PVT.

[0018] The adjustment accuracy of the equivalent impedance depends on the adjustment accuracy of the adjustable current source.

[0019] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application, the first transistor circuit and the second transistor circuit both adopt a transistor resistance array, by controlling the conduction state of the transistors in the transistor resistance array, so as to change the proportion of the resistance output of the transistor resistance array to adjust the equivalent impedance , so as to realize the quasi-continuous and wide-range gain adjustment of the gain amplifier.

[0020] The PVT-insensitive high-bandwidth variable gain amplifier provided by the application adopts a transistor resistance array composed of four groups of parallel transistors, the bandwidth of the gain amplifier reaches 28 GHz or above, and if the gain amplifier is adjusted with an accuracy of 0.1 dB, the adjustment range of 0-6 dB is covered.

[0021] The receiver analog front-end circuit comprises a receiver terminal, an AC coupling circuit and one or more PVT-insensitive high-bandwidth variable gain amplifiers, the receiver terminal is connected to a weak electric signal generated after photoelectric conversion, is used for performing preliminary gain control, noise removal and output common mode control on the weak electric signal, and outputs a voltage signal to an input end of the AC coupling circuit, the AC coupling circuit is used for isolating a direct current component in the voltage signal and transmitting an alternating current signal to an input end of the variable gain amplifier, and the gain amplifier is used for dynamically adjusting gain according to the strength of the alternating current signal, amplifying the alternating current signal and transmitting the amplified alternating current signal to a data processing circuit in a later stage of the receiver.

[0022] Therefore, compared with the prior art, the application has the following beneficial effects:

[0023] 1. The application adopts the equivalent impedance of the transistor or the transistor array controlled by the gate voltage as the source degeneration resistance, which replaces the traditional fixed resistance array, and compared with the traditional source degeneration VGA, the circuit structure of the application avoids the large parasitic capacitance problem caused by the metal resistance array, is beneficial to high-frequency application, and can realize a wide adjustment range of up to 6 dB and ensure a high gain adjustment accuracy of 0.1 dB, so as to meet the needs of gain accurate calibration of high-speed optical communication.

[0024] 2. The application introduces a PVT following circuit, which collects the source common mode voltage of the transistor in the transistor amplification circuit and dynamically adjusts the equivalent impedance of the transistor or the transistor array according to the common mode voltage Compared with the open-loop structure of the traditional source degeneration VGA, the PVT following circuit and the gain amplifier of the application form a closed-loop feedback loop, and the equivalent impedance as a constant irrelevant to PVT is greatly reduced, which greatly reduces the sensitivity of the amplifier gain to the PVT condition and ensures the consistency and reliability of the performance in different working environments.

[0025] 3. The structure design of the controllable gain amplifier circuit of the application makes the equivalent impedance The adjustment precision of the adjustable current source determines the adjustment precision of the adjustable current source, compared with the traditional switching metal resistance array or open loop structure, the adjustment precision of the adjustable current source is easier to control, and the adjustable current source is adjusted to 0.1dB precision by the transistor or transistor array adjustment.

[0026] 4、The application introduces a series peaking inductance at the output end, uses the LC resonance principle to compensate the parasitic capacitance effect of the output node, can effectively improve the load impedance at high frequency without increasing the circuit static current. Compared with the traditional scheme of increasing bias current to increase power consumption to improve performance, the application can realize high bandwidth and high gain at low power consumption.

[0027] The application will be further described in detail below in combination with the drawings and specific embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 is the circuit principle diagram of the gain amplifier in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0029] Figure 2 is the PVT following circuit principle diagram in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0030] Figure 3 is the variable gain amplifier circuit principle diagram using transistors in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0031] Figure 4 is the variable gain amplifier circuit principle diagram using transistor resistance array design in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0032] Figure 5 is the frequency domain response of the VGA gain in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0033] Figure 6 is the comparison diagram of the VGA gain of the traditional source degeneration structure and the source degeneration structure of the application in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application.

[0034] Figure 7 is the circuit schematic diagram of the optical module receiver analog front end in the PVT-insensitive high-bandwidth variable gain amplifier embodiment of the application. DETAILED DESCRIPTION

[0035] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below in conjunction with the drawings in the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0036] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art upon reading this description, the embodiments described herein are combinable with other embodiments.

[0037] Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the application. The appearances of the phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are they necessarily mutually exclusive of one another. As will be apparent to those of ordinary skill in the art upon reading this description, the embodiments described herein are combinable with other embodiments. Figures 1-2 The present application discloses a PVT-insensitive high-bandwidth variable gain amplifier, comprising a transistor amplification circuit, a source degeneration resistor and a bias circuit, the source degeneration resistor is connected in series with the source of a transistor in the transistor amplification circuit, and the bias circuit is used for providing bias for the transistor amplification circuit to make it work in a linear region; the transistor amplification circuit comprises a first transistor M1 and a second transistor M2, the first transistor M1 and the second transistor M2 constitute a differential input pair tube, which is used for amplifying and outputting a differential mode signal in a gate input signal.

[0038] The source degeneration resistor provides an equivalent impedance for a first transistor circuit The first transistor circuit at least comprises a fifth transistor Mb, and the drain and source of the fifth transistor Mb are connected with the source of the first transistor M1 and the second transistor M2 respectively.

[0039] The PVT following circuit is used for collecting the source common-mode voltage of the first transistor M1 and the second transistor M2 , and providing an adjustable voltage to the gate of the fifth transistor Mb according to the source common-mode voltage , so that the equivalent impedance of the gain amplifier working in the linear region is adjustable.

[0040] The PVT following circuit adopts an adjustable current source, the adjustable current source generates an adjustable voltage through the PVT following circuit, so that the equivalent impedance is related to the adjustable current source and device characteristic constant, and is not related to PVT.

[0041] In the embodiment, the input end of the transistor amplification circuit is connected to the gate of the first transistor M1 and the second transistor M2, the output end is connected to the drain of the first transistor M1 and the second transistor M2, and the input signal is a differential mode signal and / or a common mode signal, so that the differential mode signal is amplified and outputted and the common mode signal is suppressed.

[0042] In the embodiment, the bias circuit includes the third transistor M3 and the fourth transistor M4, the gate of the third transistor M3 and the fourth transistor M4 is connected to the bias voltage, and the drain of the third transistor M3 and the fourth transistor M4 is connected to the source of the first transistor M1 and the second transistor M2 respectively, so as to form a current mirror with the differential input pair, and provide a bias current to stabilize the working state of the transistor amplification circuit.

[0043] Specifically, the third transistor M3 and the fourth transistor M4 provide a current bias for the circuit as a tail current tube. The above bias circuit design is only exemplary and is not the only circuit structure. The circuit can be designed according to actual needs.

[0044] In the embodiment, the series peaking circuit includes the first inductor L1 and the second inductor L2, the first inductor L1 and the second inductor L2 are connected in series at the drain of the first transistor M1 and the second transistor M2 respectively, so as to form an LC resonance circuit with the parasitic capacitance of the first transistor M1 and the second transistor M2, and compensate for the high frequency gain roll-off caused by the parasitic capacitance.

[0045] Specifically, the series peaking circuit of the embodiment further includes the first resistor R1 and the second resistor R2, the first resistor R1 and the second resistor R2 are connected in series at the drain of the first transistor M1 and the second transistor M2 respectively.

[0046] When the circuit is at a high frequency point, the LC resonance circuit resonates to present a higher impedance, so that the load impedance of the gain amplifier near the frequency point increases significantly, so that the voltage gain presents a peak value at the frequency point, which compensates for the gain drop caused by the low-pass filter formed by the parasitic capacitance and the load resistance. Moreover, the gain peak effectively lifts the high frequency part of the frequency response curve, realizes the widening of the bandwidth, and through the reasonable design of the peaking inductance value, the frequency response can be more flat in the passband, or the bandwidth can be improved to be much higher than the original RC limited frequency, so as to meet the application of the circuit in the high speed scene.

[0047] When the circuit is at a high frequency point, the resonance frequency is:

[0048]

[0049] Wherein, L is the inductance value of the first inductor L1 or the second inductor L2, The parasitic capacitance is C.

[0050] In the embodiment, the PVT follower circuit samples the source common-mode voltage through a resistor , comprising a third resistor R3 and a fourth resistor R4, which are connected in series and then connected in parallel between the source of the first transistor M1 and the second transistor M2, and the sampling point is located at the common connection end of the third resistor R3 and the fourth resistor R4, so that the gain amplifier is formed into a symmetrical circuit with the first transistor circuit as the center, and the common-mode rejection ratio is improved.

[0051] Specifically, the resistance values of the third resistor R3 and the fourth resistor R4 are much larger than the equivalent impedance of the first transistor circuit .

[0052] In the embodiment, the PVT follower circuit further comprises a voltage follower circuit and a second transistor circuit, the input end of the voltage follower circuit inputs the source common-mode voltage , the output end of the voltage follower circuit is connected with the source of a sixth transistor Ma, the gate of the sixth transistor Ma is connected with the drain, and the drain is connected with the adjustable current source and outputs an adjustable voltage to the gate of a fifth transistor Mb.

[0053] Specifically, the voltage follower circuit comprises an amplifier Amp and a transistor Mpsf, the inverting input end of the amplifier Amp inputs the source common-mode voltage , and the non-inverting input end and the output end of the amplifier Amp are respectively connected with the drain and the gate of the transistor Mpsf. The amplifier Amp is used to copy the source common-mode voltage to the drain of Mpsf.

[0054] Referring to Figure 3 , the first transistor circuit adopts a single fifth transistor Mb, and the second transistor circuit adopts a single sixth transistor Ma, so as to simplify the analysis of the circuit parameters affecting the equivalent impedance . The transistors in the first transistor circuit and the second transistor circuit have the same conduction threshold voltage , so that the current model flowing through the sixth transistor Ma is established as:

[0055] Formula (1)

[0056] Wherein, is the gm constant current provided by the adjustable current source, and is a device characteristic constant related to PVT, is the width-length ratio of the sixth transistor Ma, The voltage difference between the gate and the source of the sixth transistor Ma.

[0057] From equation (1), we have:

[0058] Equation (2)

[0059] According to the series relationship of the sixth transistor Ma in the PVT follower circuit, we have the adjustable voltage as:

[0060] Equation (3)

[0061] wherein, is the source common-mode voltage.

[0062] The equivalent impedance of the source degeneration fifth transistor Mb is:

[0063] Equation (4)

[0064] wherein, is the aspect ratio of the fifth transistor Mb, is the characteristic constant of the transistor, is the voltage difference between the gate and the source of the fifth transistor Mb.

[0065] According to the circuit relationship, we have from equation (4):

[0066] Equation (5)

[0067] Substituting equation (3) into equation (5), we have:

[0068] Equation (6)

[0069] Substituting equation (2) into equation (6), we have:

[0070] Equation (7)

[0071] In equation (7), and are fixed values after the transistor selection is determined; is the gm constant current provided by the adjustable current source, which is commonly used in analog circuits, and refers to a current source achieved through constant mutual conductance biasing technology, the purpose of which is to keep the transistor transconductance constant, thereby ensuring that the current is not affected by process, voltage, or temperature changes; is a current inversely proportional to k, is a device characteristic constant related to PVT, and we have multiplied by k is a value independent of PVT, i.e.:

[0072] ≈Constant (8)

[0073] is the equivalent impedance is a constant independent of PVT, and the equivalent impedance The adjustment accuracy of the equivalent impedance

[0074] Specifically, the input signal and the output differential signal of the transistor amplifier circuit of the embodiment are respectively:

[0075] (9)

[0076] wherein, are the gate input voltage signals of the first transistor M1 and the second transistor M2 respectively, are the drain output voltage signals of the first transistor M1 and the second transistor M2 respectively.

[0077] The output single-ended gain of the controllable gain amplifier can be obtained from equation (8):

[0078] (10)

[0079] Substituting equation (8) into equation (10) can obtain:

[0080] (11)

[0081] wherein, is the transconductance of the first transistor M1 or the second transistor M2, is the load resistance of the output single-end of the controllable gain amplifier.

[0082] Since the controllable gain amplifier of the embodiment is a symmetrical circuit, the total gain of the controllable gain amplifier is:

[0083] (12)

[0084] In another embodiment, the first transistor circuit and the second transistor circuit both adopt a transistor resistance array, and by controlling the conduction state of the transistors in the transistor resistance array, the proportion of the resistance output of the transistor resistance array is changed to adjust the equivalent impedance , so as to realize the quasi-continuous and wide-range gain adjustment of the gain amplifier.

[0085] Referring to Figure 4, specifically, the embodiment takes 4 groups of transistors as an example, wherein the first transistor circuit is composed of 4 transistors with the same characteristics in parallel; the second transistor circuit is also composed of 4 transistors with the same characteristics in parallel, and the structure is the same as the first transistor circuit, and the drain of each transistor is connected to one adjustable current source and outputs one adjustable voltage to the gate of the 4 transistors in the first transistor circuit.

[0086] Specifically, the 4 groups of transistors in the transistor resistance array in the embodiment have the same characteristics, so their equivalent impedance is the same. When one transistor in the transistor resistance array is turned on, the source degeneration transistor resistance is ; if 2 transistors are turned on, according to the parallel resistance relationship, the source degeneration resistance is ; if 3 transistors are turned on, according to the parallel resistance relationship, the source degeneration resistance is ; if 4 transistors are turned on, according to the parallel resistance relationship, the source degeneration resistance is .

[0087] By analogy, if n groups of transistors with the same characteristics are connected in parallel in the transistor resistance array, the source degeneration transistor resistance is The transistor resistance array of the application ensures that the controllable gain amplifier can be adjusted with an accuracy of 0.1dB.

[0088] Referring to Figure 5 , it can be seen from the figure that the frequency domain response of the VGA gain is adjusted with an accuracy of 0.1dB, and the adjustment range of the transistor resistance array according to the number of turned-on transistors is: 0~1dB, 1~2.5dB, 2.5~4.3dB, 4.3~6.3dB, so the gain amplifier of the application can cover an adjustment range of 0~6dB, and the bandwidth reaches 28GHz or more.

[0089] Referring to Figure 6 , specifically, the embodiment Corner 1~5 respectively corresponds to SS low temperature low pressure, SS high temperature low pressure, TT normal temperature normal pressure, FF low temperature high pressure, and FF high temperature high pressure. Under the same configuration, the gain of the traditional source degeneration structure VGA changes in the range of 6.2dB~9.7dB, while the gain of the VGA of the application changes in the range of 7.1dB~9.1dB, so compared with the traditional source degeneration structure, the gain of the VGA of the application changes in the range of 3.5dB to 2.0dB.

[0090] Further, the gain of the controllable gain amplifier in formula (12) is calculated, wherein the denominator Rds is a constant term Although the transconductance and the load resistance R are still related to PVT, the PVT variation range of the VGA gain can be optimized from 3.5dB to 2dB, i.e. the gain of the controllable gain amplifier is reduced, which is weakly related to PVT.

[0091] Specifically, due to the reduction of the gain variation range, the corresponding additional power consumption or parasitic cost can be reduced. For example, for a 10mA power-consuming VGA, in order to increase the gain from 6.2dB under SS high temperature and low voltage to 8.2dB under TT normal temperature and normal pressure, the current needs to be increased to 15.6mA. Under the same conditions, the VGA of the present application only needs to increase from 7.1dB to 8.2dB, corresponding to a current of 12.8mA, i.e. a current loss of 2.8mA is reduced.

[0092] In other embodiments, the gain can be increased by increasing the size of the transistors in the circuit, and the parasitic generated by the transistors is also increased in proportion. For example, by increasing the size of the transistors in the circuit to increase the gain under SS high temperature and low voltage, the transistors will be 1.58 times the original size, and the parasitic generated by the transistors will also be increased in proportion.

[0093] Referring to Figure 7 , the receiver analog front-end circuit comprises a receiver termination, an AC coupling circuit, one or more PVT-insensitive high-bandwidth variable gain amplifiers (VGAs) described above, the receiver termination accesses the weak electrical signal generated after photoelectric conversion, and is used for preliminary gain control, noise removal and output common mode control of the weak electrical signal, and outputs a voltage signal to the input end of the AC coupling circuit, the AC coupling circuit is used for isolating the direct current component in the voltage signal and transmitting the alternating current signal to the input end of the variable gain amplifier, and the gain amplifier is used for dynamically adjusting the gain according to the strength of the alternating current signal, and transmitting the amplified alternating current signal to the data processing circuit of the receiver back stage.

[0094] Specifically, in the optical module receiver of the present embodiment, the photodiode converts the optical signal into a weak current signal, the receiver termination matches the impedance according to the current signal, and enables the current signal to be converted into a voltage signal completely and without distortion, and transmitted to the next stage AC coupling circuit. In high-speed circuits, when the output impedance of the signal source matches the load impedance, the signal power can be most effectively transmitted to the load, avoiding power reflection.

[0095] Specifically, the AC coupling circuit in the embodiment adopts a resistance-capacitance coupling mode, which is composed of a resistor and a capacitor in series, for signal transmission and DC isolation, and the output of the former stage is coupled to the input of the latter stage through the capacitor to prevent the DC bias from affecting.

[0096] Specifically, the gain amplifier in the embodiment utilizes the structure of precisely controlling the on-resistance of a transistor or a transistor array by a gate voltage, and increases a PVT following circuit to reduce the variation range of the feedback node with PVT in actual application, thereby reducing the variation of the VGA gain with PVT.

[0097] The technical features of the above embodiments can be combined in any manner, and to make the description concise, all possible combinations of the technical features in the above embodiments are not described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0098] The above embodiments are only preferred embodiments of the present application, and cannot be used to limit the protection scope of the present application, and any non-essential changes and replacements made by those skilled in the art on the basis of the present application shall fall within the protection scope of the present application.

Claims

1. A PVT-insensitive high-bandwidth variable gain amplifier, comprising a transistor amplification circuit, a source degeneration resistor connected in series with a source of a transistor in the transistor amplification circuit, and a biasing circuit for providing a source bias power supply for the transistor amplification circuit to operate in a linear region, characterized in that: the transistor amplification circuit comprises a first transistor and a second transistor, the first transistor and the second transistor constitute a differential input pair for amplifying a differential mode signal in a gate input signal and outputting from a drain; and the biasing circuit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected to a gate bias voltage and have their drains connected to sources of the first transistor and the second transistor respectively, so as to form a current mirror with the differential input pair for providing a bias current to stabilize an operating state of the transistor amplification circuit.

2. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 1, characterized in that: the transistor amplification circuit has its input taken from gates of the first transistor and the second transistor and its output taken from drains of the first transistor and the second transistor, for providing an amplification gain from the gate input signal to an output differential mode signal, wherein the gate input signal is a differential mode signal and / or a common mode signal, and the differential mode signal is amplified and outputted while the common mode signal is suppressed. The first transistor circuit further includes a source degeneration resistor providing an equivalent impedance for the first transistor circuit The first transistor circuit further includes a source degeneration resistor providing an equivalent impedance for the first transistor circuit Also included is a PVT following circuit for collecting a source common mode voltage of the first and second transistors and providing an adjustable voltage to a gate of the fifth transistor according to the source common mode voltage, causing the gain amplifier to operate in a linear region of the equivalent impedance Adjustable.

3. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 1, characterized in that: the biasing circuit comprises a third transistor and a fourth transistor, the third transistor and the fourth transistor are connected to a gate bias voltage and have their drains connected to sources of the first transistor and the second transistor respectively, so as to form a current mirror with the differential input pair for providing a bias current to stabilize an operating state of the transistor amplification circuit.

4. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 2, characterized in that: it further comprises a series peaking circuit, the series peaking circuit comprises a first inductor and a second inductor, the first inductor and the second inductor are connected in series with the drains of the first transistor and the second transistor respectively, so as to form an LC resonant circuit with parasitic capacitances of the first transistor and the second transistor for compensating a high-frequency gain roll-off caused by the parasitic capacitances.

5. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 1, characterized in that: the PVT-insensitive high-bandwidth variable gain amplifier further comprises a PVT following circuit, the PVT following circuit comprises a first voltage follower circuit, a second voltage follower circuit, a fifth transistor, a sixth transistor, and a seventh transistor, the first voltage follower circuit has an input connected to the source of the first transistor and an output connected to a gate of the fifth transistor, the second voltage follower circuit has an input connected to the source of the second transistor and an output connected to a gate of the sixth transistor, the fifth transistor has its source connected to the output of the first voltage follower circuit, its gate connected to the output of the second voltage follower circuit, and its drain connected to the adjustable current source, the sixth transistor has its source connected to the output of the second voltage follower circuit, its gate connected to the output of the first voltage follower circuit, and its drain connected to the adjustable current source, and the seventh transistor has its source connected to the output of the second voltage follower circuit, its gate connected to the output of the first voltage follower circuit, and its drain connected to the adjustable current source.

6. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 5, characterized in that: the PVT following circuit further comprises a voltage following circuit and a second transistor circuit, the second transistor circuit comprises at least a sixth transistor, the voltage following circuit has an input connected to the source common mode voltage and an output connected to the source of the sixth transistor, the sixth transistor has its gate connected to its drain, and its drain connected to the adjustable voltage source and outputting the adjustable voltage to the gate of the fifth transistor.

7. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 6, characterized in that: the PVT following circuit further comprises a seventh transistor, the seventh transistor has its source connected to the output of the second voltage follower circuit, its gate connected to the output of the first voltage follower circuit, and its drain connected to the adjustable current source.

8. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 7, characterized in that: the PVT following circuit further comprises an eighth transistor, the eighth transistor has its source connected to the output of the second voltage follower circuit, its gate connected to the output of the first voltage follower circuit, and its drain connected to the adjustable current source.

9. The PVT-insensitive high-bandwidth variable gain amplifier according to claim 8, characterized in that: the PVT following circuit further comprises a ninth transistor, the ninth transistor has its source connected to the output of the second voltage follower circuit, its gate connected to the output of the first voltage follower circuit, and its drain connected to the adjustable current source. The PVT follower circuit employs an adjustable current source that generates the adjustable voltage through the PVT follower circuit, such that the equivalent impedance is related to the adjustable current source, device characteristic constants, and is not related to PVT. ​ ​ ​ The first transistor circuit and the transistor in the second transistor circuit have the same conduction threshold voltage, and the equivalent impedance is: wherein, a width-to-length ratio of the fifth transistor, a width-to-length ratio of the sixth transistor, a gm constant current provided by the adjustable current source, a device characteristic constant related to PVT; The equivalent impedance The regulation accuracy depends on the regulation accuracy of the adjustable current source. ​ The first transistor circuit and the second transistor circuit both adopt a transistor resistance array, and by controlling the on-off state of the transistor in the transistor resistance array, the proportion of the resistance output of the transistor resistance array is changed to adjust the equivalent impedance To achieve the quasi-continuous and wide-range gain adjustment of the gain amplifier. ​ The transistor resistance array is composed of 4 groups of parallel transistors, the bandwidth of the gain amplifier reaches 28GHz or above, and if the gain amplifier is adjusted with an accuracy of 0.1dB, the adjustment range of 0-6dB is covered.

10. A receiver analog front-end circuit, characterized by The application relates to a PVT-insensitive high-bandwidth variable gain amplifier. The receiver terminal accesses a weak electric signal generated after photoelectric conversion, is used for carrying out preliminary gain control, noise removal and output common mode control on the weak electric signal, and outputs a voltage signal to the input end of the AC coupling circuit, the AC coupling circuit is used for isolating the direct current component in the voltage signal and transmitting the alternating current signal to the input end of the variable gain amplifier, and the gain amplifier is used for dynamically adjusting the gain according to the strength of the alternating current signal, transmitting the amplified alternating current signal to the data processing circuit of the receiver later stage.

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