Wide gain range VGA circuit with SAR-AGC
By introducing a SAR-AGC module and a VGA system with digital circuit design, the problem of limited gain control range in existing AGC systems is solved, achieving automatic gain control with a wide gain range, reducing circuit area and power consumption, adapting to the amplification requirements of extremely weak signals, and improving the stability and adaptability of the system.
Patent Information
- Application Number
- CN202510975256.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-15
- Publication Date
- 2025-10-31
AI Technical Summary
Existing AGC systems have limited gain control range, making it difficult to achieve wide automatic gain control of 100dB or more. Furthermore, analog circuit designs occupy a large area and consume a lot of power, making it difficult to meet the amplification requirements of extremely weak signals.
Using a SAR-AGC module combined with a differential or single-ended input/output VGA system, a wide gain range control is achieved by utilizing peak detection, a window comparator, and a SAR control module. The main circuit adopts a digital circuit design, reducing the requirements for the peak detection circuit, and maintaining the stability of the output signal through a successive approximation process.
It achieves automatic gain control with an ultra-wide gain range (>130dB), reduces circuit area and power consumption, improves noise margin, adapts to the amplification requirements of extremely weak signals, and enhances the stability and adaptability of the system.
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Figure CN120880366A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of integrated circuit technology, specifically a wide gain range VGA circuit with SAR-AGC. Background Technology
[0002] VGA (Variable Gain Amplifier) plays a crucial role in communications, audio processing, instrumentation, and video signal processing due to its adjustable gain. It can flexibly adjust the signal gain according to actual needs, ensuring the signal maintains an appropriate amplitude during transmission and processing, thereby optimizing system performance. VGA can adjust the signal gain to ensure the output signal is neither too large nor too small. The core advantage of a VGA with a wide adjustable range lies in its ability to flexibly adapt to input signals ranging from extremely weak to extremely strong. The introduction of AGC (Automatic Gain Control) further enhances the system's stability and adaptability. It monitors the strength of the input or output signal in real time and automatically adjusts the VGA's gain to keep the output signal amplitude within a preset range, ensuring the stability of signal processing. VGAs with AGC are of great significance in integrated circuit systems. In the receiver link of common communication systems, the VGA located at the front end of the ADC can automatically adjust the input signal to the ADC's optimal quantization range, ensuring that the signal-to-noise ratio does not decrease and improving the dynamic range of the entire system. In some transmit links with limited transmit power, the VGA can be used to control the signal amplitude of the input power amplifier, achieving power control.
[0003] With the continuous development and advancement of integrated circuit technology and devices, modern electronic circuit systems are evolving towards multifunctionality, high integration, miniaturization, and low power consumption. However, most current AGC systems can only achieve automatic gain control of 20-40dB, limiting system performance; some AGC systems with a wide automatic gain control range of 100dB or more are difficult to integrate on-chip. Summary of the Invention
[0004] In view of this, embodiments of this application provide a wide gain range VGA circuit with SAR-AGC to provide a wider automatic gain control range and reduce circuit area.
[0005] This application provides a wide gain range VGA circuit with SAR-AGC, the VGA circuit including: SAR-AGC module and VGA system;
[0006] The VGA system has differential input and differential output or single-ended input and single-ended output.
[0007] The output of the VGA system is connected to the SAR-AGC module, and the output of the SAR-AGC module is connected to the VGA system; the output of the VGA system is the input of the SAR-AGC module, and the output of the SAR-AGC module is the gain control signal of the VGA system.
[0008] If the VGA system is a DVGA system, then the gain control signal output by the SAR-AGC module is a digital code;
[0009] If the VGA system is an AVGA system, then the gain control signal output by the SAR-AGC module is an analog signal.
[0010] In some embodiments, the SAR-AGC module includes a peak detection module, a window comparator, and a SAR control module connected in sequence;
[0011] The input terminal of the peak detection module is connected to the output terminal of the VGA system; the peak detection module is used to detect and distinguish the target peak value, and then output DC voltage or current accordingly.
[0012] The input of the window comparator is the output of the peak detection module, and the output of the window comparator is the input of the SAR control module. The window comparator is used to output different levels based on the comparison result between the output of the peak detection module and the comparison level.
[0013] The output of the SAR control module is controlled by an external clock signal and the output of the window comparator, and the output of the SAR control module is used to determine the gain control signal.
[0014] In some embodiments, the peak detection module is used to detect and distinguish the upper limit, standard value and lower limit of the target peak value, and then output DC voltage or current accordingly.
[0015] In some embodiments, the window comparator is further connected to a first comparison level and a second comparison level; wherein the first comparison level is greater than the second comparison level;
[0016] If the input of the window comparator is greater than the first comparison level, the window comparator is used to output a low level at the COMP terminal and a high level at the READY terminal;
[0017] If the input of the window comparator is less than the second comparison level, the window comparator is used to output the COMP terminal as high and the READY terminal as high.
[0018] If the input of the window comparator is less than the first comparison level but greater than the second comparison level, then the window comparator outputs a low level at the READY terminal.
[0019] In some embodiments, the output of the SAR control module is controlled by an external clock signal and the READY terminal level of the window comparator, and the output of the SAR control module is an N-bit digital code;
[0020] If the VGA system adopts the DVGA system, the SAR control module is used to output the N-bit digital code as the gain control signal to the DVGA system;
[0021] If the VGA system adopts the AVGA system, a DAC is provided between the SAR control module and the AVGA system. The DAC is used to convert the N-bit digital code into an analog signal and output it to the AVGA system as the gain control signal.
[0022] In some embodiments, if the peak detection module detects that the target peak exceeds the range of a preset lower limit to a preset upper limit, the SAR-AGC module is used to trigger a successive approximation process, so that the digital code output after the successive approximation process stabilizes at a new level, thereby causing the target peak to return to the range of the preset lower limit to the preset upper limit.
[0023] In some embodiments, when the SAR control module operates at a set timing, the successive approximation process is triggered.
[0024] In some embodiments, the DVGA system includes an optional gain amplifier and an adjustable DVGA;
[0025] The output of the selectable gain amplifier is connected to the input of the adjustable DVGA.
[0026] The input terminal of the selectable gain amplifier serves as the input terminal of the DVGA system, and the output terminal of the adjustable DVGA serves as the output terminal of the DVGA system.
[0027] The digital code output by the SAR-AGC module is sent to the optional gain amplifier to control the optional gain amplifier.
[0028] In some embodiments, the optional gain amplifier includes a single sub-amplifier or multiple sub-amplifiers connected in series.
[0029] In some embodiments, each of the sub-amplifiers adopts a fully differential negative feedback architecture, and the input resistance and feedback resistance of each of the sub-amplifiers are composed of a deep linear region NMOS transistor connected in series with a resistor;
[0030] The NMOS transistor also serves as a transmission gate, and its conduction is controlled by a digital signal to select the input resistor and thus select the gain.
[0031] This application includes at least the following beneficial effects:
[0032] The VGA circuit provided in this application includes a SAR-AGC module and a VGA system. The VGA system has differential input and differential output, or single-ended input and single-ended output. The output of the VGA system is connected to the SAR-AGC module, and the output of the SAR-AGC module is connected to the VGA system. The output of the VGA system is the input of the SAR-AGC module, and the output of the SAR-AGC module is the gain control signal of the VGA system. If the VGA system is a DVGA system, the gain control signal output by the SAR-AGC module is a digital code; if the VGA system is an AVGA system, the gain control signal output by the SAR-AGC module is an analog signal. The SAR-AGC module of this application has an extremely wide automatic gain control range, enabling it to maintain a stable output signal amplitude for a short time even under large-scale continuous changes in the input signal. Most of the circuitry within the SAR-AGC module can be implemented using digital circuitry, resulting in a small footprint, easy integration, and the absence of static power consumption in digital circuitry, thus reducing the overall system power consumption to some extent. The SAR-AGC module also has a larger noise margin than analog circuits and is less sensitive to noise. Attached Figure Description
[0033] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0034] Figure 1 An example structural diagram of a wide gain range VGA circuit with SAR-AGC provided in an embodiment of this application;
[0035] Figure 2 An example structural diagram of the SAR-AGC module provided in the embodiments of this application;
[0036] Figure 3 This is a schematic diagram showing different inputs and outputs of the peak detection module provided in the embodiments of this application;
[0037] Figure 4 A connection diagram of the window comparator provided in an embodiment of this application;
[0038] Figure 5A schematic diagram showing the connection between the SAR control module and the VGA system provided in an embodiment of this application;
[0039] Figure 6 A flowchart illustrating the workflow of a SAR-AGC module provided in this application embodiment;
[0040] Figure 7 An example structural diagram of a DVGA system provided in this application embodiment;
[0041] Figure 8(a) is an optional example structural diagram of a single sub-amplifier provided in an embodiment of this application;
[0042] Figure 8(b) is another alternative example structural diagram of a single sub-stage amplifier provided in an embodiment of this application;
[0043] Figure 9 Example structural diagram of a window comparator provided in an embodiment of this application;
[0044] Figure 10 A structural diagram of an optional asynchronous SAR control module provided in an embodiment of this application;
[0045] Figure 11 A structural diagram of an optional synchronous SAR control module provided in an embodiment of this application;
[0046] Figure 12 A flowchart illustrating the workflow of another SAR-AGC module provided in this application embodiment;
[0047] Figure 13 A structural diagram of a DVGA system with a SAR-AGC module provided in this application embodiment;
[0048] Figure 14 This is a structural diagram of a DVGA system with a smaller step size and SAR-AGC module provided in an embodiment of this application. Detailed Implementation
[0049] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.
[0050] Before providing a detailed description of the embodiments of this application, some related technologies involved in the embodiments of this application will be described first, as follows:
[0051] First, let's explain the terminology:
[0052] AGC (Automatic Gain Control): Automatic gain control.
[0053] SAR (Successive Approximation Register): A type of digital circuit, a sequential logic circuit with standard schemes.
[0054] Pulse generator: A module in the SAR circuit used to generate sequentially pulled-up digital pulse signals.
[0055] SAR-AGC Module: An automatic gain control system based on SAR logic, the module proposed in this application.
[0056] Variable gain system: refers to systems with adjustable gain, such as VGA and PGA. In this application, it is specifically used to refer to VGA.
[0057] VGA (Variable Gain Amplifier): refers to an amplifier with continuously variable gain. It is generally an analog voltage / current controlled gain, i.e., an analog VGA (Analog Variable Gain Amplifier); it can also be a high-resolution digitally controlled VGA (Digital-controlled Variable Gain Amplifier).
[0058] VGA system: refers to a system that includes variable gain modules such as AVGA, DVGA, or PGA.
[0059] AVGA system: refers to a variable gain system that includes AVGA.
[0060] DVGA system: refers to a variable gain system that includes DVGA.
[0061] PGA: refers to a variable gain amplifier with discrete gain, such as adjustable gain of 1x, 2x, 4x, 8x, or adjustable gain of 1x, 10x, 100x.
[0062] SNR (Signal-to-Noise Ratio): The ratio of signal power to noise power.
[0063] Peak detection module: This refers to a module with peak detection function in a broad sense. That is, the output voltage value (usually a DC voltage or a small-amplitude voltage signal that is close to DC) will change with the peak value of the input signal. There are many ways to implement it, including PD, PH, RMS-to-DC converter, RMS detector, etc.
[0064] PD (peak detector): Peak detector.
[0065] PH (peak holder): Peak holder.
[0066] RMS-to-DC converter: Root Mean Square DC converter.
[0067] RMS detector: Root Mean Square detector.
[0068] Microvolt (μV): The unit of voltage. 1 microvolt is equal to 10^(-6) volts.
[0069] Vpp: A unit of voltage, representing peak-to-peak voltage.
[0070] Logarithmic amplifier: It can compress the input signal according to the log function or a similar log function, and can compress large signals.
[0071] BJT: Junction Transistor, a commonly used component in integrated circuits.
[0072] CMOS (Complementary Metal-Oxide-Semiconductor): A type of integrated circuit technology.
[0073] Automatic gain control range: This refers to the range of input signals that the AGC system can automatically control the gain of, i.e., the normal operating range of the AGC. It can be calculated by subtracting the minimum input amplitude from the maximum input amplitude during normal system operation, and is generally expressed in dB.
[0074] ADC (analog-to-digital converter): A converter that converts data from one digital source to another.
[0075] DAC (digital-to-analog converter): A digital-to-analog converter.
[0076] Clock-controlled comparator: A comparator controlled by an input clock. It is usually active when the clock is high. The strong arm latch is a type of clock-controlled comparator.
[0077] Strong-arm latch: A type of latch, a digital circuit that requires a clock. It can be used as a sensitive amplifier or a high-precision comparator, offering advantages such as high sensitivity, high speed, and small size. Its disadvantages include kickback noise and offset voltage, but these effects can be mitigated by adding a simple preamplifier.
[0078] DFF (D flip-flop): A type of digital circuit where a standard DFF cell is sampled on the clock edge.
[0079] FDA (Fully Differential Amplifier): A fully differential amplifier.
[0080] TG (transition gate): A transmission gate is a type of digital circuit that can be used as a switch, requiring a control signal to control its on / off state. It can be high-level enabled, low-level enabled, or normally open. In the embodiments of this application, the transmission gate can be any type of digital signal-controlled switch.
[0081] CMOS transmission gate: refers to the transmission gate of complementary MOS structure (i.e., the transmission gate composed of NMOS and PMOS connected in parallel).
[0082] A gate voltage bootstrap switch is a voltage switch that uses a capacitor to raise the gate voltage. It has advantages such as low on-resistance, wide signal swing range, and high linearity.
[0083] An XNOR gate (equivalence gate) is a digital logic circuit that outputs 1 when two input signals are at the same level and 0 when they are opposite. A typical two-input XNOR gate actually uses four signals: signal A, signal B, and their inverted signals Ab and Bb.
[0084] AND gate: A type of digital logic circuit where the output is 1 when all inputs are high and 0 when any input is 0.
[0085] NF (Noise figure): Noise figure, a system evaluation metric.
[0086] The relevant technologies of this application will be described below:
[0087] A typical AGC system generally consists of a peak detection module and a feedback circuit. VGA systems may have differential or single-ended inputs and outputs; this application will focus on VGA systems with differential inputs and outputs. For the peak detection module, the output can be analog or digital, while the input is generally analog. If the peak value of the input signal is in the microvolt range (≤-60dB), it is difficult to distinguish a 1dB difference using the peak detection module directly. A common approach is to pre-amplify the signal with a fixed gain before connecting it to the peak detection module. The disadvantage is that large-amplitude signals are saturated and amplified, making it impossible to distinguish differences in large-amplitude signals. In this case, a cascaded logarithmic amplifier is needed to compress the large signal. The added pre-amplification stage and logarithmic amplifier undoubtedly increase the system power consumption. A root mean square detector designed using BJTs can achieve high gain and high bandwidth, sufficient to distinguish microvolt-level input signals, but BJTs occupy a large area, are difficult to integrate, and have a larger static leakage current compared to CMOS digital circuits. The SAR-AGC module proposed in this application can greatly reduce the requirements for peak detection circuits. Since most of the circuitry within the module can be implemented using digital circuitry, the module occupies a small area. Furthermore, digital circuitry has no static power consumption, a large noise margin (insensitive to noise), and reduces the output noise requirements of the VGA system. When used in conjunction with a VGA system with a certain gain range and step size, it can achieve wide-range, high-precision gain control.
[0088] Current variable gain amplifiers (VGAs) generally have a gain adjustment range limited to below 100dB, and the positive gain range of existing wide-range adjustable VGAs is usually small, making it difficult to meet the amplification requirements of extremely weak signals (μV / nV level). This embodiment proposes a numerically controlled variable gain amplifier architecture that achieves an ultra-wide gain range (>130dB) and ultra-high gain (>130dB).
[0089] VGAs present three contradictions during signal amplification: First, the contradiction between signal gain and noise suppression. Amplifier inherent noise is positively correlated with gain, and under high gain conditions, the noise figure (NF) becomes a key parameter limiting the output signal-to-noise ratio (SNR). When the NF is not effectively controlled, the output signal may be completely overwhelmed by the floor noise. Second, the contradiction between gain enhancement and linearity degradation. High-gain operation forces the amplifier to approach the nonlinear region, leading to a sharp increase in harmonic distortion (HD) and intermodulation distortion (IMD). Third, the physical limitations of the gain-bandwidth product (GBW). Achieving ultra-high gain while maintaining a bandwidth in the MHz to GHz range presents difficulties. The technical challenges in designing ultra-high gain DVGAs include: 1) Multi-stage cascade stability control, requiring a phase margin >60° in a four-stage high-gain cascade architecture to avoid self-oscillation; 2) Precise gain control, requiring ±0.1dB step accuracy within a 120dB dynamic range; 3) Power consumption optimization challenges, as high gain and high gain-bandwidth product consume significant power, requiring optimization.
[0090] This application provides a wide gain range VGA circuit with SAR-AGC, the VGA circuit including: SAR-AGC module and VGA system;
[0091] The VGA system has differential input and differential output or single-ended input and single-ended output.
[0092] The output of the VGA system is connected to the SAR-AGC module, and the output of the SAR-AGC module is connected to the VGA system; the output of the VGA system is the input of the SAR-AGC module, and the output of the SAR-AGC module is the gain control signal of the VGA system.
[0093] If the VGA system is a DVGA system, then the gain control signal output by the SAR-AGC module is a digital code;
[0094] If the VGA system is an AVGA system, then the gain control signal output by the SAR-AGC module is an analog signal.
[0095] Optionally, the SAR-AGC module includes a peak detection module, a window comparator, and a SAR control module connected in sequence;
[0096] The input terminal of the peak detection module is connected to the output terminal of the VGA system; the peak detection module is used to detect and distinguish the target peak value, and then output DC voltage or current accordingly.
[0097] The input of the window comparator is the output of the peak detection module, and the output of the window comparator is the input of the SAR control module. The window comparator is used to output different levels based on the comparison result between the output of the peak detection module and the comparison level.
[0098] The output of the SAR control module is controlled by an external clock signal and the output of the window comparator, and the output of the SAR control module is used to determine the gain control signal.
[0099] Optionally, the peak detection module is used to detect and distinguish the upper limit, standard value and lower limit of the target peak value, and then output DC voltage or current accordingly.
[0100] Optionally, the window comparator is further connected to a first comparison level and a second comparison level; wherein the first comparison level is greater than the second comparison level;
[0101] If the input of the window comparator is greater than the first comparison level, the window comparator is used to output a low level at the COMP terminal and a high level at the READY terminal;
[0102] If the input of the window comparator is less than the second comparison level, the window comparator is used to output the COMP terminal as high and the READY terminal as high.
[0103] If the input of the window comparator is less than the first comparison level but greater than the second comparison level, then the window comparator outputs a low level at the READY terminal.
[0104] Optionally, the output of the SAR control module is controlled by an external clock signal and the READY terminal level of the window comparator, and the output of the SAR control module is an N-bit digital code;
[0105] If the VGA system adopts the DVGA system, the SAR control module is used to output the N-bit digital code as the gain control signal to the DVGA system;
[0106] If the VGA system adopts the AVGA system, a DAC is provided between the SAR control module and the AVGA system. The DAC is used to convert the N-bit digital code into an analog signal and output it to the AVGA system as the gain control signal.
[0107] Optionally, if the peak detection module detects that the target peak exceeds the range of the preset lower limit to the preset upper limit, the SAR-AGC module is used to trigger a successive approximation process, so that the digital code output after the successive approximation process stabilizes at a new level, thereby causing the target peak to return to the range of the preset lower limit to the preset upper limit.
[0108] Optionally, when the SAR control module operates in a set timing sequence, the successive approximation process is triggered.
[0109] Optionally, the DVGA system includes an optional gain amplifier and an adjustable DVGA;
[0110] The output of the selectable gain amplifier is connected to the input of the adjustable DVGA.
[0111] The input terminal of the selectable gain amplifier serves as the input terminal of the DVGA system, and the output terminal of the adjustable DVGA serves as the output terminal of the DVGA system.
[0112] The digital code output by the SAR-AGC module is sent to the optional gain amplifier to control the optional gain amplifier.
[0113] Optionally, the optional gain amplifier may include a single sub-amplifier or multiple sub-amplifiers connected in series.
[0114] Optionally, each of the sub-amplifiers adopts a fully differential negative feedback architecture, and the input resistance and feedback resistance of each sub-amplifier are composed of a deep linear region NMOS transistor connected in series with a resistor;
[0115] The NMOS transistor also serves as a transmission gate, and its conduction is controlled by a digital signal to select the input resistor and thus select the gain.
[0116] The following section will provide a detailed introduction and explanation of the solutions in the embodiments of this application, using specific application examples.
[0117] The solution provided in this embodiment is as follows: Figure 1 As shown, the wide gain range VGA circuit with SAR-AGC provided in this embodiment includes a SAR-AGC module and a VGA system. The VGA system has differential inputs Vinp and Vinn and differential outputs Voutp and Voutn (e.g., ...). Figure 1 (a) and (b) in the text may also have single-ended input Vin and single-ended output Vout (e.g., ... Figure 1(c) and (d) in the diagram). The output of the VGA system is the input of the SAR-AGC module, and the output of the SAR-AGC module is the gain control signal of the VGA system. If the VGA system is a DVGA system, the SAR-AGC outputs the digital code CTRL. <n-1:0>,like Figure 1 As shown in (a); if the VGA system is an AVGA system, the SAR-AGC outputs an analog signal (including analog voltage or analog current signals) CTRL, as shown in (a). Figure 1 As shown in (b) of the diagram.
[0118] SAR-AGC module architecture as follows Figure 2 As shown (regardless of the input and output of the VGA system), a SAR-AGC module should consist of three parts: a peak detection module, a window comparator, and a SAR control module. The input of this system is the output of the VGA system (…). Figure 2 The output of this system (Voutp, Voutn) is the gain control signal of the VGA system.
[0119] The peak detection module is required to distinguish the peak values of three input signals. For example... Figure 3 As shown, the peak values of the three input signals are denoted as Vpin1, Vpin2, and Vpin3 (Vpin1, Vinp2, and Vinp3 are equal to the peak values of Voutp - Voutn), representing the upper limit of the target peak value, the standard value of the target peak value, and the lower limit of the target peak value, respectively. The corresponding output voltages are Vpo1, Vpo2, and Vpo3. Vpo1, Vpo2, and Vpo3 should all be DC voltages (or currents) or voltages (or currents) close to DC. Distinguishing between the three input signals means that when Vpin1 > Vpin2 > Vpin3, Vpo1 > Vpo2 > Vpo3.
[0120] For example, assuming the SAR-AGC module needs to function normally, the peak-to-peak values of Voutp-Voutn should always be around 0dB (1Vpp), with an error not exceeding ±0.2dB (approximately 0.977Vpp-1.023Vpp), i.e., Vpin1=0.2dB, Vpin2=0dB, Vpin3=-0.2dB, resulting in Vpo1>Vpo2>Vpo3. In this example, Vpin1, Vpin2, and Vpin3 differ by 23mV, which is a relatively low accuracy requirement for a typical peak detection module.
[0121] Window comparator module, such as Figure 4 As shown, this module requires two comparison levels, VREF1 and VREF2, where VREF1 > VREF2, and COMP and READY are two digital signals. Its input is the output of the peak detection module, and its output is the input of the SAR control module. The functions it implements are as follows: If its input voltage Vin > VREF1, the output COMP is at a low level and READY is at a high level; if Vin < VREF2, COMP is at a high level and READY is at a high level; if VREF1 > Vin > VREF2, the level of COMP is unimportant (it can be either high or low), and READY is at a low level. By adjusting the resistors, VREF1 = Vpo1 and VREF2 = Vpo3, it can be determined whether the peak value of Voutp - Voutn is within the target range. When READY changes from a high level to a low level, it indicates that the peak value of Voutp - Voutn has converged to the range of [Vinp3, Vinp1] (represented by the closed interval [Vinp3, Vinp1], indicating an interval that is ≥ Vinp3 and ≤ Vinp1). When READY changes back from a low level to a high level, it indicates that the peak value of Voutp - Voutn has deviated from the range of [Vinp3, Vinp1] due to changes in the input amplitude or other reasons. To ensure the correct value of each gain control bit, the READY signal needs to be delayed relative to the COMP signal.
[0122] The SAR control module is as Figure 5 shown. Its working process is controlled by an external clock signal CLK and the READY signal of the window comparator. Its inputs are the outputs COMP and READY of the window comparator, and its output is an N-bit digital code. If the variable gain system is a DVGA system, the output of this module can be directly used as the gain control signal of the variable gain system. If the variable gain system is an AVGA system, a DAC is inserted between the SAR control module and the VGA control signal. The DAC converts the digital code into an analog signal CTRL, but this increases the complexity of the system. The recommended method is to use it in combination with a DVGA system.
[0123] The working process of the SAR-AGC module is as Figure 6 shown. When the peak value of Voutp - Voutn deviates from the range of [Vinp3, Vinp1], a successive approximation process is triggered. After this process, the digital code CTRL output by the SAR-AGC <n-1:0>The system stabilizes at a new level, causing the peak value of Voutp-Voutn to return to the range [Vinp3, Vinp1], or to a level closest to the range [Vinp3, Vinp1]. Simultaneously, the successive approximation process requires ensuring that the SAR control logic operates under the correct timing.
[0124] This embodiment also proposes an easy-to-implement DVGA system suitable for SAR-AGC to illustrate how the SAR-AGC module can achieve wide-range, high-precision gain control.
[0125] The architecture of a DVGA system is as follows: Figure 7 As shown, the DVGA consists of selectable gain amplifiers of 64dB / 0dB, 32dB / 0dB, and 16dB / 0dB, as well as a 10-25dB adjustable DVGA. The cascaded architecture effectively extends the system's gain-bandwidth product (GBW) by distributing the total gain to each sub-module, and the discretized gain control architecture also facilitates the implementation of large dynamic range gain step digital adjustment.
[0126] Each sub-amplifier employs the fully differential negative feedback architecture shown in Figure 8(a), with both input and feedback resistances provided by a resistor connected in series with the transmission gate TG. The transmission gate TG can be any digitally controlled switch, such as an NMOS transistor, a CMOS transistor, or a gate-driven bootstrap switch. Using a gate-driven bootstrap switch provides better linearity. The input resistance is selected to choose the gain by controlling its conduction via a digital signal.
[0127] Figure 8(b) provides another possible fully differential negative feedback architecture, where the NMOS acts as both the transmission transistor and the feedback resistor. Because there is only one switch, the charge injection is smaller, and the capacitance is lower. It can compensate for the phase margin decrease caused by the loading effect. The NMOS is turned on or off by controlling the digital signal, thereby changing the feedback resistance and thus changing the gain.
[0128] The different FDA parameters on which the various optional amplifiers and 10-25dB DVGA are based can save power and area.
[0129] The DVGA control signals consist of a 7-bit gain control signal `gain_ctl<6:0>` and an EN signal. The first three bits of `gain_ctl<6:0>` control selectable amplifiers of 64dB / 0dB, 32dB / 0dB, and 16dB / 0dB, respectively. A high level input corresponds to the gain (64dB, 32dB, or 16dB), and a low level input corresponds to 0dB. The last four bits control the 10-25dB VGA. 0000 corresponds to 10dB, and 1111 corresponds to 25dB. There are 16 states in total, corresponding to a 16dB range. 1 and 0 represent high and low levels, respectively, referring to 1.8V and 0V voltages in this design. The lowest value (all 0s) of the 7-bit control code corresponds to 10dB (0+0+0+10dB), and the highest value (all 7 bits are 1) corresponds to 137dB. 0000000-1111111 corresponds to 10-137dB.
[0130] The more specific implementation method is as follows:
[0131] Multi-stage selectable gain op-amps can be constructed by cascading multiple single-stage selectable gain op-amps. Single-stage selectable gain op-amps can be implemented using operational amplifiers, with the gain of the operational amplifier changing depending on the feedback resistor selected by the digital code. As shown in Figure 8, TG1 is composed of TG12 and TG13 connected in parallel. TG1 is a normally open transmission gate, TG2 and TG12 are high-level conduction gates, and TG3 and TG13 are low-level conduction gates. D is a 1-bit gain control digital code. If the on-resistance of TG1, TG2, and TG3 is negligible compared to R1, R2, and R3, then TG13 can be the same as TG3, and TG12 can be the same as TG2. When D is high, the gain of this selectable gain op-amp is... When D is low, the gain of this selectable gain op-amp is .
[0132] If the on-resistances of TG1, TG2, and TG3 are not negligible compared to R1, R2, and R3, then the dimensions of TG13 and TG1 need to be designed to ensure resistance matching of the transmission gates and reduce gain error. Specifically, the ratio of the on-resistances of TG13 to TG3 needs to be approximately [value missing]. The ratio of the on-resistance of TG12 to that of TG2 is approximately: Otherwise, when D is high, the gain of this selectable gain op-amp will deviate from its normal value. When D is low, the gain of this selectable gain op-amp will deviate. This results in gain error. Assume... Then the gain of the optional gain op-amp is 0dB. ) or 64dB ( ).
[0133] The peak detection module can be any circuit that can convert the three peaks Vpin1, Vpin2, and Vpin3 into three different DC voltages or near-DC voltages, such as: peak detector (PD), peak holder (PH), RMS-to-DC converter, RMS detector, or other simpler circuits.
[0134] An implementation of a window comparator is as follows: Figure 9 As shown, the two comparators CP1 and CP2 can be strong-arm latches or other types of clocked comparators. The comparator clock is CLK_COMP, and the comparator levels are set to VREF1=Vpo1 and VREF=Vpo3, respectively, where Vpo is the output of the peak detection module. When the clock CLK_COMP is high, COMP1 and COMP1b are inverted signals, and COMP2 and COMP2b are inverted signals. Delay is a delay unit, which can be achieved using 2-4 stages of inverters. COMP1 and COMP2 are passed through a NAND gate to obtain the COMP signal. The delayed clock CLK_COMP_d and DFF are used to ensure that the READY signal is delayed before the COMP signal is generated. COMP1, COMP1b, COMP2, and COMP2b are sampled and latched by a DFF to obtain COMP1', COMP1b', COMP2', and COMP2b' respectively. These four signals are input into an XOR gate to obtain the READY signal. The value of the READY signal is the value of the XOR of COMP1' and COMP2'.
[0135] Synchronous SAR logic requires an additional clock CLK_SAR to control the pulse generator, while asynchronous SAR logic can use an external low-frequency clock CLK to generate the internal clock CLK_SAR and the comparator's clock CLK_COMP. It is also faster, completing a successive approximation process more quickly, which helps shorten the settling time of the AGC system. Therefore, asynchronous SAR logic is recommended. An implementation of a SAR control module based on asynchronous SAR logic is shown below. Figure 10 The control clock CLK and READY signals, after passing through an AND gate, control the clock generator. For generalization, a SAR control module implemented based on synchronous SAR logic is shown below. Figure 11 .
[0136] Figure 12 This embodiment demonstrates the workflow of the SAR-AGC module, which is very similar to the workflow of a traditional SAR module. The difference is that the SAR-AGC module may terminate the successive approximation process in advance by using the READY signal.
[0137] A wide-range automatic control VGA system with SAR-AGC, such as Figure 13 As shown, assume the gain control signal is a 7-bit digital signal, i.e., CTRL<6:0>. The first three stages of the VGA system are selectable gain op-amps, CTRL... <6> CTRL <5> CTRL <4> The selectable gain op-amps for control have gains of 0dB / 64dB, 0dB / 32dB, and 0dB / 16dB, respectively. The final DVGA stage uses a 4-bit digital code CTRL<3:0> for control, achieving 10-25dB gain control with an accuracy of 1dB (i.e., a minimum adjustment step of 1dB). If Vpin1, Vpin2, and Vpin3 are 1dB, 0dB, and -1dB, respectively, the entire system can operate normally when the peak value of the input differential signal continuously varies from -120dB to -10dB (ideally, the maximum range is -137dB to -10dB, but this is limited by the common-mode range of the op-amp input). This means the automatic gain control range is 110dB, while the peak value of the differential output signal remains within the range of 0dB ± 1dB (error ± 1dB). Furthermore, placing the selectable gain op-amp with the highest gain in the first stage helps improve the system noise figure (NF).
[0138] To achieve higher precision control, simply increase the digital code and improve the DVGA resolution. For example... Figure 14 As shown, assuming the gain control signal is a 9-bit digital signal, i.e., CTRL<8:0>, the final DVGA stage uses a 6-bit digital code CTRL<5:0> for control, achieving 0-16dB gain control with an accuracy of 0.25dB. Vpin1, Vpin2, and Vpin3 are set to 0.25dB, 0dB, and -0.25dB respectively. With everything else unchanged, the maximum automatic gain control range is 127dB (input signal from -127dB to 0dB), and the peak value range of the differential output signal is 0±0.25dB.
[0139] The beneficial effects of this embodiment are:
[0140] The SAR-AGC module proposed in this embodiment has a simple structure and can greatly reduce the requirements for the dynamic range and accuracy of the peak detection circuit.
[0141] The SAR-AGC module proposed in this embodiment has an extremely wide automatic gain control range, and can maintain the output signal amplitude stable for a short period of time even when the input signal changes continuously over a wide range.
[0142] Most of the circuits in the SAR-AGC module proposed in this embodiment can be implemented using digital circuits, so it occupies a small area, is easy to integrate, and digital circuits have no static power consumption, thereby reducing the total power consumption of the system to a certain extent; the noise margin is relatively larger than that of analog circuits, and it is not sensitive to noise.
[0143] If asynchronous SAR logic is used to implement the SAR control module, only a low-frequency clock is added to the external input signal, and the requirements for the system input signal are not high.
[0144] The DVGA system with SAR-AGC proposed in this embodiment can achieve wide-range, high-gain, high-precision, and high-speed automatic gain control.
[0145] In the description of this specification, the references to "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.
[0146] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.
[0147] The above is a detailed description of the preferred embodiments of this application, but this application is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application, and these equivalent modifications or substitutions are all included within the scope defined by the claims of this application.
Claims
1. A wide gain range VGA circuit with SAR-AGC, characterized in that, The VGA circuit includes: a SAR-AGC module and a VGA system; The VGA system has differential input and differential output or single-ended input and single-ended output. The output of the VGA system is connected to the SAR-AGC module, and the output of the SAR-AGC module is connected to the VGA system; the output of the VGA system is the input of the SAR-AGC module, and the output of the SAR-AGC module is the gain control signal of the VGA system. If the VGA system is a DVGA system, then the gain control signal output by the SAR-AGC module is a digital code; If the VGA system is an AVGA system, then the gain control signal output by the SAR-AGC module is an analog signal.
2. The wide gain range VGA circuit with SAR-AGC according to claim 1, characterized in that, The SAR-AGC module includes a peak detection module, a window comparator, and a SAR control module connected in sequence. The input terminal of the peak detection module is connected to the output terminal of the VGA system; the peak detection module is used to detect and distinguish the target peak value, and then output DC voltage or current accordingly. The input of the window comparator is the output of the peak detection module, and the output of the window comparator is the input of the SAR control module. The window comparator is used to output different levels based on the comparison result between the output of the peak detection module and the comparison level. The output of the SAR control module is controlled by an external clock signal and the output of the window comparator, and the output of the SAR control module is used to determine the gain control signal.
3. A wide gain range VGA circuit with SAR-AGC according to claim 2, characterized in that, The peak detection module is used to detect and distinguish the upper limit, standard value and lower limit of the target peak value, and then output DC voltage or current accordingly.
4. A wide gain range VGA circuit with SAR-AGC according to claim 2, characterized in that, The window comparator is also connected to a first comparison level and a second comparison level; wherein, the first comparison level is greater than the second comparison level; If the input of the window comparator is greater than the first comparison level, the window comparator is used to output a low level at the COMP terminal and a high level at the READY terminal; If the input of the window comparator is less than the second comparison level, the window comparator is used to output the COMP terminal as high and the READY terminal as high. If the input of the window comparator is less than the first comparison level but greater than the second comparison level, then the window comparator outputs a low level at the READY terminal.
5. A wide gain range VGA circuit with SAR-AGC according to claim 2, characterized in that, The output of the SAR control module is controlled by an external clock signal and the READY terminal level of the window comparator. The output of the SAR control module is an N-bit digital code. If the VGA system adopts the DVGA system, the SAR control module is used to output the N-bit digital code as the gain control signal to the DVGA system; If the VGA system adopts the AVGA system, a DAC is provided between the SAR control module and the AVGA system. The DAC is used to convert the N-bit digital code into an analog signal and output it to the AVGA system as the gain control signal.
6. A wide gain range VGA circuit with SAR-AGC according to claim 2, characterized in that, If the peak detection module detects that the target peak exceeds the range of the preset lower limit to the preset upper limit, the SAR-AGC module is used to trigger a successive approximation process, so that the digital code output after the successive approximation process stabilizes at a new level, thereby causing the target peak to return to the range of the preset lower limit to the preset upper limit.
7. A wide gain range VGA circuit with SAR-AGC according to claim 6, characterized in that, When the SAR control module operates in the set timing sequence, the successive approximation process is triggered.
8. A wide gain range VGA circuit with SAR-AGC according to claim 1, characterized in that, The DVGA system includes an optional gain amplifier and an adjustable DVGA; The output of the selectable gain amplifier is connected to the input of the adjustable DVGA. The input terminal of the selectable gain amplifier serves as the input terminal of the DVGA system, and the output terminal of the adjustable DVGA serves as the output terminal of the DVGA system. The digital code output by the SAR-AGC module is sent to the optional gain amplifier to control the optional gain amplifier.
9. A wide gain range VGA circuit with SAR-AGC according to claim 8, characterized in that, The optional gain amplifier may include a single sub-amplifier or multiple sub-amplifiers connected in series.
10. A wide gain range VGA circuit with SAR-AGC according to claim 9, characterized in that, Each of the sub-amplifiers adopts a fully differential negative feedback architecture, and the input resistance and feedback resistance of each sub-amplifier are composed of a deep linear region NMOS transistor connected in series with a resistor; The NMOS transistor also serves as a transmission gate, and its conduction is controlled by a digital signal to select the input resistor and thus select the gain.