Impedance optimization circuit

Abstract

The invention discloses an impedance optimization circuit, which comprises a transistor and an ESD (Electro-Static Discharge) structure, one end of the ESD structure is electrically connected with an I / O PAD of the chip through the transistor, and the other end of the ESD structure is grounded; and based on the operation stage of the chip, the chip controls the transistor to be switched on or switched off. The ESD stray capacitor is connected to the I / O PAD in the debugging training stage of the chip, and the on-demand connection of the ESD stray capacitor is realized by adopting the transistor, so that the connection and disconnection of the ESD stray capacitor can be flexibly adjusted in different operation stages of the chip, the signal integrity is optimized under the condition of not needing additional capacitor resources, the performance of a communication link is improved, and the reliability of the communication link is improved. Through reutilization of the capacitor of the ESD structure, the chip area does not need to be newly increased, so that the chip area and the power consumption are effectively reduced.

Description

Technical Field

[0001] This application relates to the field of testing technology, and in particular to an impedance optimization circuit. Background Technology

[0002] Currently, in order to provide electrostatic protection to chips, chip pin processing modules (I / O PADs) typically integrate ESD (Electrostatic Discharge) structures in parallel. However, the ESD structure itself has a certain parasitic capacitance (usually ranging from a few picofarads to tens of picofarads), which is regarded as a load in high-speed signal transmission, thus causing signal edge degradation and frequency response reduction.

[0003] In related technologies, in order to increase the equivalent load during the training phase and improve the stability of the eye diagram, optional capacitors are added near the I / OPAD, such as MIM (Metal-Insulator-Metal) capacitors or MOS capacitors (the capacitance formed by the gate and channel of a MOS transistor). The capacitors are switched on and off by circuit control and turned off after training to restore the signal rate. However, by introducing on-chip capacitors, the chip area and wiring complexity are increased.

[0004] Therefore, how to optimize impedance matching and eye diagram quality in the high-speed I / O interface of a chip without adding external capacitors, thereby improving the performance of the communication link and reducing chip area and power consumption, is a problem that urgently needs to be solved. Summary of the Invention

[0005] The main objective of this application is to provide an impedance optimization circuit that aims to solve the technical problem of how to optimize impedance matching and eye diagram quality in the high-speed I / O interface of a chip without adding additional external capacitors, thereby improving the performance of the communication link and reducing chip area and power consumption.

[0006] To achieve the above objectives, this application provides an impedance optimization circuit, which is applied to a chip and includes a transistor and an ESD structure. One end of the ESD structure is electrically connected to the chip pin processing module I / O PAD of the chip through the transistor, and the other end of the ESD structure is grounded. Based on the operating phase of the chip, the chip controls the transistor to be turned on or off.

[0007] In one possible implementation, the transistor is a MOS transistor, the gate of which is electrically connected to the I / O interface of the chip through the I / OPAD, and the source of which is electrically connected to the ESD structure.

[0008] In one possible implementation, if the operation phase is a power-on phase, the chip controls the transistor to turn off so that the I / O PAD is isolated from the ESD parasitic capacitance of the ESD structure.

[0009] In one possible implementation, if the operation phase is a debugging phase, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

[0010] In one possible implementation, if the operation phase is a high-speed transmission phase, the chip controls the transistor to be turned off so that the I / O PAD is isolated from the ESD parasitic capacitance of the ESD structure.

[0011] In one possible implementation, if the current temperature of the chip is greater than a preset temperature, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

[0012] In one possible implementation, if the current voltage corresponding to the chip is greater than a preset voltage, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

[0013] In one possible implementation, if the power supply jitter information corresponding to the chip is greater than a preset jitter, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

[0014] In one possible implementation, the I / O PAD includes a transmitter TX PAD, and the impedance optimization circuit includes a transmitter impedance optimization circuit. The chip acquires the first signal quality corresponding to the TX PAD; if the first signal quality is less than the preset signal quality, the chip controls the transistor corresponding to the TX PAD to be turned on, so that the ESD parasitic capacitance corresponding to the TX PAD is connected to the TX PAD.

[0015] In one possible implementation, the I / O PAD includes a receiver RX PAD, and the impedance optimization circuit includes a receiver impedance optimization circuit. The chip acquires the second signal quality corresponding to the RX PAD; if the second signal quality is less than the preset signal quality, the chip controls the transistor corresponding to the RX PAD to be turned on, so that the ESD parasitic capacitance corresponding to the RX PAD is connected to the RX PAD.

[0016] This application utilizes transistors to electrically connect the ESD structure to the chip's pin processing module I / O PAD. By controlling the transistors to turn them on or off, the ESD parasitic capacitance of the ESD structure can be connected to or isolated from the I / O PAD. This allows the ESD parasitic capacitance to be connected to the I / O PAD during the chip's debugging and training phase. By using transistors to achieve on-demand connection of ESD parasitic capacitance, the connection and disconnection of ESD parasitic capacitance can be flexibly adjusted at different stages of chip operation. This optimizes signal integrity and improves the performance of the communication link without requiring additional capacitor resources. By reusing the capacitance of the ESD structure, no additional chip area is required, effectively reducing chip area and power consumption.

[0017] Meanwhile, without adding additional external capacitors, the capacitance of the I / O interface corresponding to the I / O PAD can be increased. The increased capacitance optimizes signal reflection, impedance matching, and eye diagram quality in the chip's high-speed I / O interface, thereby improving the performance of the communication link. Attached Figure Description

[0018] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0019] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0020] Figure 1 This is a schematic diagram of the module structure provided for an embodiment of the impedance optimization circuit of this application; Figure 2 This is a schematic diagram of the circuit structure provided for an embodiment of the impedance optimization circuit of this application; Figure 3 This is a schematic diagram of the circuit structure for another embodiment of the impedance optimization circuit of this application.

[0021] Explanation of icon numbers: 110, I / O PAD; 120, Transistor; 130, ESD structure; 131, ESD parasitic capacitance.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0025] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0026] Furthermore, the use of terms such as "first" and "second" in this application is for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. Additionally, the technical solutions of the various embodiments can be combined with each other, but only on the basis of being achievable by those skilled in the art. When the combination of technical solutions is contradictory or impossible to implement, such a combination of technical solutions should be considered non-existent and not within the scope of protection claimed in this application.

[0027] To better understand the technical solution of this application, a detailed description will be provided below in conjunction with the accompanying drawings and specific implementation methods.

[0028] The main solution of this application is: an impedance optimization circuit is applied to the chip, the impedance optimization circuit includes: a transistor and an ESD electrostatic discharge structure; one end of the ESD electrostatic discharge structure is electrically connected to the chip pin processing module I / O PAD of the chip through the transistor, and the other end of the ESD structure is grounded; based on the operating phase of the chip, the chip controls the transistor to be turned on or off.

[0029] Currently, in order to provide electrostatic protection to chips, chip pin processing modules (I / O PADs) typically integrate ESD (Electrostatic Discharge) structures in parallel. However, the ESD structure itself has a certain parasitic capacitance (usually ranging from a few picofarads to tens of picofarads), which is regarded as a load in high-speed signal transmission, thus causing signal edge degradation and frequency response reduction.

[0030] In related technologies, in order to increase the equivalent load during the training phase and improve the stability of the eye diagram, optional capacitors, such as MIM capacitors or MOS capacitors, are added near the I / OPAD. These capacitors are switched on and off by circuit control and then turned off after training to restore the signal rate. However, introducing on-chip capacitors increases the chip area and wiring complexity.

[0031] Therefore, how to optimize signal reflection, impedance matching, and eye diagram quality in the high-speed I / O interface of a chip without adding external capacitors, thereby improving the performance of the communication link and reducing chip area and power consumption, is a problem that urgently needs to be solved.

[0032] ESD structures inherently possess a certain amount of parasitic capacitance, typically ranging from a few picofarads to tens of picofarads. In high-speed signal transmission, this parasitic capacitance is considered a load, resulting in signal edge degradation and a decrease in frequency response. Furthermore, in related technologies, it is selectively connected or disconnected during system operation as needed, leading to wasted space and a lack of flexibility.

[0033] This application embodiment utilizes transistors to electrically connect the ESD structure to the chip's pin processing module I / O PAD. By controlling the transistors to turn them on or off, the ESD parasitic capacitance of the ESD structure can be connected to or isolated from the I / O PAD. This allows the ESD parasitic capacitance to be connected to the I / O PAD during the chip's debugging and training phase. By using transistors to achieve on-demand connection of ESD parasitic capacitance, the connection and disconnection of ESD parasitic capacitance can be flexibly adjusted at different operating stages of the chip. This optimizes signal integrity and improves the performance of the communication link without requiring additional capacitor resources. By reusing the capacitors of the ESD structure, no additional chip area is required, effectively reducing chip area and power consumption.

[0034] Meanwhile, without adding additional external capacitors, the capacitance of the I / O interface corresponding to the I / O PAD can be increased. The increased capacitance optimizes signal reflection, impedance matching, and eye diagram quality in the chip's high-speed I / O interface, thereby improving the performance of the communication link.

[0035] Based on this, this application proposes a voltage control system. (Refer to...) Figures 1 to 3 , Figure 1 This is a schematic diagram of the module structure provided for an embodiment of the impedance optimization circuit of this application; Figure 2 This is a schematic diagram of the circuit structure provided for an embodiment of the impedance optimization circuit of this application; Figure 3 This is a schematic diagram of the circuit structure for another embodiment of the impedance optimization circuit of this application.

[0036] In this embodiment, refer to Figure 1Impedance optimization circuitry is applied to the chip and includes transistor 120 and ESD structure 130.

[0037] One end of the ESD structure 130 is electrically connected to the chip pin processing module I / O PAD 110 via transistor 120, and the other end of the ESD structure 130 is grounded. In other words, one end of transistor 120 is electrically connected to the ESD structure 130, and the other end is electrically connected to I / O PAD 110.

[0038] Based on the chip's operating phase, the chip controls the transistor 120 to be turned on or off. Specifically, during different operating phases of the chip, the chip controls the control terminal electrically connected to the transistor 120 to be connected to a high / low level to control the transistor 120 to be turned on or off. For example, when the chip is in the debugging and training phase, the chip controls the control terminal electrically connected to the transistor 120 to be connected to a high level to turn the transistor 120 on, thereby connecting the ESD parasitic capacitance 131 of the ESD structure 130 to the I / O PAD 110. When the chip is in other operating phases, the chip controls the control terminal electrically connected to the transistor 120 to be connected to a low level to turn the transistor 120 off, thereby isolating the I / O PAD 110 from the ESD parasitic capacitance 131 of the ESD structure 130, so as to realize the on-demand connection of the ESD parasitic capacitance 131.

[0039] In one feasible implementation, refer to Figure 2 The transistor 120 is a MOS transistor. The gate of the MOS transistor is electrically connected to the I / O interface of the chip through the I / O PAD 110. The source of the MOS transistor is electrically connected to the ESD structure 130, and the drain of the MOS transistor is electrically connected to the control terminal.

[0040] In this embodiment, transistor 120 is a MOS (Metal-Oxide-Semiconductor Field-Effect Transistor), for example, a pMOS or nMOS transistor. During various operating stages of the chip, the MOS transistor can be turned on or off as needed through the control terminal to realize the on-demand connection of the ESD parasitic capacitor 131.

[0041] In one feasible implementation, refer to Figure 2 If the operation phase is the power-on phase, the chip controls the transistor 120 to be turned off so that the I / O PAD 110 is isolated from the ESD parasitic capacitance 131 of the ESD structure 130.

[0042] In this embodiment, when the chip is in the power-on phase, power is supplied to the chip, and the chip's internal power domain is gradually established. At this time, by connecting a low level to the control terminal to turn off the transistor 120, the I / O PAD 110 is isolated from the ESD parasitic capacitance 131. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD = C_buffer + C_routing, where C_buffer is the chip's buffer capacitance and C_routing is the winding capacitance. This ensures that the I / O PAD 110 maintains the minimum equivalent capacitance, so as to maintain a stable level when the chip is powered on and prevent problems such as false triggering and false identification. At the same time, it ensures that the ESD structure 130 maintains its normal protection function to avoid affecting the debugging and training phase or communication phase after initialization.

[0043] After the chip is powered on, it undergoes initialization, which is the operational phase. After completing basic initialization, the chip enters the I / O interface initialization phase, including input / output direction configuration, termination pull-level setting, and pre-configuration of some PHY layer channels. During the initialization phase, a low-level signal is applied to the control terminal to keep transistor 120 off, ensuring continuous isolation between I / O PAD 110 and ESD parasitic capacitor 131. This prevents the introduction of unnecessary capacitance during the initialization phase from interfering with the configuration process.

[0044] During the initialization phase, the chip's internal controller (such as a bootloader or configuration state machine) reads the configuration register. If a high-speed communication link (such as DDR / SerDes) is detected, it enters the pre-configuration mode. Then, by connecting a high-level signal to the control terminal to turn on the MOS transistor, the ESD parasitic capacitance 131 (C_ESD) in the ESD structure 130 is connected to the PAD, along with the internal equivalent capacitance C_ IO Parallel connection is used to increase the equivalent capacitance corresponding to the I / O PAD110, soften signal edges, and prevent reflection interference during the initial power-on / training process.

[0045] In one feasible implementation, refer to Figure 2 If the operation phase is the debugging phase, the chip controls the transistor 120 to be turned on so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110.

[0046] In this embodiment, when the chip is in the debugging phase, i.e., the link training or calibration phase, read / write latency calibration (DQS, Vref, write leveling, etc.) is performed through high-speed interfaces such as DDR (Double Data Rate), GDDR (Graphics Double Data Rate), and HBM (High Bandwidth Memory). At this time, by connecting a high-level control transistor 120 to the control terminal, the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110. The equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD = C_buffer + C_routing + C_ESD, where C_buffer is the chip's buffer capacitance, C_routing is the winding capacitance, and C_ESD is the ESD parasitic capacitance 131. By connecting the ESD parasitic capacitance 131, the I / O capacity is increased. The equivalent capacitance C_PAD of PAD110 enables flexible access to the ESD parasitic capacitance 131. This allows for an increase in the capacitance of the I / O interface corresponding to the I / O PAD110 without the need for additional external capacitors. The increased capacitance reduces signal reflection, impedance matching, suppresses overshoot and undershoot, and improves eye diagram quality in the chip's high-speed I / O interface. It also increases ESD capacitance to stabilize the signal and reduces chip area and power consumption.

[0047] In one feasible implementation, refer to Figure 2 If the operation phase is a high-speed transmission phase, the chip controls the transistor 120 to be turned off so that the I / O PAD 110 is isolated from the ESD parasitic capacitance 131 of the ESD structure 130.

[0048] In this embodiment, the operation phase is the high-speed transmission phase, i.e., the active phase (normal communication). The chip disables transistor 120 by connecting a low level to the control terminal. Specifically, after the training phase, the chip sets C_ESD_Enable to a low level through control logic, i.e., the control transistor 120 is turned off, and C_ESD is disconnected, so that I / O PAD110 is isolated from the ESD parasitic capacitance 131 of the ESD structure 130. At this time, the equivalent capacitance C_PAD of I / O PAD110 is: C_PAD=C_buffer+C_routing, thereby restoring I / O PAD110 to the minimum equivalent capacitance, thereby improving the chip's edge speed and bandwidth, and improving the eye diagram quality to adapt to high-speed data transmission.

[0049] In one feasible implementation, if the current temperature of the chip is greater than a preset temperature, the chip controls the transistor 120 to be turned on so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110.

[0050] In this embodiment, during the high-speed transmission phase of the chip, the current temperature of the chip can be obtained in real time, and it can be determined whether the current temperature is greater than the preset temperature. If the current temperature is greater than the preset temperature, a high-level control transistor 120 is connected at the control terminal to turn on, so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD=C_buffer+C_routing+C_ESD. By connecting the ESD parasitic capacitance 131, the equivalent capacitance C_PAD of the I / O PAD 110 is increased, and the flexible connection of the ESD parasitic capacitance 131 is realized. Thus, the capacitance of the I / O interface corresponding to the I / O PAD 110 can be increased without adding an external capacitor.

[0051] It should be noted that when the ESD parasitic capacitor 131 of the ESD structure 130 is connected to the I / O PAD 110, the current temperature of the chip can be continuously acquired in real time, and it can be determined whether the current temperature is greater than a preset temperature. If the current temperature is less than or equal to the preset temperature, the chip control transistor 120 is turned off, and C_ESD is disconnected, so that the I / O PAD 110 is isolated from the ESD parasitic capacitor 131 of the ESD structure 130. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD = C_buffer + C_routing. Thus, the intelligent switching of the ESD parasitic capacitor 131 can be achieved through temperature. The preset temperature can be reasonably set according to requirements.

[0052] In one feasible implementation, if the current voltage corresponding to the chip is greater than a preset voltage, the chip controls the transistor 120 to be turned on so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / OPAD 110.

[0053] In this embodiment, during the high-speed transmission phase of the chip, the current voltage of the chip can be obtained in real time, and it can be determined whether the current voltage is greater than the preset voltage. If the current voltage is greater than the preset voltage, a high-level control transistor 120 is connected at the control terminal to turn on, so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD=C_buffer+C_routing+C_ESD. By connecting the ESD parasitic capacitance 131, the equivalent capacitance C_PAD of the I / O PAD 110 is increased, and the flexible connection of the ESD parasitic capacitance 131 is realized. Thus, the capacitance of the I / O interface corresponding to the I / O PAD 110 can be increased without adding an external capacitor.

[0054] It should be noted that when the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110, the current voltage of the chip can be continuously acquired in real time, and it can be determined whether the current voltage is greater than a preset voltage. If the current voltage is less than or equal to the preset voltage, the chip control transistor 120 is turned off, and C_ESD is disconnected, so that the I / O PAD 110 is isolated from the ESD parasitic capacitance 131 of the ESD structure 130. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD = C_buffer + C_routing. Thus, the intelligent switching of the ESD parasitic capacitance 131 can be achieved through voltage. The preset voltage can be reasonably set according to requirements.

[0055] In one feasible implementation, if the power jitter information corresponding to the chip is greater than a preset jitter, the chip controls the transistor 120 to be turned on so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / OPAD 110.

[0056] In this embodiment, during the high-speed transmission phase of the chip, the power jitter information corresponding to the chip can be obtained in real time, and it can be determined whether the power jitter information is greater than the preset jitter. If the power jitter information is greater than the preset jitter, a high-level control transistor 120 is connected at the control terminal to turn on, so that the ESD parasitic capacitance 131 of the ESD structure 130 is connected to the I / O PAD 110. The equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD=C_buffer+C_routing+C_ESD. By connecting the ESD parasitic capacitance 131, the equivalent capacitance C_PAD of the I / O PAD 110 is increased, and the flexible connection of the ESD parasitic capacitance 131 is realized. Thus, the capacitance of the I / O interface corresponding to the I / O PAD 110 can be increased without adding an external capacitor.

[0057] It should be noted that when the ESD parasitic capacitor 131 of the ESD structure 130 is connected to the I / O PAD 110, the power jitter information corresponding to the chip can be continuously acquired in real time, and it can be determined whether the power jitter information is greater than a preset jitter. If the power jitter information is less than or equal to the preset jitter, the chip control transistor 120 is turned off, and C_ESD is disconnected, so that the I / O PAD 110 is isolated from the ESD parasitic capacitor 131 of the ESD structure 130. At this time, the equivalent capacitance C_PAD of the I / O PAD 110 is: C_PAD = C_buffer + C_routing. Thus, the intelligent switching of the ESD parasitic capacitor 131 can be achieved through the power jitter information. The preset jitter can be reasonably set according to requirements.

[0058] In one feasible implementation, refer to Figure 3 The I / O PAD110 includes a transmitter TX PAD, and the impedance optimization circuit includes a transmitter impedance optimization circuit. The chip acquires the first signal quality corresponding to the TX PAD; if the first signal quality is less than the preset signal quality, the chip controls the transistor 120 corresponding to the TX PAD to be turned on, so that the ESD parasitic capacitor 131 corresponding to the TX PAD is connected to the TX PAD 110.

[0059] In this embodiment of the application, an impedance optimization circuit can be set at the transmitter TX, that is, the I / O PAD110 includes TXTAD110, and the impedance optimization circuit includes the transmitter impedance optimization circuit.

[0060] During the high-speed transmission phase of the chip, the chip acquires the first signal quality corresponding to the TX PAD. For example, the chip can acquire the first signal quality corresponding to the TX PAD in real time or at regular intervals. The first signal quality can be the signal quality of the transmitter TX corresponding to the TX PAD. The chip then determines whether the first signal quality is less than a preset signal quality. If the first signal quality is less than the preset signal quality, the chip controls the transistor 120 corresponding to the TX PAD to be turned on, so that the ESD parasitic capacitor 131 corresponding to the TX PAD is connected to the TX PAD 110. By flexibly connecting the ESD parasitic capacitor 131 when the transmitter signal quality is poor, the capacitance of the I / O interface corresponding to the I / O PAD 110 can be increased without adding an external capacitor, thereby improving the SI (Signal Integrity) of the channel.

[0061] It is understandable that when the ESD parasitic capacitor 131 of the ESD structure 130 is connected to the TX PAD 110, the chip can continuously obtain the first signal quality corresponding to the TX PAD. If the first signal quality is greater than the preset signal quality, the chip controls the transistor 120 corresponding to the TX PAD to be turned off, and the C_ESD corresponding to the TX PAD is disconnected, so that the TX PAD 110 is isolated from the ESD parasitic capacitor 131 of the ESD structure 130.

[0062] In one feasible implementation, refer to Figure 3 The I / O PAD110 includes a receiver RX PAD, and the impedance optimization circuit includes a receiver impedance optimization circuit. The chip acquires the second signal quality corresponding to the RX PAD; if the second signal quality is less than the preset signal quality, the chip controls the transistor 120 corresponding to the RX PAD to be turned on, so that the ESD parasitic capacitor 131 corresponding to the RX PAD is connected to the RX PAD 110.

[0063] In this embodiment of the application, an impedance optimization circuit can be set at the receiving end RX, that is, I / O PAD110 includes RGPAD110, and the impedance optimization circuit includes the receiving end impedance optimization circuit.

[0064] During the high-speed transmission phase of the chip, the chip acquires the second signal quality corresponding to the RX PAD. For example, the chip can acquire the second signal quality corresponding to the RX PAD in real time or at regular intervals. This second signal quality can be the signal quality of the receiving end corresponding to the RX PAD. The chip then determines whether the second signal quality is less than a preset signal quality. If the second signal quality is less than the preset signal quality, the chip controls the transistor 120 corresponding to the RX PAD110 to be turned on, so that the ESD parasitic capacitor 131 corresponding to the RX PAD110 is connected to the RX PAD110. By flexibly connecting the ESD parasitic capacitor 131 when the signal quality at the receiving end is poor, the capacitance of the I / O interface corresponding to the I / O PAD110 can be increased without adding an external capacitor, thereby improving the signal integrity SI of the channel.

[0065] It is understandable that when the ESD parasitic capacitor 131 of the ESD structure 130 is connected to the RX PAD 110, the chip can continuously obtain the second signal quality corresponding to the RX PAD. If the second signal quality is greater than the preset signal quality, the chip controls the transistor 120 corresponding to the RX PAD to be turned off, and the C_ESD corresponding to the RX PAD is disconnected, so that the RX PAD 110 is isolated from the ESD parasitic capacitor 131 of the ESD structure 130.

[0066] It should be noted that when impedance optimization circuits are set at both the transmitting and receiving ends, joint adjustment can be performed at both ends according to the signal quality to improve the signal integrity of the entire high-speed link.

[0067] The impedance optimization circuit proposed in this embodiment uses transistor 120 to electrically connect ESD structure 130 to chip pin processing module I / O PAD 110. The chip controls the transistor 120 to turn on or off, so as to connect the ESD parasitic capacitance 131 of ESD structure 130 to I / O PAD 110 or isolate it from I / O PAD 110. Thus, the ESD parasitic capacitance 131 can be connected to I / O PAD 110 during the chip's debugging and training phase. By using transistor 120 to realize the on-demand connection of ESD parasitic capacitance 131, the connection and disconnection of ESD parasitic capacitance 131 can be flexibly adjusted at different operating stages of the chip. Signal integrity is optimized and the performance of communication link is improved without the need for additional capacitor resources. By reusing the capacitance of ESD structure 130, no additional chip area is required, so as to effectively reduce chip area and power consumption, ensuring low cost and high efficiency of the chip.

[0068] Meanwhile, without adding additional external capacitors, the capacitance of the I / O interface corresponding to the I / O PAD110 can be increased. The increased capacitance optimizes signal reflection, impedance matching, and eye diagram quality in the chip's high-speed I / O interface, thereby improving the performance of the communication link.

[0069] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by this application.

[0070] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. Any equivalent structural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. An impedance optimization circuit, characterized in that, The impedance optimization circuit is applied to the chip, and the impedance optimization circuit includes: transistors and ESD structures; One end of the ESD structure is electrically connected to the chip pin processing module I / O PAD of the chip through the transistor, and the other end of the ESD structure is grounded. Based on the operating phase of the chip, the chip controls the transistor to be turned on or off.

2. The impedance optimization circuit as described in claim 1, characterized in that, The transistor is a MOS transistor, and the gate of the MOS transistor is electrically connected to the I / O interface of the chip through the I / O PAD. The source of the MOS transistor is electrically connected to the ESD structure.

3. The impedance optimization circuit as described in claim 1, characterized in that, If the operation phase is the power-on phase, the chip controls the transistor to turn off so that the I / O PAD is isolated from the ESD parasitic capacitance of the ESD structure.

4. The impedance optimization circuit as described in claim 1, characterized in that, If the operation phase is the debugging phase, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

5. The impedance optimization circuit as described in claim 1, characterized in that, If the operation phase is a high-speed transmission phase, the chip controls the transistor to be turned off so that the I / O PAD is isolated from the ESD parasitic capacitance of the ESD structure.

6. The impedance optimization circuit as described in claim 1, characterized in that, If the current temperature of the chip is greater than the preset temperature, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / OPAD.

7. The impedance optimization circuit as described in claim 1, characterized in that, If the current voltage corresponding to the chip is greater than the preset voltage, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / OPAD.

8. The impedance optimization circuit as described in claim 1, characterized in that, If the power supply jitter information corresponding to the chip is greater than the preset jitter, the chip controls the transistor to turn on so that the ESD parasitic capacitance of the ESD structure is connected to the I / O PAD.

9. The impedance optimization circuit as described in any one of claims 1 to 8, characterized in that, The I / O PAD includes a transmitter TX PAD, and the impedance optimization circuit includes a transmitter impedance optimization circuit. The chip acquires the first signal quality corresponding to the TX PAD; if the first signal quality is less than the preset signal quality, the chip controls the transistor corresponding to the TX PAD to be turned on, so that the ESD parasitic capacitance corresponding to the TX PAD is connected to the TX PAD.

10. The impedance optimization circuit as described in claim 9, characterized in that, The I / O PAD includes a receiver RX PAD, and the impedance optimization circuit includes a receiver impedance optimization circuit. The chip acquires the second signal quality corresponding to the RX PAD; if the second signal quality is less than the preset signal quality, the chip controls the transistor corresponding to the RX PAD to be turned on, so that the ESD parasitic capacitance corresponding to the RX PAD is connected to the RX PAD.

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