Resistance network compression method, electronic equipment and storage medium

Abstract

The invention relates to a resistance network compression method, electronic equipment and a storage medium, and the method comprises the steps: obtaining node codes of resistance nodes in a resistance network and resistance information between the resistance nodes, and the resistance network comprises at least two resistance nodes and a resistor between the at least two resistance nodes; according to the resistance information between the resistance nodes, determining a target resistor to obtain at least one target resistor set; and coding the compression resistance network based on the at least one target resistance set and the resistance nodes. According to the technical scheme, the target resistor set to be compressed in the resistor network is determined according to the resistance information between the resistor nodes, the resistor network is compressed according to the target resistor set, the scale of the resistor network can be remarkably reduced, and the processing efficiency of the resistor network is improved.

Description

Technical Field

[0001] This application relates to the field of chip technology, specifically to a resistor network compression method, electronic device, and storage medium. Background Technology

[0002] EDA (Electronic Design Automation) refers to a series of software tools used in the physical design phase of the integrated circuit design process to ensure that the physical implementation of the design meets the predetermined functional specifications, performance indicators, and manufacturing process requirements.

[0003] With the development of semiconductor process technology, especially as process nodes shrink to 14 nanometers and below, the interconnect structures on chips have become denser and more complex. As process nodes shrink, more and finer metal layers are needed to distribute power and ground lines to maintain sufficient current density. This leads to a significant increase in the number of nodes in the VSS (ground) and VDD (power) networks. The increased complexity of the resistor network adds to the burden of matrix solving in subsequent voltage simulation stages. Storing complex resistor networks and their associated data structures requires substantial memory, and the simulation time also increases accordingly. Therefore, it is necessary to compress the resistor network before performing voltage simulation. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a resistor network compression method, electronic device, and storage medium. By determining the target set of resistors to be compressed in the resistor network through the resistance information between resistor nodes, and compressing the resistor network according to the target set of resistors, the size of the resistor network can be significantly reduced, and the processing efficiency of the resistor network can be improved.

[0005] To address the aforementioned technical problems, this application provides a resistor network compression method, comprising the following steps:

[0006] Obtain the node codes of resistor nodes and the resistance information between resistor nodes in the resistor network;

[0007] Based on the resistance information between resistor nodes, the target resistor is identified to obtain at least one target resistor set;

[0008] Based on at least one target resistor set and node-coded compressed resistor network.

[0009] In some embodiments, the resistance information between resistor nodes includes the resistance values ​​between resistor nodes, and determining the target resistance based on the resistance information between resistor nodes to obtain at least one target resistance set includes:

[0010] If the resistance value between resistor nodes is less than a preset threshold, the resistance between resistor nodes is determined as the target resistance.

[0011] At least one set of target resistors is determined based on all target resistors.

[0012] In some embodiments, before determining the target resistance based on the resistance information between resistor nodes to obtain at least one target resistance set, the process includes:

[0013] Identify the special nodes in the resistor nodes;

[0014] Based on the resistance information between resistor nodes, identifying the target resistance to obtain at least one target resistance set also includes:

[0015] Based on the resistance information between resistor nodes and special nodes, identify the target resistors to obtain at least one set of target resistors.

[0016] In some embodiments, the target resistor set includes target resistors and resistor nodes associated with the target resistors, and encoding a compressed resistor network based on at least one target resistor set and resistor nodes includes:

[0017] Compress all resistor nodes within the target resistor set.

[0018] In some embodiments, the resistor network compression method includes the following steps before compressing all resistor nodes within the target resistor set:

[0019] Update the node codes of all resistor nodes in the target resistor set based on the node code of any resistor node in the target resistor set.

[0020] In some embodiments, compressing all resistor nodes within the target resistor set includes:

[0021] Re-encode the node codes of all resistor nodes within the resistor network, and delete resistor nodes with duplicate codes; or,

[0022] Remove resistor nodes with duplicate codes within the resistor network, and recode the node codes of all resistor nodes within the resistor network.

[0023] In some embodiments, the node encoding of all resistor nodes within the resistor network is recoded, including:

[0024] Based on the correspondence between resistor nodes before and after the node encoding update, all resistor nodes in the resistor network are recoded.

[0025] In some embodiments, after encoding and compressing the resistor network based on at least one target resistor set and resistor nodes, the process includes:

[0026] Generate a visual network graph based on the compressed resistor network.

[0027] This application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the resistor network compression method described above.

[0028] This application also provides a storage medium storing a computer program, which, when executed by a processor, implements the steps of the resistor network compression method described above.

[0029] This application discloses a resistor network compression method, electronic device, and storage medium. The method includes: acquiring the node codes of resistor nodes and resistance information between resistor nodes in a resistor network, wherein the resistor network includes at least two resistor nodes and the resistance between at least two resistor nodes; identifying target resistors based on the resistance information between resistor nodes to obtain at least one target resistance set; and compressing the resistor network based on the at least one target resistance set and the resistor node codes. The technical solution of this application, by determining the target resistance set to be compressed in the resistor network through the resistance information between resistor nodes and compressing the resistor network based on the target resistance set, can significantly reduce the size of the resistor network and improve the processing efficiency of the resistor network. Attached Figure Description

[0030] Figure 1 This is one of the flowcharts illustrating the resistor network compression method provided in the embodiments of this application.

[0031] Figure 2 A schematic diagram of the resistor network provided in the embodiments of this application. Figure 1 .

[0032] Figure 3 To Figure 2 A schematic diagram of the compressed resistor network.

[0033] Figure 4 A schematic diagram of the resistor network provided in the embodiments of this application. Figure 2 .

[0034] Figure 5 To Figure 4 A schematic diagram showing the changes in resistor nodes in a medium-resistance network based on mapping relationships.

[0035] Figure 6 To Figure 4 A schematic diagram of the compressed resistor network.

[0036] Figure 7 According to Figure 4 A schematic diagram of the mapping relationship established between resistor nodes in a medium-resistance network.

[0037] Figure 8 This is a schematic diagram for updating the resistor node table based on the mapping relationship.

[0038] Figure 9 This is a schematic diagram for updating the resistor edge table based on the mapping relationship.

[0039] Figure 10 This is a schematic diagram of updating the resistor node table based on the compressed resistor network.

[0040] Figure 11 A schematic diagram of updating the resistor edge table for a compressed resistor network.

[0041] Figure 12 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0042] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0043] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, components, features, and elements with the same names in different embodiments of this application may have the same meaning or different meanings, the specific meaning of which must be determined by its interpretation in that specific embodiment or further in conjunction with the context of that specific embodiment.

[0044] It should be understood that although the terms first, second, third, etc., may be used herein to describe various information, such information should not be limited to these terms. These terms are used only to distinguish information of the same type from one another. For example, without departing from the scope of this document, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if," as used herein, can be interpreted as "when," "when," or "in response to determination." Furthermore, as used herein, the singular forms "a," "an," and "the" are intended to also include the plural forms unless the context indicates otherwise. It should be further understood that the terms "comprising," "including," indicate the presence of the stated feature, step, operation, element, component, item, kind, and / or group, but do not exclude the presence, occurrence, or addition of one or more other features, steps, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" as used herein are to be interpreted as inclusive, or mean any one or any combination thereof. Therefore, "A, B, or C" or "A, B, and / or C" means "any one of the following: A; B; C; A and B; A and C; B and C; A, B, and C". Exceptions to this definition will only occur if the combination of elements, functions, steps, or operations is inherently mutually exclusive in some way.

[0045] It should be understood that although the steps in the flowcharts of this application's embodiments are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some of the steps in the figures may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily completed at the same time, but can be executed at different times, and their execution order is not necessarily sequential, but can be performed alternately or in turn with other steps or at least a portion of the sub-steps or stages of other steps.

[0046] It should be noted that step designations such as S1 and S2 are used in this document for the purpose of more clearly and concisely describing the corresponding content, and do not constitute a substantial limitation on the order. In specific implementation, those skilled in the art may execute S2 first and then S1, etc., but these should all be within the protection scope of this application.

[0047] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0048] In the following description, the use of suffixes such as "module," "part," or "unit" to denote elements is solely for the purpose of illustrative purposes and has no specific meaning in itself. Therefore, "module," "part," or "unit" may be used interchangeably.

[0049] See Figure 1 This application provides a resistor network compression method, which can be implemented in software and / or hardware, such as a computer, server, or other computing device. The resistor network compression method provided in this embodiment includes:

[0050] S1, obtain the node codes of the resistor nodes in the resistor network and the resistance information between the resistor nodes.

[0051] The resistor network, generated after scanning and processing the pattern in the integrated circuit during parasitic resistance parameter extraction, is a network structure composed of interconnected parasitic resistances and their connection nodes. It characterizes the resistance distribution and connection relationships within the integrated circuit. The resistor network consists of resistor nodes and the resistances between them; specifically, it includes at least two resistor nodes and the resistances between at least two resistor nodes. It should be noted that resistor nodes are selected based on specific point-sampling rules during parasitic parameter extraction, and each node is identified by a unique node code within the resistor network. The node codes of the resistor nodes can be extracted from a resistor node table, which stores parameter information for the resistor nodes, including but not limited to the node code, node type, and adjacent nodes.

[0052] The resistance information between resistor nodes refers to the parameter information of the resistance between two resistor nodes, including but not limited to the resistor number, the node code mapped to the resistor number, and the resistance value. The resistor number reflects the connection relationship between resistor nodes and the connection relationship between resistors themselves. Through the resistor number, the node code mapped to that resistor number and its resistance value can be found through the mapping relationship. The resistance information between resistor nodes can be stored in the resistance edge table. It should be noted that the resistor numbers in each resistor segment in the resistance edge table are interconnected with the numbers of each resistor node in the resistance node table. The resistance network can be obtained from the resistance node table and the resistance edge table. The resistance node table mainly stores the parameter information of the resistor nodes, and in this scheme, it includes at least: node code, node type, and adjacent nodes. The resistance edge table is used to store resistance edge information, and in this scheme, it includes at least: resistor number, resistance value, and the node code mapped to the resistor number. Regarding the connection relationship between resistor nodes, two resistor nodes in the resistance number are adjacent, regardless of whether the codes of these two resistor nodes are consecutive. For example, please refer to... Figure 2In resistor numbers (1, 2) and (7, 12), resistor nodes 1 and 2 are adjacent, and resistor nodes 7 and 12 are adjacent. Regarding the connection relationship between resistors, if two resistor numbers contain duplicate resistor nodes, then the two resistors are adjacent. If two resistor numbers do not contain duplicate resistor nodes, then the two resistors are not adjacent. For example, in resistor numbers (9, 10), (10, 11), and (7, 12), resistor (9, 10) is adjacent to resistor (10, 11), while resistor (7, 12) is not adjacent to the other two resistors.

[0053] S2, Based on the resistance information between resistor nodes, identify the target resistor to obtain at least one target resistor set.

[0054] In this process, multiple target resistors are selected from the resistance information between all resistor nodes within the resistor network, based on the resistance information between all resistor nodes. At least one target resistor set is then determined based on these target resistors. The target resistor set refers to the resistors to be compressed during the resistor network compression process, selected based on the resistance information between resistor nodes. Specifically, multiple target resistors can be grouped according to the distribution rules of the target resistors in the resistor network, with each group forming a target resistor set. By scanning the resistor network, information on all resistor nodes and the resistance information between them is collected to determine the distribution pattern of the target resistors. Then, adjacent connected target resistors are considered as a single target resistor set.

[0055] S3 is based on at least one target resistor set and a node-coded compressed resistor network.

[0056] Compression refers to the process of reducing the number of resistor nodes and resistors in a resistor network. This application reduces the number of nodes in the network by merging one or more target resistors within the target resistor set, thereby achieving the purpose of compressing the resistor network. This simplifies the resistor network structure, reduces the computational complexity of parasitic parameters, improves processing efficiency, and maintains the accuracy and functionality of the resistor network.

[0057] Through steps S1 to S3 described above, the resistor network compression method of this application reduces the number of resistor nodes in the resistor network, reduces the computational load on processing the resistor network, lowers the demand for computing resources, and makes the simulation process more efficient. At the same time, although the resistor network is compressed, the main characteristics and functions of the circuit are preserved, maintaining signal integrity and quality, and avoiding signal distortion caused by short circuits or redundant components.

[0058] In some embodiments, the resistance information between resistor nodes includes the resistance values ​​between resistor nodes, and determining the target resistance based on the resistance information between resistor nodes to obtain at least one target resistance set includes:

[0059] If the resistance value between resistor nodes is less than a preset threshold, the resistance between resistor nodes is determined as the target resistance.

[0060] At least one set of target resistors is determined based on all target resistors.

[0061] In one implementation of this embodiment, it is determined whether the resistance value between resistor nodes is less than a preset threshold. The preset threshold can be a small resistance value, such as 0.1 ohms. Target resistors selected by comparison with the preset threshold have very small resistance values ​​relative to other resistors in the resistor network, and can be considered short-circuit resistors, having little impact on the overall performance of the resistor network. Compression of the resistor network can be achieved by compressing the target resistors. Next, at least one target resistor set is determined based on all target resistors. That is, all selected target resistors can be grouped into one target resistor set for compression, or they can be grouped into multiple different target resistor sets according to their distribution patterns, and then each target resistor set is compressed separately.

[0062] In some embodiments, the target resistors are divided into multiple sets according to the distribution rules of the target resistors, including at least one of the following:

[0063] If multiple target resistors are continuously connected, then the multiple target resistors are grouped into the same target resistor set;

[0064] If multiple target resistors are not continuously connected, they are divided into different target resistor sets.

[0065] In this embodiment, the distribution rules of the target resistors are derived by analyzing the topology of the resistor network. Then, multiple target resistors can be grouped. Specifically, circuit simulation tools, such as SPICE (Simulation Programming with Integrated Circuit Emphasis) or EDA (Electronic Design Automation) tools, can be used to scan the resistor network. First, the circuit netlist is read, and the resistor node information and the resistance information between resistor nodes are retrieved from the netlist. Next, based on all the resistor node information and the resistance information between resistor nodes, the distribution rules of multiple target resistors are obtained. For example, a DFS (Depth-First Search) or BFS (Breadth-First Search) algorithm can be used to traverse the resistor network, identifying the main paths and branch paths in the resistor network, as well as the target resistors distributed on each path.

[0066] As one implementation of this embodiment, a breadth-first search (BFS) algorithm is used, starting from the root node (any resistor node in the resistor network can be considered the root node), visiting all adjacent nodes layer by layer, and then visiting all unvisited adjacent nodes of those nodes, and so on, until all nodes have been visited. The BFS algorithm prioritizes exploring all nodes closest to the root node, and then expands outward layer by layer to explore nodes further away. This ensures that when the target node is found, the path taken is the shortest path from the root node to that node.

[0067] As one implementation of this embodiment, a depth-first search algorithm is used, starting from the root node (any resistor node in the resistor network can be considered the root node). The algorithm first visits the root node, then recursively visits one of its unvisited neighboring nodes. This process continues, visiting the unvisited neighboring nodes of that node until no further depth is possible. At this point, the algorithm backtracks to the previous node and continues visiting its other unvisited neighboring nodes until all nodes have been visited. This ensures that nodes are visited as deeply as possible during the exploration process, until all possible paths have been explored.

[0068] As one implementation of this embodiment, when multiple target resistors are in a continuous connection state, that is, without any other connection method or component inserted therein, these target resistors can be classified into the same target resistor set.

[0069] Please continue to refer to this. Figure 2 Black dots represent resistor nodes, solid lines represent target resistors, and dashed lines represent non-target resistors. For the target resistors (7, 8), (8, 9), and (9, 10), these three target resistors are in a continuous connection state, so they can be grouped into a target resistor set.

[0070] In one implementation of this embodiment, when multiple target resistors are in a discontinuous connection state, such as when there are non-target resistors among the multiple target resistors, these resistors should be classified into different target resistor sets. In the case of non-target resistors, if multiple target resistors on the same path are separated by non-target resistors and cannot form a direct connection path, the separated target resistors are classified into different target resistor sets. Specifically, the resistance value of the non-target resistor is higher than a preset threshold, or the non-target resistor is connected to a feature node.

[0071] Please continue to refer to this. Figure 2For target resistors (2, 3) and (7, 8), these two target resistors are in a discontinuous connection state, with non-target resistors (3, 4) and (4, 7) existing between them, respectively. Therefore, target resistors (2, 3) and (7, 8) need to be classified into two different target resistor sets. Similarly, for target resistors (2, 3) and (4, 5), these two target resistors are in a discontinuous connection state, with non-target resistor (3, 4) existing between them. Therefore, target resistors (2, 3) and (4, 5) need to be classified into two different target resistor sets.

[0072] In some embodiments, before determining the target resistance based on the resistance information between resistor nodes to obtain at least one target resistance set, the process includes:

[0073] Identify the special nodes in the resistor nodes;

[0074] Based on the resistance information between resistor nodes, identifying the target resistance to obtain at least one target resistance set includes:

[0075] Based on the resistance information between resistor nodes and special nodes, identify the target resistors to obtain at least one set of target resistors.

[0076] In one implementation of this embodiment, special nodes refer to resistor nodes in the chip that have specific functions or attributes and cannot be compressed, such as vias, pins, power nodes, ground nodes, input / output nodes, etc. When processing the resistor network, all special nodes in the resistor network are first identified based on their types. Then, when screening target resistors, if a resistor node connecting one or both ends of a resistor is a special node, that resistor will not be selected as a target resistor. For example... Figure 4 As shown, resistor nodes 7 and 8 are special nodes (marked by circles), therefore resistors (7, 8) are not classified as target resistors. Thus, by pre-excluding resistors connected to special nodes, the selection range of target resistors is narrowed, improving the efficiency of resistor network compression. Simultaneously, modifications to critical nodes in the circuit can be avoided, thereby maintaining the overall functionality and performance stability of the resistor network.

[0077] In some embodiments, the target resistor set includes target resistors and resistor nodes associated with the target resistors, and encoding a compressed resistor network based on at least one target resistor set and resistor nodes includes:

[0078] Compress all resistor nodes within the target resistor set.

[0079] In one implementation of this embodiment, after identifying the target resistors to obtain at least one set of target resistors, the scope of the resistor network requiring compression processing is defined as the target resistors within the target resistor sets and the resistor nodes associated with those target resistors. All resistor nodes within the target resistor sets are compressed, thereby reducing the complexity of the resistor network by merging the resistor nodes. If multiple target resistor sets are determined based on the target resistors, these sets can be compressed simultaneously, improving processing speed through parallel compression.

[0080] In some embodiments, the resistor network compression method includes the following steps before compressing all resistor nodes within the target resistor set:

[0081] Update the node codes of all resistor nodes in the target resistor set based on the node code of any resistor node in the target resistor set.

[0082] In one implementation of this embodiment, the node codes of the resistor nodes at both ends of the target resistor within the target resistor set are obtained and used as the first number. By changing the resistor nodes within the target resistor set to have the same number, the node codes of all resistor nodes within the target resistor set can be updated based on the node code of any resistor node within the target resistor set, resulting in the second number of the resistor nodes within the target resistor set. A mapping table is formed based on the one-to-one correspondence between the first and second numbers before and after the change.

[0083] like Figure 4 As shown, multiple target resistors (2,3), (4,5), (5,6), (8,9), and (9,10) are selected based on the resistance information between resistor nodes. First, according to the distribution rules of the target resistors, they are divided into three target resistor sets. The first target resistor set includes target resistor (2,3), as well as resistor nodes 2 and 3. The second target resistor set includes target resistors (4,5) and (5,6), as well as resistor nodes 4, 5, and 6. The third target resistor set includes target resistors (8,9) and (9,10), as well as resistor nodes 9 and 10, where resistor node 8 is a special node. Then, the resistor nodes within each target resistor set are changed to have the same number. (See diagram). Figure 5 As shown, the numbering of the first group is changed to (2, 2), the numbering of the second group is changed to (4, 4) and (4, 4), and the numbering of the third group is changed to (8, 8) and (8, 8). Of course, in other embodiments, the resistor nodes in the target resistor can also be changed to the same number (3, 3), and so on. Next, the resistor network is scanned again, and the resistor numbers of the resistor nodes in the resistor node table and the resistor edge table are updated sequentially according to the new second number.

[0084] In some embodiments, compressing all resistor nodes within the target resistor set includes:

[0085] Re-encode the node codes of all resistor nodes within the resistor network, and delete resistor nodes with duplicate codes; or,

[0086] Remove resistor nodes with duplicate codes within the resistor network, and recode the node codes of all resistor nodes within the resistor network.

[0087] In some embodiments, after updating the node codes of all resistor nodes within the target resistor set, the node codes of resistor nodes with connections may no longer be continuous. Therefore, the node codes of all resistor nodes in the resistor network can be recoded according to the connection order of the resistor nodes to make the codes continuous and facilitate data management. After updating the node codes of all resistor nodes within the target resistor set, resistor nodes with duplicate codes in the resistor network are deleted, reducing the number of resistor nodes. Specifically, resistor nodes with duplicate numbers can be removed from the resistor node table; at the same time, target resistors with duplicate numbers can be removed from the resistor edge table, thereby simplifying the resistor network.

[0088] In some embodiments, resistor nodes with duplicate codes within the resistor network can be deleted first. Resistor nodes with duplicate numbers are removed from the resistor node table, and target resistors with duplicate numbers are also removed from the resistor edge table. Then, the node codes of all resistor nodes within the resistor network are recoded to simplify the resistor network and optimize storage space.

[0089] In some embodiments, the node encoding of all resistor nodes within the resistor network is recoded, including:

[0090] Based on the correspondence between resistor nodes before and after the node encoding update, all resistor nodes in the resistor network are recoded.

[0091] As one implementation method of this embodiment, a mapping relationship can be established based on the node codes of the resistor nodes before and after the change, and then all resistor nodes in the resistor network can be recoded based on the mapping relationship. Specifically, the mapping relationship between the first number and the second number of the resistor node is obtained; the resistor node number in the resistor node table and the resistor node number in the resistor edge table are updated sequentially according to the mapping relationship.

[0092] In some embodiments, exemplarily, such as Figure 6 As shown, after removing resistors with duplicate numbers, the resistor nodes in the resistor network are renumbered to obtain a new resistor network. After compression, Figure 6 Compared to the resistor network in the middle Figure 4 The resistor network in this design is more streamlined. Furthermore, the compression process described above can be achieved through only two scans of the resistor network, resulting in better performance.

[0093] For example, please refer to Figure 7 A mapping table is created based on the mapping relationship between the first and second numbers. Then, the resistor node numbers in the resistor node table and the resistor node numbers in the resistor edge table are updated sequentially according to the mapping table. Specifically, the entire resistor node table is traversed using the mapping table. For each resistor node, its current number is checked to see if it exists in the mapping table. If it does, the original first number is replaced with the corresponding second number in the mapping table. Figure 8 As shown, firstly, the numbers [1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15] in the old resistor node table (old table) are updated according to the second number of the resistor node stored in the mapping table to obtain an intermediate table with the numbers [1, 2, 2, 4, 4, 4, 7, 8, 8, 8, 11, 12, 13, 14, 15]. Then, the non-contiguous numbers in the intermediate table are reordered to obtain a new table with the numbers [1, 2, 2, 3, 3, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10].

[0094] Similarly, when the resistance edge table needs to be updated, for each record in the resistance edge table, check the numbers of the two resistance nodes that make up this edge, and update these two numbers using the mapping table. If any one or both node numbers change, update the node numbers in the resistance edge table. For example... Figure 9 As shown, the resistor numbers [(1,2), (2,3), (3,4), (4,5), (5,6), (4,7), (7,8), (8,9), (9,10), (10,11), (7,12), (12,13), (12,14), (14,15)] in the old resistor node table (old table) are updated according to the latest resistor node table to obtain a new table, where the new resistor numbers are [(1,2), (2,2), (2,3), (3,3), (3,3), (3,4), (4,5), (5,5), (5,5), (5,6), (4,7), (7,8), (7,9), (9,10)].

[0095] Please refer to Figure 10 Remove the resistor nodes with duplicate numbers from the resistor node table. The numbers in the resistor node table are updated from [1, 2, 2, 3, 3, 3, 4, 5, 5, 5, 6, 7, 8, 9, 10] to [1, 2, 3, 4, 5, 6, 7, 8, 9, 10].

[0096] Please refer to Figure 11Resistor numbers with duplicates are removed from the resistor edge table. The resistor numbers in the edge table are updated from [(1,2), (2,2), (2,3), (3,3), (3,3), (3,4), (4,5), (5,5), (5,5), (5,6), (4,7), (7,8), (7,9), (9,10)] to [(1,2), (2,3), (3,4), (4,5), (5,6), (4,7), (7,8), (7,9), (9,10)]. This achieves the compression of the resistor network.

[0097] In some embodiments, after encoding and compressing the resistor network based on at least one target resistor set and resistor nodes, the process includes:

[0098] Generate a visual network graph based on the compressed resistor network.

[0099] In one implementation of this embodiment, the parameter information of the compressed resistor network, namely the compressed resistor node table and resistor edge table, is obtained, and the latest resistor node information and the resistance information between resistor nodes are extracted. Then, based on the resistor node information and the resistance information between resistor nodes, a visualized network graph is generated. The compressed visualized graph can be as follows: Figure 3 or Figure 6 The network diagram shown illustrates the compressed resistor network. This allows for a visual review and analysis of the network structure. By comparing the resistor network diagrams before and after compression, the changes in the network can be quickly understood, the effectiveness of compression can be evaluated, and further optimization or adjustments can be made.

[0100] The resistor network compression method of this application includes: obtaining the node codes of resistor nodes and the resistance information between resistor nodes in a resistor network, wherein the resistor network includes at least two resistor nodes and the resistance between at least two resistor nodes; identifying target resistors based on the resistance information between resistor nodes to obtain at least one target resistance set; and compressing the resistor network based on the at least one target resistance set and the resistor node codes. The technical solution of this application, by determining the target resistance set to be compressed in the resistor network through the resistance information between resistor nodes and compressing the resistor network based on the target resistance set, can significantly reduce the size of the resistor network and improve the processing efficiency of the resistor network.

[0101] Based on the same inventive concept as the foregoing embodiments, this invention provides an electronic device, such as... Figure 12 As shown, the electronic device includes: a processor 310 and a memory 311 storing a computer program; wherein, Figure 12The processor 310 shown in the diagram does not indicate that there is only one processor 310, but only indicates the positional relationship of the processor 310 relative to other devices. In practical applications, there can be one or more processors 310; similarly, Figure 12 The memory 311 shown in the diagram has the same meaning, that is, it is only used to indicate the positional relationship of memory 311 relative to other devices. In practical applications, there can be one or more memories 311. When the processor 310 runs the computer program, the resistor network compression method applied to the above-mentioned electronic device is implemented.

[0102] The electronic device may also include at least one network interface 312. The various components of the electronic device are coupled together via a bus system 313. It is understood that the bus system 313 is used to implement communication between these components. In addition to a data bus, the bus system 313 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 12 The general designated all buses as Bus System 313.

[0103] The memory 311 can be volatile memory or non-volatile memory, or both. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), ferromagnetic random access memory (FRAM), flash memory, magnetic surface memory, optical disc, or compact disc read-only memory (CD-ROM); the magnetic surface memory can be disk storage or magnetic tape storage. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Synchronous Static Random Access Memory (SSRAM), Dynamic Random Access Memory (DRAM), Synchronous Dynamic Random Access Memory (SDRAM), Double Data Rate Synchronous Dynamic Random Access Memory (DDRSDRAM), Enhanced Synchronous Dynamic Random Access Memory (ESDRAM), SyncLink Dynamic Random Access Memory (SLDRAM), and Direct Rambus Random Access Memory (DRRAM).The memory 311 described in the embodiments of the present invention is intended to include, but is not limited to, these and any other suitable types of memory.

[0104] The memory 311 in this embodiment of the invention is used to store various types of data to support the operation of the electronic device. Examples of this data include: any computer programs used to operate on the electronic device, such as operating systems and applications; contact data; phonebook data; messages; pictures; videos, etc. The operating system includes various system programs, such as the framework layer, core library layer, driver layer, etc., used to implement various basic services and handle hardware-based tasks. Applications can include various applications, such as media players, browsers, etc., used to implement various application services. Here, the program implementing the method of this embodiment of the invention can be included in the application.

[0105] Based on the same inventive concept as the foregoing embodiments, this embodiment also provides a storage medium storing a computer program. The storage medium can be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; it can also be various devices including one or any combination of the above-mentioned memories, such as mobile phones, computers, tablet devices, personal digital assistants, etc. When the computer program stored in the storage medium is run by a processor, it implements the above-described resistor network compression method. For the specific steps implemented when the computer program is executed by the processor, please refer to [link to relevant documentation]. Figure 2 The description of the illustrated embodiments will not be repeated here.

[0106] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0107] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0108] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A method for compression using a resistor network, characterized in that, The method includes the following steps: Obtain the node codes of the resistor nodes in the resistor network and the resistance information between the resistor nodes; Based on the resistance information between the resistor nodes, the target resistor is identified to obtain at least one target resistor set; The resistor network is compressed based on the at least one target resistor set and the node encoding.

2. The method according to claim 1, characterized in that, The resistance information between the resistor nodes includes the resistance values ​​between the resistor nodes. Based on this resistance information, identifying the target resistor to obtain at least one target resistance set includes: If the resistance value between the resistor nodes is less than a preset threshold, the resistance between the resistor nodes is determined to be the target resistance. At least one set of target resistors is determined based on all the target resistors.

3. The method according to claim 1, characterized in that, Before determining the target resistance based on the resistance information between the resistor nodes to obtain at least one target resistance set, the process includes: Identify the special nodes among the resistor nodes; The step of confirming the target resistance based on the resistance information between the resistor nodes to obtain at least one target resistance set further includes: Based on the resistance information between the resistor nodes and the special node, the target resistor is identified to obtain at least one target resistor set.

4. The method according to claim 1, characterized in that, The target resistor set includes the target resistor and the resistor node associated with the target resistor, and the encoding and compression of the resistor network based on the at least one target resistor set and the resistor node includes: All resistor nodes within the target resistor set are compressed.

5. The method according to claim 1 or 4, characterized in that, Before compressing all resistor nodes within the target resistor set, the method includes: Update the node codes of all resistor nodes in the target resistor set based on the node code of any resistor node in the target resistor set.

6. The method according to claim 5, characterized in that, The step of compressing all resistor nodes within the target resistor set includes: Re-encode the node codes of all resistor nodes within the resistor network, and delete resistor nodes with duplicate codes within the resistor network; or, Delete resistor nodes with duplicate codes in the resistor network, and recode the node codes of all resistor nodes in the resistor network.

7. The method according to claim 6, characterized in that, The recoding of the node codes of all resistor nodes in the resistor network includes: Based on the correspondence between the resistor nodes before and after the node encoding update, all resistor nodes in the resistor network are recoded.

8. The method according to claim 1, characterized in that, After encoding and compressing the resistor network based on the at least one target resistor set and the resistor nodes, the process includes: A visual network graph is generated based on the compressed resistor network.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor, when executing the computer program, implements the method as claimed in any one of claims 1 to 8.

10. A storage medium, characterized in that, The storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1 to 8.

Images