A DDS-based narrow-band spectrum time gating method, system, medium and device

Abstract

The application discloses a narrow-band spectrum time gating method and system based on DDS, a medium and equipment, and relates to the technical field of spectrum analysis. The application realizes time gating by utilizing a DDS direct frequency synthesizer in an FPGA. On the one hand, the entire time gating function is realized in the FPGA, is not related to a front-end radio frequency circuit, and a plurality of registers in a VCO in the front-end radio frequency circuit no longer need to be configured, so that the configuration interface is simplified, the control efficiency is improved, the digital circuit does not need to be synchronously controlled with the radio frequency circuit, and the system structure is simplified. On the other hand, as a core for realizing scanning, the DDS has very low and controllable lock delay, greatly improves the analysis speed of the system, and can process the delay in the FPGA, further simplifies the control process of the system, and improves the narrow-band spectrum time gating level.

Description

Technical Field

[0001] This application relates to the field of spectrum analysis technology, specifically to a narrowband spectrum time gating method, system, medium, and device based on DDS. Background Technology

[0002] Narrowband time-division multiplexed signals refer to signals composed of multiple sub-signals with bandwidths in the tens of MHz range, which occupy the same frequency band in a time-division manner and are superimposed, such as pulse-modulated signals and time-division multiple access signals. General spectrum analysis of narrowband time-division multiplexed signals in modern spectrum analyzers mainly relies on the time gating function, which allows for spectrum analysis of only specific sub-signals within the narrowband time-division multiplexed signal at a specific time.

[0003] However, the existing method is of low quality. Whenever the GATE time gate signal goes high, the host computer must reconfigure numerous registers, resulting in low control efficiency. Furthermore, it must poll the VCO lock flag to ensure that the VCO is stably locked, leading to a slow response speed. Summary of the Invention

[0004] In summary, the main objective of this application is to provide a narrowband spectrum time gating method, system, medium, and device based on DDS, aiming to solve the problem of low narrowband spectrum time gating level in the prior art.

[0005] To achieve the above objectives, the technical solutions adopted in the embodiments of this application are as follows:

[0006] In a first aspect, embodiments of this application provide a narrowband spectrum time gating method based on DDS, applied to FPGA, comprising the following steps:

[0007] Receive and store calculation parameters from the host computer; among which, the calculation parameters include the frequency control word corresponding to the starting frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal;

[0008] The time gate signal is generated based on the start time of the high level of the time gate signal and the duration of the high level of the time gate signal;

[0009] The scanning state of the DDS and the on / off state of the digital detector are controlled according to the time gate signal;

[0010] Obtain the target frequency control word based on the DDS scanning status;

[0011] Narrowband frequency time gating is achieved based on the target frequency control word.

[0012] In one possible implementation of the first aspect, obtaining the target frequency control word based on the scanning state of the DDS includes:

[0013] The state of the gate signal is obtained based on the scan state of the DDS;

[0014] Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is changed to obtain the target frequency control word.

[0015] In one possible implementation of the first aspect, the frequency control word of the DDS is controlled to change based on the state of the gate signal, the frequency control word corresponding to the start frequency, and the scan slope to obtain the target frequency control word, including:

[0016] Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is controlled to increment or remain constant until the scanning is completed and the target frequency control word is obtained.

[0017] In one possible implementation of the first aspect, the frequency control word of the DDS is incremented or held, including:

[0018] When the gate signal is high, the frequency control word of the DDS is incremented by summing the product of the counter's incrementing output value and the scan slope with the frequency control word corresponding to the starting frequency.

[0019] When the gate signal is low, the frequency control word of DDS is kept at the last output value calculated by the previous increment based on the previous auto-increment output value of the counter.

[0020] In one possible implementation of the first aspect, controlling the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal includes:

[0021] Based on the time gate signal, the scanning state of the DDS is controlled to switch between different states, and the digital detector is turned on and off.

[0022] In one possible implementation of the first aspect, controlling the switching of the DDS scanning state between different states and the on / off state of the digital detector according to the time gate signal includes:

[0023] The scanning state of the DDS is switched from the first state to the second state based on the arrival of the scan start pulse;

[0024] Once the count of the high-level start time of the time gate signal is full, the time gate signal is pulled high, and the count of the high-level duration of the time gate signal begins.

[0025] Once the high-level duration of the time gate signal is full, the time gate signal is pulled low. Then, depending on whether the number of detected data output by the digital detector matches the number required by the host computer, the system jumps to the third or first state until the scan end pulse arrives.

[0026] In one possible implementation of the first aspect, before receiving and storing the computational parameters from the host computer, the method further includes:

[0027] Configure multiple registers;

[0028] Receive and store calculation parameters from the host computer, including:

[0029] Based on the configured multiple registers, a calculation parameter from the host computer is received and stored respectively.

[0030] Secondly, embodiments of this application provide a narrowband spectrum time gating system based on DDS, applied to an FPGA, comprising:

[0031] The parameter configuration module is used to receive and store calculation parameters from the host computer; among which, the calculation parameters include the frequency control word corresponding to the starting frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal;

[0032] The GATE generation module is used to generate a time gate signal based on the high-level start time and high-level duration of the time gate signal.

[0033] The DDS control module is used to control the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal, obtain the target frequency control word according to the scanning state of the DDS, and realize narrowband frequency time gating according to the target frequency control word.

[0034] Thirdly, embodiments of this application provide a computer-readable storage medium storing a computer program, which, when loaded and executed by a processor, implements the narrowband spectrum time gating method based on DDS as provided in any of the first aspects above.

[0035] Fourthly, embodiments of this application provide an electronic device, including a processor and a memory, wherein,

[0036] Memory is used to store computer programs;

[0037] The processor is used to load and execute a computer program to cause the electronic device to perform a narrowband spectral time gating method based on DDS as provided in any of the first aspects above.

[0038] Compared with the prior art, the beneficial effects of this application are:

[0039] This application proposes a narrowband spectrum time gating method, system, medium, and device based on DDS. The method includes: receiving and storing calculation parameters from a host computer; wherein the calculation parameters include a frequency control word corresponding to the starting frequency, a scanning slope, a high-level start time of the time gate signal, and a high-level duration of the time gate signal; generating a time gate signal based on the high-level start time and high-level duration of the time gate signal; controlling the scanning state of the DDS and the on / off state of the digital detector based on the time gate signal; obtaining a target frequency control word based on the scanning state of the DDS; and realizing narrowband frequency time gating based on the target frequency control word. This application utilizes the DDS direct frequency synthesizer within the FPGA to achieve time gating. On one hand, the entire time gating function is implemented within the FPGA, independent of the front-end RF circuitry. This eliminates the need to configure multiple registers in the VCO of the front-end RF circuitry, simplifying the configuration interface and improving control efficiency. Furthermore, the digital circuitry does not require synchronization control with the RF circuitry, simplifying the system structure. On the other hand, as the core of the scanning implementation, the DDS has a very low and controllable lock-on delay, greatly improving the system's analysis speed. Moreover, the delay can be handled within the FPGA, further simplifying the system's control flow and enhancing the level of narrowband spectrum time gating. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the electronic device structure of the hardware operating environment involved in the embodiments of this application;

[0041] Figure 2 Here is a block diagram of a system for implementing time gating in the prior art;

[0042] Figure 3 A flowchart illustrating the narrowband spectrum time gating method based on DDS provided in this application embodiment;

[0043] Figure 4 A schematic diagram illustrating the transition of the scanning state of the DDS in the narrowband spectrum time gating method based on DDS provided in the embodiments of this application;

[0044] Figure 5 A schematic diagram illustrating the principle of DDS-based gating in the narrowband spectrum time gating method provided in this application embodiment;

[0045] Figure 6 A schematic diagram illustrating the relationship between the frequency control word FW and the time gate signal GATE in the narrowband spectrum time gating method based on DDS provided in the embodiments of this application;

[0046] Figure 7 A schematic diagram of the module structure of the DDS control module in the narrowband spectrum time gating method based on DDS provided in the embodiments of this application;

[0047] Figure 8 A schematic diagram of a narrowband spectrum time gating system based on DDS provided in an embodiment of this application;

[0048] The diagram is labeled as follows: 101-Processor, 102-Communication bus, 103-Network interface, 104-User interface, 105-Memory. Detailed Implementation

[0049] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0050] See attached document Figure 1 , attached Figure 1 This is a schematic diagram of the electronic device structure of the hardware operating environment involved in the embodiments of this application. The electronic device may include: a processor 101, such as a central processing unit (CPU), a communication bus 102, a user interface 104, a network interface 103, and a memory 105. The communication bus 102 is used to realize the connection and communication between these components. The user interface 104 may include a display screen and an input unit such as a keyboard. Optionally, the user interface 104 may also include a standard wired interface and a wireless interface. The network interface 103 may optionally include a standard wired interface and a wireless interface (such as a Wi-Fi interface). The memory 105 may be a storage device independent of the aforementioned processor 101. The memory 105 may be a high-speed random access memory (RAM) or a stable non-volatile memory (NVM), such as at least one disk storage device. The processor 101 may be a general-purpose processor, including a central processing unit, a network processor, etc., or it may be a digital signal processor, an application-specific integrated circuit, a field-programmable gate array or other programmable logic device, discrete gate or transistor logic device, or discrete hardware component.

[0051] Those skilled in the art will understand that the appendix Figure 1 The structure shown does not constitute a limitation on the electronic device and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0052] As attached Figure 1 As shown, the memory 105, which serves as a storage medium, may include an operating system, a network communication module, a user interface module, and a narrowband spectrum time gating system based on DDS.

[0053] In the appendix Figure 1 In the electronic device shown, the network interface 103 is mainly used for data communication with the network server; the user interface 104 is mainly used for data interaction with the user; the processor 101 and the memory 105 in this application can be set in the electronic device. The electronic device calls the narrowband spectrum time gating system based on DDS stored in the memory 105 through the processor 101 and executes the narrowband spectrum time gating method based on DDS provided in the embodiment of this application.

[0054] Narrowband time-division multiplexed signals refer to signals composed of multiple sub-signals with bandwidths in the tens of MHz range, superimposed and time-division multiple access (TDMA) signals, etc. General spectrum analysis of narrowband time-division multiplexed signals in modern spectrum analyzers mainly relies on the time gating function. This function allows for spectrum analysis of only specific sub-signals within the narrowband time-division multiplexed signal at a specific time. A basic implementation scheme is shown in the appendix. Figure 2 As shown, typically a 1-bit time gate signal (GATE) is first generated inside the FPGA. The start time and duration of the high level of GATE are calculated by the host computer based on the specified sub-signal characteristics and sent to the FPGA. Then, the FPGA controls the voltage-controlled oscillator (VCO) chip in the RF circuit and the digital detector in the FPGA according to the state of GATE. The VCO is only allowed to scan when GATE is high; otherwise, the local oscillator signal output by the VCO is kept at the frequency of the last scan stop. At the same time, the digital detector in the FPGA is only turned on when GATE is high; otherwise, it is turned off. That is, only the sub-signals within the high level duration of GATE are analyzed.

[0055] From the appendix Figure 2 It can be observed that the first drawback of this approach is the complexity of the control method. The GATE spans both the RF and digital circuits, and the RF circuit directly controls the fully custom-designed VCO chip. This means that when the system is working, the scanning process in the RF circuit must be synchronized with the processing process in the digital circuit. Furthermore, controlling the VCO requires configuring its internal registers, and the VCO often has multiple internal registers. For example, the existing HMC703 series VCO has as many as 21 internal registers that need to be configured. This means that whenever the GATE state goes high, the host computer must reconfigure these registers, resulting in low control efficiency and considerable inconvenience.

[0056] The second drawback of this approach is its slow response speed. This is because the RF local oscillator module, which is based on the VCO, is essentially a phase-locked loop. Before starting the scan, it must ensure that the frequency of the output local oscillator signal is stably locked at the scan start frequency. However, the VCO locking usually takes a period of time, typically several hundred milliseconds, and the locking time is uncontrollable. This means that whenever the GATE state goes high, the host computer must poll the VCO's locking flag until the VCO has been stably locked before it can start controlling the VCO scan. This creates a bottleneck in the measurement speed of narrowband time-division multiplexed signals.

[0057] Therefore, to solve the above problems, this application provides a solution that utilizes the DDS direct frequency synthesizer inside the FPGA to achieve time gating. On the one hand, the entire time gating function is implemented inside the FPGA and is not related to the front-end RF circuit. It eliminates the need to configure multiple registers in the VCO of the front-end RF circuit, simplifying the configuration interface and improving control efficiency. The digital circuit also does not need to be synchronized with the RF circuit, simplifying the system structure. On the other hand, as the core of scanning, the DDS has a very low and controllable lock-on delay, which greatly improves the system analysis speed. Furthermore, the delay can be processed inside the FPGA, further simplifying the system control flow and improving the level of narrowband spectrum time gating.

[0058] See attached document Figure 3 Based on the hardware device of the foregoing embodiments, embodiments of this application provide a narrowband spectrum time gating method based on DDS, applied to FPGA, including the following steps:

[0059] S10: Receive and store the calculation parameters from the host computer; wherein, the calculation parameters include the frequency control word corresponding to the start frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal.

[0060] In the specific implementation process, when the system starts working, the host computer first calculates the four parameters required for this narrowband time gating analysis: the frequency control word FW0 corresponding to the starting frequency f, the scan slope k, the high-level start time of the time gate signal gate_dly, and the high-level duration of the time gate signal gate_len. Specifically, based on the analysis center frequency, scan time, and SPAN specified by the user, the values ​​of FW0 and k corresponding to this scan are calculated. Based on the narrowband time-division multiplexing sub-signal characteristics specified by the user, the values ​​of gate_dly and gate_len corresponding to this scan are calculated. Then, the host computer sends these four parameters to the parameter configuration module in the FPGA for storage and starts the analysis. Since there are only four calculation parameters, the number of registers that need to be configured is greatly reduced. In this application, only four registers need to be configured, and each register receives and stores one calculation parameter. That is, before receiving and storing the calculation parameters from the host computer, the method also includes:

[0061] Configure multiple registers;

[0062] Receive and store calculation parameters from the host computer, including:

[0063] Based on the configured multiple registers, a calculation parameter from the host computer is received and stored respectively.

[0064] S20: Generate a time gate signal based on the start time of the high level of the time gate signal and the duration of the high level of the time gate signal.

[0065] In practice, the GATE generation module generates a GATE based on the stored values ​​of gate_dly and gate_len, thereby controlling the scanning state of the direct frequency synthesizer (DDS) and the on / off state of the digital detector.

[0066] S30: Controls the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal.

[0067] In the specific implementation process, the DDS (specifically the frequency control word of the DDS) and the digital detector are controlled according to the state of the GATE. The DDS is only allowed to scan when the GATE is high; otherwise, the signal output by the DDS is kept at the frequency when the last scan was stopped. At the same time, the digital detector in the FPGA is only turned on when the GATE is high; otherwise, it is turned off.

[0068] The logic for controlling the scanning state of the DDS and the on / off state of the digital detector can be abstracted as a state machine. This machine controls the switching of the DDS scanning state between different states; that is, it controls the scanning state of the DDS and the on / off state of the digital detector based on time gate signals, including:

[0069] Based on the time gate signal, the scanning state of the DDS is controlled to switch between different states, and the digital detector is turned on and off.

[0070] The DDS scan states include three states: first state, second state, and third state. The state transitions are shown in the attached figure. Figure 4 As shown, specifically: based on the time gate signal, the scanning state of the DDS is switched between different states, and the digital detector is switched on and off, including:

[0071] The scanning state of the DDS is switched from the first state to the second state based on the arrival of the scan start pulse;

[0072] Once the count of the high-level start time of the time gate signal is full, the time gate signal is pulled high, and the count of the high-level duration of the time gate signal begins.

[0073] Once the high-level duration of the time gate signal is full, the time gate signal is pulled low. Then, depending on whether the number of detected data output by the digital detector matches the number required by the host computer, the system jumps to the third or first state until the scan end pulse arrives.

[0074] In the specific implementation process, in the IDLE state (the first state), the module waits for the scan start pulse from the host computer. When the scan start pulse arrives, it jumps to the GEN state (the second state). In the GEN state, the module first counts the value of gate_dly. When the count is full, it pulls GATE high and starts counting the value of gate_len. When the count is full, it pulls GATE low, completing one generation of a high-level GATE. At the same time, GATE is output to the DDS control module and the digital detector. If the number of detected data output by the digital detector is equal to the number required by the host computer, it jumps to the DONE state (the third state). Otherwise, it jumps back to the IDLE state to continue the next generation of GATE. In the DONE state, the module waits for the scan end pulse from the host computer. When the scan end pulse arrives, it jumps back to the IDLE state, thus completing one scan.

[0075] S40: Obtain the target frequency control word based on the DDS scanning status.

[0076] In practical implementation, this application uses the DDS (Direct Frequency Synthesizer) inside the FPGA to replace the VCO for gating. In narrowband systems, this scheme is very simple to control, with a very short and controllable lock-in time, thus offering advantages such as fast response speed and high control efficiency. Its implementation principle is shown in the attached figure. Figure 5 As shown, by appendix Figure 5As can be seen, the entire time gating function is implemented internally within the FPGA and is independent of the front-end RF circuitry. Therefore, the digital circuitry does not need to be synchronized with the RF circuitry. In the original scheme, the DDS was only used to generate a fixed-frequency single-tone signal with the same frequency as the narrowband intermediate frequency signal to achieve down-conversion. However, in this scheme, the output of the DDS is no longer a single-tone signal but a scanning signal similar to a linear frequency modulation (LFM) signal. The FPGA needs to control the DDS to scan, and the scanning bandwidth is the display width (SPAN) for this spectrum analysis. The gate is still generated internally within the FPGA. The mathematical principle is as follows:

[0077] Let the starting frequency of the scan signal output by the DDS be f, the scan slope be k, and the time be t. For ease of description, assume that the gate has only one high level, with the rise time and fall time being ta and tb respectively, and j being the imaginary unit. Then, under the time gating function, the scan signal N output by the DDS can be expressed as:

[0078]

[0079] According to equation (1), N is divided into a piecewise function by the high level of GATE. During the duration of the high level of GATE, N is a linear frequency modulation function, and at other times it is a constant. The constant value is the last function value of the previous linear frequency modulation function. This conclusion also applies when GATE has multiple high levels.

[0080] According to digital signal processing theory, the frequency of the output signal N of the DDS at a certain moment is uniquely determined by the frequency control word at that moment. Let the frequency control word of the DDS be FW, and the frequency control word corresponding to the initial frequency f be FW0. Then, the floating-point expression of FW can be written from equation (1):

[0081]

[0082] Equation (2) above proves from a mathematical perspective that as long as FW can be controlled to increment only when GATE is high, N can be controlled to satisfy equation (1), thereby realizing the narrowband time gating function based on DDS. According to equation (2), the relationship between the frequency control word FW and the time gate signal GATE can be plotted as shown in the appendix. Figure 6 As shown.

[0083] Based on the aforementioned theoretical foundation, in order to achieve time gating, the target frequency control word is obtained according to the scanning state of the DDS, including:

[0084] The state of the gate signal is obtained based on the scan state of the DDS;

[0085] Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is changed to obtain the target frequency control word.

[0086] In the specific implementation process, the frequency control word of the DDS is incremented or held based on the values ​​of FW0 and k, as well as the state of GATE. That is, the frequency control word of the DDS is changed according to the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scan slope to obtain the target frequency control word, including:

[0087] Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is controlled to increment or remain constant until the scanning is completed and the target frequency control word is obtained.

[0088] The DDS control module internally includes a DDS circuit, a counter, a multiplier, and an adder, all implemented using sequential logic. Its module structure is shown in the attached figure. Figure 7 As shown, when GATE is high, the counter increments by 1 with each clock cycle. The output value of the counter is multiplied by the k sent by the host computer and then added to FW0 to complete the increment calculation of the frequency control word FW. When GATE is low, the counter stops incrementing and retains the last value of the previous increment. At this time, FW will also retain the last value of the previous increment. Inputting FW into the DDS circuit can complete the digital circuit implementation of the principle represented by equations (1) and (2), thereby realizing the entire narrowband time gating function, i.e., step S50: realize the narrowband frequency time gating according to the target frequency control word.

[0089] In this embodiment, time gating is achieved by utilizing the DDS direct frequency synthesizer inside the FPGA. On the one hand, the entire time gating function is implemented inside the FPGA and is not related to the front-end RF circuit. This eliminates the need to configure multiple registers in the VCO of the front-end RF circuit, simplifying the configuration interface and improving control efficiency. The digital circuit also does not need to be synchronized with the RF circuit, simplifying the system structure. On the other hand, as the core of scanning, the DDS has a very low and controllable lock-on delay, which greatly improves the system's analysis speed. Furthermore, the delay can be processed inside the FPGA, further simplifying the system's control flow and improving the level of narrowband spectrum time gating.

[0090] See attached document Figure 8 Based on the same inventive concept as in the foregoing embodiments, this application also provides a narrowband spectrum time gating system based on DDS, applied to an FPGA, comprising:

[0091] The parameter configuration module is used to receive and store calculation parameters from the host computer; among which, the calculation parameters include the frequency control word corresponding to the starting frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal;

[0092] The GATE generation module is used to generate a time gate signal based on the high-level start time and high-level duration of the time gate signal.

[0093] The DDS control module is used to control the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal, obtain the target frequency control word according to the scanning state of the DDS, and realize narrowband frequency time gating according to the target frequency control word.

[0094] Those skilled in the art should understand that the division of the various modules in the embodiments is merely a logical functional division. In actual applications, they can be fully or partially integrated onto one or more actual carriers. These modules can be implemented entirely in software through processing unit calls, entirely in hardware, or a combination of software and hardware. It should be noted that in this embodiment, each module in the DDS-based narrowband spectrum time gating system corresponds one-to-one with each step in the DDS-based narrowband spectrum time gating method in the aforementioned embodiments. Therefore, the specific implementation of this embodiment can refer to the implementation of the aforementioned DDS-based narrowband spectrum time gating method, which will not be repeated here.

[0095] Based on the same inventive concept as in the foregoing embodiments, embodiments of this application also provide a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the narrowband spectrum time gating method based on DDS as provided in the embodiments of this application.

[0096] Based on the same inventive concept as in the foregoing embodiments, embodiments of this application also provide an electronic device, including a processor and a memory, wherein,

[0097] Memory is used to store computer programs;

[0098] The processor is used to load and execute computer programs to enable electronic devices to perform the narrowband spectrum time gating method based on DDS as provided in the embodiments of this application.

[0099] In some embodiments, the computer-readable storage medium may be a memory such as FRAM, ROM, PROM, EPROM, EEPROM, flash memory, magnetic surface memory, optical disk, or CD-ROM; or it may be a device including one or any combination of the above-mentioned memories. The computer may be a variety of computing devices, including smart terminals and servers.

[0100] In some embodiments, executable instructions may take the form of a program, software, software module, script, or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a standalone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0101] As an example, executable instructions may, but do not necessarily, correspond to files in the file system. They may be stored as part of a file that holds other programs or data, for example, in one or more scripts in a Hyper Text Markup Language (HTML) document, in a single file dedicated to the program in question, or in multiple collaborative files (e.g., a file that stores one or more modules, subroutines, or code sections).

[0102] As an example, executable instructions can be deployed to execute on a single computing device, or on multiple computing devices located in one location, or on multiple computing devices distributed across multiple locations and interconnected via a communication network.

[0103] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0104] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as read-only memory / random access memory, magnetic disk, optical disk) and includes several instructions to cause a multimedia terminal device (which may be a mobile phone, computer, television receiver, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0106] In summary, this application provides a narrowband spectrum time gating method, system, medium, and device based on DDS. The method includes: receiving and storing calculation parameters from a host computer; wherein the calculation parameters include a frequency control word corresponding to the starting frequency, a scanning slope, a high-level start time of the time gate signal, and a high-level duration of the time gate signal; generating a time gate signal based on the high-level start time and high-level duration of the time gate signal; controlling the scanning state of the DDS and the on / off state of the digital detector based on the time gate signal; obtaining a target frequency control word based on the scanning state of the DDS; and realizing narrowband frequency time gating based on the target frequency control word. This application utilizes the DDS direct frequency synthesizer within the FPGA to achieve time gating. On one hand, the entire time gating function is implemented within the FPGA, independent of the front-end RF circuitry. This eliminates the need to configure multiple registers in the VCO of the front-end RF circuitry, simplifying the configuration interface and improving control efficiency. Furthermore, the digital circuitry does not require synchronization control with the RF circuitry, simplifying the system structure. On the other hand, as the core of the scanning implementation, the DDS has a very low and controllable lock-on delay, greatly improving the system's analysis speed. Moreover, the delay can be handled within the FPGA, further simplifying the system's control flow and enhancing the level of narrowband spectrum time gating.

[0107] The above description is only a preferred embodiment of this application and is not intended to limit this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A narrowband spectral time gating method based on DDS, characterized in that, When applied to FPGAs, the following steps are included: Receive and store calculation parameters from the host computer; wherein, the calculation parameters include the frequency control word corresponding to the starting frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal; A time gate signal is generated based on the high-level start time and the high-level duration of the time gate signal; Based on the time gate signal, the scanning state of the DDS and the on / off state of the digital detector are controlled; the control of the scanning state of the DDS and the on / off state of the digital detector based on the time gate signal includes: Based on the time gate signal, the scanning state of the DDS is controlled to switch between different states and the digital detector is turned on and off. The step of controlling the switching of the DDS scanning state between different states and the on / off state of the digital detector according to the time gate signal includes: The scanning state of the DDS is controlled to switch from the first state to the second state according to the arrival of the scan start pulse; wherein, the first state is the IDLE state and the second state is the GEN state; Once the count of the high-level start time of the time gate signal is full, the time gate signal is pulled high, and the count of the high-level duration of the time gate signal begins. The time gate signal is pulled low after the high-level duration of the time gate signal is counted to full. Then, the signal jumps to the third state or the first state depending on whether the number of detected data output by the digital detector matches the number required by the host computer, until the scan end pulse arrives. The third state is the DONE state. Based on the scanning state of the DDS, a target frequency control word is obtained; the process of obtaining the target frequency control word based on the scanning state of the DDS includes: The state of the gate signal is obtained based on the scan state of the DDS; Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is controlled to change to obtain the target frequency control word; Narrowband frequency time gating is achieved based on the target frequency control word.

2. The narrowband spectrum time gating method based on DDS according to claim 1, characterized in that, The step of controlling the frequency control word of the DDS to change according to the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scan slope to obtain the target frequency control word includes: Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is controlled to increment or remain constant until the scanning is completed and the target frequency control word is obtained.

3. The narrowband spectrum time gating method based on DDS according to claim 2, characterized in that, The incrementing or holding of the frequency control word controlling the DDS includes: When the gate signal is high, the frequency control word of the DDS is incremented by summing the product of the counter's incremented output value and the scan slope with the frequency control word corresponding to the starting frequency. When the gate signal is low, the frequency control word of the DDS is kept at the last output value calculated in the previous increment, based on the previous auto-increment output value of the counter.

4. The narrowband spectrum time gating method based on DDS according to claim 1, characterized in that, Before receiving and storing the calculation parameters from the host computer, the method further includes: Configure multiple registers; The receiving and storing of calculation parameters from the host computer includes: Each of the configured registers receives and stores a calculation parameter from the host computer.

5. A narrowband spectrum time gating system based on DDS, characterized in that, Applied to FPGAs, including: The parameter configuration module is used to receive and store calculation parameters from the host computer; wherein, the calculation parameters include the frequency control word corresponding to the start frequency, the scan slope, the high-level start time of the time gate signal, and the high-level duration of the time gate signal; The GATE generation module is used to generate a time gate signal based on the high-level start time and the high-level duration of the time gate signal. The DDS control module is used to control the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal, obtain the target frequency control word according to the scanning state of the DDS, and realize narrowband frequency time gating according to the target frequency control word; the step of controlling the scanning state of the DDS and the on / off state of the digital detector according to the time gate signal includes: Based on the time gate signal, the scanning state of the DDS is controlled to switch between different states and the digital detector is turned on and off. The step of controlling the switching of the DDS scanning state between different states and the on / off state of the digital detector according to the time gate signal includes: The scanning state of the DDS is controlled to switch from the first state to the second state according to the arrival of the scan start pulse; wherein, the first state is the IDLE state and the second state is the GEN state; Once the count of the high-level start time of the time gate signal is full, the time gate signal is pulled high, and the count of the high-level duration of the time gate signal begins. The time gate signal is pulled low after the high-level duration of the time gate signal is counted to full. Then, the signal jumps to the third state or the first state depending on whether the number of detected data output by the digital detector matches the number required by the host computer, until the scan end pulse arrives. The third state is the DONE state. The step of obtaining the target frequency control word based on the scanning state of the DDS includes: The state of the gate signal is obtained based on the scan state of the DDS; Based on the state of the gate signal, the frequency control word corresponding to the starting frequency, and the scanning slope, the frequency control word of the DDS is controlled to change, thereby obtaining the target frequency control word.

6. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is loaded and executed by the processor, it implements the narrowband spectrum time gating method based on DDS as described in any one of claims 1-4.

7. An electronic device, characterized in that, Including processor and memory, among which, The memory is used to store computer programs; The processor is used to load and execute the computer program to cause the electronic device to perform the narrowband spectrum time gating method based on DDS as described in any one of claims 1-4.

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