Slope signal generation circuit, control method thereof, image sensor, and electronic device

Abstract

The application discloses a slope signal generation circuit and a control method thereof, an image sensor and an electronic device, and relates to the field of image sensor chip design. The slope signal generation circuit comprises: a current source array comprising a plurality of array basic units arranged in m rows and n columns; a logic control module comprising a row-column total control module, a row control module and a column control module connected with the row-column total control module; an output end of the column control module is connected with an input end of the row control module; the column control module comprises a logic operation gate and a plurality of column control units, each column control unit comprises a column flip-flop, and a plurality of column flip-flops are connected in sequence to form a shift register chain; an output end of the logic operation gate is connected with a first column flip-flop of the shift register chain, a first input end of the logic operation gate is used for inputting an initial level signal, and a second input end of the logic operation gate is connected with a feedback node; and the slope signal can be efficiently and reliably generated.

Description

Technical Field

[0001] This application relates to the field of image sensor chip design, and in particular to a ramp signal generation circuit and its control method, an image sensor, and an electronic device. Background Technology

[0002] In an image sensor (CIS) chip, a ramp circuit (RAMP) is used to generate a ramp signal with good linearity (the slope remains constant during the ramp descent). This ramp signal serves as a metric for the Chip-On-Lock and DC Characteristics (COLADC) module to quantize the pixel signal.

[0003] In traditional ramp circuits, the control logic for the current source array uses a row-column scanning method: the current sources are arranged in an array and controlled through both row and column dimensions. The row control signal selects each row of the array at a time, while all rows share the same set of column signals. Therefore, the traditional control timing for the current source array is as follows: first, the row selection signal for the first row of the current source array is enabled; then, the column selection signals are generated sequentially based on the clock frequency (control pulse shifting). During this process, the unit current sources in the first row switch their differential current outputs sequentially. After the last column selection signal is generated, the row selection signal acting on the first row must immediately become invalid. Simultaneously, before the last column selection signal becomes invalid and the first column selection signal of the new round arrives, the row selection signal for the next row must be established. This process continues until all unit current sources have been traversed, completing the ramp signal generation. The column control signal generation circuit is the fastest node in the ramp signal generation circuit. Furthermore, a frequency divider is needed to generate the row control signal from the column clock.

[0004] The aforementioned ramp signal generation and control strategy is designed for low-frame-rate, low-resolution CIS chips, enabling better ramp generation in CIS chips with low readout circuit operating frequencies. There is a negative correlation between operating frequency and clock cycle. As the performance requirements of CIS chips increase, their operating frequencies rise, resulting in shorter clock cycles. Consequently, the effective pulse width of the column control signal (column select signal) in the ramp signal generation circuit gradually narrows (because the column pulse width is equal to half the CIS chip's clock cycle). This places higher demands on the synchronous flip-flops in the column control signal generation circuit. Secondly, since the switching of the row control signal needs to occur within the interval between the failure of the last column control signal in the current row and the activation of the first column control signal in the next row, which is also half the corresponding clock cycle of the operating frequency, this interval becomes increasingly narrower with increasing operating frequency, posing a challenge to the speed of row logic switching. If the row control signal cannot switch within half a clock cycle, the ramp signal descent will be discontinuous, ultimately leading to inconsistent ramp LSBs and affecting the linearity of the ramp signal. On the other hand, since current source arrays typically operate in the analog voltage domain to obtain sufficient voltage margin and more consistent, controllable device performance, while high-speed row and column control signals are generated in the digital voltage domain, the row and column control signals need to be boosted by a level shifter stage before finally controlling the switching of the unit current source from the low-voltage domain to the high-voltage domain. The positive feedback structure of the level shifter stage determines its limited high-speed performance and the inconsistency of rise and fall edges, becoming a major bottleneck for the high-frequency ramp signal generation circuit: the column control signal gradually narrows with the working clock cycle, and the level shifter stage (boost module) cannot boost the narrow low-voltage column pulse in a short time interval, causing the high-voltage column control signal that actually triggers the current source switching to become a straight line without a control pulse, ultimately leading to the failure of ramp signal generation. Finally, the clock of the row control signal is generated from the column control clock by a frequency divider. The 2^N frequency divider circuit limits the row-to-column ratio of the current source array. Introducing other types of frequency dividers will cause area and power consumption overhead, and the row and column delay introduced by the frequency divider will make it difficult for the row control signal to switch within half a clock cycle. It is evident that current ramp signal generation circuits suffer from several drawbacks. At high operating frequencies, the pulse duration is too short, causing the boost module to fail to boost voltage properly and the latch to fail to switch correctly, resulting in an inefficient and unreliable ramp signal generation. Furthermore, the introduction of a frequency divider leads to high hardware and power consumption costs. Summary of the Invention

[0005] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a ramp signal generation circuit and its control method, an image sensor, and an electronic device, which can generate ramp signals efficiently and reliably, and can reduce the hardware cost and power consumption cost of the ramp signal generation circuit.

[0006] In a first aspect, embodiments of this application provide a ramp signal generation circuit, including:

[0007] The current source array comprises multiple array basic units arranged in m rows and n columns;

[0008] The logic control module includes: a row and column overall control module, a row control module and a column control module connected to the output of the row and column overall control module; the output of the column control module is connected to the input of the row control module.

[0009] The row control module is used to control each row of the array base unit;

[0010] The column control module includes logic gates and multiple column control units. Each column control unit controls one column of the array base units. Each column control unit includes a column flip-flop, and multiple column flip-flops are connected in sequence to form a shift register chain. The output of the logic gate is connected to the first column flip-flop in the shift register chain. The first input of the logic gate is used to input an initial level signal, and the second input of the logic gate is connected to a feedback node, which refers to the output of a selected column flip-flop in the shift register chain.

[0011] The logic control module is used to: perform logical operations and step-by-step shifting processing on the received initial level signal and the feedback signal returned by the feedback node through the column control module to obtain multiple column control signals generated in sequence; generate row control signals based on the column control signals through the row control module based on the odd and even row signal switching logic; and generate ramp signals by controlling the current source array according to the column control signals and the row control signals.

[0012] Secondly, this application provides a control method for a ramp signal generation circuit, applied to the logic control module of the ramp signal generation circuit as described in the first aspect embodiment. The ramp signal generation circuit further includes a current source array and a logic control module. The logic control module includes a row and column control module, a row control module connected to the output of the row and column control module, and a column control module. The output of the column control module is connected to the input of the row control module. The row control module controls each row of the array base units. The column control module includes logic gates and multiple column control units, each column control unit controlling one column of the array base units. Each column control unit includes a column flip-flop, and multiple column flip-flops are sequentially connected to form a shift register chain. The output of the logic gate is connected to the first column flip-flop in the shift register chain. The first input of the logic gate is used to input an initial level signal, and the second input of the logic gate is connected to a feedback node, which refers to the output of a selected column flip-flop in the shift register chain.

[0013] The control method includes:

[0014] The column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node to obtain multiple column control signals generated in sequence.

[0015] Based on the odd-even row signal switching logic, the row control module generates a row control signal based on the column control signal, and generates a ramp signal by controlling the current source array according to the column control signal and the row control signal.

[0016] Thirdly, embodiments of this application provide an image sensor, including the ramp signal generation circuit as described in the first aspect embodiment.

[0017] Fourthly, embodiments of this application provide an electronic device including an image sensor as described in the third aspect embodiment.

[0018] The embodiments of this application include:

[0019] A ramp signal generation circuit includes: a current source array and a logic control module; wherein, the current source array includes multiple array base units arranged in m rows and n columns; the logic control module includes: a row and column master control module, a row control module and a column control module connected to the output of the row and column master control module; the output of the column control module is connected to the input of the row control module; the row control module is used to control each row array base unit; the column control module includes logic gates and multiple column control units, each column control unit is used to control one column array base unit; each column control unit includes a column flip-flop, and multiple column flip-flops are connected in sequence to form a shift register chain; the output of the logic gate is connected to the first column flip-flop in the shift register chain, the first input of the logic gate is used to input an initial level signal, and the second input of the logic gate is connected to a feedback node, which refers to the output of a selected column flip-flop in the shift register chain; in the ramp signal... When the generation circuit is working, in the logic control module, firstly, the column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node, resulting in multiple column control signals generated in sequence. The width of the column control signal can be flexibly changed by selecting different feedback nodes in the shift register chain, increasing the time margin of column control and ensuring efficient and reliable generation of the ramp signal. Then, based on the odd / even row signal switching logic, the row control module generates row control signals based on the column control signals. The ramp signal is generated by controlling the current source array according to the column and row control signals. Thus, without using a frequency divider, the generation of row control signals based on column control signals reduces the hardware and power consumption costs of the ramp signal generation circuit. In other words, the embodiments of this application can generate ramp signals efficiently and reliably, and can reduce the hardware and power consumption costs of the ramp signal generation circuit.

[0020] Other features and advantages of this application will be set forth in the following description and will be apparent in part from the description or may be learned by practicing the application. The objectives and other advantages of this application may be realized and obtained by means of the structures particularly pointed out in the description and the accompanying drawings. Attached Figure Description

[0021] Figure 1 This is a control timing diagram of a traditional ramp signal generation circuit;

[0022] Figure 2 This is a schematic diagram of the ramp signal generation circuit provided in one embodiment of this application;

[0023] Figure 3 This is a schematic diagram of the logic function of a logic gate provided in one embodiment of this application;

[0024] Figure 4This is a schematic diagram of the modular structure of an array base unit provided in one embodiment of this application;

[0025] Figure 5 This is a schematic diagram of the module structure of a column control unit provided in one embodiment of this application;

[0026] Figure 6 This is a schematic diagram of the module structure of a row control unit provided in one embodiment of this application;

[0027] Figure 7 This is a schematic diagram of the specific module connection of the logic control module provided in one embodiment of this application;

[0028] Figure 8 This is a schematic diagram showing the connection relationship between logic gates, shift register chain, and first level shift module in a logic control module provided in one embodiment of this application;

[0029] Figure 9 This is a schematic diagram of the overall module of a ramp generation circuit according to one embodiment of this application;

[0030] Figure 10 This is a schematic flowchart of a control method for a ramp signal generation circuit provided in one embodiment of this application;

[0031] Figure 11 This is a schematic diagram of the control timing of the logic control module in a ramp signal generation circuit provided in one embodiment of this application. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments.

[0033] It should be noted that although a logical order is shown in the flowcharts in this application, in some cases, the steps shown or described may be performed in a different order than that shown in the flowcharts. In the description of this application, "several" means one or more, and "more" means two or more. The terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of technical features indicated, or implicitly indicating the order in which the technical features are indicated.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0035] First, let me explain some of the terms used in this application:

[0036] Total slope voltage range: The maximum range of the slope signal from the initial voltage to the final voltage, which is the maximum input voltage range that the ADC can measure.

[0037] Ramp voltage per LSB: LSB (Least Significant Bit): This is the voltage value represented by the least significant bit of the digital output code. It represents the smallest voltage change that the ADC can resolve, directly determining the ADC's accuracy.

[0038] In image sensor (CIS) chips, the ramp circuit (RAMP) is used to generate a ramp signal with good linearity (the slope remains constant during the ramp descent). This ramp signal serves as a metric, and the ramp signal, acting as the metric for a column analog-to-digital converter (COLADC), quantizes the pixel signal. Typically, the ramp circuit in an image sensor (CIS) chip is based on the principle of a current-driven DAC (digital-to-analog converter): according to Ohm's law V (voltage) = I (current) * R (resistance), it uses a current source array with variable total output current and a resistor array with variable total resistance to achieve a ramp signal with variable slope and descent range. A general-purpose current-driven DAC can flexibly adjust the output current based on the input digital code, switching between two differential output paths. In other words, the DAC's input digital code is a mapping of the actual analog output, and there are countless combinations depending on the application requirements. The output of the ramp circuit is a fixed-mode signal, so it does not require a multi-bit digital input port. It only needs to generate a control code with a fixed transformation mode through the internal control module under the control of the working clock.

[0039] In traditional ramp circuits, the control logic for current source arrays employs a row-column scanning method: current sources are arranged in an array and controlled through both row and column dimensions. The row control signal selects each row at a time, while all rows share the same set of column signals. The latch within a single current source only changes its differential output path when both its corresponding column and row signals are simultaneously valid, maintaining this state throughout the subsequent ramp signal generation process until the overall reset or set signal of the ramp circuit arrives. Therefore, the traditional control timing for a current source array is as follows: First, the row selection signal of the first row of the current source array is made valid; then, the column selection signals are generated sequentially based on the clock frequency (control pulse shifting). During this process, the unit current sources in the first row switch their differential current outputs sequentially. After the last column selection signal is generated, the row selection signal acting on the first row must immediately become invalid; simultaneously, before the last column selection signal becomes invalid and the first column selection signal of the new round arrives, the row selection signal for the next row must be established. This process continues until all unit current sources have been traversed, completing the ramp signal generation. The traditional control timing for a current source array is as follows: Figure 1 As shown, for a 16-column array, the column control signals (COLUMN0~COLUMN15) are triggered sequentially and cyclically under the control of the rising edge of the master clock signal MAIN CLK (it can also be designed as a falling edge, but this is only a reference example of one implementation method). The column width of each column control signal is half a cycle of the master clock signal MAIN CLK; the row control signals (ROW0, ROW1...) are generated before the first column control signal COLUMN0 is valid, and disappear after the last column control signal COLUMN15 is invalidated and before the next first column control signal COLUMN0 is valid. Figure 1 (Only two ROW control signals are shown as examples). Assuming there are 32 row control signals, the ramp generation array has a total of 32 * 16 = 512 unit current sources. The ramp signal has 9-bit precision. The voltage per LSB of the ramp signal and the total ramp voltage drop range are determined by the size of the unit current sources and the resistor array, which is determined by the actual requirements of the CIS chip. From the above control method, it can be seen that the row control signal period is a division of the column control signal: for example, in a 16-column * 32-row array, the generation frequency of the row control signal is 16 times the generation frequency of the column control signal. The column control signal generation circuit is the fastest node in the ramp signal generation circuit. Furthermore, a frequency divider is needed to generate the row control signal from the column clock.

[0040] The aforementioned ramp signal generation and control strategy is designed for low-frame-rate, low-resolution CIS chips, enabling better ramp generation in CIS chips with low readout circuit operating frequencies. There is a negative correlation between operating frequency and clock cycle. As the performance requirements of CIS chips increase, their operating frequencies rise, resulting in shorter clock cycles. Consequently, the effective pulse width of the column control signal (column select signal) in the ramp signal generation circuit gradually narrows (because the column pulse width is equal to half the CIS chip's clock cycle). This places higher demands on the synchronous triggers in the column control signal generation circuit. Furthermore, since the switching of row control signals needs to occur within the interval between the failure of the last column control signal in the current row and the activation of the first column control signal in the next row, the... Figure 1 It is known that this interval is also half a cycle wide of the operating frequency. As the operating frequency increases, this interval becomes narrower and narrower, posing a challenge to the speed of row logic switching. If the row control signal cannot complete the switching within half a clock cycle, the ramp signal descent will become discontinuous: the simultaneous switching of two current sources or the ramp descent pauses, both of which are nonlinearities, ultimately leading to inconsistent ramp LSBs and affecting the linearity of the ramp signal. On the other hand, since current source arrays typically operate in the analog voltage domain to obtain sufficient voltage margin and more consistent and controllable device performance, while high-speed row and column control signals are generated based on the digital voltage domain, the row and column control signals need to be boosted by a level shift stage (Levelshift module) from the low voltage domain to the high voltage domain before finally controlling the switching of the unit current source. The positive feedback structure of the level shift stage limits its high-speed performance and causes inconsistencies in rise and fall edges, becoming a major bottleneck for high-frequency ramp signal generation circuits. As the column control signal narrows with the operating clock cycle, the level shift stage (Levelshift module) cannot boost the narrow low-voltage column pulse within a short time interval. This results in the high-voltage column control signal, which actually triggers current source switching, becoming a straight line with no control pulse, ultimately leading to ramp signal generation failure. Finally, the row control signal clock is generated from the column control clock using a frequency divider. The 2^N frequency divider limits the row-to-column ratio of the current source array. Introducing other types of frequency dividers would incur area and power consumption overhead, and the row and column delays introduced by the frequency divider would make it difficult for the row control signal to switch within half a clock cycle. Therefore, current ramp signal generation circuits suffer from problems such as excessively short column pulse duration at high operating frequencies, preventing the boost module from boosting properly and the latch from switching correctly, thus hindering efficient and reliable ramp signal generation. Furthermore, the introduction of frequency dividers increases hardware and power costs.

[0041] The embodiments of this application will be further described below with reference to the accompanying drawings.

[0042] Firstly, combining Figure 2 and Figure 8As shown in the figure, this application embodiment provides a ramp signal generation circuit 1000, including: a current source array 100 and a logic control module 200. The specific structure and connection relationship of the current source array 100 and the logic control module 200 are further described below.

[0043] The current source array 100 includes multiple array base units 110 arranged in m rows and n columns.

[0044] The logic control module 200 includes: a row and column master control module 230, a row control module 210 and a column control module 220 connected to the output of the row and column master control module 230; the output of the column control module 220 is connected to the input of the row control module 210. The row control module 210 is used to control each row array base unit 110. The column control module 220 includes logic gates 221 and multiple column control units 222, each column control unit 222 is used to control one column array base unit 110; each column control unit 222 includes a column flip-flop 2221, and multiple column flip-flops 2221 are connected in sequence to form a shift register chain; the output of the logic gate 221 is connected to the first column flip-flop 2221 in the shift register chain, the first input of the logic gate 221 is used to input an initial level signal, and the second input of the logic gate 221 is connected to a feedback node, which refers to the output of a selected column flip-flop 2221 in the shift register chain.

[0045] Specifically, Figure 2 In this diagram, P00 represents the array base unit 110 in row 0 and column 0; B0 represents the column control unit 222 in column 0 (i.e., the first column); and A0 represents the row control unit 211 in row 0 (i.e., the first row).

[0046] It should be emphasized that the logic control module 200 is used to: perform logical operations and step-by-step shifting processing on the received initial level signal and the feedback signal returned by the feedback node through the column control module 220 to obtain multiple column control signals generated in sequence; generate row control signals based on the column control signals through the row control module 210; and perform control processing on the current source array 100 based on the odd-even row signal switching logic according to the column control signals and the row control signals to generate ramp signals.

[0047] like Figure 3 As shown, specifically, logic gate 221 is a NOR gate. The NOR gate performs a NOR operation on the input feedback signal and the initial level signal. After processing by the NOR gate, a column pulse signal of the required width is generated.

[0048] Specifically, the logical expression of the NOR gate is: Y = A NOR B. The NOR operation means: first, perform an OR operation on the input signal A and the input signal B, and then perform a NOT operation on the result of the OR operation to obtain the NOR result Y (which is a pulse signal in this application).

[0049] Specifically, logic gate 221 is used to feed back the positive output (a step signal from 0 to 1) of a subsequent column of flip-flops to the NOR gate before the first column. The other end of the NOR gate is an initial level signal (a step signal from 1 to 0; when the feedback signal arrives, the initial signal is 0, and after the NOR operation, a pulse is generated to circulate in the column flip-flop 2221 chain (i.e., the shift register chain). The positive output of a certain column of flip-flops is the feedback node of this application.

[0050] like Figure 4 As shown, according to some embodiments of this application, each array base unit 110 includes a unit latch 111 and a unit differential current source 112 connected in sequence. Specifically, the input terminal of the unit latch 111 is connected to the output terminals of the column control unit 222 and the row control unit 211; the unit latch 111 is used to switch its operating state under the control of the row control signal and the column control signal; the unit differential current source 112 includes a positive output terminal and a negative output terminal, and the unit differential current source 112 is used to determine the target output current from the positive output terminal and the negative output terminal according to the output terminal control signal output by the unit latch 111.

[0051] It should be noted that in the current source array 100, the unit differential current source 112 can flow current through two output terminals (i.e., positive output terminal and negative output terminal). The output terminal control signal output by the unit latch 111 (the value of the output terminal control signal is 0 or 1) switches the positive output terminal or the negative output terminal as the target output terminal, thereby controlling the unit differential current source 112 to output current from the target output terminal.

[0052] like Figure 5 As shown, according to some embodiments of this application, each column control unit 222 further includes: a column buffer 2222, a first level shift module 2223 and a column output buffer stage 2224. The input terminal of the first level shift module 2223 is connected to the output terminal of the column trigger 2221, and the output terminal of the first level shift module 2223 is used to output the generated column control signal to the corresponding column array base unit 110.

[0053] like Figure 6As shown, according to some embodiments of this application, the row control module 210 includes a plurality of row control units 211, each row control unit 211 being used to control a row array base unit 110; the row control unit 211 includes: a data selector, a row trigger, a row buffer, a second level shift module, and a row output buffer stage connected in sequence.

[0054] For example, combined with Figure 7 The logic control module 200 is further described below. The logic control module 200 includes: a row / column master control module 230, a row control module 210, and a column control module 220. The connection relationships between the row / column master control module 230, the row control module 210, and the column control module 220 in the logic control module 200 are as follows: Figure 7 As shown.

[0055] Specifically, the line control module 210 has seven input terminals and four output terminals; the seven input terminals of the line control module 210 are respectively used to input: ramp resolution selection signal (RESOLUTION_SEL), even half-line trigger signal (EVENROW_TRIG), odd half-line trigger signal (ODDROW_TRIG), ramp change enable signal (ROW_ENABLE), ramp reset signal (RST_ROW), ramp set enable signal (SET_RAMP_EN), and ramp set amount setting signal (SET_RAMP). <a:0>). The four outputs of the line control module 210 respectively output: an odd row setting signal (ODD_SET<Y:0), an even row setting signal (EVEN_SET <y:0>), Odd Behavior Control Signal (ODDROW <y:0>), even row control signal (EVENROW) <y:0>).

[0056] Specifically, the column control module 220 has three input terminals and three output terminals; the three input terminals of the column control module 220 are used to input: a ramp change working clock signal (COL_CLK), a ramp change enable signal (COL_ENABLE), and a ramp reset signal (RST_COL); the three output terminals of the column control module 220 output: a column control signal (COL_CLK). <x:0>Even half-line trigger signal (TRIG_EVENROW), odd half-line trigger signal (TRIG_ODDROW), and ramp resolution selection signal (RESOLUTION_SELIN).

[0057] Specifically, the row and column control module 230 provides unified management, buffering, and buck-boosting operations for a series of control logic signals from the row control module 210 and the column control module 220. The row and column control module 230 has five input terminals and four output terminals. The five input terminals of the row and column control module 230 are used to input: ramp change clock (CLK_IN), ramp change enable signal (RAMP_ENIN), and ramp reset signal (RAMP_RSTIN). The four output terminals of the row and column control module 230 are used to output: total enable signal (ENABLE), total reset signal (RST), ramp resolution selection signal (RESOLUTION_SELIN), and ramp change working clock signal (COL_CLK).

[0058] According to some embodiments of this application, the ramp signal generation circuit 1000 further includes: a current source bias module 300 and a resistor array module 400; the output terminal of the current source bias module 300 is connected to the input terminal of the current source array 100; the input terminal of the resistor array module 400 is connected to the output terminal of the current source array 100; the current source bias module 300 is used to provide the same current source bias signal to the global array base unit 110 in the current source array 100; the resistor array module 400 is used to convert the output current of the current source array into the final ramp signal, the final ramp signal is a voltage signal, and the swing, slope, and step size of the final ramp signal can be adjusted by adjusting the total resistance value of the resistor array module.

[0059] In some embodiments of this application, it should be noted that, in order to solve the high-speed bottleneck of the aforementioned conventional ramp generation circuit, such as... Figure 9 As shown, this application provides a high-speed control logic module for a current source array 100; and the ramp generation circuit includes a logic control module 200, a current source bias module 300, a current source array 100, and a resistor array module 400.

[0060] Specifically, the current source array 100 includes a plurality of array basic units 110. Each array basic unit 110 includes: a unit current source with a differential switch and a unit latch 111. The unit latch 111 is used to maintain the output of the unit current source in the state after the switch is switched. That is, during the ramp generation process, if a certain unit current source is selected by the corresponding row and column control signals once, unless there is a set signal, the current leaving path of the current source remains unchanged. The input end of the current source array 100 is used to input the following seven signals: current source bias signal 1 (VB1, corresponding to the output of ISOURCE_BIAS), current source bias signal 2 (VB2, corresponding to the output of ISOURCE_BIAS), odd row set signal (ODD_SET<Y:0, corresponding to the output of the logic control module 200), even row set signal (EVEN_SET <y:0>(corresponding to the output of logic control module 200), and odd-movement control signal (ODDROW) <y:0>(Corresponding to the output of logic control module 200), even row control signal (EVENROW) <y:0>(corresponding to the output of logic control module 200), column control signal (COL) <x:0>(corresponding to the output of logic control module 200); the output terminal of current source array 100 is used to output the following two signals: positive output of current source array 100 (IOUTP) and negative output of current source array 100 (IOUTN).

[0061] Specifically, the current source bias module 300 provides a globally uniform bias for the current source array 100, ideally outputting the same current to each array base unit 110 in the current source array 100. The current source bias module 300 also provides adjustable output current for each current source. The input terminals of the current source bias module 300 are used to input the following three signals: a reference voltage signal (VR), a reference current signal (IR), and an output current selection signal ISEL. <a:0>The output terminal of the current source bias module 300 is used to output the following two signals: current source bias signal 1 (VB1) and current source bias signal 2 (VB2).

[0062] Specifically, the logic control module 200 provides row-by-row and column-by-column scanning control signals to the differential switches of each current source unit in the current source array 100 to switch the outflow path of the current source.

[0063] Specifically, the input terminals of the logic control module 200 are used to input the following five signals: operating clock (MAINCLK), current source set row number signal (SET_IARRAY). <a:0>), current source set enable signal (SET_ISOURCE), ramp generation enable signal (RAMP_ENABLE), and ramp generator reset signal (RAMP_RST).

[0064] Specifically, the output terminal of the logic control module 200 is used to output the following five signals: odd row set signal (ODD_SET<Y:0), even row set signal (EVEN_SET <y:0>), Odd Behavior Control Signal (ODDROW <y:0>), even row control signal (EVENROW) <y:0>), column control signal (COL) <x:0>).

[0065] Specifically, the resistor array module 400, in conjunction with the current source array 100, generates the final ramp voltage output and provides slope and swing adjustment for the ramp. The resistor array module 400 has two input signals: a current input signal (IIN, corresponding to IOUTP or IOUTN of the current source array 100) and a slope / swing adjustment signal (GAIN). <b:0>).

[0066] According to the ramp signal generation circuit 1000 provided in the embodiments of this application, when the ramp signal generation circuit 1000 is working, in the logic control module 200, firstly, the column control module 220 performs logical operation processing and step-by-step shift processing based on the received initial level signal and the feedback signal returned by the feedback node, to obtain multiple column control signals generated in sequence; the width of the column control signal can be flexibly changed by selecting different feedback nodes in the shift register chain, increasing the time margin of column control and ensuring that the ramp signal can be generated efficiently and reliably; then, based on the odd-even row signal switching logic, the row control module 210 generates row control signals based on the column control signals, and generates ramp signals by controlling the current source array 100 according to the column control signals and row control signals; thus, the row control signals are generated based on the column control signals without using a frequency divider, which can reduce the hardware cost and power consumption cost of the ramp signal generation circuit 1000; that is to say, the embodiments of this application can generate ramp signals efficiently and reliably, and can reduce the hardware cost and power consumption cost of the ramp signal generation circuit 1000.

[0067] Those skilled in the art will understand that the system structure shown in the figures does not constitute a limitation on the embodiments of this application, and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0068] It will be understood by those skilled in the art that the system architecture and application scenarios described in the embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided in the embodiments of this application. It is known by those skilled in the art that with the evolution of system architecture and the emergence of new application scenarios, the technical solutions provided in the embodiments of this application are also applicable to similar technical problems.

[0069] Based on the above system structure, various embodiments of the control method for the ramp signal generation circuit of this application are proposed below.

[0070] Secondly, such as Figure 10 As shown, this application embodiment provides a control method for a ramp signal generation circuit, applicable to, for example... Figure 1 The logic control module of the ramp signal generation circuit includes a current source array and a logic control module. The logic control module includes a row and column control module, a row control module and a column control module connected to the output of the row and column control module. The output of the column control module is connected to the input of the row control module. The row control module is used to control each row array base unit. The column control module includes logic gates and multiple column control units, each column control unit is used to control one column array base unit. Each column control unit includes a column flip-flop, and multiple column flip-flops are connected in sequence to form a shift register chain. The output of the logic gate is connected to the first column flip-flop in the shift register chain. The first input of the logic gate is used to input an initial level signal, and the second input of the logic gate is connected to a feedback node, which refers to the output of a selected column flip-flop in the shift register chain.

[0071] The control method for the ramp signal generation circuit includes, but is not limited to, steps S100 to S200.

[0072] Step S100: The column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node to obtain multiple column control signals generated in sequence.

[0073] Step S200: Based on the odd-even row signal switching logic, the row control module generates a row control signal based on the column control signal, and generates a ramp signal by controlling the current source array according to the column control signal and the row control signal.

[0074] According to some embodiments of this application, each column control unit further includes: a first level shifting module, the input terminal of which is connected to the output terminal of the column trigger. Further explanation of step S100: Step S100 involves the column control module performing logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node, to obtain multiple column control signals generated in sequence, including but not limited to steps S110 to S130.

[0075] Step S110: Perform logical operations on the initial level signal and the feedback signal returned by the feedback node through logic gates to obtain the column pulse signal.

[0076] Step S120: Under the control of the received synchronous clock signal, the column pulse signal is shifted step by step in the shift register chain, so that the column flip-flops in each column control unit output a low voltage signal in sequence. The first level shift module in each column control unit boosts the low voltage signal to obtain a column control signal to control the corresponding column array base unit.

[0077] Specifically, the working principle of steps S110 and S120 is explained. In this embodiment, the column pulse signal is generated by shift register chain feedback, and the generated column pulse signal is moved column by column under the control of the working clock cycle to sequentially select the current source array. Each column of the array base unit corresponds to a column control module, such as... Figure 1 As shown. The column flip-flops are the core of the logic. In the logic control module, a simple logic gate (or NOT gate) is inserted in front of the first column flip-flop to receive the initial level signal and the signal fed back from subsequent columns, and then performs the operation to obtain the column pulse. Under the control of the synchronous clock, the pulse is shifted stage by stage between the column flip-flop chains. The pulse width of the column pulse signal can be determined by the node selection of the feedback signal, such as... Figure 8 As shown: Selecting the output of the 5th column flip-flop as the feedback node results in a column pulse signal width of 4 clock cycles. That is, when the output of the Mth column flip-flop is selected as the feedback node, the column pulse signal width is M-1 clock cycles. The low-voltage signal generated by the shift is boosted by the first level shift module (Levelshift) and becomes the actual column control signal to control the state switching of the unit latch, thereby changing the output of the final ramp signal. The column pulse signal and row pulse signal control the latch switching when both are high. Once the switching is complete, the latch will maintain its state during subsequent ramp changes, regardless of the state of its corresponding row and column signals. During this period, only the ramp reset signal can change the latch's state. Therefore, the falling edge and low level of the column pulse only indicate pulling the column signal low, i.e., resetting the column signal, preparing for the next row, and do not change the already switched unit current source latch.

[0078] Compared with the prior art, the embodiments of this application extend the width of the column pulse signal through steps S110 to S120: by selecting different feedback nodes, the width of the column pulse can be flexibly changed instead of a pulse with only half a clock cycle width, which increases the time margin of column control and avoids the problem that the boost module cannot boost normally and the latch cannot switch normally when the column pulse is too short when the operating frequency is high.

[0079] According to some embodiments of this application, the row control signal includes: an even row control signal and an odd row control signal; further describing step S200, wherein the row control module generates the row control signal based on the column control signal, including: triggering an odd row control signal for controlling the first odd half row in response to a falling edge of the column control signal for controlling the first column or a rising edge of the column control signal for controlling the sixth column; and triggering an even row control signal for controlling the second even half row in response to a falling edge of the column control signal for controlling the ninth column or a rising edge of the column control signal for controlling the thirteenth column.

[0080] The theoretical basis for the aforementioned extended column control pulse width is as follows: to achieve equal-interval ramp changes, it is only necessary to control the generation of column pulses at equal intervals. The width of the column pulse itself only needs to be sufficient to not affect the normal triggering of the next row. That is, all column signals are reset before the start of the next row, waiting for a new round of complete and sequential triggering. Therefore, the column pulse does not need to fail before the arrival of the next column signal; the column pulse has the potential to be wider. Wider column pulses reduce the pressure on the level shift stage (Levelshift module), avoiding the problem of ramp column control signals not being generated in high-frequency applications. Of course, to implement this column control logic, the row control signals also need to be adjusted accordingly. The working principle and beneficial effects of step S200 are further explained below.

[0081] In traditional timing methods, row control signals must switch between the pulses of two adjacent column control signals (i.e., after the last column of the current row becomes invalid and before the first column of the next row becomes valid) to avoid deterioration of ramp linearity; however, this interval is only half a clock cycle. This application introduces odd / even row signal switching logic, allowing the row switching interval to be extended to multiple clock cycles as needed, and also making it feasible to extend the column control pulse width. The odd / even row signal switching logic is described below.

[0082] Specifically, in combination Figure 11 and Figure 8 The shift register chain used in this application to generate the extended column control signals has 16 nodes (16 column flip-flops), corresponding to 16 column control signals. These 16 column control signals are recorded as COLUMN0~COLUMN15 according to the column number being controlled. The row control signal ROWX and column control signals COLUMN0~COLUMN7 control 8 current sources, referred to as the first half: even-numbered rows. The row control signal ODDROWX and column control signals COLUMN8~COLUMN15 control another 8 current sources, referred to as the second half: odd-numbered rows. Based on the different controlled objects, the row control signals are divided into even-numbered row control signals (EVENROW0, EVENROW1, EVENROW2) and odd-numbered row control signals (ODDROW0, ODDROW1).

[0083] The even-row control signal EVENROW0, used to control the first even-half row, is enabled following a ramp-enabling signal to ensure its validity before the arrival of the COLUMN series signals. Subsequently, column control signals COLUMN0~COLUMN7 are generated sequentially, meaning the current sources for the first half of the current row are turned on sequentially. During this period, for the second half of the row, because column control signals COLUMN8~COLUMN15 are not generated, even if the odd-row control signal ODDROW0, used to control the first odd-half row, is enabled, the current sources for the second half will not be turned on; for example... Figure 11 If ODDROW0 is enabled when EVENROW 0 is enabled and COLUMN5 is generated, then ODDROW0 will arrive three cycles before COLUMN8. Figure 11 The yellow shading in ODDROW0 indicates the lead time of the ROW signal relative to its corresponding column signal group. This increases the switching margin of the row signals (compared to only half a clock cycle in traditional structures). In the next stage, when ODDROW0 is enabled and COLUMN8~COLUMN15 are generated sequentially, COLUMN0~COLUMN7 will not cause a ramp change until EVENROW1 arrives. Therefore, COLUMN0~COLUMN7 can be gradually reset during the changes in COLUMN8~COLUMN15, as long as the reset is completed before EVENROW1 (even-numbered rows) becomes effective. Figure 11 As shown, the blue shading represents the time margin between the completion of the reset of the last signal in the COLUMN series and the completion of the enable of its corresponding next ROW signal. For example, COLUMN7, as the last signal to be reset in the first half of the column series, has a time margin of two clock cycles between its reset and the enable of EVENROW1 or EVENROW2. Figure 11 In the example, as long as COLUMN7 is low (reset) and COLUMN0 is high (enable), the next EVENROW signal corresponding to COLUMN0~COLUMN7 can be enabled. This is based on the even half row, and the same applies to the odd half row.

[0084] Similar to the column control layout, each row of the current source array corresponds to a row control module. The specific structure of the row control module is as follows: Figure 6 As shown, this will not be elaborated further. Since each half-line (whether odd or even) only needs to be enabled once within a single ramp generation frame, without repeated operation, the row control signal only needs to generate a suitable rising edge within the time margin to ensure the latch in the corresponding half-line current source is enabled. That is, during one ramp change process, each half-line control signal does not need to be pulled low. After the ramp change ends, all half-line signals are uniformly reset to low level before the next ramp change begins. Therefore, the row control signal changes from the traditional wide-pulse type to a step type. On the other hand, the two-to-one data selector in the row control logic can be used to adjust the ramp resolution, that is, by controlling the simultaneous activation of two odd / even rows or only one odd / even row, several current source units can be operated within one clock cycle.

[0085] In the above design, the row control signal is optimized from a pulse signal to a step signal. Since the current source array has latches, the state is latched after each row switch until the ramp is established or interrupted. As long as the row control signal is completely reset before the next ramp is established, the normal generation of the ramp is not affected. The step signal reduces the signal switching of the control logic during ramp establishment, saving power consumption and reducing power supply noise injection. On the other hand, the resolution condition mentioned above is to meet the quantization requirements under different conditions. The ramp change step size needs to be adjustable. In traditional structures, resolution adjustment is designed in column control, which introduces more sub-circuits into the high-frequency link, creating a bottleneck in high-frequency applications. This application design designs the resolution adjustment in the row direction because the row frequency is lower. After decoupling the parity design, the time margin for row switching is also larger.

[0086] It should be emphasized that the triggering of the half-row step control signal (i.e., the row control signal) in this application can be introduced from the column control signal. For example, in Figure 11 In the timing diagram, ODDROW0 can be triggered by the falling edge of COLUMN1 or the rising edge of COLUMN5; similarly, EVENROW1 can be triggered by the falling edge of COLUMN9 or the rising edge of COLUMN13. This means the row control signals no longer require a frequency divider to generate a specific clock signal and can be triggered by the existing column signals. This change optimizes circuit area and power consumption, and also allows for greater flexibility in the row-to-column ratio of the current source array (traditional structures are limited by the frequency divider, and rows and columns always need to follow a certain division ratio). It should be noted that ODDROW0 refers to the odd-numbered row control signal used to control the first odd half-row, and EVENROW1 refers to the even-numbered row control signal used to control the second even half-row.

[0087] There is a reason for selecting the falling edge of COLUMN1, the rising edge of COLUMN5, the falling edge of COLUMN9, or the rising edge of COLUMN13 to trigger the row trigger signal: First, the next even-half row signal must appear only after all the column control signals corresponding to the current even-half row have been reset, such as... Figure 4 As shown, EVENROW1 is only enabled after COLUMN7 corresponding to EVENROW0 returns to zero, to prevent the next even half-row from recognizing the column signal of the previous even half-row, which would degrade the slope linearity (the same applies to odd half-rows). On the other hand, considering consistency, except for the first even half-row signal which is directly triggered by the slope change enable signal, the timing of the lead time between the generation of all subsequent odd and even half-row signals and their corresponding column signals is consistent: the falling edge of COLUMN1 or the rising edge of COLUMN5 triggers ODDROW1, which leads COLUMN8~COLUMN15 by 2 cycles; the falling edge of COLUMN9 or the rising edge of COLUMN13 triggers EVENROW1, which leads COLUMN0~COLUMN7 by 2 cycles, which is sufficient for the row signal to be established and does not affect the linear change of the slope; for the last column signal of each half-row, namely COLUMN7 and COLUMN15, the arrival time of the next row is also two cycles later, which is sufficient for the column signal to be reset normally.

[0088] It needs to be emphasized that, Figure 11 The timing sequence shown is merely one implementation method within the design concept described in this application. Based on this concept, the number of columns, the number of half-rows, the column pulse width, and the triggering timing of the half-row step signal can be flexibly adjusted, as long as it is ensured that the corresponding column signal has been fully reset when a new odd or even half-row signal is generated.

[0089] In this embodiment, through steps S100 to S200, when the ramp signal generation circuit is working, in the logic control module, firstly, the column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node, to obtain multiple column control signals generated in sequence. The width of the column control signal can be flexibly changed by selecting different feedback nodes in the shift register chain, increasing the time margin of column control and ensuring efficient and reliable ramp signal generation. Then, based on the odd / even row signal switching logic, the row control module generates row control signals based on the column control signals, and the ramp signal is generated by controlling the current source array according to the column and row control signals. Thus, without using a frequency divider, the row control signal is generated based on the column control signals, reducing the hardware cost and power consumption cost of the ramp signal generation circuit. In other words, this embodiment can generate ramp signals efficiently and reliably, and can reduce the hardware cost and power consumption cost of the ramp signal generation circuit.

[0090] It is important to emphasize that this application offers more flexible adjustment of the column pulse signal width. This application can ensure that the width of each column pulse is the same, and the width of the pulse in the last column will not continuously decrease to an unusable state as the operating frequency increases, thus guaranteeing both time margin and control signal consistency. In related technologies, column signal generation is achieved through complex logic control or frequency division, which causes signal delay and imposes higher operating frequency requirements on the first division point of the frequency divider, as this node directly connects to the high-frequency operating frequency. The high-frequency node includes the frequency divider and column flip-flops in the shift register. In this application, the generation of column control signal pulses does not require a frequency divider; only a basic logic gate is needed in the logic control module of the first column to receive the subsequent shift signal fed back from the feedback node. The high-frequency node is simply a column flip-flop, which can be selected as either a traditional master-slave type or a higher-speed TSPC type as needed.

[0091] Thirdly, embodiments of this application provide an image sensor, including a ramp signal generation circuit as described in the first aspect embodiment.

[0092] In the image sensor provided in this application embodiment, the ramp signal generation circuit utilizes a logic control module. First, the column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node, obtaining multiple column control signals generated sequentially. Second, the row control module generates row control signals based on the column control signals. The current source array is then controlled based on odd / even row signal switching logic according to the column and row control signals to generate the ramp signal. On one hand, the ramp signal generation circuit can flexibly change the width of the column control signal by selecting different feedback nodes in the shift register chain, increasing the time margin of column control and ensuring efficient and reliable generation of the ramp signal. This allows the image sensor to reliably quantize pixel signals based on the ramp signal. On the other hand, the ramp signal generation circuit generates row control signals based on the column control signals without using a frequency divider, reducing the hardware and power consumption costs of the ramp signal generation circuit, thereby helping to reduce the hardware and power consumption costs of the image sensor.

[0093] Fourthly, embodiments of this application provide an electronic device including an image sensor as described in the third aspect embodiment. This image sensor includes a highly efficient, reliable, and low-cost (both hardware and power consumption) ramp signal generation circuit. The image sensor can reliably quantize pixel signals and output reliable image signals, enabling the electronic device to perform other post-processing based on the reliable image signals; it also helps improve the reliability of the electronic device and reduce its hardware cost.

[0094] The above provides a detailed description of the preferred embodiments of this application. However, this application is not limited to the above-described embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of this application. All such equivalent modifications or substitutions are included within the scope defined by this application.

Claims

1. A ramp signal generation circuit, characterized in that, include: The current source array comprises multiple array basic units arranged in m rows and n columns; The logic control module includes: a row and column overall control module, a row control module and a column control module connected to the output of the row and column overall control module; The output of the column control module is connected to the input of the row control module; The row control module is used to control each row of the array base unit; The column control module includes logic gates and multiple column control units. Each column control unit controls one column of the array base units. Each column control unit includes a column flip-flop, and multiple column flip-flops are connected in sequence to form a shift register chain. The output of the logic gate is connected to the first column flip-flop in the shift register chain. The first input of the logic gate is used to input an initial level signal, and the second input of the logic gate is connected to a feedback node, which refers to the output of a selected column flip-flop in the shift register chain. The logic control module is used to: perform logical operations and step-by-step shifting processing on the received initial level signal and the feedback signal returned by the feedback node through the column control module to obtain multiple column control signals generated in sequence; generate row control signals based on the column control signals through the row control module based on the odd and even row signal switching logic; and generate ramp signals by controlling the current source array according to the column control signals and the row control signals.

2. The ramp signal generation circuit according to claim 1, characterized in that, The row control module includes multiple row control units, each of which controls a corresponding row of the array base unit; the row control unit includes: a data selector, a row trigger, a row buffer, a second level shift module, and a row output buffer stage connected in sequence.

3. The ramp signal generation circuit according to claim 2, characterized in that, Each of the array base units includes: a unit latch and a unit differential current source connected in sequence; the input terminal of the unit latch is connected to the output terminal of the column control unit and the row control unit; the unit latch is used to switch operating states under the control of the row control signal and the column control signal; the unit differential current source includes a positive output terminal and a negative output terminal, and the unit differential current source is used to determine the target output current from the positive output terminal and the negative output terminal according to the output terminal control signal output by the unit latch.

4. The ramp signal generation circuit according to claim 1, characterized in that, Each of the column control units further includes: a column buffer, a first level shift module, and a column output buffer stage. The input of the first level shift module is connected to the output of the column trigger, and the output of the first level shift module is used to output the generated column control signal to the corresponding column of the array base unit.

5. The ramp signal generation circuit according to claim 1, characterized in that, The ramp signal generation circuit further includes: a current source bias module and a resistor array module; the output terminal of the current source bias module is connected to the input terminal of the current source array; the input terminal of the resistor array module is connected to the output terminal of the current source array; the current source bias module is used to provide the same current source bias signal to all array base units in the current source array; the resistor array module is used to convert the output current of the current source array into the final ramp signal, the final ramp signal is a voltage signal, and the swing, slope, and step size of the final ramp signal can be adjusted by adjusting the total resistance value of the resistor array module.

6. A control method for a ramp signal generation circuit, characterized in that, A logic control module applied to the ramp signal generation circuit as described in any one of claims 1 to 5, wherein the ramp signal generation circuit further includes: a current source array and a logic control module; the logic control module includes: a row and column overall control module, a row control module and a column control module connected to the output terminal of the row and column overall control module; the output terminal of the column control module is connected to the input terminal of the row control module; the row control module is used to control each row of the array base unit; the column control module includes logic gates and multiple column control units, each column control unit is used to control one column of the array base unit; each column control unit includes a column flip-flop, and multiple column flip-flops are connected in sequence to form a shift register chain; the output terminal of the logic gate is connected to the first column flip-flop in the shift register chain, the first input terminal of the logic gate is used to input an initial level signal, and the second input terminal of the logic gate is connected to a feedback node, the feedback node being the output terminal of a selected column flip-flop in the shift register chain; The control method includes: The column control module performs logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node to obtain multiple column control signals generated in sequence. Based on the odd-even row signal switching logic, the row control module generates a row control signal based on the column control signal, and generates a ramp signal by controlling the current source array according to the column control signal and the row control signal.

7. The control method for the ramp signal generation circuit according to claim 6, characterized in that, Each of the column control units further includes: a column buffer, a first level shift module, and a column output buffer stage, wherein the input terminal of the first level shift module is connected to the output terminal of the column trigger; The process of sequentially performing logical operations and step-by-step shifting based on the received initial level signal and the feedback signal returned by the feedback node by the column control module to obtain multiple column control signals generated in sequence includes: The initial level signal and the feedback signal returned by the feedback node are processed by the logic gate to obtain the column pulse signal; Under the control of the received synchronous clock signal, the column pulse signal is shifted step by step in the shift register chain, causing the column flip-flops in each column control unit to output a low-voltage signal in sequence. The first level shift module in each column control unit boosts the low-voltage signal to obtain a corresponding column control signal to control the corresponding column of array base units.

8. The control method for the ramp signal generation circuit according to claim 6, characterized in that, in, The row control signals include: even row control signals and odd row control signals; The process of generating row control signals based on column control signals via the row control module includes: In response to the falling edge of the column control signal used to control the first column, or the rising edge of the column control signal used to control the sixth column, the odd row control signal used to control the first odd half row is triggered. In response to the falling edge of the column control signal used to control the ninth column, or the rising edge of the column control signal used to control the thirteenth column, the even-numbered row control signal used to control the second even half row is triggered.

9. An image sensor, characterized in that, Includes the ramp signal generation circuit as described in any one of claims 1 to 5.

10. An electronic device, characterized in that, Including the image sensor as described in claim 9.

Images