Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a storage system. The semiconductor structure comprises a plurality of semiconductor columns, a gate structure, a first dielectric layer and a capacitor contact structure. The gate structure is located on a first side of the semiconductor column along the first direction. The first dielectric layer is located on the first side of the semiconductor column and extends to the gate structure in the second direction. The capacitor contact structure passes through the first dielectric layer along the second direction and extends to the semiconductor column. The first direction intersects the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to semiconductor structures, methods for manufacturing semiconductor structures, and memory systems. Background Technology

[0002] With the rise and development of artificial intelligence, big data, the Internet of Things, mobile communications, mobile devices, and cloud storage, the requirements for storage density of semiconductor structures, such as three-dimensional semiconductor storage devices, are becoming increasingly stringent. However, as the storage density of semiconductor structures increases, the number of related components in the semiconductor structure increases, their size decreases, and their spatial density increases. This makes it easy for coupling phenomena to occur between adjacent components, which in turn leads to a gradual decline in the performance of the semiconductor structure and an increasingly complex manufacturing process. Summary of the Invention

[0003] The embodiments proposed in this application can solve or partially solve the deficiencies mentioned in the background section above or other deficiencies in the prior art.

[0004] This application provides a semiconductor structure. The semiconductor structure includes a plurality of semiconductor pillars, a gate structure, a first dielectric layer, and a capacitor contact structure. The gate structure is located on a first side of the semiconductor pillars along a first direction. The first dielectric layer is located on the first side of the semiconductor pillars and extends to the gate structure along a second direction. The capacitor contact structure passes through the first dielectric layer along the second direction and extends to the semiconductor pillars. The first direction intersects with the second direction.

[0005] In one embodiment, the first dielectric layer extends along a first direction and protrudes toward the gate structure along a second direction.

[0006] In one embodiment, the material of the first dielectric layer includes a nitride.

[0007] In one embodiment, the semiconductor structure further includes an isolation structure and a second dielectric layer. The isolation structure is located on a second side of the semiconductor pillar along a first direction, opposite to the first side. The second dielectric layer is located on the second side of the semiconductor pillar and is in contact with the isolation structure. The second dielectric layer is located between the first dielectric layer and the isolation structure along the second direction. A portion of the second dielectric layer is in contact with a capacitor contact structure along the first direction, and a portion of the second dielectric layer is adjacent to the semiconductor pillar along the first direction.

[0008] In one embodiment, the capacitive contact structure includes: a contact layer in contact with a semiconductor pillar; and a multilayer conductive layer located on the contact layer.

[0009] In one embodiment, the gate structure includes: a gate dielectric layer located on a first side of the semiconductor pillar; and a gate layer located on a side of the gate dielectric layer away from the semiconductor pillar.

[0010] In one embodiment, the semiconductor structure further includes a third dielectric layer located on the side of the gate layer away from the gate dielectric layer. A portion of the third dielectric layer is in contact with the first dielectric layer along a first direction, and a portion of the third dielectric layer is in contact with the gate layer along the first direction.

[0011] In one embodiment, the semiconductor structure further includes a fourth dielectric layer located between the first dielectric layer and the second dielectric layer.

[0012] In one embodiment, the portion of the first dielectric layer that protrudes toward the gate structure contacts the gate structure and is adjacent to the semiconductor pillar along a first direction.

[0013] In one embodiment, the first dielectric layer includes a first end located away from the capacitor contact structure along a second direction, wherein the first end has an inverted U-shaped structure and surrounds a portion of the third dielectric layer.

[0014] In one embodiment, the dimension of the first dielectric layer along the second direction is larger than the dimension of the capacitor contact structure along the second direction.

[0015] In one embodiment, at least a portion of the first dielectric layer is located on one side of the capacitor contact structure along the first direction.

[0016] In one embodiment, the capacitive contact structure and a portion of the semiconductor pillar are adjacent to the first dielectric layer along a first direction.

[0017] In one embodiment, the end face of the first dielectric layer away from the gate structure along the second direction is coplanar with the end face of the capacitor contact structure away from the semiconductor pillar along the second direction.

[0018] In one embodiment, the material of the third dielectric layer includes an oxide.

[0019] This application also provides a method for manufacturing a semiconductor structure. The method includes: forming a plurality of semiconductor pillars within a semiconductor layer; forming a gate structure on a first side of the semiconductor pillars along a first direction; forming a first dielectric layer on the first side of the semiconductor pillars extending to the gate structure along a second direction; and forming a capacitive contact structure extending through the first dielectric layer and to the semiconductor pillars along the second direction. The first direction intersects with the second direction.

[0020] In one embodiment, the method further includes: forming an isolation structure on a second side of the semiconductor pillar along a first direction, opposite to the first side; and forming a second dielectric layer on the second side of the semiconductor pillar extending along a second direction to the isolation structure. The second dielectric layer along the second direction is located between the first dielectric layer and the isolation structure. A capacitive contact structure passes through the first and second dielectric layers along the second direction and extends to the semiconductor pillar. A portion of the second dielectric layer contacts the capacitive contact structure along the first direction, and a portion of the second dielectric layer is adjacent to the semiconductor pillar along the first direction.

[0021] In one embodiment, forming a first dielectric layer extending to a gate structure along a second direction on a first side of a semiconductor pillar includes: forming the first dielectric layer on one side of the semiconductor pillar and the second dielectric layer along a direction opposite to the second direction. The first dielectric layer extends along a first direction and protrudes toward the gate structure along the second direction. The portion of the first dielectric layer protruding toward the gate structure contacts the gate structure and is adjacent to the semiconductor pillar along the first direction.

[0022] In one embodiment, the method further includes planarizing the surface of the first dielectric layer away from the semiconductor pillar.

[0023] In one embodiment, the capacitive contact structure includes a contact layer and a multilayer conductive layer on the contact layer. Forming a capacitive contact structure that extends through a first dielectric layer in a second direction and reaches a semiconductor pillar includes: forming a contact hole extending through the first dielectric layer in a second direction and reaching the semiconductor pillar; forming a contact layer within the contact hole; and forming a multilayer conductive layer on the contact layer.

[0024] In one embodiment, forming an isolation structure on a second side of the semiconductor pillars along a first direction and opposite to the first side includes: forming a plurality of initial semiconductor pillars within a semiconductor layer; forming a plurality of first trenches that pass through the initial semiconductor pillars along a third direction and are arranged along the first direction; and forming an isolation structure on the second side of the semiconductor pillars via the first trenches. The first direction, the second direction, and the third direction intersect each other.

[0025] In one embodiment, forming a gate structure on a first side of a semiconductor pillar along a first direction includes: forming a plurality of second trenches that pass through the initial semiconductor pillar along a third direction and are arranged along the first direction, wherein the plurality of first trenches and the plurality of second trenches divide the initial semiconductor pillar into a plurality of semiconductor pillars; and forming a gate structure on the first side of the semiconductor pillar via the second trenches.

[0026] In one embodiment, the gate structure includes a gate dielectric layer and a gate layer. Forming the gate structure on a first side of the semiconductor pillar via a second trench includes: forming a gate dielectric layer on the first side of the semiconductor pillar via the second trench; and forming a gate layer on the side of the gate dielectric layer away from the semiconductor pillar.

[0027] In one embodiment, the method further includes forming a third dielectric layer on the side of the gate layer away from the gate dielectric layer via a second trench. The first dielectric layer includes a first end away from the capacitor contact structure along a second direction, the first end having an inverted U-shaped structure and surrounding a portion of the third dielectric layer.

[0028] In one embodiment, forming a plurality of initial semiconductor pillars within a semiconductor layer includes forming a plurality of isolation portions within the semiconductor layer, wherein the plurality of isolation portions divide a portion of the semiconductor layer into a plurality of initial semiconductor pillars.

[0029] In one embodiment, the method further includes disconnecting the gate structure from the side of the gate structure away from the first dielectric layer.

[0030] Another aspect of this application provides a storage system including a semiconductor structure as described above; and a controller coupled to the semiconductor structure for controlling the semiconductor structure to store data. Attached Figure Description

[0031] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments, taken in conjunction with the accompanying drawings. In the drawings:

[0032] Figure 1 This is a flowchart of a method for manufacturing a semiconductor structure according to an exemplary embodiment of this application;

[0033] Figures 2 to 6 This is a process step diagram of forming a semiconductor pillar provided in this application;

[0034] Figure 7 and Figure 8 This is a schematic diagram of the structure forming a first sacrificial layer and a second sacrificial layer according to an exemplary embodiment of this application, wherein, Figure 8 for Figure 7 Schematic diagram of the cross section along the BB direction;

[0035] Figure 9 and Figure 10 This is a schematic diagram of a structure forming an isolation structure according to an exemplary embodiment of this application, wherein, Figure 10 for Figure 9 Schematic diagram of the cross section along the BB direction;

[0036] Figure 11 and Figure 12 This is a schematic diagram of the structure for forming a second dielectric layer according to an exemplary embodiment of this application, wherein, Figure 12 for Figure 11 A schematic diagram of the cross-section along the CC direction;

[0037] Figure 13 and Figure 14 This is a schematic diagram of the structure for forming a second trench according to an exemplary embodiment of this application, wherein, Figure 14 for Figure 13 A schematic diagram of the cross-section along the CC direction;

[0038] Figures 15 to 17 This is a process step diagram of forming a gate structure provided in this application, wherein, Figure 16 for Figure 15 A schematic diagram of the cross-section along the CC direction;

[0039] Figure 18 This is a schematic diagram of the structure after forming the first dielectric layer according to an exemplary embodiment of this application;

[0040] Figure 19 This is a schematic diagram of the structure after planarization of the surface of the first dielectric layer according to an exemplary embodiment of this application;

[0041] Figures 20 to 22 This is a process step diagram of forming a capacitor contact structure provided in this application;

[0042] Figure 23 yes Figure 22 Enlarged view of the middle section structure;

[0043] Figure 24 To be Figure 22 A schematic diagram of a structure that has been thinned after being flipped 180°.

[0044] Figure 25 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of this application;

[0045] Figures 26 to 30 This is a process step diagram of a method for manufacturing a semiconductor structure according to another embodiment of this application; and

[0046] Figure 31 This is an exemplary block diagram of a system having a storage system according to an exemplary embodiment of this application. Detailed Implementation

[0047] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0048] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first dielectric layer discussed herein may also be referred to as the second dielectric layer, and the first direction may also be referred to as the second direction, and vice versa.

[0049] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0050] Furthermore, in this text, when describing a part as being "on" another part, such as "on," "above," and "above," the meaning should be interpreted in the broadest possible sense, such that "on" not only means "directly on" something, but also includes the meaning of "on" something with intermediate features or layers in between. Moreover, "above" or "above" does not absolutely mean being above something with respect to the direction of gravity, nor does it only mean "on" something or "above" something, but can also include the meaning of "on" something or "above" something without intermediate features or layers in between (i.e., directly on) something.

[0051] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplarily" is intended to refer to examples or illustrations.

[0052] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0053] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0054] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer can be a region of a homogeneous or non-homogeneous continuous structure, the height of which is less than the height of the continuous structure. For example, a layer can be located at or between any set of horizontal planes on or between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer can include multiple layers.

[0055] Furthermore, in this application, the use of "connection" or "linkage" may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0056] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0057] Figure 1 This is a flowchart of a method 1000 for manufacturing a semiconductor structure according to an exemplary embodiment of this application.

[0058] The method 1000 for manufacturing a semiconductor structure may include: S1100, forming a plurality of semiconductor pillars within a semiconductor layer; S1200, forming a gate structure on a first side of the semiconductor pillars along a first direction; S1300, forming a first dielectric layer on the first side of the semiconductor pillars extending to the gate structure along a second direction; and S1400, forming a capacitive contact structure that extends through the first dielectric layer along a second direction and to the semiconductor pillars. Steps S1100 to S1400 will be described in detail below.

[0059] Figures 2 to 6 This is a process step diagram for forming a semiconductor pillar 1100 provided in this application. It should be understood that the process for forming the semiconductor pillar 1100 provided in this application is only an example and not a specific limitation. In actual processes, the process for forming the semiconductor pillar 1100 can be reasonably set according to actual needs.

[0060] Figure 2 This is a partial structural schematic diagram of a semiconductor layer 100 provided according to an exemplary embodiment of this application on a plane formed by a first direction X and a third direction Y.

[0061] For example, the first direction X, the second direction Z, and the third direction Y can intersect each other. Subsequently, semiconductor pillars 1100 can be formed by etching the semiconductor layer 100. Figure 5 and Figure 6 The material of semiconductor layer 100 may include at least one of monocrystalline silicon, polycrystalline silicon, monocrystalline germanium, III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art.

[0062] Figure 3 and Figure 4This is a schematic diagram of the structure forming the initial semiconductor pillar 110 and the isolation portion 1200 according to an exemplary embodiment of this application, wherein, Figure 4 for Figure 3 A schematic cross-sectional view along the AA direction. Exemplarily, a plurality of initial semiconductor pillars 110 may be formed within the semiconductor layer 100. The initial semiconductor pillars 110 may extend along a first direction X and a second direction Z.

[0063] For example, forming a plurality of initial semiconductor pillars 110 may include: forming a plurality of isolation portions 1200 within a semiconductor layer 100, wherein the plurality of isolation portions 1200 divide a portion of the semiconductor layer 100 into a plurality of initial semiconductor pillars 110. The isolation portions 1200 may extend along a first direction X and a second direction Z. The initial semiconductor pillars 110 and the isolation portions 1200 may be arranged alternately along a third direction Y. For example, a plurality of grooves (not shown) extending along the first direction X and the second direction Z may be formed within the semiconductor layer 100; and isolation portions 1200 may be formed within the grooves, wherein the unremoved semiconductor layer 100 may form the initial semiconductor pillars 110.

[0064] For example, the semiconductor layer 100 can be etched by one or more dry etching and / or wet etching processes to etch grooves in the semiconductor layer 100, wherein the unremoved semiconductor layer 100 can form initial semiconductor pillars 110.

[0065] Exemplarily, the material of the isolation portion 1200 may include, but is not limited to, insulating materials such as oxides. Exemplarily, the insulating material can be deposited in the trench to form the isolation portion 1200 by a thin film deposition process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, so that adjacent initial semiconductor pillars 110 are isolated by the isolation portion 1200.

[0066] Figure 5 and Figure 6 This is a schematic diagram of the structure for forming a semiconductor pillar 1100, a first trench 210, and an initial second trench 220' according to an exemplary embodiment of this application, wherein, Figure 6 for Figure 5 A schematic cross-sectional view along the BB direction. For example, a plurality of semiconductor pillars 1100 may be formed within the semiconductor layer 100.

[0067] For example, forming a plurality of semiconductor pillars 1100 may include forming a plurality of first trenches 210 and initial second trenches 220' that pass through the initial semiconductor pillar 110 along a third direction Y and are alternately arranged along a first direction X. The plurality of first trenches 210 and initial second trenches 220' may divide the initial semiconductor pillar 110 into a plurality of semiconductor pillars 1100. The semiconductor pillar 1100 may include a first side 1110 and a second side 1120 opposite each other along the first direction X, wherein the first trenches 210 may be located on the second side 1120 and the initial second trenches 220' may be located on the first side 1110. For example, the first trenches 210 and the initial second trenches 220' may be etched using one or more dry etching and / or wet etching processes.

[0068] Multiple semiconductor pillars 1100 may extend along a second direction Z and be arrayed along a first direction X and a third direction Y. Exemplarily, multiple semiconductor pillars 1100 may be formed by removing a portion of the semiconductor layer 100. In other words, the unremoved portion of the semiconductor layer 100 may include multiple semiconductor pillars 1100. Therefore, the semiconductor pillars 1100 may have the same material as the unremoved portion of the semiconductor layer 100, such as monocrystalline silicon.

[0069] For example, a plurality of semiconductor pillars 1100 are spaced apart from each other to expose one or more sidewalls of the semiconductor pillars 1100, such as exposing a first side 1110 and a second side 1120 of the semiconductor pillars 1100. The semiconductor pillars 1100 may have a cubic shape to expose their four sidewalls. It should be understood that the semiconductor pillars 1100 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillars 1100 in a planar view (e.g., in the XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape.

[0070] Figure 7 and Figure 8 This is a schematic diagram of the structure forming the first sacrificial layer 310 and the second sacrificial layer 320 according to an exemplary embodiment of this application, wherein, Figure 8 for Figure 7 A schematic cross-sectional view along the BB direction. Exemplarily, a first sacrificial layer 310 and a second sacrificial layer 320 may be formed within the first trench 210 and the initial second trench 220', respectively. For example, the first sacrificial layer 310 and the second sacrificial layer 320 may be formed by depositing a dielectric material such as silicon oxide or carbon material using one or more thin-film deposition processes.

[0071] Figure 9 and Figure 10 This is a schematic diagram of the structure forming the isolation structure 1300 according to an exemplary embodiment of this application, wherein, Figure 10 for Figure 9 A schematic diagram of the cross-section along the BB direction.

[0072] Exemplarily, an isolation structure 1300 may be formed on a second side 1120 of the semiconductor pillar 1100 along a first direction X. Exemplarily, a first sacrificial layer 310 within a first trench 210 may be removed; and the isolation structure 1300 may be formed on the second side 1120 of the semiconductor pillar 1100 via the first trench 210 after the removal of the first sacrificial layer 310. The isolation structure 1300 may extend along a third direction Y.

[0073] For example, the isolation structure 1300 may include an isolation conductive layer 1310 and an isolation dielectric layer 1320 surrounding the isolation conductive layer 1310. The isolation dielectric layer 1320 may be located on the second side 1120 of the semiconductor pillar 1100 and the top surface of the semiconductor pillar 1100. The isolation conductive layer 1310 may be located on the side of the isolation dielectric layer 1320 away from the semiconductor pillar 1100 along a first direction X.

[0074] Exemplarily, the material of the conductive isolation layer 1310 may include, but is not limited to, metallic materials such as tungsten and copper. The material of the dielectric isolation layer 1320 may include, but is not limited to, silicon oxide. Exemplarily, the first sacrificial layer 310 may be removed using photolithography, one or more dry etching and / or wet etching processes; then, one or more thin film deposition processes may be used to sequentially form the dielectric isolation layer 1320 and the conductive isolation layer 1310 in the removed space to form the isolation structure 1300. It should be understood that in actual processes, the formed dielectric isolation layer 1320 may be located on the sidewalls and surface of the semiconductor pillar 1100.

[0075] For example, such as Figure 10 As shown, the dimension H1 of the conductive isolation layer 1310 along the second direction Z can be smaller than the dimension H2 of the dielectric isolation layer 1320 along the second direction Z. In other words, the isolation structure 1300 does not completely fill the first trench 210.

[0076] Figure 11 and Figure 12 This is a schematic diagram of the structure of the second dielectric layer 1410 provided according to an exemplary embodiment of this application, wherein, Figure 12 for Figure 11 A schematic cross-sectional view along the CC direction. Exemplarily, a second dielectric layer 1410 extending along the second direction Z to the isolation structure 1300 may be formed on the second side 1120 of the semiconductor pillar 1100. As... Figure 11 As shown, the second dielectric layer 1410 may be located on the surface of the isolation dielectric layer 1320 and in contact with the isolation conductive layer 1310.

[0077] Exemplarily, one or more thin-film deposition processes may be used to form the second dielectric layer 1410 within the remaining space of the first trench 210. It should be understood that, in actual processes, the formed second dielectric layer 1410 may be located in the remaining space of the first trench 210 and on the surface of the insulating dielectric layer 1320 along the second direction Z.

[0078] Exemplarily, the material of the second dielectric layer 1410 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material. Exemplarily, the material of the second dielectric layer 1410 may include silicon nitride.

[0079] Figure 13 and Figure 14 This is a schematic diagram of the structure forming the second trench 220 according to an exemplary embodiment of this application, wherein, Figure 14 for Figure 13 A schematic cross-sectional view along the CC direction. Exemplarily, the second sacrificial layer 320 may be removed, and the width of the initial second trench 220' may be increased to form the second trench 220.

[0080] The second trench 220 can pass through the initial semiconductor pillar 110 along the third direction Y and be arranged along the first direction X. At this time, the isolation structure 1300 and the second trench 220 can be located on both sides of the semiconductor pillar 1100 along the first direction X, for example, the isolation structure 1300 can be located on the second side 1120 of the semiconductor pillar 1100 along the first direction X, and the second trench 220 can be located on the first side 1110 of the semiconductor pillar 1100 along the first direction X.

[0081] For example, the second sacrificial layer 320 may be removed using photolithography, one or more dry etching and / or wet etching processes. Exemplarily, during the removal of the second sacrificial layer 320, the initial second trench 220' may be enlarged to form a second trench 220 with a width greater than that of the initial second trench 220'.

[0082] Figures 15 to 17 This is a process step diagram of forming a gate structure 1500 provided in this application, wherein, Figure 16 for Figure 15 A schematic cross-sectional view along the CC direction. It should be understood that the process for forming the gate structure 1500 provided in this application is merely an example and not a specific limitation. In actual processes, the process for forming the gate structure 1500 can be reasonably configured according to actual needs.

[0083] For example, such as Figure 17 As shown, a gate structure 1500 may be formed on a first side 1110 of the semiconductor pillar 1100 along a first direction X. Exemplarily, the gate structure 1500 may be formed on the first side 1110 of the semiconductor pillar 1100 via a second trench 220.

[0084] Exemplarily, the gate structure 1500 may include a gate dielectric layer 1510 and a gate layer 1520. Forming the gate structure 1500 may include forming the gate dielectric layer 1510 on the first side 1110 of the semiconductor pillar 1100 via a second trench 220. Figure 15 and Figure 16 An initial gate layer 1520' is formed on the side 1110 of the gate dielectric layer 1510 away from the semiconductor pillar 1100. Figure 15 and Figure 16 ); and removing a portion of the initial gate layer 1520' along the second direction Z to form the gate layer 1520 ( Figure 17 ).

[0085] For example, such as Figure 15 As shown, in the process of forming the gate dielectric layer 1510, a fourth dielectric layer 1430 may also be formed on the side of the second dielectric layer 1410 away from the isolation structure 1300 along the second direction Z. For example, the gate dielectric layer 1510 may be located on the first side 1110 of the semiconductor pillar 1100, and the fourth dielectric layer 1430 may be located on the surface of the second dielectric layer 1410 away from the isolation structure 1300 along the second direction Z. The gate dielectric layer 1510 and the fourth dielectric layer 1430 may be an integral structure. The initial gate layer 1520' may be located on the side of the gate dielectric layer 1510 away from the semiconductor pillar 1100 along the first direction X.

[0086] For example, after the initial gate layer 1520' is formed, a third dielectric layer 1420 may also be formed on the side of the gate layer 1520 away from the gate dielectric layer 1510 via the second trench 220. The third dielectric layer 1420 may be used to isolate the initial gate layers 1520' adjacent to each other along the first direction X.

[0087] Exemplarily, a gate dielectric layer 1510, a fourth dielectric layer 1430, an initial gate layer 1520', and a third dielectric layer 1420 may be sequentially deposited using one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof. The initial gate layer 1520' may subsequently be used to form the gate layer 1520.

[0088] Exemplarily, the gate dielectric layer 1510, the fourth dielectric layer 1430, and the third dielectric layer 1420 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 1510, the fourth dielectric layer 1430, and the third dielectric layer 1420 may comprise silicon oxide. The initial gate layer 1520' may comprise one or more conductive materials, such as metals and / or metal compounds, such as tungsten W and / or titanium nitride TiN. Exemplarily, a planarization process, such as a chemical mechanical polishing process, may be performed to remove excess conductive and dielectric materials on the fourth dielectric layer 1430.

[0089] For example, such as Figure 16 As shown, a partition structure 400 can be formed along the second direction Z through the gate dielectric layer 1510 and the initial gate layer 1520' to divide the annular gate dielectric layer 1510 and the initial gate layer 1520' in the second trench 220 into at least two parts. For example, two partition structures 400 with a certain interval can be formed in each annular gate dielectric layer 1510 and the initial gate layer 1520' to divide the annular gate dielectric layer 1510 and the initial gate layer 1520' into two parts. In other words, the two partition structures 400 divide the annular gate dielectric layer 1510 into two parts and the initial gate layer 1520' into two parts.

[0090] It should be understood that this application does not specifically limit the size and / or position of the partition structure 400. The size and / or position of the partition structure 400 can be arbitrarily set according to the actual process to separate the gate dielectric layer 1510 and the initial gate layer 1520' in the second trench 220 into two parts respectively.

[0091] For example, such as Figure 17 As shown, the two side portions of the initial gate layer 1520' disposed along the second direction Z can be removed to form the gate layer 1520. For example, a gap 500 can be formed by removing a portion of the third dielectric layer 1420 and the initial gate layer 1520' along the second direction Z using a back-etching process, wherein the gate layer 1520 can be formed after removing a portion of the initial gate layer 1520'. The upper end of the formed gate layer 1520 can be located below the top surface of the semiconductor pillar 1100. Furthermore, since the gate dielectric layer 1510 is not etched back, the upper end of the gate layer 1520 can be located below the upper end of the gate dielectric layer 1510. In this way, the formed gate layer 1520 can extend along the third direction Y, and the portion corresponding to the semiconductor pillar 1100 can serve as the gate electrode. The gate structure 1500 (including the gate dielectric layer 1510 and the gate layer 1520) can be connected to a peripheral circuit to realize the transmission of electrical signals between the gate electrode and the peripheral circuit.

[0092] Exemplarily, the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a vertical transistor, wherein the semiconductor pillar 1100 can be used to form the active region of a plurality of channels in the vertical transistor. Exemplarily, the gate structure 1500 can be located on at least one sidewall of the semiconductor pillar 1100, i.e., the semiconductor pillar 1100 can be at least partially surrounded by the gate structure 1500. For example, the semiconductor pillar 1100, the gate dielectric layer 1510, and the gate layer 1520 can be arranged radially from the center of the vertical transistor in this order. Exemplarily, the gate dielectric layer 1510 can surround and contact the semiconductor pillar 1100. The gate layer 1520 can surround and contact the gate dielectric layer 1510.

[0093] It should be understood that Figure 17 The case shown where the gate structure 1500 is located on one sidewall of the semiconductor pillar 1100 is merely an example and not a specific limitation.

[0094] In one embodiment of this application, the gate structure 1500 may be located on multiple sidewalls of the semiconductor pillar 1100. In this case, the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). Multi-gate transistors can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the multi-gate transistor can also be significantly reduced because the channel is completely depleted. Therefore, using a multi-gate transistor can achieve better speed (saturation drain current) / leakage current performance.

[0095] In another embodiment of this application, the gate structure 1500 may be located on one sidewall of the semiconductor pillar 1100, in which case the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a single-gate transistor. Exemplarily, adjacent single-gate transistors along the first direction X can be arranged symmetrically. By providing single-gate transistors, this application can significantly increase the density of the semiconductor pillars 1100 in the first direction X, reducing the difficulty of the manufacturing process. Furthermore, mirror-symmetric single-gate transistors can have a larger process window, which is beneficial for reducing subsequent bit lines, word lines, and the spacing between transistors.

[0096] Figure 18 This is a schematic diagram of the structure after forming the first dielectric layer 1600 according to an exemplary embodiment of this application. Exemplarily, the first dielectric layer 1600 extending along the second direction Z to the gate structure 1500 can be formed on the first side 1110 of the semiconductor pillar 1100.

[0097] For example, a first dielectric layer 1600 may be formed on the side of the semiconductor pillar 1100, on the side opposite to the second direction Z, where the first side 1110 and the second dielectric layer 1410 are located. Alternatively, the first dielectric layer 1600 may be formed on the side of the gap 500 and the fourth dielectric layer 1430 away from the second dielectric layer 1410 along the second direction Z. In this case, the fourth dielectric layer 1430 may be located between the first dielectric layer 1600 and the second dielectric layer 1410.

[0098] Exemplarily, the formed first dielectric layer 1600 may extend along a first direction X and protrude towards the gate structure 1500 along a second direction Z, such as towards the gate layer 1520 in the gate structure 1500. The portion of the first dielectric layer 1600 protruding towards the gate layer 1520 may contact the gate layer 1520 and may be adjacent to the semiconductor pillar 1100 along the first direction X. In other words, the portion of the first dielectric layer 1600 protruding towards the gate layer 1520 may be located below the top surface of the semiconductor pillar 1100. Exemplarily, the first dielectric layer 1600 may include a first end 1610 protruding from the gate layer 1520 along the second direction Z, wherein the first end 1610 may have an inverted U-shaped structure and surround a portion of the third dielectric layer 1420. In this case, a portion of the third dielectric layer 1420 may contact the first dielectric layer 1600 along the first direction X and a portion of the third dielectric layer 1420 may contact the gate layer 1520 along the first direction X.

[0099] Exemplarily, one or more thin-film deposition processes, including but not limited to CVD, PVD, ALD, or any combination thereof, may be used to deposit the first dielectric layer 1600. The material of the first dielectric layer 1600 may include any one or any combination of two or more of silicon nitride, silicon oxynitride, and aluminum oxide. Furthermore, the first dielectric layer 1600 may be doped with at least one of carbon, boron, and phosphorus. Exemplarily, the material of the first dielectric layer 1600 may be, for example, silicon nitride.

[0100] In this application, by setting the material of the first dielectric layer 1600, such as silicon nitride, it is possible to achieve subsequent processing of the contact hole 600 ( Figure 20 During cleaning, the cleaning solution, such as an acidic cleaning solution, has a low corrosion rate on the first dielectric layer 1600. This helps reduce the risk that the contact hole 600 may penetrate into the gate layer 1520 due to the removal of too much of the first dielectric layer 1600 by the cleaning solution. This, in turn, helps reduce the impact on the gate layer 1520 and the subsequently formed capacitor contact structure 1700. Figure 22 This reduces the risk of coupling between components, thereby helping to decrease the risk of leakage current in the semiconductor structure. For example, the acidic cleaning solution may include, for instance, a hydrofluoric acid solution.

[0101] Furthermore, since the cleaning solution, such as an acidic cleaning solution, has a low corrosion rate on the first dielectric layer 1600, the connection between two adjacent contact holes 600 formed subsequently along the first direction X can be reduced. This helps to reduce the risk of coupling between two adjacent capacitor contact structures 1700 (formed within the contact holes 600) formed subsequently along the first direction X, thereby helping to reduce the risk of leakage in the semiconductor structure.

[0102] On the other hand, this application forms a first dielectric layer 1600 extending along the second direction Z to the gate structure 1500 on the first side 1110 of the semiconductor pillar 1100. For example, the first dielectric layer 1600 is formed on the side of the first side 1110 of the semiconductor pillar 1100 and the second dielectric layer 1410 in a direction opposite to the second direction Z. The first dielectric layer 1600 can serve as a contact hole 600. Figure 20 The material layer (i.e., the contact hole 600 penetrates the first dielectric layer 1600) is used, which helps to simplify the process steps. For example, by using the first dielectric layer 1600 as the material layer for the contact hole 600, it is possible to omit the steps in forming the contact hole 600. Figure 20 The process of removing other material layers on the semiconductor pillar 1100 can also reduce the consumption of the semiconductor pillar 1100 due to the removal process, which not only helps to reduce costs but also helps to increase storage density.

[0103] like Figure 18 As shown, the surface of the deposited first dielectric layer 1600 (e.g., the surface of the first dielectric layer 1600 away from the semiconductor pillar 1100) may have poor planarization, such as the presence of some unevenness or defects. For example, as... Figure 19 As shown, the surface of the first dielectric layer 1600 away from the semiconductor pillar 1100 can be planarized. Exemplarily, a planarization process such as chemical mechanical polishing can be used to remove unevenness defects on the surface of the first dielectric layer 1600 away from the semiconductor pillar 1100 to make the surface more flat.

[0104] Figures 20 to 22 This is a process step diagram of forming a capacitor contact structure 1700 according to the present application. It should be understood that the process for forming the capacitor contact structure 1700 provided in this application is only an example and not a specific limitation. In actual processes, the process for forming the capacitor contact structure 1700 can be reasonably set according to actual needs.

[0105] Figure 20 and Figure 21 This is a schematic diagram of the structure after forming the contact hole 600 according to an exemplary embodiment of this application, wherein... Figure 21 for Figure 20 A schematic diagram of the cross-section along the CC direction.

[0106] Figure 22 This is a schematic diagram of the structure after forming the capacitor contact structure 1700 according to an exemplary embodiment of this application.

[0107] Exemplarily, a capacitor contact structure 1700 may be formed that extends along the second direction Z through the first dielectric layer 1600 and to the semiconductor pillar 1100. The capacitor contact structure 1700 may include a contact layer 1710 and a multilayer conductive layer 1720 located on the contact layer 1710. Exemplarily, forming the capacitor contact structure 1700 may include forming a contact hole 600 that extends along the second direction Z through the first dielectric layer 1600 and to the semiconductor pillar 1100. Figure 20 and Figure 21 A contact layer 1710 is formed within the contact hole 600. Figure 22 ); and forming a multilayer conductive layer 1720 on the contact layer 1710. Figure 22 ).

[0108] For example, a portion of the first dielectric layer 1600, the fourth dielectric layer 1430, the third dielectric layer 1420, and the isolation dielectric layer 1320 may be removed along the second direction Z using photolithography, one or more dry etching and / or wet etching processes to form a contact hole 600 extending to the semiconductor pillar 1100; then one or more thin film deposition processes may be used to sequentially form a contact layer 1710 and a multilayer conductive layer 1720 within the contact hole 600 to form a capacitive contact structure 1700.

[0109] For example, the contact layer 1710 may contact the semiconductor pillar 1100, and its material includes, but is not limited to, at least one of semiconductor materials such as polysilicon, germanium silicon, etc. By setting the material of the contact layer 1710 to, for example, polysilicon, this application can reduce the resistance between the contacting semiconductor pillar 1100 (whose material may be, for example, silicon) and the contact layer 1710.

[0110] Exemplarily, the multilayer conductive layer 1720 may be located on one side of the contact layer 1710 along the second direction Z. The multilayer conductive layer 1720 may include one or more conductive materials such as metals and / or metal compounds. Exemplarily, forming the multilayer conductive layer 1720 may include: depositing, for example, cobalt metal on one side of the contact layer 1710 along the second direction Z, and reacting the cobalt metal with the contact layer 1710 to form cobalt silicide; then forming, for example, titanium nitride (TiN) and tungsten metal (W) surrounded by titanium nitride (TiN) on the cobalt silicide. By providing the multilayer conductive layer 1720 with various conductive materials such as cobalt silicide, titanium nitride (TiN), and tungsten metal (W), this application is beneficial to reduce the resistance between the contacting multilayer conductive layer 1720 and the contact layer 1710, as well as the resistance between different contacting layers in the multilayer conductive layer 1720.

[0111] For example, such as Figure 22As shown, along the second direction Z, the second dielectric layer 1410 may be located between the first dielectric layer 1600 and the isolation structure 1300, such as the isolation conductive layer 1310. A portion of the second dielectric layer 1410 may contact the capacitor contact structure 1700, such as the contact layer 710, along the first direction X, and a portion of the second dielectric layer 1410 may be adjacent to the semiconductor pillar 1100 along the first direction X.

[0112] Figure 23 yes Figure 22 An enlarged view of the middle part of the structure. Exemplarily, the end face S1 of the first dielectric layer 1600 away from the gate structure 1500 along the second direction Z may be coplanar with the end face S2 of the capacitor contact structure 1700 away from the semiconductor pillar 1100. Exemplarily, the capacitor contact structure 1700 and a portion of the semiconductor pillar 1100 may be adjacent to the first dielectric layer 1600 along the first direction X. At least a portion of the first dielectric layer 1600 is located on one side of the capacitor contact structure 1700 along the first direction X. The dimension H3 of the first dielectric layer 1600 along the second direction Z may be larger than the dimension H4 of the capacitor contact structure 1700 along the second direction Z.

[0113] In an exemplary embodiment of this application, a capacitor 1900 may also be formed connected to the capacitor contact structure 1700. Figure 25 The capacitor 1900 may include a first electrode (not shown) connected to the capacitor contact structure 1700, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1900 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. Exemplarily, the capacitor may be a vertical capacitor, wherein the first electrode, capacitor dielectric, and second electrode are stacked along a second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0114] Figure 24 To be Figure 22 This is a schematic diagram of a structure that has been thinned after being flipped 180°. For example, the gate structure 1500 can be disconnected from the side of the gate structure 1500 away from the first dielectric layer 1600.

[0115] Exemplarily, disconnecting the gate structure 1500 may include: removing a portion of the semiconductor layer 100 in a direction opposite to the second direction Z to expose the gate dielectric layer 1510; and removing a portion of the gate dielectric layer 1510 and the gate layer 1520 in a direction opposite to the second direction Z to expose the third dielectric layer 1420. Exemplarily, a reverse etching process may also be used to remove a portion of the gate layer 1520, such that the upper end of the gate layer 1520 in the second direction is located below the top surface of the semiconductor pillar 1100.

[0116] For example, a dielectric layer 1810 may also be formed in the removed space; and a gate lead-out structure 1800 may be formed through the dielectric layer 1810 and extending to the gate layer 1520.

[0117] This application enables the connection between the word line and the gate lead structure 1800 by connecting the gate lead structure 1800 to the gate layer 1520, thereby facilitating the transmission of electrical signals between the gate structure 1500 (such as the gate layer 1520) and the peripheral circuits through the gate lead structure 1800 and the word line.

[0118] Exemplarily, the dielectric layer 1810 and the gate lead structure 1800 can be formed by a combination of one or more dry etching and / or wet etching processes, and one or more thin film deposition processes. The material of the dielectric layer 1810 may include, but is not limited to, insulating materials such as oxides. The material of the gate lead structure 1800 may include, but is not limited to, metallic materials such as tungsten and copper.

[0119] Figure 25 This is a partial structural schematic diagram of a semiconductor structure provided according to an exemplary embodiment of this application.

[0120] For example, the semiconductor structure manufactured in this application may include a memory device with memory functionality. For instance... Figure 25 As shown, the storage device may include storage cells MC and word lines WL and bit lines BL coupled to the storage cells MC. Exemplarily, the storage device may include at least one of dynamic random access memory (DRAM), phase-change memory (PCM), and ferroelectric random access memory (FRAM). For ease of description, the following description primarily uses DRAM memory as an example.

[0121] The memory cell MC may include DRAM cells and may be arrayed along a first direction X and a third direction Y. Each DRAM cell may include a capacitor 1900 for storing bits of data as positive or negative charges and one or more transistors (also known as transistors, including portions of semiconductor pillar 1100 and gate structure 1500 corresponding to semiconductor pillar 1100) for controlling (e.g., switching and selecting) access to it. Exemplarily, the transistor may be a vertical transistor such as a vertical metal-oxide-semiconductor field-effect transistor (MOSFET) to facilitate the subsequent formation of capacitor 1900 on one side of the transistor along the second direction Z.

[0122] A word line WL can be coupled to a memory cell MC along a third direction Y to control the switching of vertical transistors in a row of memory cells MC located in the third direction Y. A bit line BL can be coupled to a memory cell MC along a first direction X to send data to and / or receive data from memory cells MC located in a column of memory cells MC located in the first direction X. That is, each word line WL can be coupled to a memory cell MC in the corresponding row and each bit line BL can be coupled to a memory cell MC in the corresponding column.

[0123] For example, the gate of the transistor (the portion of the gate structure 1500 corresponding to the semiconductor pillar 1100) can be connected to the word line WL, the drain to the bit line BL, and the source to the capacitor 1900. The voltage signal on the word line WL can control the transistor to turn on or off, thereby reading data information stored in the capacitor 1900 via the bit line BL, or writing data information into the capacitor 1900 for storage via the bit line BL.

[0124] Figures 26 to 30 This is a process step diagram of a method for manufacturing a semiconductor structure provided in another embodiment of this application.

[0125] For example, such as Figure 26 As shown, an isolation structure 2300 may be formed on a second side 2120 of the semiconductor pillar 2100 along a first direction X, opposite to the first side 2110. The isolation structure 2300 may extend along a third direction Y. The isolation structure 2300 may include an isolation conductive layer 2310 and an isolation dielectric layer 2320 surrounding the isolation conductive layer 2310. The isolation dielectric layer 2320 may be located on the second side 2120 of the semiconductor pillar 2100 and on the top surface of the semiconductor pillar 2100. The isolation conductive layer 2310 may be located on the side of the isolation dielectric layer 2320 away from the semiconductor pillar 2100 along the first direction X.

[0126] For example, a second dielectric layer 2410 extending along the second direction Z to the isolation structure 2300 may be formed on the second side 2120 of the semiconductor pillar 2100. The second dielectric layer 2410 may be located on the surface of the isolation dielectric layer 2320 and in contact with the isolation conductive layer 2310.

[0127] Exemplarily, a gate structure 2500 may also be formed on a first side 2110 of the semiconductor pillar 2100 along a first direction X. Exemplarily, the gate structure 2500 may extend along a third direction Y. The gate structure 2500 may include a gate dielectric layer 2510 and a gate layer 2520.

[0128] For example, such as Figure 26As shown, in the process of forming the gate dielectric layer 2510, a fourth dielectric layer 2430 may also be formed on the side of the second dielectric layer 2410 away from the isolation structure 2300 along the second direction Z. For example, the gate dielectric layer 2510 may be located on the first side 2110 of the semiconductor pillar 2100, and the fourth dielectric layer 2430 may be located on the surface of the second dielectric layer 2410 away from the isolation structure 2300 along the second direction Z. The gate dielectric layer 2510 and the fourth dielectric layer 2430 may be an integral structure. The gate layer 2520 may be located on the side of the gate dielectric layer 2510 away from the semiconductor pillar 2100 along the first direction X.

[0129] Exemplarily, a third dielectric layer 2420 may also be formed on the side of the gate layer 2520 away from the gate dielectric layer 2510. The third dielectric layer 2420 may be used to isolate adjacent gate layers 2520 along the first direction X. Exemplarily, the two side portions of the gate layer 2520 disposed along the second direction Z may be removed. For example, a back-etching process may be used to remove a portion of the third dielectric layer 2420 and the gate layer 2520 along the second direction Z to form a gap 700, wherein the upper end after the removal of a portion of the gate layer 2520 may be located below the top surface of the semiconductor pillar 2100.

[0130] It should be noted that, Figure 26 The structure shown is similar to Figure 17 The structures shown are the same or similar. To avoid redundancy, this application will not describe them in detail here; please refer to the above for specific details. Figures 2 to 17 The description.

[0131] For example, such as Figure 27 As shown, a first dielectric layer 2600 extending along the second direction Z to the gate structure 2500 can be formed on the first side 2110 of the semiconductor pillar 2100. The material of the first dielectric layer 2600 may be, for example, silicon oxide.

[0132] For example, a mechanical polishing process may be used to remove the fourth dielectric layer 2430, the second dielectric layer 2410, the gate dielectric layer 2510, the first dielectric layer 2600 and the isolation dielectric layer 2320 on one side of the semiconductor pillar 2100 along the second direction Z to expose the semiconductor pillar 2100.

[0133] For example, such as Figure 28 As shown, it is possible to Figure 27 Based on this, a dielectric layer 2700 is formed on one side of the semiconductor pillar 2100 along the second direction Z. The material of the dielectric layer 2700 may be, for example, silicon nitride.

[0134] For example, such as Figure 29 As shown, a contact hole 800 can be formed along the second direction Z, passing through the dielectric layer 2700 and extending to the semiconductor pillar 2100. For example, as... Figure 30As shown, a capacitive contact structure 2800 can be formed within the contact hole 800. The capacitive contact structure 2800 may include a contact layer 2810 and a multilayer conductive layer 2820 located on the contact layer 2810.

[0135] Figure 24 This is a schematic diagram of a semiconductor structure according to an exemplary embodiment of this application.

[0136] The semiconductor structure may include a plurality of semiconductor pillars 1100, a gate structure 1500, a first dielectric layer 1600, and a capacitive contact structure 1700. The gate structure 1500 may be located on a first side 1110 of the semiconductor pillars 1100 along a first direction X. The first dielectric layer 1600 may be located on the first side 1110 of the semiconductor pillars 1100 and extend to the gate structure 1500 along a second direction Z. The capacitive contact structure 1700 may extend through the first dielectric layer 1600 along the second direction Z and extend to the semiconductor pillars 1100.

[0137] Exemplarily, the first direction X, the second direction Z, and the third direction Y may intersect each other pairwise. Multiple semiconductor pillars 1100 are spaced apart from each other. The semiconductor pillars 1100 may have a cubic shape. It should be understood that the semiconductor pillars 1100 may have any suitable three-dimensional shape, such as a polyhedral shape or a cylindrical shape. That is, the cross-section of the semiconductor pillar 1100 in a planar view (e.g., in the XY plane) may have a square shape, a rectangular shape (or a trapezoidal shape), a circular shape (or an elliptical shape), or any other suitable shape. Exemplarily, the material of the semiconductor pillars 1100 may include single-crystal silicon, polycrystalline silicon, single-crystal germanium, group III-V compound semiconductor materials, group II-VI compound semiconductor materials, or at least one of other semiconductor materials known in the art.

[0138] In an exemplary embodiment of this application, the semiconductor structure may further include an isolation structure 1300 and a second dielectric layer 1410. The isolation structure 1300 may be located on a second side 1120 of the semiconductor pillar 1100 along a first direction X, opposite to the first side 1110. The second dielectric layer 1410 may be located on the second side 1120 of the semiconductor pillar 1100 and in contact with the isolation structure 1300.

[0139] For example, the isolation structure 1300 may include an isolation conductive layer 1310 and an isolation dielectric layer 1320 surrounding the isolation conductive layer 1310. The isolation dielectric layer 1320 may be located on the second side 1120 of the semiconductor pillar 1100 and the top surface of the semiconductor pillar 1100. The isolation conductive layer 1310 may be located on the side of the isolation dielectric layer 1320 away from the semiconductor pillar 1100 along a first direction X.

[0140] Exemplarily, the material of the insulating conductive layer 1310 may include, but is not limited to, metallic materials such as tungsten and copper. The material of the insulating dielectric layer 1320 may include, but is not limited to, silicon oxide. Exemplarily, such as Figure 10 As shown, the dimension H1 of the insulating conductive layer 1310 along the second direction Z can be smaller than the dimension H2 of the insulating dielectric layer 1320 along the second direction Z.

[0141] Exemplarily, the second dielectric layer 1410 may be located on the surface of the isolation dielectric layer 1320 and in contact with the isolation conductive layer 1310. Exemplarily, a portion of the second dielectric layer 1410 may be located on the second side 1120 of the semiconductor pillar 1100, and a portion of the second dielectric layer 1410 may be located on one side of the semiconductor pillar 1100 along the second direction Z. In other words, at least a portion of the second dielectric layer 1410 may have a T-shaped structure protruding toward the isolation conductive layer 1310.

[0142] Exemplarily, the material of the second dielectric layer 1410 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high dielectric constant material. Exemplarily, the material of the second dielectric layer 1410 may include silicon nitride.

[0143] Exemplarily, the gate structure 1500 may extend in a third direction Y. The gate structure 1500 may include a gate dielectric layer 1510 and a gate layer 1520. The gate dielectric layer 1510 may be located on a first side 1110 of the semiconductor pillar 1100. The gate layer 1520 may be located on a side of the gate dielectric layer 1510 away from the semiconductor pillar 1100.

[0144] For example, the end of the gate layer 1520 may be located below the end face of the semiconductor pillar 1100. The end of the gate layer 1520 may be located below the end face of the gate dielectric layer 1510. In this way, the portion of the gate layer 1520 corresponding to the semiconductor pillar 1100 can serve as the gate electrode. The gate structure 1500 (including the gate dielectric layer 1510 and the gate layer 1520) can be connected to a peripheral circuit to realize the transmission of electrical signals between the gate electrode and the peripheral circuit.

[0145] Exemplarily, the gate dielectric layer 1510 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For example, the gate dielectric layer 1510 may comprise silicon oxide. The gate layer 1520 may comprise one or more conductive materials such as metals and / or metal compounds such as tungsten W and / or titanium nitride TiN.

[0146] Exemplarily, the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a vertical transistor, wherein the semiconductor pillar 1100 can be used to form the active region of a plurality of channels in the vertical transistor. Exemplarily, the gate structure 1500 can be located on at least one sidewall of the semiconductor pillar 1100, i.e., the semiconductor pillar 1100 can be at least partially surrounded by the gate structure 1500. For example, the semiconductor pillar 1100, the gate dielectric layer 1510, and the gate layer 1520 can be arranged radially from the center of the vertical transistor in this order. Exemplarily, the gate dielectric layer 1510 can surround and contact the semiconductor pillar 1100. The gate layer 1520 can surround and contact the gate dielectric layer 1510.

[0147] It should be understood that Figure 24 The case shown where the gate structure 1500 is located on one sidewall of the semiconductor pillar 1100 is merely an example and not a specific limitation.

[0148] In one embodiment of this application, the gate structure 1500 may be located on multiple sidewalls of the semiconductor pillar 1100. In this case, the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a multi-gate transistor (e.g., a gate-all-around (GAA) transistor, a tri-gate transistor, or a dual-gate transistor). Multi-gate transistors can have a larger gate control area to achieve better channel control with a smaller subthreshold swing. During the off-state, the leakage current of the multi-gate transistor can also be significantly reduced because the channel is completely depleted. Therefore, using a multi-gate transistor can achieve better speed (saturation drain current) / leakage current performance.

[0149] In another embodiment of this application, the gate structure 1500 may be located on one sidewall of the semiconductor pillar 1100, in which case the semiconductor pillar 1100 and the gate structure 1500 can be used together to form a single-gate transistor. Exemplarily, adjacent single-gate transistors along the first direction X can be arranged symmetrically. By providing single-gate transistors, this application can significantly increase the density of the semiconductor pillars 1100 in the first direction X, reducing the difficulty of the manufacturing process. Furthermore, mirror-symmetric single-gate transistors can have a larger process window, which is beneficial for reducing subsequent bit lines, word lines, and the spacing between transistors.

[0150] In an exemplary embodiment of this application, the semiconductor structure may further include a third dielectric layer 1420. The third dielectric layer 1420 may be located on the side of the gate layer 1520 away from the gate dielectric layer 1510. The third dielectric layer 1420 may be used to isolate adjacent gate layers 1520 along the first direction X. Exemplarily, a portion of the third dielectric layer 1420 may contact the first dielectric layer 1600 along the first direction X, and a portion of the third dielectric layer 1420 may contact the gate layer 1520 along the first direction X. Exemplarily, the semiconductor structure may further include a fourth dielectric layer 1430 located between the first dielectric layer 1600 and the second dielectric layer 1410.

[0151] For example, the third dielectric layer 1420 and the fourth dielectric layer 1430 may comprise any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or a high-k dielectric. For instance, the third dielectric layer 1420 and the fourth dielectric layer 1430 may comprise silicon oxide.

[0152] Exemplarily, the first dielectric layer 1600 may be located on the first side 1110 of the semiconductor pillar 1100 and on one side of the second dielectric layer 1410 along the second direction Z. Exemplarily, the first dielectric layer 1600 may extend along the first direction X and protrude toward the gate structure 1500 along the second direction Z, such as protruding toward the gate layer 1520 in the gate structure 1500. The portion of the first dielectric layer 1600 protruding toward the gate layer 1520 may contact the gate layer 1520 and may be adjacent to the semiconductor pillar 1100 along the first direction X. In other words, the portion of the first dielectric layer 1600 protruding toward the gate layer 1520 may be located below the end face of the semiconductor pillar 1100. Exemplarily, the first dielectric layer 1600 may include a first end 1610 along the second direction Z near the gate layer 1520, wherein the first end 1610 may have an inverted U-shaped structure and surround a portion of the third dielectric layer 1420. At this time, a portion of the third dielectric layer 1420 can contact the first dielectric layer 1600 along the first direction X, and a portion of the third dielectric layer 1420 can contact the gate layer 1520 along the first direction X.

[0153] Exemplarily, the material of the first dielectric layer 1600 may include any one or any combination of two or more of silicon nitride, silicon oxynitride, and aluminum oxide. Furthermore, the first dielectric layer 1600 may be doped with at least one of carbon, boron, and phosphorus. Exemplarily, the material of the first dielectric layer 1600 may be, for example, silicon nitride.

[0154] In this application, by setting the material of the first dielectric layer 1600, such as silicon nitride, it is beneficial to reduce the risk of coupling between the gate layer 1520 and the capacitor contact structure 1700, thereby reducing the risk of leakage in the semiconductor structure, and also to reduce the risk of coupling between two adjacent capacitor contact structures 1700 along the first direction X, thereby reducing the risk of leakage in the semiconductor structure.

[0155] On the other hand, this application provides a first dielectric layer 1600 located on the first side 1110 of the semiconductor pillar 1100 and extending along the second direction Z to the gate structure 1500. For example, the first dielectric layer 1600 can be located on the first side 1110 of the semiconductor pillar 1100 and the second dielectric layer 1410 along the second direction Z. This not only simplifies the process steps but also reduces the consumption of the semiconductor pillar 1100, thereby not only reducing costs but also increasing storage density.

[0156] For example, such as Figure 22 As shown, along the second direction Z, the second dielectric layer 1410 may be located between the first dielectric layer 1600 and the isolation structure 1300, such as the isolation conductive layer 1310. A portion of the second dielectric layer 1410 may contact the capacitor contact structure 1700, such as the contact layer 710, along the first direction X, and a portion of the second dielectric layer 1410 may be adjacent to the semiconductor pillar 1100 along the first direction X.

[0157] The capacitive contact structure 1700 may include a contact layer 1710 and a multilayer conductive layer 1720. The contact layer 1710 may contact the semiconductor pillar 1100. The multilayer conductive layer 1720 may be located on the contact layer 1710.

[0158] For example, the contact layer 1710 may contact the semiconductor pillar 1100, and its material includes, but is not limited to, at least one of semiconductor materials such as polysilicon, germanium silicon, etc. By setting the material of the contact layer 1710 to, for example, polysilicon, this application can reduce the resistance between the contacting semiconductor pillar 1100 (whose material may be, for example, silicon) and the contact layer 1710.

[0159] Exemplarily, the multilayer conductive layer 1720 may be located on one side of the contact layer 1710 along the second direction Z. The multilayer conductive layer 1720 may include one or more conductive materials such as metals and / or metal compounds. Exemplarily, forming the multilayer conductive layer 1720 may include: depositing, for example, cobalt metal on one side of the contact layer 1710 along the second direction Z, and reacting the cobalt metal with the contact layer 1710 to form cobalt silicide; then forming, for example, titanium nitride (TiN) and tungsten metal (W) surrounded by titanium nitride (TiN) on the cobalt silicide. By providing the multilayer conductive layer 1720 with various conductive materials such as cobalt silicide, titanium nitride (TiN), and tungsten metal (W), this application is beneficial to reduce the resistance between the contacting multilayer conductive layer 1720 and the contact layer 1710, as well as the resistance between different contacting layers in the multilayer conductive layer 1720.

[0160] For example, such as Figure 23As shown, the first dielectric layer 1600 may include a first end 1610 along the second direction Z away from the capacitor contact structure 1700, wherein the first end 1610 may have an inverted U-shaped structure and surround a portion of the third dielectric layer 1420. The end face S1 of the first dielectric layer 1600 along the second direction Z away from the gate structure 1500 may be coplanar with the end face S2 of the capacitor contact structure 1700 away from the semiconductor pillar 1100. Exemplarily, the capacitor contact structure 1700 and a portion of the semiconductor pillar 1100 may be adjacent to the first dielectric layer 1600 along the first direction X. At least a portion of the first dielectric layer 1600 is located on one side of the capacitor contact structure 1700 along the first direction X. The dimension H3 of the first dielectric layer 1600 along the second direction Z may be larger than the dimension H4 of the capacitor contact structure 1700 along the second direction Z.

[0161] In an exemplary embodiment of this application, the semiconductor structure may further include a capacitor 1900 connected to the capacitor contact structure 1700. Figure 25 The capacitor 1900 may include a first electrode (not shown) connected to the capacitor contact structure 1700, a capacitor dielectric (not shown) in contact with the first electrode, and a second electrode (not shown) in contact with the capacitor dielectric. The capacitor 1900 may include, but is not limited to, planar capacitors, stacked capacitors, multi-fin capacitors, cylindrical capacitors, trench capacitors, or substrate-planar capacitors. Exemplarily, the capacitor may be a vertical capacitor, wherein the first electrode, capacitor dielectric, and second electrode are stacked along a second direction Z, and the capacitor dielectric may be sandwiched between the first electrode and the second electrode.

[0162] In an exemplary embodiment of this application, the semiconductor structure may further include a dielectric layer 1810 and a gate lead-out structure 1800. The dielectric layer 1810 may be located on one side of the gate structure along the second direction Z. The gate lead-out structure 1800 may penetrate the dielectric layer 1810 and extend to the gate layer 1520. The gate lead-out structure 1800 is connected to the gate layer 1520, which enables the connection between the word line and the gate lead-out structure 1800, thereby facilitating the transmission of electrical signals between the gate structure 1500 (e.g., the gate layer 1520) and the peripheral circuitry through the gate lead-out structure 1800 and the word line. Exemplarily, the material of the dielectric layer 1810 may include, but is not limited to, insulating materials such as oxides. The material of the gate lead-out structure 1800 may include, but is not limited to, metallic materials such as tungsten and copper.

[0163] Since the content and structure described above in the method 1000 for manufacturing a semiconductor structure can be applied in whole or in part to the semiconductor structure described herein, related or similar content will not be repeated here.

[0164] Although exemplary structures and fabrication methods of semiconductor structures have been described herein, it is understood that one or more features may be omitted, substituted, or added from the fabrication methods of the semiconductor structure. Furthermore, the layers and materials described are merely exemplary.

[0165] Figure 31 This is a block diagram of a system 10 having a storage system 12 according to an exemplary embodiment of this application.

[0166] System 10 can be a mobile phone, desktop computer, laptop, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device (which has a storage system 12 located therein). Figure 31 As shown, system 10 may include a host 18 and a storage system 12, the storage system 12 having one or more semiconductor structures (such as including 3D memory 14) and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to and from 3D memory 14.

[0167] The three-dimensional memory 14 may include the semiconductor structure described in any embodiment of this application. According to some embodiments, a controller 16 is coupled to the three-dimensional memory 14 and the host 18 and is configured to control the three-dimensional memory 14. The controller 16 may manage data stored in the three-dimensional memory 14 and communicate with the host 18. For example, the controller 16 may communicate with an external device (e.g., the host 18) according to a specific communication protocol.

[0168] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A semiconductor structure, comprising: Multiple semiconductor pillars; A gate structure is located on a first side of the semiconductor pillar along a first direction; A first dielectric layer is located on the first side of the semiconductor pillar and extends along the second direction to the gate structure; and A capacitive contact structure extends along the second direction through the first dielectric layer and to the semiconductor pillar; The first direction intersects with the second direction.

2. The semiconductor structure according to claim 1, wherein, The first dielectric layer extends along the first direction and protrudes toward the gate structure along the second direction.

3. The semiconductor structure according to claim 2, wherein, The material of the first dielectric layer includes nitrides.

4. The semiconductor structure according to claim 1, wherein, The semiconductor structure also includes: An isolation structure is located on the second side of the semiconductor pillar along the first direction, opposite to the first side; and A second dielectric layer is located on the second side of the semiconductor pillar and is in contact with the isolation structure; Wherein, the second dielectric layer is located between the first dielectric layer and the isolation structure along the second direction; and A portion of the second dielectric layer is in contact with the capacitor contact structure along the first direction, and a portion of the second dielectric layer is adjacent to the semiconductor pillar along the first direction.

5. The semiconductor structure according to claim 1, wherein, The capacitor contact structure includes: Contact layer, in contact with the semiconductor pillar; and A multilayer conductive layer is located on the contact layer.

6. The semiconductor structure according to claim 2, wherein, The gate structure includes: A gate dielectric layer is located on the first side of the semiconductor pillar; and A gate layer is located on the side of the gate dielectric layer away from the semiconductor pillar.

7. The semiconductor structure according to any one of claims 1-6, wherein, The semiconductor structure also includes: A third dielectric layer is located on the side of the gate layer away from the gate dielectric layer, wherein a portion of the third dielectric layer is in contact with the first dielectric layer along the first direction and a portion of the third dielectric layer is in contact with the gate layer along the first direction.

8. The semiconductor structure according to claim 4, wherein, The semiconductor structure also includes: The fourth dielectric layer is located between the first dielectric layer and the second dielectric layer.

9. The semiconductor structure according to claim 2, wherein, The portion of the first dielectric layer that protrudes toward the gate structure is in contact with the gate structure and is adjacent to the semiconductor pillar along the first direction.

10. The semiconductor structure according to any one of claims 7, wherein, The first dielectric layer includes a first end located away from the capacitor contact structure along the second direction, wherein the first end has an inverted U-shaped structure and surrounds a portion of the third dielectric layer.

11. The semiconductor structure according to any one of claims 1-6, wherein, The dimension of the first dielectric layer along the second direction is larger than the dimension of the capacitor contact structure along the second direction.

12. The semiconductor structure according to any one of claims 1-6, wherein, At least a portion of the first dielectric layer is located on one side of the capacitor contact structure along the first direction.

13. The semiconductor structure according to claim 12, wherein, The capacitive contact structure and a portion of the semiconductor pillars are adjacent to the first dielectric layer along the first direction.

14. The semiconductor structure according to any one of claims 1-6, wherein, The end face of the first dielectric layer away from the gate structure along the second direction is coplanar with the end face of the capacitor contact structure away from the semiconductor pillar along the second direction.

15. The semiconductor structure according to any one of claims 7, wherein, The material of the third dielectric layer includes oxides.

16. A method for manufacturing a semiconductor structure, comprising: Multiple semiconductor pillars are formed within the semiconductor layer; A gate structure is formed on a first side of the semiconductor pillar along a first direction; A first dielectric layer extending in a second direction to the gate structure is formed on the first side of the semiconductor pillar; as well as A capacitive contact structure is formed that passes through the first dielectric layer along the second direction and extends to the semiconductor pillar; The first direction intersects with the second direction.

17. The method according to claim 16, wherein, The method further includes: An isolation structure is formed on the second side of the semiconductor pillar along the first direction, opposite to the first side; and A second dielectric layer is formed on the second side of the semiconductor pillar, extending along the second direction to the isolation structure. The second dielectric layer is located between the first dielectric layer and the isolation structure along the second direction. The capacitive contact structure passes through the first dielectric layer and the second dielectric layer along the second direction and extends to the semiconductor pillar. A portion of the second dielectric layer contacts the capacitive contact structure along the first direction, and a portion of the second dielectric layer is adjacent to the semiconductor pillar along the first direction.

18. The method according to claim 17, wherein, A first dielectric layer extending in a second direction to the gate structure is formed on the first side of the semiconductor pillar, comprising: The first dielectric layer is formed on the first side of the semiconductor pillar and on the side of the second dielectric layer in a direction opposite to the second direction, wherein the first dielectric layer extends in the first direction and protrudes toward the gate structure in the second direction, and the portion of the first dielectric layer protruding toward the gate structure contacts the gate structure and is adjacent to the semiconductor pillar in the first direction.

19. The method according to claim 18, wherein, The method further includes: The surface of the first dielectric layer away from the semiconductor pillar is planarized.

20. The method according to claim 18, wherein, The capacitor contact structure includes a contact layer and multiple conductive layers located on the contact layer. The formation of a capacitive contact structure that extends along the second direction through the first dielectric layer and to the semiconductor pillar includes: A contact hole is formed that passes through the first dielectric layer along the second direction and extends to the semiconductor pillar; The contact layer is formed within the contact hole; and The multilayer conductive layer is formed on the contact layer.

21. The method according to claim 17, wherein, An isolation structure is formed on the second side of the semiconductor pillar along the first direction, opposite to the first side, comprising: Multiple initial semiconductor pillars are formed within the semiconductor layer; Forming a plurality of first trenches that pass through the initial semiconductor pillar along a third direction and are arranged along the first direction; and The isolation structure is formed on the second side of the semiconductor pillar via the first trench; The first direction, the second direction, and the third direction intersect each other.

22. The method according to claim 21, wherein, A gate structure is formed on a first side of the semiconductor pillar along the first direction, including: Forming a plurality of second trenches passing through the initial semiconductor pillar along the third direction and arranged along the first direction, wherein the plurality of first trenches and the plurality of second trenches divide the initial semiconductor pillar into a plurality of semiconductor pillars; and The gate structure is formed on the first side of the semiconductor pillar via the second trench.

23. The method according to claim 22, wherein, The gate structure includes a gate dielectric layer and a gate layer. The gate structure is formed on the first side of the semiconductor pillar via the second trench, including: The gate dielectric layer is formed on the first side of the semiconductor pillar via the second trench; and The gate layer is formed on the side of the gate dielectric layer away from the semiconductor pillar.

24. The method according to claim 23, wherein, The method further includes: A third dielectric layer is formed on the side of the gate layer away from the gate dielectric layer via the second trench, wherein the first dielectric layer includes a first end away from the capacitor contact structure along the second direction, the first end having an inverted U-shaped structure and surrounding a portion of the third dielectric layer.

25. The method according to claim 21, wherein, Multiple initial semiconductor pillars are formed within the semiconductor layer, including: A plurality of isolation portions are formed within the semiconductor layer, wherein the plurality of isolation portions divide a portion of the semiconductor layer into a plurality of the initial semiconductor pillars.

26. The method according to any one of claims 16-25, wherein, The method further includes: The gate structure is disconnected from the side of the gate structure away from the first dielectric layer.

27. A storage system, wherein, include: The semiconductor structure as described in any one of claims 1 to 15; as well as A controller, coupled to the semiconductor structure, is used to control the semiconductor structure to store data.

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