Memory device and manufacturing method thereof

Abstract

The embodiment of the invention provides a memory device and a manufacturing method thereof, and the memory device comprises a semiconductor structure; the semiconductor structure includes a semiconductor pillar extending in a first direction; the gate structure is located on at least one side of the semiconductor column; the first doped regions are located at the two opposite ends of the semiconductor column in the first direction; the doping concentration of the first side, close to the gate structure, of the first doped region is larger than the doping concentration of the second side, away from the gate structure, of the first doped region in the direction from the gate structure to the semiconductor column.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a memory device and a method for manufacturing the same. Background Technology

[0002] Memory devices, such as Dynamic Random Access Memory (DRAM), are among the most important access components in electronic systems. They typically employ a 1T1C structure, consisting of a transistor and a capacitor, as a single memory cell. This 1T1C structure allows DRAM to achieve high integration density and low cost, giving it an irreplaceable position in computer memory devices. With the rapid development of semiconductor technology, DRAM is rapidly evolving towards higher density and higher quality. Summary of the Invention

[0003] In view of the above, this disclosure provides a memory device and a method for manufacturing the same.

[0004] According to a first aspect of the present disclosure, a memory device is provided, comprising: a semiconductor structure; the semiconductor structure comprising: a semiconductor pillar extending along a first direction; a gate structure located on at least one side of the semiconductor pillar; and a first doped region located at opposite ends of the semiconductor pillar along the first direction; wherein, along a direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on a first side closer to the gate structure is greater than the doping concentration of the first doped region on a second side farther from the gate structure.

[0005] In one alternative implementation, the doping concentration of the first doped region decreases along the direction of the gate structure toward the semiconductor pillar.

[0006] In one optional embodiment, the first doped region includes a first portion located at a first end of the semiconductor pillar and a second portion located at a second end of the semiconductor pillar, the first end and the second end being opposite ends of the semiconductor pillar along the first direction; wherein, the distance between the end face of the gate structure near the first portion and the end face of the first portion near the gate structure along the first direction, and the distance between the end face of the gate structure near the second portion and the end face of the second portion near the gate structure, are both less than or equal to a first preset threshold.

[0007] In one optional implementation, the first preset threshold ranges from 5nm to 10nm.

[0008] In one optional embodiment, the semiconductor structure includes a plurality of semiconductor structures, which are arranged adjacently and separated by a dielectric layer; the first doped region extends by a first predetermined dimension from the side contacting the dielectric layer toward the gate structure in the direction pointing toward the semiconductor pillar; in the direction of the gate structure pointing toward the semiconductor pillar, the maximum doping concentration of the first doped region is located on the side of the first doped region in contact with the dielectric layer.

[0009] In one optional embodiment, the semiconductor structure further includes a source and a drain; the source and the drain are respectively located at a first portion and a second portion of the first doped region away from the gate structure along the first direction; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the first doped region.

[0010] In one alternative embodiment, the doping concentration of the source decreases in the direction from the first end to the second end, and the doping concentration of the drain decreases in the direction from the second end to the first end.

[0011] In one optional embodiment, the semiconductor structure further includes a channel region, which is the region between the source and the drain, excluding the first doped region; the minimum doping concentration of the first doped region is greater than the maximum doping concentration of the channel region.

[0012] In one optional embodiment, the semiconductor structure comprises a plurality of semiconductor structures, which are arranged adjacently and separated by a dielectric layer; the doping ion concentration of the dielectric layer is less than or equal to a second preset threshold.

[0013] In one optional embodiment, the plurality of semiconductor structures includes a first semiconductor structure and a second semiconductor structure disposed adjacent to each other; the gate structures of the first semiconductor structure and the second semiconductor structure are both located on the side of the respective semiconductor pillars away from the dielectric layer; the plurality of semiconductor structures further includes a third semiconductor structure located on the side of the first semiconductor structure away from the second semiconductor structure; the memory device further includes a word line isolation structure, the gate structures of the third semiconductor structure and the gate structures of the first semiconductor structure are separated by the word line isolation structure; the dimension of the word line isolation structure along the first direction is larger than the dimension of the gate structure along the first direction.

[0014] In one optional embodiment, the plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure disposed adjacent to each other; the gate structure of the first semiconductor structure and the gate structure of the second semiconductor structure are both located on the side of the corresponding semiconductor pillar away from the dielectric layer; the first semiconductor structure and the second semiconductor structure further include: a second doped region, the second doped region extending from the side in contact with the dielectric layer toward the gate structure by a second predetermined dimension, and the doping type of the second doped region is different from the doping type of the source and the drain.

[0015] In one alternative implementation, the minimum doping concentration of both the source and the drain is greater than the maximum doping concentration of the second doped region.

[0016] In one optional implementation, the source and drain are N-type doped, and the second doped region is P-type doped.

[0017] According to a second aspect of the present disclosure, a memory device is provided, comprising: a semiconductor pillar array including a plurality of rows of semiconductor pillars and a plurality of columns of semiconductor pillars; the semiconductor pillars extending along a first direction; a plurality of word lines; one word line covering a portion of the sidewall of a row of semiconductor pillars; a first doped region located at opposite ends of the semiconductor pillars in the first region along the first direction, the first region being a region through which both word lines and bit lines pass; in a direction pointing from the word lines to the semiconductor pillars, the doping concentration of the first doped region on a first side near the word lines is greater than the doping concentration of the first doped region on a second side away from the word lines; a third doped region located at opposite ends of the semiconductor pillars in the second region along the first direction; the second region being located between the first region and the third region, the third region being used to provide a word line contact structure; the doping concentration of the third doped region on the first side near the word lines is equal to the doping concentration of the third doped region on the second side away from the word lines.

[0018] In one optional embodiment, the distance between the end face of the word line near the first doped region and the end face of the first doped region near the word line along the first direction is less than or equal to a first preset threshold; the distance between the end face of the word line near the third doped region and the end face of the third doped region near the word line along the first direction is greater than the first preset threshold.

[0019] In one optional implementation, the first preset threshold ranges from 5nm to 10nm.

[0020] In one optional embodiment, the dimension of the first doped region along a preset direction is less than or equal to the dimension of the semiconductor pillar along the preset direction; the preset direction is the same as the arrangement direction of each semiconductor pillar in a column of semiconductor pillars; the dimension of the third doped region along the preset direction is equal to the dimension of the semiconductor pillar along the preset direction.

[0021] In an optional embodiment, the memory device further includes: a source and a drain; both the first doped region and the third doped region include a first portion located at a first end of the semiconductor pillar and a second portion located at a second end of the semiconductor pillar, the first end and the second end being opposite ends of the semiconductor pillar along the first direction; the source and the drain are respectively located at the ends of the first and second portions of the first doped region / third doped region away from the word line along the first direction; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the first doped region; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the third doped region.

[0022] According to a third aspect of the present disclosure, a method for fabricating a memory device is provided, comprising: providing a semiconductor layer; forming a semiconductor structure in the semiconductor layer; the semiconductor structure comprising: a semiconductor pillar, a gate structure, and a first doped region; forming the semiconductor structure comprising: forming a semiconductor pillar extending along a first direction; forming the gate structure on at least one side of the semiconductor pillar; forming the first doped region at opposite ends of the semiconductor pillar along the first direction; wherein, along the direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on a first side closer to the gate structure is greater than the doping concentration of the first doped region on a second side farther from the gate structure.

[0023] In one optional embodiment, forming the gate structure and the first doped region includes: forming a first initial gate covering at least one side of the semiconductor pillar; removing a portion of the first initial gate from a first surface and a second surface of the semiconductor layer along the first direction to form the gate structure and expose a portion of the semiconductor pillar; the first surface and the second surface are two surfaces of the semiconductor layer opposite each other along the first direction; and forming the first doped region from the surface exposing the portion of the semiconductor pillar in a region extending a first predetermined size perpendicular to the first direction.

[0024] In one alternative embodiment, forming the gate structure and the first doped region includes: forming a sacrificial layer at the bottom of at least one side of the semiconductor pillar; forming a second initial gate covering the corresponding side of the semiconductor pillar on the sacrificial layer; removing a portion of the top of the second initial gate and the sacrificial layer to form the gate structure and expose the top and bottom of the corresponding side of the semiconductor; and forming the first doped region, respectively, starting from the surface of the exposed semiconductor pillar and extending to a region of a first predetermined size perpendicular to the first direction.

[0025] In one alternative embodiment, forming the first doped region includes: starting from the surface of a partially exposed semiconductor pillar, forming a first portion and a second portion of the first doped region in a region extending a first predetermined size perpendicular to the first direction using a molecular layer deposition process or a rapid vapor phase doping process.

[0026] In one optional embodiment, forming a first portion of the first doped region includes: starting from a first surface of the semiconductor layer, along the first direction, removing a portion of the first initial gate to form a third initial gate, thereby exposing a portion of the semiconductor pillar; starting from the surface exposing the partial semiconductor pillar, forming a first initial portion of the first doped region extending a first predetermined size perpendicular to the first direction; starting from the first surface of the semiconductor layer, along the first direction, doping a portion of the first initial portion away from the third initial gate using an ion implantation process, with the doped portion forming a source; and the remaining first initial portion not doped by the ion implantation process forming the first portion of the first doped region.

[0027] In one optional embodiment, forming a second portion of the first doped region includes: after forming the source and the first portion, removing a portion of the third initial gate from the second surface of the semiconductor layer along the first direction to form the gate structure to expose a portion of the semiconductor; forming a second initial portion of the first doped region from the surface of the exposed semiconductor pillar in a region extending a first predetermined size perpendicular to the first direction; doping a portion of the second initial portion away from the gate structure by an ion implantation process from the second surface of the semiconductor layer along the first direction, with the doped portion forming the drain; and the remaining second initial portion not doped by the ion implantation process forming the second portion of the first doped region.

[0028] In one optional embodiment, forming the first portion and the second portion of the first doped region includes: forming a drain at the bottom of at least one side of the semiconductor pillar by a diffusion process; forming a first initial portion and a second portion of the first doped region extending in a region perpendicular to the first direction from the top and bottom of the respective side of the semiconductor pillar, respectively, into a region of a first predetermined size; starting from the top of the semiconductor layer, doping a portion of the first initial portion away from the gate structure along the first direction by an ion implantation process, wherein the doped portion forms a source; and the remaining first initial portion that has not been doped by the ion implantation process forms the first portion of the first doped region.

[0029] This disclosure provides a memory device and a method for fabricating the same. The method includes: providing a semiconductor layer; forming a semiconductor structure in the semiconductor layer; the semiconductor structure includes: a semiconductor pillar, a gate structure, and a first doped region; forming the semiconductor structure includes: forming a semiconductor pillar extending along a first direction; forming a gate structure on at least one side of the semiconductor pillar; forming first doped regions at opposite ends of the semiconductor pillar along the first direction; and, along the direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on the first side near the gate structure is greater than the doping concentration of the first doped region on the second side away from the gate structure. In this disclosure, when forming the gate structure, removing the initial gate (first / second initial gate) exposes a portion of the surface of the semiconductor pillar, providing a positioning reference for the formation position of the first doped region. This increases the alignment accuracy between the first doped region and the gate structure, reduces the alignment difficulty, and improves the reliability of the memory device. Furthermore, the greater doping concentration of the first doped region on the first side near the gate structure compared to the second side helps reduce the lateral (X-direction) electric field and improves the performance and reliability of the memory device. Attached Figure Description

[0030] In the accompanying drawings (which are not necessarily drawn to scale), similar reference numerals may describe similar parts in different views. Similar reference numerals with different letter suffixes may indicate different examples of similar parts. The drawings illustrate, by way of example and not limitation, the various embodiments discussed herein.

[0031] Figure 1 This is a schematic diagram of the circuit connection of a transistor provided in an embodiment of this disclosure;

[0032] Figure 2A A schematic diagram of the structure of a dynamic random access memory provided in this embodiment of the present disclosure;

[0033] Figure 2B for Figure 2AEnlarged view of region A in the middle;

[0034] Figure 2C A partial structural diagram of a dynamic random access memory provided in an embodiment of this disclosure;

[0035] Figure 3 A schematic flowchart illustrating a method for fabricating a memory device according to an embodiment of this disclosure;

[0036] Figure 4 A schematic flowchart illustrating a method for forming a semiconductor structure according to an embodiment of this disclosure;

[0037] Figures 5A to 5C A cross-sectional schematic diagram of the process of forming a semiconductor pillar provided in an embodiment of this disclosure;

[0038] Figures 5D to 5J A cross-sectional schematic diagram of the process of forming a gate structure and a first doped region provided for an embodiment of this disclosure;

[0039] Figures 6A to 6B A cross-sectional schematic diagram of a process for forming a memory device provided in an embodiment of this disclosure;

[0040] Figures 7A to 7D A cross-sectional schematic diagram of another process for forming a memory device provided in this disclosure;

[0041] Figure 8A This is a schematic diagram of the structure of a memory device provided in an embodiment of the present disclosure;

[0042] Figure 8B for Figure 8A Enlarged view of region C in the middle;

[0043] Figure 9 This is a schematic diagram of the structure of another memory device provided in an embodiment of the present disclosure. Detailed Implementation

[0044] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0045] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0046] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0047] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0048] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0049] In order to gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0050] The memory devices involved in the embodiments of this disclosure are at least a portion of those to be used in subsequent processes to form the final device structure. Here, the final device may include memory, including but not limited to dynamic random access memory (DRAM). The following description uses DRAM as an example only. However, it should be noted that the following descriptions of DRAM in the embodiments are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0051] With the development of dynamic random access memory technology, the size of memory cells is getting smaller and smaller, and their array architecture has increased from 8F. 2 Go to 6F 2 Then go to 4F 2 Furthermore, based on the requirements of dynamic random access memory for ions and leakage current, the memory architecture has evolved from planar array transistors to recessed gate array transistors, then from recessed gate array transistors to buried saddle fin array transistors, and finally from buried saddle fin array transistors to vertical gate transistors.

[0052] In practical applications, regardless of whether it is a planar transistor, a recessed gate array transistor, a buried transistor, or a vertical gate transistor, dynamic random access memory is composed of multiple memory cell structures. Each memory cell structure mainly consists of a transistor and a memory cell (storage capacitor) controlled by the transistor. That is, dynamic random access memory includes an architecture of 1 transistor (T) and 1 capacitor (C) (1T1C). Its main working principle is to use the amount of charge stored in the capacitor to represent whether a binary bit is 1 or 0.

[0053] Figure 1 This is a circuit connection diagram of a 1T1C architecture provided in an embodiment of this disclosure, as shown below. Figure 1 As shown, the drain of transistor T is electrically connected to the bit line (BL), the source of transistor T is electrically connected to one of the electrode plates of capacitor C, the other electrode plate of capacitor C is grounded through the ground terminal (GND), and the gate of transistor T is connected to the word line (WL). The voltage applied through the word line WL controls the transistor T to turn on or off. The bit line BL is used to perform read or write operations on transistor T when it is turned on.

[0054] The following is combined Figure 2AOne architecture of dynamic random access memory is described in detail. In the introduction... Figure 2A Before illustrating the memory device, we first define the various directions that may be used in the following description. The direction of extension of the semiconductor pillar is defined as the first direction (i.e., the Z direction). A second direction (i.e., the X direction) and a third direction (i.e., the Y direction) are defined in a plane perpendicular to the Z direction. In some embodiments, the X, Y, and Z directions may be mutually perpendicular.

[0055] Figure 2A This is a cross-sectional view of a three-dimensional (3D) dynamic random access memory 100 including vertical transistors provided in an embodiment of this disclosure; as shown... Figure 2A As shown, the dynamic random access memory 100 includes a first device 102 and a second device 104 stacked on top of the first device 102 along the Z-axis direction. The first device 102 and the second device 104 are connected via a bonding interface 106. The first device 102 and the second device 104 can be connected by a hybrid bonding method or the like. In some embodiments, the second device 104 can be bonded face-to-face to the top of the first device 102 at the bonding interface 106. The first device 102 may include a first substrate 1010, peripheral circuitry 1012 located on one side of the first substrate 1010, and a first interconnect layer 1016 located on the side of the peripheral circuitry 1012 away from the first substrate 1010. The first interconnect layer 1016 is used to transmit electrical signals of the peripheral circuitry 1012. The peripheral circuitry 1012 may include a plurality of transistors 1014. In some embodiments, trench isolation (such as shallow trench isolation (STI)) and doped regions (such as the well, source and drain of transistor 1014) may also be formed on or in the first substrate 1010.

[0056] The first device 102 may further include a first bonding layer 1018 located at the bonding interface 106 and on the side of the first interconnect layer 1016 away from the peripheral circuit 1012. The first bonding layer 1018 may include a plurality of first bonding contacts 1019 and a dielectric material electrically isolating the first bonding contacts 1019. The first bonding contacts 1019 in the first bonding layer 1018 and the surrounding dielectric material can be used for mixed bonding. Conversely, the second device 104 may also include a second bonding layer 1020 located at the bonding interface 106 and on the side of the first bonding layer 1018 away from the first interconnect layer 1016. The second bonding layer 1020 may include a plurality of second bonding contacts 1021 and a dielectric material electrically isolating the second bonding contacts 1021. The second bonding contacts 1021 in the second bonding layer 1020 and the surrounding dielectric material can be used for mixed bonding. Here, the second bonding contact 1021 contacts the first bonding contact 1019 at the bonding interface 106.

[0057] In some embodiments, the peripheral circuitry 1012 may further include word lines and word line drivers / row decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. In other embodiments, the peripheral circuitry 1012 may further include bit lines 1023 and bit line drivers / column decoders coupled to the second interconnect layer 1022 via second bonding contacts 1021 in the second bonding layer 1020, first bonding contacts 1019 in the first bonding layer 1018, and the first interconnect layer 1016. Here, the second interconnect layer 1022 includes bit lines 1023 above the second bonding layer 1020, and the bit lines 1023 are used to transmit electrical signals. In other embodiments, the stacked first device 102 and second device 104 may not be connected by bonding, but rather integrated on the same substrate (only the first substrate, no second substrate), and directly connected through one or more interconnect layers between the first device 102 and the second device 104. In this case, the first device 102 does not have a first bonding layer 1018 and a first bonding contact 1019; the second device 104 does not have a second bonding layer 1020 and a second bonding contact 1019; and the bonding interface 106 between the first device 102 and the second device 104 also does not exist.

[0058] refer to Figure 2A The second device 104 also includes a memory cell array located on the second interconnect layer 1022. The memory cell array may include a plurality of memory cells 1024, a second substrate 1048 located on the memory cells 1024, and a third interconnect layer 1050 located on the second substrate 1048. Figure 2A The cross section of the dynamic random access memory 100 can be cut along the bit line direction (X-axis direction), and a bit line 1023 in the second interconnect layer 1022 extending laterally in the X-axis direction can be coupled to a column of memory cells 1024.

[0059] Here, each memory cell 1024 may include a vertical transistor 1026 and a capacitor structure 1028 coupled to the vertical transistor 1026; the vertical transistor 1026 includes a semiconductor pillar 1030 extending vertically (in the Z-axis direction) and a gate structure 1036 contacting one side of the semiconductor pillar 1030 in the bit line direction (X-axis direction); in other embodiments, the gate structure may also completely surround the semiconductor pillar, partially surround the semiconductor pillar, or be located on two opposite sides of the semiconductor pillar, etc., which will not be elaborated here. Here, the gate structure 1036 includes a gate electrode 1034 and a gate dielectric 1032 located between the gate electrode 1034 and the semiconductor pillar 1030 in the bit line direction (X-axis direction). In some embodiments, the gate dielectric 1032 is adjacent to one side of the semiconductor pillar 1030, and the gate electrode 1034 is adjacent to the gate dielectric 1032.

[0060] In some embodiments, the semiconductor pillar 1030 has two ends (upper end and lower end) in the vertical direction (Z-axis direction). The vertical transistor 1026 may also include a source 1038 and a drain 1040 respectively disposed at the two ends (upper end and lower end) of the semiconductor pillar 1030 in the vertical direction (Z-axis direction). (The positions of the source and drain can be interchanged; here and below, the upper end is the source 1038 and the lower end is the drain 1040 as an example.) In some embodiments, the source 1038 is coupled to the capacitor 1028, and the drain 1040 is coupled to the bit line 1023.

[0061] Since the gate electrode can be part of a word line or extend as a word line in the word line direction, the second device 104 of the dynamic random access memory 100 can also include multiple word lines, each extending in the word line direction (Y-axis direction). Here, each word line 1034 can be coupled to a row of memory cells 1024.

[0062] Vertical transistor 1026 extends vertically through and contacts word line 1034, and its drain 1040 at its lower end contacts bit line 1023. Therefore, due to the vertical arrangement of vertical transistor 1026, word line 1034 and bit line 1023 can be arranged in different planes in the vertical direction, which simplifies the wiring of word line 1034 and bit line 1023. Here, vertical transistor 1026 can be arranged in a mirror-symmetric manner to increase the density of memory cells 1024 in the bit line direction (X-axis direction). Two adjacent vertical transistors 1026 in the bit line direction are mirror-symmetric with respect to trench isolation 1060; that is, the second device 104 may include a plurality of trench isolations 1060, each trench isolation 1060 extending parallel to word line 1034 in the word line direction (Y-axis direction) and disposed between semiconductor pillars 1030 of two adjacent rows of vertical transistor 1026. In some embodiments, the rows of vertical transistors 1026 separated by trench isolation 1060 are mirror-symmetrical to each other with respect to trench isolation 1060. It should be understood that trench isolation 1060 may include air gaps, each air gap being laterally disposed between adjacent semiconductor pillars 1030. The second device 104 also includes a plurality of gate isolations 1062, each gate isolation 1062 extending parallel to word lines 1034 in the word line direction (Y-axis direction) and disposed between word lines 1034 of two adjacent rows of vertical transistors 1026. It should be understood that the dimensions of the gate isolations 1062 and word lines 1034 in the bit line direction (X-axis direction) may be the same as or different from the dimensions of the trench isolation 1060 in the bit line direction (X-axis direction); when their dimensions in the bit line direction (X-axis direction) are different, the spacing between the plurality of semiconductor pillars 1030 arranged along the bit line direction (X-axis direction) is different, i.e., the plurality of semiconductor pillars 1030 arranged along the bit line direction (X-axis direction) are non-uniformly arranged.

[0063] like Figure 2A As shown, the capacitor structure 1028 is located above and in contact with the source 1038 (i.e., the upper end of the semiconductor pillar 1030) of the vertical transistor 1026. The capacitor structure 1028 can be a vertical capacitor.

[0064] like Figure 2AAs shown, the second device 104 may further include a capacitive contact 1047 that contacts the common plate of the vertical transistor 1026 for coupling the second electrode 1046 of the capacitor structure 1028 to the peripheral circuit 1012 or directly to ground. In some embodiments, the material forming the interlayer dielectric (ILD) layer of the capacitor structure 1028 includes, but is not limited to, silicon oxide. The construction of the capacitor structure 1028 may include any suitable structure and construction, such as a planar capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-planar capacitor.

[0065] like Figure 2A As shown, the vertical transistor 1026 extends vertically through and contacts the word line 1034. The drain 1040 at its lower end contacts the bit line 1023, and the source 1038 at its upper end contacts the capacitor structure 1028. That is, due to the vertical arrangement of the vertical transistor 1026, the bit line 1023 and the capacitor structure 1028 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 1026 of the memory cell 1024. In some embodiments, the bit line 1023 and the capacitor structure 1028 are arranged on opposite sides of the vertical transistor 1026 in the vertical direction. Compared to conventional memory cells where the bit line and capacitor structure are arranged on the same side of a planar transistor, this simplifies the wiring of the bit line 1023 and reduces the coupling capacitance between the bit line 1023 and the capacitor structure 1028.

[0066] In some embodiments, the vertical transistor 1026 is vertically disposed between the capacitor structure 1028 and the bonding interface 106. That is, the vertical transistor 1026 can be arranged closer to the peripheral circuitry 1012 and the bonding interface 106 of the first device 102 than the capacitor structure 1028. Since the bit line 1023 and the capacitor structure 1028 are coupled to opposite ends of the vertical transistor 1026, the bit line 1023 (as part of the second interconnect layer 1022) is vertically disposed between the vertical transistor 1026 and the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0067] In some embodiments, the second device 104 further includes a second substrate 1048 disposed above the memory cell 1024, and a third interconnect layer 1050 with pads leading out above the memory cell 1024. The third interconnect layer 1050 with pads leading out may include interconnects in one or more ILD layers, such as contact pads 1054.

[0068] In some embodiments, the second device 104 further includes one or more contacts 1052 extending through a portion of the third interconnect layer 1050 and a second substrate 1048 to couple the pads out of the third interconnect layer 1050 to the memory cell 1024 and the second interconnect layer 1022. Thus, peripheral circuitry 1012 can be coupled to memory cell 1024 via the first interconnect layer 1016 and the second interconnect layer 1022, as well as the second bonding layer 1020 and the first bonding layer 1018, and peripheral circuitry 1012 and memory cell 1024 can be coupled to external circuitry via the contacts 1052 and the pads out of the third interconnect layer 1050.

[0069] refer to Figure 2A and Figure 2B In some embodiments, in order to improve the hot carrier injection (HCI) effect, lightly doped drain (LDD) 1064 is formed at both ends (upper and lower ends) of the semiconductor pillar 1030.

[0070] For example, after forming a gate structure 1036 on one side of the semiconductor pillar 1030, a lightly doped region 1064 is formed at the upper end of the semiconductor pillar 1030 using a diffusion process, and a lightly doped region 1064 is formed at the lower end of the semiconductor pillar 1030 using an ion implantation process.

[0071] Because the position and depth of the lightly doped region 1064 are difficult to control, the alignment between the lightly doped region 1064 and the gate structure 1036 becomes more challenging. In some embodiments, such as Figure 2B As shown, there is excessive overlap between the lightly doped region 1064 and the gate structure 1036. For example, the height of the overlap between the lightly doped region 1064 at the upper end of the semiconductor pillar 1030 and the gate structure 1036 in the Z-axis direction is h1. When h1 is too large, it will increase the risk of gate-induced drain leakage current (GIDL) effect and also lead to... Figure 2A A short circuit between bit line 1023 and word line / gate electrode 1034 or between word line / gate electrode 1034 and capacitor structure 1028.

[0072] Figure 2C This is a partial structural diagram of a dynamic random access memory provided in an embodiment of this disclosure. It should be noted that... Figure 2C To and Figure 2A An enlarged view of the corresponding location in region A. (See diagram below.) Figure 2CAs shown, in other embodiments, there is no overlap between the lightly doped region 1064 and the gate structure 1036 in the Z-axis direction. However, the distance between the bottom surface of the lightly doped region 1064 at the upper end of the semiconductor pillar 1030 and the top surface of the gate structure 1036 in the Z-axis direction is h2, and the distance between the top surface of the lightly doped region 1064 at the lower end of the semiconductor pillar 1030 and the bottom surface of the gate structure 1036 in the Z-axis direction is h2. In other words, the gate structure 1036 has a smaller vertical dimension than the vertical dimension (such as the depth in the Z-axis direction) of the semiconductor pillar 1030. When h2 is too large, it will reduce the control capability of the gate structure 1036 over the channel region 1037 (the region between the source 1038 and the drain 1040, excluding the lightly doped region 1064), thereby reducing the performance and reliability of the memory device.

[0073] In some embodiments, such as Figure 2B and Figure 2C As shown, a dynamic random access memory (DRAM) includes multiple vertical transistors (1026-1, 1026-2, 1026-3, and 1026-4). To prevent mutual coupling between adjacent transistors, isolation structures (such as trench 1060) are often used to reduce mutual coupling. For example, in... Figure 2A In the architecture of the dynamic random access memory shown, in order to prevent back-to-back adjacent transistors ( Figure 2B and Figure 2C The mutual coupling of vertical transistors 1026-2 and 1026-3 shown in the diagram is often reduced by trench isolation 1060, which includes a metal shielding layer, to decrease the mutual coupling of adjacent transistors back-to-back. However, as the integration density of memory devices increases and their size and critical dimensions continue to shrink, the distance between adjacent transistors also becomes smaller. The manufacturing process for setting up the metal shielding layer is difficult and costly, which is detrimental to future miniaturization of memory devices.

[0074] Therefore, to address one or more of the aforementioned problems, this disclosure also provides a method for fabricating a memory device. (See reference...) Figure 3 , Figure 3 This is a schematic flowchart illustrating a method for fabricating a memory device according to an embodiment of the present disclosure; the method includes:

[0075] Step S10: Provide a semiconductor layer;

[0076] Step S20: Form a semiconductor structure in the semiconductor layer; the semiconductor structure includes: semiconductor pillars, gate structure and first doped region.

[0077] It should be noted that a memory device may include multiple semiconductor structures; here and in the following text, we will take the example of a memory device including multiple semiconductor junctions.

[0078] Figure 4 This is a schematic flowchart of a method for forming a semiconductor structure according to an embodiment of the present disclosure, as shown below. Figure 3 and Figure 4 As shown, Figure 3 Step S20 in the process of forming a semiconductor structure includes:

[0079] Step S201: Form a semiconductor pillar extending along the first direction;

[0080] Step S202: Form a gate structure on at least one side of the semiconductor pillar;

[0081] Step S203: A first doped region is formed at opposite ends of the semiconductor pillar along a first direction; along the direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on the first side closer to the gate structure is greater than the doping concentration of the first doped region on the second side farther from the gate structure.

[0082] It should be understood that Figure 4 The steps shown are not exclusive; other steps may be performed before, after, or between any of the steps shown. Figure 4 The steps shown can be adjusted in order according to actual needs.

[0083] As mentioned earlier, there can be various different relative positions between the gate structure and the semiconductor pillar in a memory device, and different relative positions correspond to different specific fabrication methods. In this embodiment, the two gate structures corresponding to two adjacent semiconductor pillars are respectively arranged back-to-back. Figure 2A The example shown is a back-to-back arrangement. Based on this, a memory device may include multiple semiconductor pillars arranged in an array along the X-axis and Y-axis directions. However, it should be understood that the following methods for forming semiconductor structures are for illustrative purposes only and are not intended to limit the scope of this disclosure.

[0084] There are various methods for forming semiconductor pillars, gate structures, and first doped regions. Several methods are illustrated by way of example in the embodiments of this disclosure. The formation process of semiconductor pillars, gate structures, and first doped regions in memory devices will be described in detail below with reference to the accompanying drawings.

[0085] Figures 5A to 5C This is a cross-sectional schematic diagram illustrating the process of forming a semiconductor pillar according to an embodiment of this disclosure. It should be noted that... Figure 5C for Figure 5B A schematic diagram of the cross-section along the AA' direction is shown below; the formation process of multiple semiconductor pillars is described in detail below with reference to the accompanying drawings.

[0086] refer to Figure 5A A semiconductor layer 2000 is provided, having opposing first and second surfaces along a first direction (i.e., the Z direction). The semiconductor layer 2000 may be made of a semiconductor material, such as silicon; more specifically, the semiconductor layer 2000 may be made of single-crystal silicon.

[0087] refer to Figure 5B , Figure 5C A plurality of semiconductor pillars 2010 arranged in an array are formed in the semiconductor layer 2000, and the semiconductor pillars 2010 extend along a first direction. In some embodiments, the formation of the semiconductor pillars 2010 may include: first forming a plurality of trenches extending along the X-axis direction in the semiconductor layer 2000, filling the trenches with an insulating material (such as silicon oxide), and then forming a plurality of trenches extending along the Y-axis direction in the semiconductor layer 2000, wherein the trenches extending along the Y-axis direction are adjusted according to the relative position between the gate structure and the semiconductor pillars. Figure 5B The diagram shows that when two gate structures corresponding to two adjacent semiconductor pillars are arranged back to back, the trenches extending along the Y-axis include alternately arranged trenches of different sizes. After removing the remaining insulating material that previously filled the trenches, an array of semiconductor pillars 2010 is formed.

[0088] It should be noted that, Figure 5C The semiconductor pillar 2010 shown in the figure has a square shape along the X and Y axes. This shape is only for example and is not intended to limit the shape of the semiconductor pillar in this cross section. The shape of the semiconductor pillar in this cross section may also include rectangle, circle, ellipse, and approximate shapes of these shapes.

[0089] In other embodiments, the method of forming the semiconductor pillar 2010 may also include: first forming multiple trenches extending along the Y-axis in the semiconductor layer 2000, filling the trenches with an insulating material (such as silicon oxide), and then forming multiple trenches extending along the X-axis in the semiconductor layer 2000.

[0090] In some specific embodiments, trenches along the X-axis and / or Y-axis can be formed by photolithography (here and hereinafter, this can be understood as lithography-etching (LE)). Methods for filling the trenches with insulating material include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), and atomic layer deposition (ALD).

[0091] In some embodiments, forming a gate structure and a first doped region includes: forming a first initial gate covering at least one side of a semiconductor pillar; removing a portion of the first initial gate from a first surface and a second surface of the semiconductor layer along a first direction to form a gate structure and expose a portion of the semiconductor pillar; the first surface and the second surface are two surfaces of the semiconductor layer opposite each other along the first direction; and forming a first doped region from the surface exposing the portion of the semiconductor pillar to a region extending a first predetermined size perpendicular to the first direction.

[0092] Figures 5D to 5J This is a cross-sectional schematic diagram illustrating the process of forming a gate structure and a first doped region, as provided in an embodiment of this disclosure.

[0093] refer to Figure 5D A first dielectric layer 2011 and a first initial gate 2014 covering at least one side of a semiconductor pillar are formed in a trench extending along the Y-axis direction. It is understood that the first dielectric layer 2011 between adjacent semiconductor pillars 2010 is similar to... Figure 2A The function of the trench isolation 1060. For example, the material of the first dielectric layer 2011 is silicon oxide.

[0094] In some embodiments, the first initial gate 2014 may include an initial gate electrode 2013 and an initial gate dielectric 2012. Optionally, the first initial gate 2014 may further include a barrier layer located between the initial gate electrode 2013 and the initial gate dielectric 2012. The material of the initial gate electrode 2013 may include, but is not limited to, tungsten; the material of the initial gate dielectric 2012 may include, but is not limited to, silicon oxide; and the material of the barrier layer may include, but is not limited to, titanium nitride.

[0095] In some embodiments, the method for forming the first initial gate 2014 includes, but is not limited to, processes such as deposition and etching; the method for forming the first dielectric layer 2011 includes, but is not limited to, processes such as PVD, CVD, and ALD.

[0096] In some embodiments, forming the first doped region includes: starting from the surface of a partially exposed semiconductor pillar, forming a first portion and a second portion of the first doped region in a region extending a first predetermined size perpendicular to a first direction using a molecular layer deposition (MLD) or rapid vapor phase doping (RVD) process.

[0097] refer to Figure 5EIn some embodiments, starting from the first surface of the semiconductor layer and along a first direction, a portion of the first initial gate is removed to form a third initial gate 2014' and an opening 2015 to expose a portion of the semiconductor pillar 2010. In some specific embodiments, the method for removing a portion of the first initial gate includes, but is not limited to, dry etching. The third initial gate 2014' may include an intermediate gate electrode 2013' and an intermediate gate dielectric 2012'.

[0098] refer to Figure 5F A first initial portion 2016 is formed in a region extending from the surface of the exposed semiconductor pillar 2010 to a first preset size w1 perpendicular to the first direction, forming a first doped region.

[0099] In some embodiments, a first initial portion 2016 of the first doped region is formed in a region extending a first predetermined size w1 perpendicular to a first direction using a molecular layer deposition process or a rapid vapor phase doping process. For example, the first initial portion 2016 of the first doped region is formed using a boron (B)-containing first dopant via a molecular layer deposition process, or the first initial portion 2016 of the first doped region is formed using a phosphorus (P)-containing second dopant via a rapid vapor phase deposition doping process.

[0100] In some embodiments, the distance between the end face of the third initial gate 2014' near the first initial portion 2016 of the first doped region and the end face of the first initial portion 2016 of the first doped region near the third initial gate 2014' along the first direction is less than or equal to a first preset threshold.

[0101] It is understandable that when the height of the overlapping region between the first initial portion 2016 of the first doped region and the third initial gate 2014' in the Z-axis direction is less than or equal to the first preset threshold, the risk of the GIDL effect is greatly reduced.

[0102] By removing part of the first initial gate to form the third initial gate 2014' and the opening 2015, an accurate positioning reference is provided for forming the first initial portion 2016 of the first doped region. In addition, the surface of the semiconductor pillar 2010 exposed by the opening 2015 has a significant difference in material from the third initial gate 2014'. Therefore, the third initial gate 2014' can act as a barrier layer or stop layer in the process of forming the first initial portion 2016 of the first doped region, thereby making the formation position of the first initial portion 2016 of the first doped region highly aligned with the position of the third initial gate 2014' in the first direction.

[0103] Understandable, Figure 5FThe size h3 of the first initial portion 2016 of the first doped region in the first direction (Z direction) is related to the depth of the opening 2015. For example, the size h3 of the first initial portion 2016 of the first doped region in the first direction (Z direction) is equal to the depth of the opening 2015.

[0104] Molecular layer deposition (MLD) and rapid vapor phase doping (XPV) processes do not require photolithography masks to define the doping region, thus avoiding the influence of photolithography alignment errors and improving the alignment accuracy between the first doped region and the gate structure formed in subsequent processes. Furthermore, MLD and XPV processes achieve material deposition by controlling surface chemical reactions, which can be performed under very precise conditions. By adjusting the reaction conditions, precise control over the formation position of the doped region can be achieved. For example, the first initial portion 2016 of the first doped region formed along the opening 2015 using MLD or XPV can be considered an ultra-shallow junction. The first preset size w1 is the junction depth of the ultra-shallow junction, and the size of the first preset size w1 can be controlled by process parameters (temperature or concentration, etc.).

[0105] In practical applications, the first preset dimension w1 is mainly related to the diameter of the semiconductor pillar 2010. The larger the diameter of the semiconductor pillar 2010, the larger the first preset dimension w1 can be set.

[0106] In some embodiments, the ratio of the diameter of the semiconductor pillar to the first preset size w1 ranges from 1 to 10. For example, the ratio of the diameter of the semiconductor pillar to the first preset size w1 can be 1, 5, or 10. It should be noted that when the ratio of the diameter of the semiconductor pillar to the first preset size w1 is 1, it indicates that the size of the first doped region in the X direction is equal to the diameter of the semiconductor pillar.

[0107] It should be noted that the ratio range of the diameter and width of the semiconductor pillar 2010 to the first preset size w1 is merely an illustrative example and is not intended to limit the ratio range of the diameter and width of the semiconductor pillar 2010 to the first preset size w1 in the embodiments of this disclosure.

[0108] In some implementations, the first preset size w1 ranges from 5nm to 10nm, and more specifically, the first preset size w1 can be 5nm, 7nm or 10nm.

[0109] like Figure 5FAs shown, in some embodiments, in the direction from the third initial gate 2014' to the semiconductor pillar 2010 in the semiconductor structure, the doping concentration of the first initial portion 2016 of the first doped region near the third initial gate 2014' is greater than the doping concentration of the second initial portion 2016 of the first doped region away from the third initial gate 2014'.

[0110] In some embodiments, the doping concentration of the first initial portion 2016 of the first doped region decreases along the direction from the third initial gate 2014' toward the semiconductor pillar 2010. The doping concentration of the first initial portion 2016 of the first doped region has a concentration gradient in the X direction, which helps to reduce the lateral (X direction) electric field and improve the performance and reliability of the memory device.

[0111] refer to Figure 5G Starting from the first surface of the semiconductor layer, along a first direction, the portion of the first initial portion 2016 furthest from the third initial gate 2014' is doped using an ion implantation process, and the doped portion forms the source 2017; the remaining first initial portion that has not been doped by the ion implantation process forms the first portion 2018-1 of the first doped region. In some embodiments, the minimum doping concentration of the source 2017 is greater than the maximum doping concentration of the first portion 2018-1 of the first doped region.

[0112] refer to Figure 5G and Figure 5H After forming the source 2017 and the first portion 2018-1 of the first doped region, the semiconductor layer is flipped; starting from the second surface of the semiconductor layer, along the first direction, a portion of the third initial gate 2014' is removed to form the gate structure 2022 and the cavity 2023 to expose a portion of the semiconductor pillar 2010.

[0113] In some embodiments, the gate structure 2022 includes a gate electrode 2021 and a gate dielectric 2020.

[0114] In some implementations, such as Figure 5G and Figure 5H As shown, after forming the source 2017 and the first portion 2018-1 of the first doped region, dielectric material is filled into the opening 2015 to form the second dielectric layer 2019 and the semiconductor layer is flipped to perform back-side thinning. The material of the second dielectric layer 2019 can be the same as or different from the material of the first dielectric layer 2011. For example, the material of the second dielectric layer 2019 and the material of the first dielectric layer 2011 are both silicon oxide.

[0115] In some embodiments, a plurality of trenches extending in the X direction and arranged in the Y direction can be formed from the back side (second surface) of the semiconductor layer. These trenches are located on adjacent semiconductor pillars 2010 along the Y direction. The trench formation locations can be referenced. Figure 5C The location shown in region B is understood. By removing a portion of the third initial gate 2014' through the aforementioned trench removal, a gate structure 2022 and a cavity 2023 are formed to expose a portion of the semiconductor pillar 2010.

[0116] refer to Figure 5I A second initial portion 2024 of the first doped region is formed in a region extending perpendicular to the first direction and into a region with a first preset size w1, starting from the surface of the exposed semiconductor pillar 2010.

[0117] refer to Figures 5I to 5J Starting from the second surface of the semiconductor layer, along the first direction, the portion of the second initial portion 2024 away from the gate structure 2022 is doped by ion implantation, and the doped portion forms the drain 2025; the remaining second initial portion 2024 that has not been doped by ion implantation forms the second portion 2018-2 of the first doped region.

[0118] In some implementations, the minimum doping concentration of the drain 2025 is greater than the maximum doping concentration of the second portion 2018-2 of the first doped region.

[0119] In some embodiments, a dielectric material is filled into the cavity 2023 to form a third dielectric layer 2026, preventing the semiconductor structure from collapsing and enhancing the support effect. For example... Figure 5J As shown, the third dielectric layer 2026, the second dielectric layer 2019, and the remaining first dielectric layer 2011 constitute the dielectric layer 2027. The first doped region 2018 includes a first portion 2018-1 and a second portion 2018-2 of the first doped region.

[0120] exist Figure 5J In any of the semiconductor structures in the memory device shown, in the direction from the gate structure 2022 to the semiconductor pillar 2011, the doping concentration of the first doped region 2018 on the first side near the gate structure 2022 is greater than the doping concentration of the second side of the first doped region 2018 away from the gate structure 2022.

[0121] exist Figure 5J In any of the semiconductor structures in the memory device shown, the doping concentration of the first doped region 2018 decreases along the direction from the gate structure 2022 toward the semiconductor pillar 2010.

[0122] In some embodiments, the distance between the end face of the gate structure 2022 near the first portion 2018-1 and the end face of the first portion 2018-1 near the gate structure 2022 along a first direction (reference) Figure 2B (For understanding h1) and the spacing between the end face of the gate structure 2022 near the second part 2018-2 and the end face of the second part 2018-2 near the gate structure 2022 (refer to h1). Figure 2B (For understanding h1) all are less than or equal to the first preset threshold.

[0123] The method of this disclosure improves the alignment accuracy between the first doped region and the gate structure. In the first direction, the distance between the bottom surface of the first portion of the first doped region at the first end of the semiconductor pillar and the top surface of the gate structure, and the distance between the top surface of the second portion of the first doped region at the second end of the semiconductor pillar and the bottom surface of the gate structure, are both less than or equal to a first preset threshold. This improves the reliability of the memory device. It should be understood that this alignment requires excluding minor deviations caused by manufacturing errors, etc.

[0124] In some embodiments, the range of the first preset threshold is 5nm to 10nm. More specifically, the first preset threshold is 5nm, 7nm, or 10nm.

[0125] It should be noted that, Figure 2B h1 and Figure 2C The h2 values ​​are all much greater than the first preset threshold.

[0126] Figures 6A to 6B This is a cross-sectional schematic diagram illustrating another process for forming a memory device according to an embodiment of this disclosure. Figure 5J After the steps, refer to Figure 6A A portion of the dielectric layer 2027 between the semiconductor pillars 2010 of the first semiconductor structure 201 and the second semiconductor structure 202 of the memory device is removed. Specifically, a portion of the first dielectric layer 2011 between the semiconductor pillars 2010 of the first semiconductor structure 201 and the second semiconductor structure 202 is removed to form an opening 2028 that exposes a portion of the surface of the semiconductor pillars of the first semiconductor structure 201 and the second semiconductor structure 202.

[0127] refer to Figure 6B A second doped region 2030 is formed in a region extending a second predetermined size w2 perpendicular to the first direction using a molecular layer deposition process or a rapid vapor phase doping process. Subsequently, dielectric material is filled into the openings of the semiconductor pillars exposing the first semiconductor structure 201 and the second semiconductor structure 202 to form a fourth dielectric layer 2029. The fourth dielectric layer 2029, the third dielectric layer 2026, the second dielectric layer 2019, and the remaining first dielectric layer 2011 constitute dielectric layer 2031.

[0128] like Figure 6B As shown, the second doped region 2030 extends a second preset size w2 from the side that contacts the dielectric layer (fourth dielectric layer 2029) toward the gate structure 2022, and the doping type of the second doped region is different from the doping type of the source 2017 and the drain 2025.

[0129] In practical applications, the second preset dimension w2 is mainly related to the diameter of the semiconductor pillar 2010. The larger the diameter of the semiconductor pillar 2010, the larger the second preset dimension w2 can be set.

[0130] In some implementations, the first preset size w1 and the second preset size w2 may be the same or different.

[0131] In some embodiments, the ratio of the diameter of the semiconductor pillar 2010 to the second preset size w2 ranges from 2 to 7. For example, the ratio of the diameter of the semiconductor pillar to the second preset size w2 can be 2, 3, 4, 5, 6 or 7.

[0132] In some implementations, when the diameter of the semiconductor pillar is 10-20 nm, the second preset size w2 ranges from 1 nm to 10 nm. More specifically, the second preset size w2 can be 1 nm, 5 nm, or 10 nm.

[0133] It should be noted that the ratio range of the diameter and width of the semiconductor pillar 2010 to the second preset size w2 is merely an illustrative example and is not intended to limit the ratio range of the diameter and width of the semiconductor pillar 2010 to the second preset size w2 in the embodiments of this disclosure.

[0134] In some embodiments, the minimum doping concentration of both the source 2017 and the drain 2025 is greater than the maximum doping concentration of the second doping region 2030.

[0135] In some embodiments, the source 2017 and drain 2025 are N-type doped, and the second doped region 2030 is P-type doped.

[0136] In this embodiment of the present disclosure, by providing a second doped region with a different doping type than that of the source and drain in the semiconductor pillars of the adjacent semiconductor structures, extending from the side in contact with the dielectric layer toward the gate structure with a second preset size, when one of the first and second semiconductor structures is turned on, the channel region of the turned-on semiconductor structure becomes high voltage. By providing the second doped region to form a barrier layer, electrons can be prevented from easily moving through the channel region of the turned-on transistor semiconductor structure to the dielectric layer and entering the channel region of the other semiconductor structure to affect the other semiconductor structure. This can improve the coupling effect between the adjacent first and second semiconductor structures in the semiconductor structure and is more conducive to the future miniaturization of memory devices.

[0137] Figures 7A to 7D A cross-sectional schematic diagram of another process for forming a memory device provided in this disclosure.

[0138] refer to Figures 5A to 5C The method and related descriptions form semiconductor pillars 2010.

[0139] Next reference Figure 7A A sacrificial layer 2032 is formed at the bottom of at least one side of the semiconductor pillar 2010. A second initial gate 2033 covering the corresponding side of the semiconductor pillar 2010 is formed on the sacrificial layer 2032. The second initial gate 2033 may include an initial gate electrode 2013 and an initial gate dielectric 2012. The structure and composition of the second initial gate 2033 can be found in [reference needed]. Figure 5D The first initial gate 2014 in the process is understood.

[0140] exist Figure 5C Subsequently, it forms in the groove extending along the Y-axis direction. Figure 7A The first dielectric layer 2011 is shown in the diagram. It is understood that... Figure 7A The first dielectric layer 2011 between adjacent semiconductor pillars 2010 is similar. Figure 2A The function of the trench isolation 1060. For example, the material of the first dielectric layer 2011 is silicon oxide.

[0141] refer to Figure 7A and Figure 7B The top portion of the second initial gate 2033 and the sacrificial layer 2032 is removed to form the gate structure 2034 and the opening 2035, exposing the top and bottom of the corresponding sides of the semiconductor pillar 2010. In some embodiments, the material of the sacrificial layer 2032 includes, but is not limited to, silicon nitride or silicon oxynitride.

[0142] In some embodiments, a first doped region is formed, starting from the surface of a partially exposed semiconductor pillar and extending to a region of a first predetermined size perpendicular to a first direction.

[0143] In some embodiments, forming the first doped region includes: starting from the surface of a partially exposed semiconductor pillar, forming a first portion and a second portion of the first doped region in a region extending a first predetermined size perpendicular to a first direction using a molecular layer deposition process or a rapid vapor phase doping process.

[0144] refer to Figure 7C A drain 2036 is formed at the bottom of at least one side of the semiconductor pillar 2010 by a diffusion process; a first initial portion 2037-1' and a second portion 2037-2 of the first doped region are formed in a region extending perpendicular to the first direction and with a first preset size w1, starting from the top and bottom of the respective side of the semiconductor pillar 2010.

[0145] It should be noted that, starting from the exposure of the semiconductor pillar 2010 surface from the top and bottom of the corresponding side along the opening 2035, and simultaneously forming the first initial portion 2037-1' and the second portion 2037-2 of the first doped region using a molecular layer deposition process or a rapid vapor phase doping process, a third portion 2039 is also formed between the drain 2036 at the bottom of the opening 2035. In subsequent processes, the drain 2036 and the third portion 2039 will be connected to the bit line. (Reference) Figure 7D Starting from the top of the semiconductor layer, along the first direction, the portion of the first initial part away from the gate structure 2034 is doped by ion implantation, and the doped portion forms the source 2038; the remaining first initial part that is not doped by ion implantation forms the first part 2037-1 of the first doped region.

[0146] In some embodiments, after forming the drain, source, and first doped region, a dielectric material is filled into the opening to form a fifth dielectric layer 2040. The material of the fifth dielectric layer 2040 includes, but is not limited to, silicon oxide. In embodiments of this disclosure, when forming the gate structure, removing the initial gate (first / second / third initial gate) exposes a portion of the surface of the semiconductor pillar, providing a positioning reference for the formation position of the first doped region. This increases the alignment accuracy between the first doped region and the gate structure, reduces the alignment difficulty, and improves the reliability of the memory device. Furthermore, the doping concentration of the first doped region on the first side near the gate structure is greater than the doping concentration on the second side of the first doped region away from the gate structure, which helps to reduce the lateral (X-direction) electric field and improve the performance and reliability of the memory device.

[0147] It should be noted that the embodiments of this disclosure show the case where the semiconductor pillar has the same size on the Z-axis, but this shape is only for example and is not used to limit the size of the semiconductor pillar on the Z-axis. It is not excluded that the semiconductor pillar may be wider at the top and narrower at the bottom due to factors such as manufacturing process deviations.

[0148] This disclosure also provides a memory device. Figure 8A This is a schematic diagram of the structure of a memory device provided in an embodiment of the present disclosure. Figure 8A The architecture of the memory device shown in the figure is related to Figure 2A The same structure shown can be referenced. Figure 2A To understand the relevant descriptions, it is important to note that... Figure 8A The structure of the vertical transistor (semiconductor structure) in the middle is similar to Figure 2A The difference of the vertical transistor 1026.

[0149] Figure 8B for Figure 8A An enlarged diagram of region C in the middle, as shown below. Figure 8B As shown, the memory device includes: a semiconductor structure; the semiconductor structure includes: a semiconductor pillar 2010 extending along a first direction; a gate structure 2022 located on at least one side of the semiconductor pillar 2010; and a first doped region 2018 located at opposite ends of the semiconductor pillar 2010 along the first direction; along the direction from the gate structure 2022 to the semiconductor pillar 2010, the doping concentration of the first doped region 2018 on the first side near the gate structure 2022 is greater than the doping concentration of the first doped region 2018 on the second side away from the gate structure 2022.

[0150] In some embodiments, the gate structure 2022 includes a gate electrode 2021 and a gate dielectric 2020. Optionally, the gate structure 2022 may further include a barrier layer located between the gate electrode 2021 and the gate dielectric 2020. The material of the gate electrode may include, but is not limited to, tungsten; the material of the gate dielectric may include, but is not limited to, silicon oxide; and the material of the barrier layer may include, but is not limited to, titanium nitride.

[0151] The doping concentration of the first doped region on the first side closer to the gate structure is greater than the doping concentration on the second side farther from the gate structure, which helps to reduce the lateral (X-direction) electric field and improve the performance and reliability of the memory device.

[0152] In some embodiments, the doping concentration of the first doped region 2018 decreases along the direction from the gate structure 2022 toward the semiconductor pillar 2010.

[0153] In some embodiments, the first doped region includes a first portion 2018-1 located at a first end of the semiconductor pillar 2010 and a second portion 2018-2 located at a second end of the semiconductor pillar 2010, wherein the first end and the second end are two opposite ends of the semiconductor pillar 2010 along a first direction; wherein the distance between the end face of the gate structure 2022 near the first portion 2018-1 and the end face of the first portion 2018-1 near the gate structure 2022 along the first direction, and the distance between the end face of the gate structure 2022 near the second portion 2018-2 and the end face of the second portion 2018-2 near the gate structure 2022, are both less than or equal to a first preset threshold.

[0154] In some embodiments, the range of the first preset threshold is 5nm to 10nm. More specifically, the first preset threshold can be 5nm, 7nm, or 10nm.

[0155] In some embodiments, the semiconductor structure includes multiple semiconductor structures, which are arranged adjacently and spaced apart by a dielectric layer 2025. For example, as shown... Figure 8B As shown, the first semiconductor structure 201 and the second semiconductor structure 202, which are arranged adjacent to each other, are separated by a dielectric layer 2031.

[0156] In some embodiments, the material of the dielectric layer 2031 includes, but is not limited to, silicon oxide.

[0157] In some embodiments, the first doped region 2018 extends by a first preset dimension w1 from the side contacting the dielectric layer 2031 toward the direction of the gate structure 2022 pointing toward the semiconductor pillar 2010; in the direction of the gate structure 2022 pointing toward the semiconductor pillar 2010, the maximum doping concentration of the first doped region 2018 is located on the side of the first doped region 2018 in contact with the dielectric layer 2031.

[0158] In practical applications, the first preset dimension w1 is mainly related to the diameter of the semiconductor pillar 2010. The larger the diameter of the semiconductor pillar 2010, the larger the first preset dimension w1 can be set.

[0159] In some embodiments, the ratio of the diameter of the semiconductor pillar to the first preset size w1 ranges from 1 to 10. For example, the ratio of the diameter of the semiconductor pillar to the first preset size w1 can be 1, 5, or 10. It should be noted that when the ratio of the diameter of the semiconductor pillar to the first preset size w1 is 1, it indicates that the size of the first doped region in the X direction is equal to the diameter of the semiconductor pillar.

[0160] It should be noted that the ratio range of the diameter and width of the semiconductor pillar 2010 to the first preset size w1 is merely an illustrative example and is not intended to limit the ratio range of the diameter and width of the semiconductor pillar 2010 to the first preset size w1 in the embodiments of this disclosure.

[0161] In some implementations, the first preset size w1 ranges from 5nm to 10nm, and more specifically, the first preset size w1 can be 5nm, 7nm or 10nm.

[0162] In some embodiments, the semiconductor structure further includes: a source and a drain; the source and drain are respectively located at a first portion and a second portion of the first doped region away from the end of the gate structure along a first direction; the minimum doping concentration of the source and drain is greater than the maximum doping concentration of the first doped region.

[0163] For example, the first semiconductor structure 201 includes a source 2017 and a drain 2025; the source 2017 and the drain 2025 are respectively located at the first part 2018-1 and the second part 2018-2 of the first doped region 2018 away from the end of the gate structure 2022 along the first direction; the minimum doping concentration of the source 2017 and the drain 2025 is greater than the maximum doping concentration of the first doped region 2018.

[0164] In some embodiments, the doping concentration of the source 2017 decreases in the direction from the first end to the second end, and the doping concentration of the drain 2025 decreases in the direction from the second end to the first end.

[0165] In some embodiments, the semiconductor structure further includes a channel region, which is the region between the source 2017 and the drain 2025 excluding the first doped region 2018; the minimum doping concentration of the first doped region 2018 is greater than the maximum doping concentration of the channel region.

[0166] In some embodiments, the semiconductor structure comprises multiple semiconductor structures, with adjacent semiconductor structures separated by a dielectric layer; the doping ion concentration of the dielectric layer is less than or equal to a second preset threshold. For example, the adjacent first semiconductor structure 201 and second semiconductor structure 202 are separated by a dielectric layer 2031. The doping ion concentration of the dielectric layer 2031 is less than or equal to the second preset threshold.

[0167] In some embodiments, the second preset threshold is 0, and the doping ion concentration of the dielectric layer 2031 is equal to the second preset threshold, that is, the dielectric layer 2031 is not doped.

[0168] In some embodiments, the plurality of semiconductor structures include a first semiconductor structure 201 and a second semiconductor structure 202 disposed adjacent to each other; the gate structure 2022 of the first semiconductor structure 201 and the gate structure 2022 of the second semiconductor structure 202 are both located on the side of the respective semiconductor pillar 2010 away from the dielectric layer 2025; the plurality of semiconductor structures further include a third semiconductor structure 203, the third semiconductor structure 203 being located on the side of the first semiconductor structure 201 away from the second semiconductor structure 202.

[0169] In some embodiments, the memory device further includes a word line isolation structure, wherein the gate structure 2022 of the third semiconductor structure 203 and the gate structure 2022 of the first semiconductor structure 201 are separated by the word line isolation structure (not shown); the dimension of the word line isolation structure along the first direction is larger than the dimension of the gate structure 2022 along the first direction.

[0170] The vertical dimension of the word line isolation structure in the Z direction here is the same as that of the gate structure 2022 in the Z direction, which can achieve better isolation. (See reference...) Figure 2A We will understand the role of the gate isolation 1062.

[0171] In some embodiments, the plurality of semiconductor structures include a first semiconductor structure 201 and a second semiconductor structure 202 disposed adjacently; the gate structure 2022 of the first semiconductor structure 201 and the gate structure 2022 of the second semiconductor structure 202 are both located on the side of the corresponding semiconductor pillar 2010 away from the dielectric layer 2025; the first semiconductor structure 201 and the second semiconductor structure 202 further include: a second doped region 2030, the second doped region 2030 extending a second preset size w2 from the side contacting the dielectric layer 2025 toward the gate structure 2022, and the doping type of the second doped region 2030 is different from the doping type of the source 2017 and the drain 2025.

[0172] In practical applications, the second preset dimension w2 is mainly related to the diameter of the semiconductor pillar 2010. The larger the diameter of the semiconductor pillar 2010, the larger the second preset dimension w2 can be set.

[0173] In some implementations, the first preset size w1 and the second preset size w2 may be the same or different.

[0174] In some embodiments, the ratio of the diameter of the semiconductor pillar 2010 to the second preset size w2 ranges from 2 to 7. For example, the ratio of the diameter of the semiconductor pillar to the second preset size w2 can be 2, 3, 4, 5, 6 or 7.

[0175] In some implementations, when the diameter of the semiconductor pillar is 10-20 nm, the second preset size w2 ranges from 1 nm to 10 nm. More specifically, the second preset size w2 can be 1 nm, 5 nm, or 10 nm.

[0176] In some embodiments, the minimum doping concentration of both the source 2017 and the drain 2025 is greater than the maximum doping concentration of the second doping region 2030.

[0177] In some embodiments, the source 2017 and drain 2025 are N-type doped, and the second doped region 2030 is P-type doped.

[0178] This disclosure also provides a memory device, such as... Figure 9 As shown, the memory device includes: a semiconductor pillar array, including a plurality of rows of semiconductor pillars 3020 and a plurality of columns of semiconductor pillars 3030; semiconductor pillars 3010 extending along a first direction; a plurality of word lines 3011; one word line 3011 covering a portion of the sidewall of a row of semiconductor pillars; a first doped region located at opposite ends of the semiconductor pillars 3010 in a first region 3040 along the first direction, the first region 3040 being the region through which both word lines and bit lines 3012 pass; the first doped region is located along the direction from the word line 3011 to the semiconductor pillar 3010. The doping concentration on the first side near the word line 3011 is greater than the doping concentration on the second side of the first doped region away from the word line 3011; the third doped region is located at the two opposite ends of the semiconductor pillar 3010 in the second region 3050 along the first direction; the second region 3050 is located between the first region 3040 and the third region 3060, and the third region 3060 is used to set the word line contact structure 3013; the doping concentration on the first side of the third doped region 3060 near the word line 3011 is equal to the doping concentration on the second side of the third doped region away from the word line.

[0179] It should be noted that the character lines in the first area were formed after passing through... Figure 5H The process of etching back the initial gate (third initial gate) on the back side shown in the illustration thus provides the conditions for forming the first doped region as described in the foregoing embodiments. Here and thereafter, the semiconductor pillars, the first doped region, and the word lines in the first region 3040 can be referred to... Figure 8B The semiconductor pillar 2010, the first doped region 2018, and the gate structure 2022 shown are understood.

[0180] No process is required when forming the word lines in the second area. Figure 5H The process of etching back the initial gate (third initial gate) on the back side is shown, so the semiconductor pillars, third doped region, and word lines in the second region 3050 can be referenced. Figure 2B The semiconductor pillar 1030, lightly doped region 1064, and gate structure 1036 shown are understood.

[0181] In some embodiments, the distance between the end face of the word line near the first doped region and the end face of the first doped region near the word line along the first direction is less than or equal to a first preset threshold; the distance between the end face of the word line near the third doped region and the end face of the third doped region near the word line along the first direction is greater than the first preset threshold. It is understood that the first doped region in the first region is aligned with the word line, while the word line in the third doped region in the second region is not aligned.

[0182] For example, refer to Figure 8B The distance between the end face of the word line (gate structure 2022) near the first doped region 2018 and the end face of the first doped region 2018 near the word line (gate structure 2022) along the first direction is less than or equal to a first preset threshold. (Reference) Figure 2B The distance between the end face of the word line (gate structure 1036) near the third doped region (lightly doped region 1064) and the end face of the third doped region near the word line (gate structure 1036) in the first direction is greater than a first preset threshold.

[0183] In some embodiments, the range of the first preset threshold is 5nm to 10nm. The first preset threshold can be 5nm, 7nm, or 10nm.

[0184] In some embodiments, the size of the first doped region along a preset direction is less than or equal to the size of the semiconductor pillar along the preset direction; the preset direction is the same as the arrangement direction (X direction) of each semiconductor pillar in a column of semiconductor pillars; the size of the third doped region along the preset direction (X direction) is equal to the size of the semiconductor pillar along the preset direction.

[0185] For example, the dimension of the first doped region along the preset direction being less than or equal to the dimension of the semiconductor pillar along the preset direction can be understood as... Figure 8B The first preset dimension w1 is less than or equal to the diameter of the semiconductor pillar 2010.

[0186] The dimension of the third doped region along the preset direction (X direction) is equal to the dimension of the semiconductor pillar along the preset direction, which can be understood as... Figure 2B The size of the medium-light doped region 1064 in the X direction is equal to the diameter of the semiconductor pillar.

[0187] In some embodiments, the memory device further includes: a source and a drain; both the first doped region and the third doped region include a first portion located at a first end of a semiconductor pillar and a second portion located at a second end of a semiconductor pillar, the first end and the second end being opposite ends of the semiconductor pillar along a first direction; the source and the drain are respectively located at the ends of the first portion and the second portion of the first doped region / third doped region away from the word line along the first direction; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the first doped region; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the third doped region.

[0188] Here, the locations of the source and drain in the memory device can be referenced. Figure 8B or Figure 2B To understand the location of the source and drain in the process.

[0189] The first and third doped regions have lower doping concentrations than the source / drain regions, which are used to improve the hot carrier injection effect.

[0190] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0191] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A memory device, characterized in that, include: Semiconductor structure; The semiconductor structure includes: Semiconductor pillars, extending along a first direction; A gate structure is located on at least one side of the semiconductor pillar; and The first doped region is located at opposite ends of the semiconductor pillar along the first direction; along the direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on the first side closer to the gate structure is greater than the doping concentration of the first doped region on the second side farther from the gate structure.

2. The memory device according to claim 1, characterized in that, The doping concentration of the first doped region decreases along the direction of the gate structure toward the semiconductor pillar.

3. The memory device according to claim 1, characterized in that, The first doped region includes a first portion located at a first end of the semiconductor pillar and a second portion located at a second end of the semiconductor pillar, wherein the first end and the second end are two opposite ends of the semiconductor pillar along the first direction; wherein the distance between the end face of the gate structure near the first portion and the end face of the first portion near the gate structure along the first direction, and the distance between the end face of the gate structure near the second portion and the end face of the second portion near the gate structure, are both less than or equal to a first preset threshold.

4. The memory device according to claim 3, characterized in that, The range of the first preset threshold is 5nm to 10nm.

5. The memory device according to claim 2, characterized in that, The semiconductor structure includes multiple semiconductor structures, and adjacent semiconductor structures are separated by a dielectric layer. The first doped region extends by a first predetermined dimension from the side that contacts the dielectric layer toward the direction of the gate structure pointing toward the semiconductor pillar; In the direction from the gate structure to the semiconductor pillar, the maximum doping concentration of the first doped region is located on the side where the first doped region contacts the dielectric layer.

6. The memory device according to claim 3, characterized in that, The semiconductor structure further includes a source and a drain; the source and the drain are respectively located at a first part and a second part of the first doped region away from the end of the gate structure along the first direction; The minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the first doping region.

7. The memory device according to claim 6, characterized in that, The doping concentration of the source electrode decreases in the direction from the first end to the second end, and the doping concentration of the drain electrode decreases in the direction from the second end to the first end.

8. The memory device according to claim 6, characterized in that, The semiconductor structure further includes a channel region, which is the region between the source and the drain, excluding the first doped region; the minimum doping concentration of the first doped region is greater than the maximum doping concentration of the channel region.

9. The memory device according to claim 1, characterized in that, The semiconductor structure includes multiple semiconductor structures, which are arranged adjacently and separated by a dielectric layer; the doping ion concentration of the dielectric layer is less than or equal to a second preset threshold.

10. The memory device according to claim 9, characterized in that, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure arranged adjacent to each other. The gate structure of the first semiconductor structure and the gate structure of the second semiconductor structure are both located on the side of the corresponding semiconductor pillar that is far away from the dielectric layer. The plurality of semiconductor structures further includes a third semiconductor structure, which is located on the side of the first semiconductor structure away from the second semiconductor structure; The memory device further includes a word line isolation structure, wherein the gate structure of the third semiconductor structure and the gate structure of the first semiconductor structure are separated by the word line isolation structure. The dimension of the word line isolation structure along the first direction is larger than the dimension of the gate structure along the first direction.

11. The memory device according to claim 9, characterized in that, The plurality of semiconductor structures include a first semiconductor structure and a second semiconductor structure arranged adjacent to each other. The gate structure of the first semiconductor structure and the gate structure of the second semiconductor structure are both located on the side of the corresponding semiconductor pillar that is far away from the dielectric layer. The first semiconductor structure and the second semiconductor structure further include: The second doped region extends a second predetermined dimension from the side contacting the dielectric layer toward the gate structure, and the doping type of the second doped region is different from the doping types of the source and drain.

12. The memory device according to claim 11, characterized in that, The minimum doping concentration of both the source and the drain is greater than the maximum doping concentration of the second doping region.

13. The memory device according to claim 11, characterized in that, The source and drain are N-type doped, and the second doped region is P-type doped.

14. A memory device, characterized in that, include: A semiconductor pillar array, comprising several rows of semiconductor pillars and several columns of semiconductor pillars; The semiconductor pillar extends along a first direction; Multiple letter lines; One of the word lines covers a portion of the sidewall of a row of semiconductor pillars; The first doped region is located at the two opposite ends of the semiconductor pillars in the first region along the first direction, and the first region is the region through which both word lines and bit lines pass. Along the direction from the word line to the semiconductor pillar, the doping concentration of the first doped region on the first side closer to the word line is greater than the doping concentration of the first doped region on the second side farther from the word line; The third doped region is located at the two opposite ends of the semiconductor pillars in the second region along the first direction; the second region is located between the first region and the third region, and the third region is used to set the word line contact structure; the doping concentration of the third doped region on the first side near the word line is equal to the doping concentration of the third doped region on the second side away from the word line.

15. The memory device according to claim 14, characterized in that, The distance between the end face of the word line near the first doped region and the end face of the first doped region near the word line along the first direction is less than or equal to a first preset threshold. The distance between the end face of the word line near the third doped region and the end face of the third doped region near the word line in the first direction is greater than the first preset threshold.

16. The memory device according to claim 15, characterized in that, The range of the first preset threshold is 5nm to 10nm.

17. The memory device according to claim 14, characterized in that, The dimension of the first doped region along a preset direction is less than or equal to the dimension of the semiconductor pillar along the preset direction; the preset direction is the same as the arrangement direction of each semiconductor pillar in a column of semiconductor pillars; The dimension of the third doped region along the preset direction is equal to the dimension of the semiconductor pillar along the preset direction.

18. The memory device according to claim 14, characterized in that, The memory device further includes: a source and a drain; Both the first doped region and the third doped region include a first portion located at a first end of the semiconductor pillar and a second portion located at a second end of the semiconductor pillar, wherein the first end and the second end are opposite ends of the semiconductor pillar along the first direction; the source and the drain are respectively located at the ends of the first and second portions of the first doped region / third doped region that are away from the word line along the first direction; The minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the first doping region; the minimum doping concentration of the source and the drain is greater than the maximum doping concentration of the third doping region.

19. A method for manufacturing a memory device, characterized in that, include: Provides a semiconductor layer; A semiconductor structure is formed in the semiconductor layer; The semiconductor structure includes: a semiconductor pillar, a gate structure, and a first doped region; forming the semiconductor structure includes: Forming semiconductor pillars extending along the first direction; The gate structure is formed on at least one side of the semiconductor pillar; The first doped regions are formed at opposite ends of the semiconductor pillar along the first direction; along the direction from the gate structure to the semiconductor pillar, the doping concentration of the first doped region on the first side closer to the gate structure is greater than the doping concentration of the first doped region on the second side farther from the gate structure.

20. The manufacturing method according to claim 19, characterized in that, Forming the gate structure and the first doped region includes: A first initial gate is formed covering at least one side of the semiconductor pillar; Starting from the first surface and the second surface of the semiconductor layer, respectively, along the first direction, a portion of the first initial gate is removed to form the gate structure and expose a portion of the semiconductor pillar; the first surface and the second surface are two surfaces of the semiconductor layer opposite each other along the first direction; The first doped region is formed starting from the surface of the exposed semiconductor pillar and extending into a region of a first predetermined size perpendicular to the first direction.

21. The manufacturing method according to claim 19, characterized in that, Forming the gate structure and the first doped region includes: A sacrificial layer is formed at the bottom of at least one side of the semiconductor pillar; A second initial gate is formed on the sacrificial layer, covering the corresponding side of the semiconductor pillar; The top portion of the second initial gate and sacrificial layer is removed to form the gate structure and expose the top and bottom of the corresponding sides of the semiconductor; The first doped region is formed starting from the surface of the exposed semiconductor pillar and extending into a region of a first predetermined size perpendicular to the first direction.

22. The manufacturing method according to claim 20 or 21, characterized in that, Forming the first doped region includes: Starting from the surface of the exposed semiconductor pillar, a first portion and a second portion of the first doped region are formed in a region extending a first preset size perpendicular to the first direction using a molecular layer deposition process or a rapid vapor phase doping process.

23. The manufacturing method according to claim 20, characterized in that, The first portion forming the first doped region includes: Starting from the first surface of the semiconductor layer, along the first direction, a portion of the first initial gate is removed to form a third initial gate, thereby exposing a portion of the semiconductor pillar; Starting from the surface of the exposed semiconductor pillar, a first initial portion of the first doped region is formed in a region extending a first predetermined size perpendicular to the first direction; Starting from the first surface of the semiconductor layer, along the first direction, the portion of the first initial portion away from the third initial gate is doped by an ion implantation process, and the doped portion forms the source; the remaining first initial portion that is not doped by the ion implantation process forms the first portion of the first doped region.

24. The manufacturing method according to claim 23, characterized in that, The second portion forming the first doped region includes: After forming the source and the first portion, starting from the second surface of the semiconductor layer, a portion of the third initial gate is removed along the first direction to form the gate structure, thereby exposing a portion of the semiconductor pillar; Starting from the surface of the exposed semiconductor pillar, a second initial portion of the first doped region is formed in a region extending a first predetermined size perpendicular to the first direction; Starting from the second surface of the semiconductor layer, along the first direction, a portion of the second initial portion away from the gate structure is doped by an ion implantation process, and the doped portion forms the drain; the remaining second initial portion that is not doped by the ion implantation process forms the second portion of the first doped region.

25. The manufacturing method according to claim 21, characterized in that, The first portion and the second portion forming the first doped region include: A drain is formed at the bottom of at least one side of the semiconductor pillar by a diffusion process; Starting from the surfaces of the semiconductor pillars exposed at the top and bottom of their respective sides, a first initial portion and a second portion of the first doped region are formed in a region extending perpendicular to the first direction and into a region of a first predetermined size. Starting from the top of the semiconductor layer, along the first direction, a portion of the first initial portion away from the gate structure is doped by an ion implantation process, and the doped portion forms the source; the remaining first initial portion that is not doped by the ion implantation process forms the first portion of the first doped region.

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