Memory and manufacturing method thereof

Abstract

The invention provides a memory and a memory manufacturing method, the memory comprises a substrate, a plurality of bit lines and N transistors, the plurality of bit lines are arranged on the surface of the substrate at intervals along a first direction, each bit line is connected with M transistors, each row comprises S transistors arranged at intervals along a second direction, the bit lines are conducted with the transistors, and N is a positive integer greater than or equal to 1. The transistor comprises a channel, a gate dielectric layer and a gate structure, the gate structure comprises a gate main body, and a first extension part and a second extension part connected to two ends of the gate main body in the height direction, and the first extension part is close to the bit line; the gate dielectric layer surrounds the periphery of the channel and is connected to the peripheral side surface of the channel, and the gate main body surrounds the outer surface, opposite to the channel, of the gate dielectric layer; and in every two adjacent gate structures, the first extension part and the second extension part of one gate structure are respectively connected and conducted with the first extension part and the second extension part of the other gate structure, and gaps are formed between the gate main bodies arranged along the second direction.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more particularly to a memory and a method for manufacturing the memory. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a type of memory that occupies a large market share. With the rapid development of communication and digital technologies, the electrical performance of DRAM urgently needs improvement to meet the performance requirements of electronic products. However, existing 4F... 2 Dynamic random access memory that arranges transistors, but vertical transistors require high precision and have complex fabrication processes. Summary of the Invention

[0003] This application provides a memory and a method for manufacturing the memory, which can further improve the electrical performance of the memory.

[0004] One embodiment of this application provides a memory, the memory including a substrate, multiple bit lines, and N transistors. The multiple bit lines are spaced apart on the surface of the substrate along a first direction. The N transistors are arranged in an array, with M transistors connected to each bit line. Along a second direction, the N transistors are arranged in multiple rows, each row including S transistors spaced apart, where M multiplied by S equals N, M and S are both greater than 2, and M, S, and N are all integers. The bit lines are connected to the transistors. Each transistor includes a channel, a gate dielectric layer, and a gate structure. The gate structure includes a gate body, a first extension, and a second extension. The first extension and the second extension are connected to opposite ends of the gate body in the height direction and are disposed opposite to each other. Both the first extension and the second extension extend along the first direction, with the first extension close to the bit line. The gate dielectric layer surrounds the outer periphery of the channel and is connected to the outer peripheral side of the channel. The gate body surrounds the gate dielectric layer and faces away from the outer surface of the channel. In the S transistors, in every two adjacent gate structures, the first extension of one gate structure is connected and conducts with the first extension of the other gate structure, and the second extension of one gate structure is connected and conducts with the second extension of the other gate structure. A gap is formed between the gate bodies arranged along the second direction, wherein the first direction and the second direction are perpendicular, and the height direction of the channel and the height direction of the gate body are both perpendicular to the first direction and the second direction.

[0005] In one embodiment, the transistor includes a source and a drain, the source and the drain being connected to the two ends of the channel in the height direction, the source being connected to the bit line, the drains of N transistors being spaced apart, and a blocking element being connected between every two adjacent drains of S transistors in the same row.

[0006] In one embodiment, the gate dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer covers the peripheral surface of the source electrode, and the drains of the S transistors in the same row and the opposite sides of the blocking member are connected to the second dielectric layer. The first extension is connected to the first dielectric layer, and the second extension is connected to the second dielectric layer in a second direction.

[0007] In one embodiment, the memory further includes a packaging layer that covers a plurality of the transistors and a plurality of the bit lines, the packaging layer filling the gaps between the gate bodies, the opposite ends of the bit lines being exposed by the packaging layer, the drains being exposed by the packaging layer, and in the first direction, second extensions located in the same row being exposed by the packaging layer, and the drains of the N transistors being exposed by the packaging layer at the ends facing away from the substrate.

[0008] In one embodiment, the memory further includes an insulating layer and an isolation layer, the insulating layer and the isolation layer being sequentially connected to the side of the substrate where the bit lines are located, and insulating the plurality of bit lines, the bit lines being exposed on the surface of the isolation layer away from the substrate, and the encapsulation layer being connected to the surface of the isolation layer away from the substrate.

[0009] Another aspect of this application provides a method for manufacturing a memory, comprising:

[0010] A substrate is provided, and multiple bit lines, a source layer, a channel base layer, and a drain layer are formed on the substrate. The bit lines, the source layer, the channel base layer, and the drain layer are stacked sequentially along the height direction of the memory and form sidewalls. Along a second direction, a first trench is formed between every two sidewalls, and the first trench exposes the surface of the substrate.

[0011] An insulating layer is formed on the substrate, the insulating layer covering the surface of the substrate located within the first trench and covering a portion of the peripheral side surface of the bit line.

[0012] An isolation layer is formed on the side of the insulating layer facing away from the substrate, the isolation layer covering the peripheral side of the bit lines exposed by the insulating layer. Along the thickness direction of the substrate, the orthographic projection of the isolation layer coincides with the orthographic projection of the insulating layer.

[0013] A sacrificial layer is formed on the side of the isolation layer facing away from the substrate, and the drain layer is exposed on the side of the sacrificial layer facing away from the substrate. The sacrificial layer is located within the first trench and covers the periphery of the channel base layer and the source layer.

[0014] A plurality of spaced-apart barrier layers and a plurality of second trenches are formed on the sacrificial layer, with each pair of barrier layers separated by a second trench. The extension directions of the plurality of barrier layers intersect the extension direction of the bit line, and the barrier layers cover the drain layer, exposing the outer side of the sacrificial layer.

[0015] Using multiple barrier layers as masks, the drain layer and the sacrificial layer are etched using a photomask process to form a channel base layer, a source layer, and a drain layer. The isolation layer, facing away from the substrate, is exposed through a second trench, and the bit line is exposed on the surface of the isolation layer. The source, the channel, and the drain form a columnar structure.

[0016] A gate oxide layer and a gate material layer are sequentially formed on the isolation layer. The gate oxide layer covers the surface of the isolation layer facing away from the insulating layer, exposes the ends of the plurality of bit lines of the isolation layer, the outer surfaces of the plurality of pillar-shaped structures, and the plurality of barrier layers. The gate material layer covers the outer surface of the gate oxide layer.

[0017] The gate material layer is formed by dry etching on the side opposite to the substrate and the gate material layer located in the second trench, partially exposing part of the gate oxide material layer.

[0018] A dielectric material layer is deposited on a substrate, and the dielectric material layer, the barrier layer, and the gate oxide layer are planarized on the side opposite to the substrate, so that the barrier layer forms a barrier element, the gate oxide layer forms a gate dielectric layer, and the planarized dielectric material layer forms an encapsulation layer.

[0019] A portion of the gate layer located between the gate dielectric layer and the packaging layer is etched to form a gate structure, and the gate structure, the gate dielectric layer, and the pillar structure form a transistor.

[0020] In one embodiment, before forming an insulating layer on the substrate, the method further includes forming a protective layer on the outer surface of the sidewall. The protective layer covers the outer surface of the sidewall.

[0021] In one embodiment, the step of forming multiple bit lines, a source layer, a channel base layer, and a drain layer on the substrate includes sequentially growing a bit line material layer and a transistor material layer on the surface of the substrate, wherein the transistor material layer is located on the surface of the bit line material layer facing away from the substrate. A patterning process is used to form multiple bit lines on the bit line material layer, and simultaneously, the transistor material layer forms the source layer, the channel base layer, and the drain layer.

[0022] In one embodiment, the step of forming a plurality of spaced-apart barrier layers and a plurality of second trenches on the sacrificial layer includes depositing a barrier material layer in the drain layer, within the first trench, and on the sacrificial layer, and patterning the barrier material layer to form a plurality of barrier layers and a second trench between two barrier layers. During the deposition of the barrier material layer, the barrier material layer fills the remaining portion of the first trench and completely covers the side of the sacrificial layer facing away from the isolation layer, and also covers the sidewalls exposed by the sacrificial layer. Along a second direction, one barrier layer connects to a plurality of drain layers, and the thickness of the barrier layer is greater than the thickness of the drain layers exposed by the sacrificial layer.

[0023] In one embodiment, in the step of etching the drain layer and the sacrificial layer using a photomask process with multiple barrier layers as masks, two adjacent columnar structures are spaced apart, and the sacrificial layer surrounding the outside of the columnar structure is removed by wet etching to expose the isolation layer and part of the bit line not covered by the source, wherein one barrier layer spaced multiple drains arranged in a row along a second direction.

[0024] Based on existing mature process technologies, the memory and its fabrication method provided in this application are simple and highly feasible. Directly stacking the bit line material layer and transistor material layer followed by patterned etching ensures the accuracy of the first trench formation, facilitates the establishment of the transistor channel, reduces overall memory performance fluctuations, and improves memory stability. Furthermore, existing memory fabrication methods often require two masks or photomasks for etching, leading to issues with bit line fabrication, alignment accuracy, and channel miniaturization. In this application, without changing the number of required masks, a barrier layer is used as the mask in memory fabrication. This not only saves on the number of masks needed for etching the channel base layer, drain layer, and source layer, reducing fabrication costs, but also solves the overlay misalignment problem in traditional memory fabrication processes, increasing alignment accuracy and further reducing memory costs and improving manufacturing yield. Attached Figure Description

[0025] Figure 1A schematic diagram of a memory with vertical transistors provided in an embodiment of this application;

[0026] Figure 2 for Figure 1 The diagram shows the perspective structure of the memory.

[0027] Figure 3 for Figure 1 The diagram shows a cross-sectional view of the memory along the first direction X.

[0028] Figure 4 for Figure 1 The diagram shows a cross-sectional view of the memory along the second direction Y.

[0029] Figure 5 for Figure 4 A partially enlarged view of a transistor and its surrounding structure in the memory shown.

[0030] Figure 6 A schematic flowchart illustrating a method for fabricating a memory with vertical transistors according to an embodiment of this application;

[0031] Figure 7 for Figure 6 The diagram shows the structure formed by sequentially depositing a bit line material layer and a transistor material layer in step S1.

[0032] Figure 8 for Figure 6 The schematic diagram of the structure formed corresponding to step S1 shown;

[0033] Figure 9 for Figure 8 The cross-sectional view of the structure formed in step S1 along the second direction Y is shown.

[0034] Figure 10 for Figure 6 The diagram shows the structure formed by depositing the protective layer in step S2.

[0035] Figure 11 for Figure 10 The cross-sectional view of the structure formed in step S2 shown is along the second direction Y.

[0036] Figure 12 for Figure 6 The diagram shows the structure formed by depositing the insulating material layer in step S3.

[0037] Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure of the deposited insulating material layer along the second direction Y.

[0038] Figure 14 for Figure 6The schematic diagram of the structure formed corresponding to step S3 is shown below;

[0039] Figure 15 for Figure 14 The cross-sectional view of the structure formed in step S3 along the second direction Y is shown.

[0040] Figure 16 for Figure 6 The diagram shows the structure formed by depositing the isolation material layer in step S4.

[0041] Figure 17 for Figure 16 The diagram shows a cross-sectional view of the structure of the deposited isolation material layer along the second direction Y.

[0042] Figure 18 for Figure 6 The schematic diagram of the structure formed corresponding to step S4 is shown below;

[0043] Figure 19 for Figure 18 The cross-sectional view of the structure formed in step S4 shown is along the second direction Y.

[0044] Figure 20 for Figure 6 The diagram shows the structure formed by depositing the first sacrificial material layer in step S5.

[0045] Figure 21 for Figure 20 The diagram shows a cross-sectional view of the structure of the first sacrificial material layer along the second direction Y.

[0046] Figure 22 for Figure 6 The schematic diagram of the structure formed corresponding to step S5 is shown below;

[0047] Figure 23 for Figure 22 The cross-sectional view of the structure formed in step S5 along the second direction Y is shown.

[0048] Figure 24 for Figure 6 A schematic diagram of the structure formed by depositing the barrier material layer in the first embodiment of step S6 shown;

[0049] Figure 25 for Figure 6 A schematic diagram of the structure formed in the first embodiment of step S6 shown;

[0050] Figure 26 for Figure 25 The diagram shows a cross-sectional view of the structure formed in step S6 along the second direction Y.

[0051] Figure 27 for Figure 6 A schematic diagram of the structure formed by depositing the second sacrificial material layer in the second embodiment of step S6 is shown;

[0052] Figure 28 for Figure 27 The diagram shows a structure in which the second sacrificial material layer is deposited to form a groove.

[0053] Figure 29 for Figure 6 The schematic diagram of the structure formed corresponding to step S7 is shown below;

[0054] Figure 30 for Figure 29 The cross-sectional view of the structure formed in step S7 shown is along the first direction X.

[0055] Figure 31 for Figure 29 The cross-sectional view of the structure formed in step S7 shown is along the second direction Y.

[0056] Figure 32 for Figure 6 The diagram shows the structure formed by depositing the gate oxide material layer in step S8.

[0057] Figure 33 for Figure 32 The diagram shows a cross-sectional view of the structure of the deposited gate oxide material layer along the first direction X.

[0058] Figure 34 for Figure 32 The diagram shows a cross-sectional view of the structure of the deposited gate oxide material layer along the second direction Y.

[0059] Figure 35 for Figure 6 The diagram shows the structure formed by depositing the gate material layer in step S8.

[0060] Figure 36 for Figure 35 The diagram shows a cross-sectional view of the structure of the deposited gate material layer along the first direction X.

[0061] Figure 37 for Figure 35 The diagram shows a cross-sectional view of the structure of the deposited gate material layer along the second direction Y.

[0062] Figure 38 for Figure 6 The schematic diagram of the structure formed corresponding to step S9 is shown below;

[0063] Figure 39 for Figure 38 The cross-sectional view of the structure formed in step S9 shown is along the first direction X.

[0064] Figure 40 for Figure 6 The diagram shows the structure formed by depositing the dielectric material layer in step S10.

[0065] Figure 41 for Figure 40 The schematic diagram of the structure formed corresponding to step S10 shown;

[0066] Figure 42 for Figure 41 The diagram shows a cross-sectional view of the structure formed in step S10 along the first direction X.

[0067] The terms corresponding to the reference numerals in the figures are as follows: memory 100, transistor 10, substrate 20, word line WL, bit line BL, source 11, channel 12, drain 13, gate structure 14, gate body 141, first extension 142, second extension 143, gate dielectric layer 15, dielectric body 151, first dielectric layer 152, second dielectric layer 153, insulating layer 30, isolation layer 40, barrier 50, encapsulation layer 60, gap H, source layer 71, channel base layer 72, drain layer 73, sidewall 70, first trench A, bit line material layer 1, transistor material layer 2, protective layer 81, insulating material layer 3, isolation material layer 4, sacrificial layer 82, first sacrificial material layer 5a, barrier layer 83, second trench B, barrier material layer 6, second sacrificial material layer 5b, groove 84, gate oxide material layer 7, gate material layer 8, dielectric material layer 9, gate layer 85, columnar structure F. Detailed Implementation

[0068] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0069] This application provides an electronic device (not shown in the figures) in its embodiments. The electronic device may include different types of user equipment or terminal devices such as mobile phones, tablets, computers, smart wearable devices (such as smartwatches, smart bracelets, and smart rings), in-vehicle devices, and home appliances, and may also be network equipment such as base station servers and data centers. In this application's embodiments, no specific limitations are placed on the type of electronic device.

[0070] The processor in the aforementioned electronic device is equipped with transistor-based memory. This memory can be Dynamic Random Access Memory (DRAM), used to temporarily store data processed by the Central Processing Unit (CPU) and data exchanged between the CPU and external storage devices such as hard drives. DRAM is a crucial component of a computing system. The basic unit constituting DRAM is called a Dynamic Random Access Memory Cell (DRAM Cell), also known as a storage unit. Currently, the mainstream DRAM cell size is 6F. 2 The architecture, i.e., the area of ​​the storage unit, is 6F. 2 Here, F represents the feature size. With the development of photolithography technology, the feature size F has gradually decreased, thus reducing the area of ​​the memory cell. However, due to limitations in photolithography technology and cost, the reduction of the memory cell area has reached a bottleneck. Therefore, a memory cell with an even smaller area is needed.

[0071] The memory can be a 1T1C dynamic random access memory (DRAM), or a DRAM containing 2T0C memory cells, or a DRAM containing memory cells of other structures. Here, 1T1C represents a memory cell including one transistor and one capacitor. 2T0C represents a memory cell including two transistors but not a capacitor. In this application, the number of memory cells is not limited, as long as it meets the memory's storage requirements. Similarly, the number of transistors and capacitors in the memory cells is not limited, as long as data writing, modification, or reading is possible.

[0072] Please see Figure 1 and Figure 2 , Figure 1 This is a schematic diagram of a memory structure with vertical transistors provided in an embodiment of this application. Figure 2 for Figure 1 The diagram shows a perspective view of the memory. It should be noted that... Figure 1 The diagram only schematically shows a portion of the structure of memory 100. In reality, memory 100 can be multiple such... Figure 1 The structure shown is formed by repeating the structure. Figure 2 The image shows only the encapsulation layer 60, the insulating layer 30, the isolation layer 40, and the first dielectric layer 152.

[0073] For ease of description, the length direction of the memory 100 is defined as the first direction X, the width direction as the second direction Y, and the height direction as the third direction Z. The first direction X, the second direction Y, and the third direction Z are mutually perpendicular. The first direction X and the second direction Y are parallel to the substrate, and the third direction Z is perpendicular to the substrate 20. In this application, spatial relative terms such as "top," "bottom," and "full bottom" describe the orientation of the components, with the positive direction towards the third direction Z being "top" or "full top," and the opposite direction towards the third direction Z being "bottom" or "full bottom," and so on.

[0074] like Figure 1 As shown, this embodiment provides a 4F 2 The memory 100 has a vertical transistor 10 architecture and can be a 1T1C memory cell. The memory 100 typically includes multiple memory cells arranged in a matrix. Each memory cell includes a transistor 10 and a capacitor (not shown). The area of ​​the transistor 10 is 4F. 2 This can be understood as follows: a transistor 10 of memory 100 has only 1F of active region and 1F of field region in the first direction X and the second direction Y, respectively. Ultimately, one memory cell occupies 2F × 2F = 4F. 2 Each region.

[0075] like Figure 1 As shown, the memory 100 includes a transistor 10, a capacitor (C) (not shown), a bit line (BL), and a word line (WL). The bit line BL is connected to the transistor 10. The bit line BL is connected to one end of the capacitor via the transistor 10, and the other end of the capacitor is connected to ground. The bit line BL and the word line WL are perpendicular to each other. The word line WL is formed by the gate structure 14 of the transistor 10. The word line WL can be electrically connected to external electronic devices. The transistor 10 can be used as a switch for the memory 100, enabling data reading and writing by charging and discharging the capacitor.

[0076] In this embodiment, transistor 10 can adopt a vertical pillar transistor (VPT) structure. The channel region of the vertical pillar transistor is perpendicular to the substrate of memory 100. Compared with transistor structures where the channel region is parallel to the substrate, the vertical pillar transistor occupies a smaller area. Therefore, the vertical pillar transistor has a higher integration density, thereby increasing the storage capacity of memory 100.

[0077] In this embodiment, transistor 10 can be a gate-all-around (GAA) FET. A GAA FET can achieve the smallest pattern size under given process conditions and allows transistor 10 to be stacked in three dimensions, which is beneficial for increasing the integration density of memory 100, thereby achieving high-density storage. Simultaneously, the GAA FET also increases the on-state current of memory 100, thereby improving the performance of memory 100.

[0078] The memory 100 may include a substrate 20, which serves as a support structure for the layers of the memory 100. The height direction of the substrate 20 is perpendicular to the first direction X and the second direction Y.

[0079] The memory 100 may further include multiple word lines WL and multiple bit lines BL. Along a third direction Z, the multiple word lines WL and multiple bit lines BL are stacked on one side of the substrate 20. In this embodiment, along a third direction Y, the multiple bit lines BL are located on one side of the substrate 20 and connected to the substrate 20. The multiple bit lines BL extend along a first direction X and are spaced apart along a second direction Y. The multiple word lines WL are located on the side of the bit lines BL facing away from the substrate 20, and the multiple word lines WL extend along the second direction Y and are spaced apart along the first direction X. Since the first direction X and the second direction Y intersect, the word lines WL and bit lines BL intersect. The multiple word lines WL are mutually insulated. A single word line WL is formed by the gate structures 14 of multiple transistors 10. The multiple transistors 10 connected to each word line WL are spaced apart along the second direction Y. The multiple bit lines BL are mutually insulated. The intersection of the word lines WL and bit lines BL constitutes a transistor 10 region. Each bit line BL is connected to multiple transistors 10, and the multiple transistors 10 connected to each bit line BL are arranged at intervals in the first direction X.

[0080] For example, the memory 100 includes N transistors 10, and multiple bit lines BL are arranged at intervals along a first direction X on the surface of the substrate 20. The N transistors 10 are arranged in an array, and M transistors 10 are connected to each bit line BL. Along a second direction Y, the N transistors 10 are arranged in multiple rows, and each row includes S transistors 10 spaced apart, where M multiplied by S equals N. Both M and S are greater than 2. M, S, and N are all integers.

[0081] Each transistor 10 includes a source 11, a channel 12, a drain 13, a gate structure 14, and a gate dielectric layer 15. Along the height direction (third direction Z) of the transistor 10, the source 11 and drain 13 are located at opposite ends of the channel 12 and are electrically connected to the channel 12. In this embodiment, the channel 12 is columnar, and may be a rectangular column. The height direction of the channel 12 is perpendicular to the first direction X and the second direction Y. The gate dielectric layer 15 surrounds the periphery of the channel 12 and covers the periphery of the channel 12. The gate structure 14 surrounds the periphery of the channel 12 and is connected to the surface of the gate dielectric layer 15 facing away from the channel 12. In this embodiment, the bit line BL may be connected to the source 11 of the transistor 10. In some embodiments, the bit line BL may be connected to the drain 13.

[0082] For example, the drains 13 of N transistors 10 are spaced apart, and a blocking member 50 is connected between every two adjacent drains 13 of S transistors 10 in the same row.

[0083] In this embodiment, the gate dielectric layer 15 can be located between every two adjacent transistors 10, and insulates the gate structure 14 between every two adjacent transistors 10 from the source 11, channel 12, and drain 13 of the transistor 10. The gate dielectric layer 15 can be made of a gate oxide material, such as silicon dioxide. The gate structure 14 can be made of a gate material, which can serve to conduct electricity. The gate material can include, but is not limited to, metals such as titanium (Ti), tungsten, molybdenum (Mo), copper, cobalt, nickel, platinum, ruthenium (Ru), gold, iridium, rhodium, and tantalum, as well as metal alloys containing the aforementioned metals. In this embodiment, the gate structure 14 can be made of ruthenium.

[0084] See also Figure 3 , Figure 4 and Figure 5 , Figure 3 for Figure 1 The diagram shown is a cross-sectional view of the memory along the first direction X. Figure 4 for Figure 1 The diagram shows a cross-sectional view of the memory along the second direction Y. Figure 5 for Figure 4 A magnified view of a transistor and its surrounding structure in the memory shown.

[0085] The gate structure 14 includes a gate body 141, a first extension 142, and a second extension 143. The gate body 141 surrounds the outer peripheral surface of the gate dielectric layer 15 facing away from the channel 12. The gate body 141 is insulated from the channel 12 through the gate dielectric layer 15. In fact, the gate body 141 is a cylindrical structure. Along the third direction Z, the first extension 142 and the second extension 143 are located at opposite ends in the height direction of the gate body 141, and both are conductive to the gate body 141. The first extension 142 is located at the end of the gate body 141 near the source 11, and the second extension 143 is located at the end of the gate body 141 near the drain 13. The extension directions of the first extension 142 and the second extension 143 are both consistent with the second direction Y. The first extension 142 and the second extension 143 can be located on opposite sides of the gate body 141 in the second direction Y. It can be understood that the second extension 143 is located at one end of the gate body 141 and extends along the positive and negative directions of the second direction Y. The first extension 142 is located at the other end of the gate body 141 and extends along the positive and negative directions of the second direction Y.

[0086] For example, in the S transistors 10, in every two adjacent gate structures 14, the first extension 142 of one gate structure 14 and the first extension 142 of the other gate structure 14 are connected and conduction are performed, the second extension 143 of one gate structure 14 and the second extension 143 of the other gate structure 14 are connected and conduction are performed, and a gap H is formed between the gate bodies 141 arranged along the second direction Y.

[0087] Along the second direction Y, a plurality of transistors 10, perpendicular to the extension direction of multiple bit lines BL, are arranged in a row. The first extension 142 of the gate structure 14 of the plurality of transistors 10 in each row is connected to each other, and the second extension 143 of the gate structure 14 of the plurality of transistors 10 in each row is connected to each other. The gate bodies 141 of the gate structure 14 of the plurality of transistors 10 in each row are spaced apart and insulated from each other. The gate structure 14 of the plurality of transistors 10 in each row constitutes a word line WL. Along the second direction Y, the arrayed transistors 10 are arranged in multiple rows, and the gate structures 14 of the multiple rows of transistors 10 constitute multiple rows of word lines WL. The transistors 10 of every two adjacent word lines WL are spaced apart and face each other. In this embodiment, the gate structure 14 surrounds the periphery of the channel 12 and is provided with the first extension 142 and the second extension 143, which increases the cross-sectional area of ​​the gate structure 14 in the second direction Y and can improve the conductivity of the gate structure 14. The second extension 143 and the first extension 142 not only serve to connect each gate body 141, but also increase the stability of the word line WL.

[0088] It should be noted that, as Figure 4Along the second direction Y, the first extensions 142 of two adjacent gate structures 14 are connected to each other, the second extensions 143 of two adjacent gate structures 14 are connected to each other, and the two adjacent gate bodies 141 are spaced apart from each other, that is, the two adjacent gate structures 14 form a gap H. The cross-section of the gap H is a closed ring, which is approximately "O" shaped or "U" shaped. In other embodiments, this gap can be of other shapes, and the gap will be smaller when the distance between the two transistors decreases. In this embodiment, the gap H formed by the gate body 141, the first extension 142, and the second extension 143 can be filled with a dielectric material, so that the first extension 142 and the second extension 143 are insulated from each other. In some embodiments, the gap H formed by the gate body 141, the first extension 142, and the second extension 143 may not be filled with a dielectric material.

[0089] The memory 100 also includes an insulating layer 30, an isolation layer 40, and a barrier element 50. Along the third direction Z, the insulating layer 30, the isolation layer 40, and the gate dielectric layer 15 are sequentially stacked on the substrate 20. Both the insulating layer 30 and the isolation layer 40 cover the peripheral side surfaces of the bit line BL. The surface of the isolation layer 40 facing away from the insulating layer 30 is flush with the surface of the bit line BL facing away from the substrate 20. The gate dielectric layer 15 connects to the surface of the isolation layer 40 facing away from the insulating layer 30 and covers the portion of the bit line BL exposed by the isolation layer 40. It can be understood that along the second direction Y, the width of the orthogonal projection of the transistor 10 is the same as the width of the bit line BL.

[0090] like Figure 4 As shown, the insulating layer 30 and the isolation layer 40 are located between two adjacent bit lines BL and insulate the two adjacent bit lines BL. The transistor 10 protrudes from the isolation layer 40.

[0091] The gate dielectric layer 15 includes a dielectric body 151, a first dielectric layer 152, and a second dielectric layer 153. The dielectric body 151 covers the peripheral side surface of the channel 12. Along the third direction Z, the first dielectric layer 152 and the second dielectric layer 153 are located at opposite ends of the dielectric body 151, and can be located on opposite sides of the dielectric body 151 in the second direction Y. It is understood that the second dielectric layer 153 is located at one end of the dielectric body 151 and extends along both the positive and negative directions of the second direction Y. The first dielectric layer 152 is located at the other end of the dielectric body 151 and extends along both the positive and negative directions of the second direction Y. The first dielectric layer 152 covers the peripheral surface of the source 11 and covers the surface of the isolation layer 40 facing away from the insulating layer 30. A first extension 142 is located near the source 11 and connected to the first dielectric layer 152. The length of the first extension 142 is equal to the width of the first dielectric layer 152. Along the first direction X, the second dielectric layer 153 covers the two opposite ends of the drain 13 and the two opposite ends of the blocking member 50. The second extension 143 is located near the drain 13 and connected to the second dielectric layer 153, with its extension direction parallel to that of the second dielectric layer 153. The length of the second extension 143 is equal to the length of the second dielectric layer 153. The gate body 141 is connected to the outer peripheral surface of the dielectric body 151 facing away from the channel 12. Along the third direction Z, the height of the gate body 141 is less than the height of the dielectric body 151. It can be understood that along the third direction Z, the first dielectric layer 152 is located between the first extension 142 and the isolation layer 40, and the second extension 143 is stacked on the side of the second dielectric layer 153 facing the first dielectric layer 152. Figure 5 As shown, the cross-section of the gate dielectric layer 15 and the gate structure 14 of a transistor 10 in one direction is approximately “][” shaped.

[0092] For example, the drains 13 and the blocking members 50 of the S transistors 10 in the same row are connected to the opposite sides of a second dielectric layer 153. The peripheral surfaces of the sources 11 of the S transistors 10 in the same row are surrounded by a first dielectric layer 152. The peripheral surfaces of the channels 12 of the S transistors 10 in the same row are surrounded by a dielectric body 151.

[0093] The blocking member 50 is embedded in the second dielectric layer 153 of the gate dielectric layer 15 and is separated from the second dielectric layer 153 and the second extension 143. Specifically, the blocking member 50 is connected to the side of the second dielectric layer 153 facing away from the gate structure 14. The orthogonal projection of the blocking member 50 falls within the orthogonal projection of the gate dielectric layer 15 and the gate structure 14, and the orthogonal projection of the blocking member 50 falls within the orthogonal projection of the second dielectric layer 153. Along the second direction Y, the blocking member 50 covers the two opposite end faces of the drain 13 and exposes the end face of the drain 13 facing away from the channel 12. The blocking member 50 is used to insulate two adjacent drains 13. The gate dielectric layer 15 isolates the channel 12, the blocking member 50 and the gate structure 14, not only providing insulation but also protecting the channel 12 to prevent damage to the channel 12 during the fabrication of the memory 100.

[0094] In this embodiment, the memory 100 further includes an encapsulation layer 60. Along the third direction Z, the encapsulation layer 60 is stacked on the side of the first dielectric layer 152 facing away from the isolation layer 40. The encapsulation layer 60 connects the gate structures 14 of every two adjacent transistors 10 and exposes the end of the drain 13 of the transistor 10 facing away from the substrate 20. Exemplarily, the surfaces of the drains 13 of N transistors 10 facing away from the substrate 20 are all exposed in the encapsulation layer 60.

[0095] Along the second direction Y, the encapsulation layer 60 fills the space between every two adjacent word lines WL, thus insulating multiple word lines WL from each other. The encapsulation layer 60 also fills the gap H formed between the gate structures 14 of adjacent transistors 10 connected to a single word line WL, thus insulating adjacent gate structures 14 of the transistors 10 from each other. Specifically, the encapsulation layer 60 connects the first extension 142, the second extension 143, and the gate body 141 of every two connected gate structures 14. It can be understood that part of the encapsulation layer 60 fills the gap H, while another part of the encapsulation layer 60 can fill the space between two adjacent transistors 10 located on the same bit line. The encapsulation layer 60 supports the word lines WL and transistors 10, thereby improving the structural stability of the word lines WL and transistors 10. Simultaneously, the encapsulation layer 60 also protects the word lines WL and transistors 10.

[0096] Another aspect of this application embodiment also provides a method for manufacturing a memory 100, which can be used to manufacture the memory 100 described in the above embodiments. For example... Figure 6 As shown, Figure 6 This is a schematic flowchart illustrating a method for fabricating a memory with vertical transistors, as provided in an embodiment of this application.

[0097] This application provides a method for manufacturing a memory 100, including:

[0098] S1: A substrate 20 is provided, and multiple bit lines BL, a source layer 71, a channel base layer 72 and a drain layer 73 are formed on the substrate 20; the bit lines BL, the source layer 71, the channel base layer 72 and the drain layer 73 are stacked sequentially along the height direction of the memory 100 and form a sidewall 70; along the second direction Y, a first trench B is formed between every two sidewalls 70, and the first trench B exposes the surface of the substrate 20.

[0099] S2: A protective layer 81 is formed on the outer surface of the sidewall 70. The protective layer 81 covers the entire outer surface of the sidewall 70.

[0100] S3: An insulating layer 30 is formed on the substrate 20. The insulating layer 30 covers the surface of the substrate 20 located in the first trench A and covers a portion of the peripheral side surface of the bit line BL.

[0101] S4: An isolation layer 40 is formed on the side of the insulating layer 30 facing away from the substrate 20. The isolation layer 40 covers the peripheral side surface of the bit line BL exposed by the insulating layer 30. Along the thickness direction of the substrate 20, the orthographic projection of the isolation layer 40 coincides with the orthographic projection of the insulating layer 30.

[0102] S5: A sacrificial layer 82 is formed on the side of the isolation layer 40 facing away from the substrate 20, and the drain layer 73 is exposed on the side of the sacrificial layer 82 facing away from the substrate 20; wherein, the sacrificial layer 82 is located in the first trench B and covers the periphery of the channel base layer 72 and the source layer 71.

[0103] S6: Multiple spaced-apart barrier layers 83 and multiple second trenches B are formed on the sacrificial layer 82, with each pair of barrier layers 83 separated by a second trench B. The extension direction of the multiple barrier layers 83 intersects the extension direction of the bit line BL, and the barrier layers 83 cover the drain layer 73 and expose the outer side of the sacrificial layer 82.

[0104] S7: Using the barrier layer 83 as a mask, the sidewall 70 and sacrificial layer 82 are etched using a photomask process to form the channel base layer 72 constituting the sidewall 70 into the channel 12, the source layer 71 into the source 11, and the drain layer 73 into the drain 13. The portion of the isolation layer 40 facing away from the substrate 20 is exposed through the second trench B, and the bit line BL is exposed on the surface of the isolation layer 40. The source 11, channel 12, and drain 13 form a columnar structure F.

[0105] S8: A gate oxide layer 7 and a gate material layer 8 are sequentially formed on the isolation layer 40. The gate oxide layer 7 covers the surface of the isolation layer 40 facing away from the insulating layer 30, exposes the ends of multiple bit lines BL of the isolation layer 40, the outer surfaces of multiple pillar structures F, and multiple barrier layers 83. The gate material layer 8 covers the outer surface of the gate oxide layer 7.

[0106] S9: Dry etching is used to etch the gate material layer 8 on the side opposite to the substrate 20 and the gate material layer 8 located in the second trench B, and partially exposes the gate oxide material layer 7 to form the gate layer 85.

[0107] S10: Deposit a dielectric material layer 9 on the substrate 20, and planarize the dielectric material layer 9, the barrier layer 83, and the gate oxide material layer 7 on the side opposite to the substrate 20, so that the barrier layer 83 forms a barrier 50, the gate oxide material layer 7 forms a gate dielectric layer 15, and the planarized dielectric material layer 9 forms an encapsulation layer 60.

[0108] S11: Etch a portion of the gate layer 85 located between the gate dielectric layer 15 and the package layer 60 to form a gate structure 14, and the gate structure 14, the gate dielectric layer 15 and the pillar structure F form a transistor 10.

[0109] Specifically, the following will be combined with the appendix Figures 7 to 42 The method for manufacturing the memory 100 provided in this application embodiment will be described in detail. It should be noted that the parts that are the same as or corresponding to those in the foregoing embodiments can be referred to in the detailed description of the foregoing embodiments, and will not be repeated hereafter. Figures 7 to 42 The diagram shows the structural schematic and cross-sectional schematic of each step in the fabrication method of the memory 100 provided in the embodiments of this application.

[0110] like Figure 7 , Figure 8 and Figure 9 As shown, Figure 7 for Figure 6 The diagram shown is a schematic of the structure formed by sequentially depositing a bit line material layer and a transistor material layer in step S1. Figure 8 for Figure 6 The schematic diagram of the structure formed corresponding to step S1 shown is as follows: Figure 9 for Figure 8 The diagram shows a cross-sectional view of the structure formed in step S1 along the second direction Y.

[0111] Step S1 includes: providing a substrate 20, and forming multiple bit lines BL, a source layer 71, a channel base layer 72, and a drain layer 73 on the substrate 20; the bit lines BL, the source layer 71, the channel base layer 72, and the drain layer 73 are stacked sequentially along the height direction of the memory 100 to form sidewalls 70; along the second direction Y, a first trench B is formed between every two sidewalls 70, and the first trench B exposes the surface of the substrate 20.

[0112] This step specifically includes sequentially growing a bit line material layer 1 and a transistor material layer 2 on the surface of the substrate 20. The transistor material layer 2 is located on the surface of the bit line material layer 1 facing away from the substrate 20. The substrate 20 can be made of semiconductor materials, such as silicon (Si), polycrystalline silicon (Poly-Si), crystalline silicon, germanium (Ge), gallium arsenide (GaAs), indium phosphide (lnP), etc. Alternatively, the substrate 20 can also be made of non-conductive materials such as glass, plastic, or sapphire wafers. The bit line material layer 1 can be made of materials such as tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polycrystalline silicon, doped silicon, and silicides. The transistor material layer 2 can be made of materials such as polycrystalline silicon, doped silicon, and silicides. In this embodiment, the substrate 20 is a silicon substrate 20. The bit line material layer 1 can be made of tungsten. The transistor material layer 2 can be made of polycrystalline silicon.

[0113] The bit line material layer 1 and the transistor material layer 2 are patterned using a photomask process. The patterned bit line material layer 1 forms multiple bit lines BL spaced apart along the second direction Y. The patterned transistor material layer 2 also forms multiple source layers 71, multiple channel base layers 72, and multiple drain layers 73 spaced apart along the second direction Y. Each source layer 71, its corresponding channel base layer 72, and its drain layer 73 form a sidewall 70. Patterning involves forming the desired pattern across the entire material layer using a photomask process. A photomask process refers to a process using a mask or photomask, or a process that can be combined with etching. Photomask processes can process planar material layers, removing unwanted areas and retaining desired areas.

[0114] For example, along the third direction Z, a patterned mask (not shown) is first formed on top of the transistor material layer 2; using the patterned mask as a mask, a photomask process is performed on the transistor material layer 2 and bit line material layer 1 at the bottom of the mask along the pattern. After the photomask process, multiple sidewalls 70 and multiple first trenches A are formed, consisting of bit lines BL, source layer 71, channel base layer 72, and drain layer 73. The bit lines BL, source layer 71, channel base layer 72, and drain layer 73 are sequentially stacked on the substrate 20 along the height direction (third direction Z) of the memory 100. Each bit line BL corresponds to one source layer 71, one channel base layer 72, and one drain layer 73. One drain layer 73, one channel base layer 72, one source layer 71, and one bit line BL constitute one sidewall 70. The extension direction of the multiple sidewalls 70 is consistent with the first direction X. The multiple sidewalls 70 are arranged at intervals along the second direction Y. Along the second direction Y, a first trench A is formed between two adjacent sidewalls 70. The extension direction of the plurality of first trenches A is consistent with the first direction X. The plurality of first trenches A are arranged at intervals along the second direction Y. The first trenches A expose the substrate 20 located between the plurality of sidewalls 70.

[0115] It should be noted that, along the third direction Z, the depth of the first trench A is equal to the height of the sidewall 70. Along the second direction Y, the width of the first trench A can be greater than the width of the bit line BL; its specific dimensions can be determined according to the actual application scenario of the memory 100, and this embodiment does not impose any restrictions on this. Along the second direction Y, the widths of the source layer 71, the channel base layer 72, and the drain layer 73 are all equal to the width of the bit line BL, and the widths of the source layer 71, the channel base layer 72, the drain layer 73, and the bit line BL are all smaller than the width of the substrate 20. That is, the orthographic projections of the bit line BL, the source layer 71, the channel base layer 72, and the drain layer 73 along the height direction of the memory 100 completely overlap.

[0116] The bit line material layer 1 and the transistor material layer 2 can be formed on the substrate 20 using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy (EPI), and metal-organic chemical vapor deposition (MOCVD). The bit line material layer 1 can also be formed on the substrate 20 using metal-CVD (M-CVD). This application does not impose any limitations on this.

[0117] like Figure 10 and Figure 11 As shown, Figure 10 for Figure 6 The diagram shown illustrates the structure formed by the deposition of the protective layer in step S2. Figure 11 for Figure 10 The diagram shows a cross-sectional view of the structure formed in step S2 along the second direction Y.

[0118] Step S2 includes forming a protective layer 81 on the outer surface of the sidewall 70. The protective layer 81 covers the entire outer surface of the sidewall 70.

[0119] Specifically, an atomic layer deposition (ALD) device is used to deposit a protective layer 81 on the sidewall 70 and the substrate 20. The protective layer 81 can be made of materials such as amorphous silicon (α-Si).

[0120] A protective layer 81 covers the outer surface of the sidewall 70. The protective layer 81 can also cover the surface of the substrate 20 exposed between the two sidewalls 70. The protective layer 81 serves to protect the bit line BL, source layer 71, channel base layer 72, and drain layer 73 during subsequent processing, reducing losses in these components and improving processing accuracy. It should be noted that the protective layer 81 located on the substrate 20... Figure 11 and Figure 12 Not shown in the image.

[0121] In some embodiments, along the third direction Z, the protective layer 81 on the sidewall 70 facing away from the substrate 20 needs to be etched to expose the drain layer 73. Similarly, the protective layer 81 on the substrate 20 can also be removed.

[0122] In some embodiments, step S2 may be omitted if necessary.

[0123] like Figures 12 to 15 As shown, Figure 12 for Figure 6 The diagram shown is a schematic representation of the structure formed by depositing the insulating material layer in step S3. Figure 13 for Figure 12 The diagram shows a cross-sectional view of the structure of the deposited insulating material layer along the second direction Y. Figure 14 for Figure 6 The schematic diagram of the structure formed corresponding to step S3 is shown. Figure 15 for Figure 14 The diagram shows a cross-sectional view of the structure formed in step S3 along the second direction Y.

[0124] Step S3 includes forming an insulating layer 30 on the substrate 20. The insulating layer 30 covers the surface of the substrate 20 located in the first trench A and covers a portion of the peripheral side surface of the bit line BL.

[0125] Specifically, an insulating material layer 3 is formed by deposition, and then the insulating material layer 3 is etched. The resulting insulating layer 30 surrounds a portion of the bit line BL. The thickness of the insulating layer 30 is less than the thickness of the bit line BL. It can be understood that the insulating layer 30 covers a portion of the first trench A. Dry or wet etching methods can be used to etch the insulating material layer 3.

[0126] The insulating material layer 3 can be deposited using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy (EPI), and metal-organic chemical vapor deposition (MOCVD). This application does not impose any restrictions on this method.

[0127] The insulating material layer 3 includes, but is not limited to, Hf-based materials, silicon dioxide (SiO2), silicon nitride (Si3N4), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and combinations thereof. In this embodiment, the insulating material layer 3 may be made of silicon dioxide. During deposition, the insulating material layer 3 fills the first trench A between the sidewalls 70 and completely covers the sidewalls 70 and the surface of the substrate 20. Along the third direction Z, the deposition height of the insulating material layer 3 is greater than the height of the sidewalls 70. Along the first direction X, the deposition length of the insulating material layer 3 is equal to the length of the substrate 20. Along the second direction Y, the deposition width of the insulating material layer 3 is equal to the width of the substrate 20.

[0128] The insulating layer 30 not only separates the multiple bit lines BL and insulates them from each other, but also protects the bit lines BL and the substrate 20, reducing the loss of the bit lines BL and the substrate 20 in subsequent processing.

[0129] like Figures 16 to 19 As shown, Figure 16 for Figure 6 The diagram shown is a schematic of the structure formed by depositing the isolation material layer in step S4. Figure 17 for Figure 16 The diagram shows a cross-sectional view of the structure of the deposited isolation material layer along the second direction Y. Figure 18 for Figure 6 The schematic diagram of the structure formed corresponding to step S4 shown is shown below. Figure 19 for Figure 18 The diagram shows a cross-sectional view of the structure formed in step S4 along the second direction Y.

[0130] Step S4 includes forming an isolation layer 40 on the side of the insulating layer 30 facing away from the substrate 20. The isolation layer 40 covers the peripheral side surface of the bit line BL exposed by the insulating layer 30. Along the thickness direction of the substrate 20, the orthographic projection of the isolation layer 40 coincides with the orthographic projection of the insulating layer 30.

[0131] Specifically, an isolation material layer 4 is deposited on the substrate 20, and then the isolation material layer 4 is etched to form an isolation layer 40. The isolation layer 40 covers a portion of the first trench A and surrounds the periphery of the bit line BL exposed by the insulating layer 30. Along the third direction Z, the sum of the heights of the isolation layer 40 and the insulating layer 30 is equal to the height of the bit line BL.

[0132] In this embodiment, the isolation material layer 4 can be deposited using methods such as chemical vapor deposition, physical vapor deposition, epitaxy, and metal-organic chemical vapor deposition. This application does not impose any limitations on this method.

[0133] The isolation material layer 4 can be, but is not limited to, Hf-based materials, silicon dioxide (SiO2), silicon nitride (Si3N4), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and combinations thereof. In this embodiment, the isolation material layer 4 can be made of silicon nitride. During deposition, the isolation material layer 4 fills the first trench A and completely covers the sidewall 70 and the side surface of the insulating layer 30 facing away from the substrate 20. Along the third direction Z, the sum of the deposition height of the isolation material layer 4 and the height of the insulating layer 30 is greater than the height of the sidewall 70. Along the first direction X, the deposition length of the isolation material layer 4 is equal to the length of the insulating layer 30. Along the second direction Y, the deposition width of the isolation material layer 4 is equal to the width of the insulating layer 30.

[0134] The isolation layer 40 not only further separates the multiple bit lines BL and insulates them from each other, but also protects the bit lines BL and the insulation layer 30, reducing the damage to the bit lines BL and the insulation layer 30 caused by subsequent processing.

[0135] like Figures 20 to 23 As shown, Figure 20 for Figure 6 The diagram shown is a schematic of the structure formed by depositing the first sacrificial material layer in step S5. Figure 21 for Figure 20 The diagram shown is a cross-sectional view of the structure of the first sacrificial material layer deposited along the second direction Y. Figure 22 for Figure 6 The schematic diagram of the structure formed corresponding to step S5 is shown below. Figure 23 for Figure 22 The diagram shows a cross-sectional view of the structure formed in step S5 along the second direction Y.

[0136] Step S5 includes: forming a sacrificial layer 82 on the side of the isolation layer 40 facing away from the substrate 20, and exposing the side of the sacrificial layer 82 facing away from the substrate 20; wherein the sacrificial layer 82 is located in the first trench B and covers the periphery of the channel base layer 72 and the source layer 71.

[0137] Specifically, a first sacrificial material layer 5a is deposited on the substrate 20 where the isolation layer 40 is formed. Then, the first sacrificial material layer 5a is etched to reduce its thickness, forming a sacrificial layer 82. A portion of the first trench A away from the substrate 20 exposes the sacrificial layer 82; that is, the end of the sidewall 70 away from the substrate 20 protrudes from the sacrificial layer 82. Along the third direction Z, the sum of the heights of the insulating layer 30, the isolation layer 40, and the sacrificial layer 82 is less than the height of the sidewall 70. It can be understood that the sidewall 70 and the first trench A expose the sacrificial layer 82. The sacrificial layer 82 is the bottom wall of the first trench A. The portion of the sidewall 70 exposed above the sacrificial layer 82 is the drain layer 73. The height of the drain layer 73 exposed above the sacrificial layer 82 (i.e., the thickness of the drain layer 73) can be determined according to the actual application scenario of the drain 13 of the memory 100; this embodiment does not impose any limitations on this.

[0138] The first sacrificial material layer 5a can be deposited using methods such as chemical vapor deposition, physical vapor deposition, epitaxy, and metal-organic chemical vapor deposition. This application does not impose any restrictions on this method.

[0139] In this embodiment, during deposition, the first sacrificial material layer 5a fills the remaining portion of the first trench A and completely covers the sidewall 70 and the side of the isolation layer 40 facing away from the insulating layer 30. Along the third direction Z, the sum of the deposition height of the first sacrificial material layer 5a, the height of the isolation layer 40, and the height of the insulating layer 30 is greater than the height of the sidewall 70. Along the first direction X, the deposition length of the first sacrificial material layer 5a is equal to the length of the isolation layer 40. Along the second direction Y, the deposition width of the first sacrificial material layer 5a is equal to the width of the isolation layer 40. The first sacrificial material layer 5a can be made of materials such as silicon dioxide.

[0140] The sacrificial layer 82 not only separates the source layer 71 and the channel base layer 72 and insulates them from each other, but also protects the source layer 71, the channel base layer 72 and the isolation layer 40, reducing the damage to the channel base layer 72 and the isolation layer 40 caused by subsequent processing.

[0141] like Figures 24 to 26 As shown, Figure 24 for Figure 6 The diagram shown in the first embodiment of step S6 illustrates the structure formed by the deposition of the barrier material layer. Figure 25 for Figure 6 The schematic diagram of the structure formed in the first embodiment of step S6 is shown. Figure 26 for Figure 25 The diagram shows a cross-sectional view of the structure formed in step S6 along the second direction Y.

[0142] Step S6 includes forming a plurality of spaced-apart barrier layers 83 and a plurality of second trenches B on the sacrificial layer 82, wherein each pair of barrier layers 83 is spaced apart by a second trench B. The extension directions of the plurality of barrier layers 83 intersect the extension direction of the bit line BL, and the barrier layers 83 cover the drain layer 73 and expose the outer side of the sacrificial layer 82.

[0143] Specifically, a barrier material layer 6 is deposited on the drain layer 73, the first trench A, and the sacrificial layer 82, and the barrier material layer 6 is patterned. The patterned barrier material layer 6 forms multiple barrier layers 83 and a second trench B located between two adjacent barrier layers 83. The multiple barrier layers 83 cover a portion of the drain layer 73 and a portion of the sacrificial layer 82. The second trench B exposes the portions of the sacrificial layer 82 and the drain layer 73 that are not covered by the barrier layers 83.

[0144] The barrier material layer 6 includes, but is not limited to, Hf-based materials, silicon dioxide (SiO2), silicon nitride (Si3N4), zirconium dioxide (ZrO2), aluminum oxide (Al2O3), and combinations thereof. In this embodiment, the barrier material layer 6 is made of silicon nitride.

[0145] The barrier material layer 6 can be deposited using the same method as the isolation material layer 4 in step S5 above. This application does not impose any limitations on this.

[0146] In this embodiment, during deposition, the barrier material layer 6 fills the remaining portion of the first trench A and completely covers the side of the sacrificial layer 82 facing away from the isolation layer 40 and the sidewall 70 exposed above the sacrificial layer 82. Along the third direction Z, the sum of the deposition height of the barrier material layer 6, the height of the sacrificial layer 82, the isolation layer 40, and the insulating layer 30 is greater than the height of the sidewall 70. Along the first direction X, the deposition length of the barrier material layer 6 is equal to the length of the sacrificial layer 82. Along the second direction Y, the deposition length of the barrier material layer 6 is equal to the width of the sacrificial layer 82.

[0147] For example, the specific fabrication process for forming the barrier layer 83 and the second trench B can be as follows: along the third direction Z, a patterned mask (not shown) is first formed on the side of the barrier material layer 6 facing away from the sacrificial layer 82; using the patterned mask as a mask; a photomask process is performed on the barrier material layer 6 at the bottom of the mask along the pattern; the remaining barrier material layer 6 after the photomask process is planarized using chemical mechanical polishing (CMP); after planarization, the barrier material layer 6 forms a plurality of second trenches B spaced apart along the first direction X, and a plurality of barrier layers 83 spaced apart along the first direction X. The plurality of barrier layers 83 extend along the second direction Y and are perpendicular to the bit line BL. The plurality of second trenches B extend along the second direction Y and are perpendicular to the extension direction of the first trench A. Along the first direction X, the barrier layers 83 and the second trenches B are arranged alternately. The second trenches B expose the sacrificial layer 82 located between the plurality of barrier layers 83 and the portion of the drain layer 73 not covered by the barrier layers 83. The barrier layer 83, the sacrificial layer 82, and the drain layer 73 form a second trench B. Along the first direction X, the sidewalls of the barrier layer 83 form the trench sidewalls of the second trench B. The surfaces of the sacrificial layer 82 and the drain layer 73 form the trench bottom wall of the second trench B. It should be noted that along the second direction Y, the length of the barrier layer 83 is equal to the length of the sacrificial layer 82.

[0148] It should be noted that in this embodiment, the barrier layer 83 covers a portion of the drain layer 73, that is, along the third direction Z, the drain layer 73 exposed on the sacrificial layer 82 is at least partially embedded in the barrier layer 83. Along the second direction Y, one barrier layer 83 connects multiple drain layers 73. Along the third direction Z, the thickness of the barrier layer 83 is greater than the thickness of the drain layer 73 exposed on the sacrificial layer 82. The barrier layer 83 not only separates and insulates the drain layers 73, but also protects the drain layer 73, the channel base layer 72, and the source layer 71 of the isolation layer 40 from damage in subsequent processing.

[0149] like Figure 25 , Figure 27 and Figure 28 As shown, Figure 27 for Figure 6 The diagram shown is a schematic representation of the structure formed by depositing the second sacrificial material layer in the second embodiment of step S6. Figure 28 for Figure 27 The diagram shows a structure in which the second sacrificial material layer is deposited to form the groove 84.

[0150] In other embodiments, step S6 may further include: forming a plurality of spaced-apart barrier layers 83 and a plurality of second trenches B on the sacrificial layer 82, wherein each pair of barrier layers 83 is spaced apart by a second trench B. The extension directions of the plurality of barrier layers 83 intersect the extension direction of the bit line BL, and the barrier layers 83 cover the drain layer 73, exposing the outer side of the sacrificial layer 82.

[0151] Specifically, a second sacrificial material layer 5b is deposited on a substrate 20 having a sacrificial layer 82, and the second sacrificial material layer 5b is patterned. The patterned second sacrificial material layer 5b is etched to form grooves 84, and multiple grooves 84 are spaced apart along the second direction Y. Next, a barrier material layer 6 is filled into the grooves 84, and then the remaining second sacrificial material layer 5b is removed by etching using dry or wet methods. The barrier material layer 6 is then planarized by chemical mechanical polishing, forming multiple barrier layers 83 spaced apart along the second direction Y, and second trenches B located between adjacent barrier layers 83. The multiple barrier layers 83 extend along the second direction Y and are perpendicular to the bit line BL. The multiple barrier layers 83 are spaced apart along the first direction X. A second trench B is formed between adjacent barrier layers 83. The multiple second trenches B extend along the second direction Y and are perpendicular to the extension direction of the first trench A. The multiple second trenches B are spaced apart along the first direction X.

[0152] It should be noted that in this embodiment, the material selected to form the second sacrificial material layer 5b is different from the material selected to form the first sacrificial material layer 5a, such as aluminum oxide. It is understood that when etching the second sacrificial material layer 5b, the second sacrificial material layer 5b has lower hardness and a higher etching rate compared to the material used to form the sacrificial layer 82, which ensures that the sacrificial layer 82 will not suffer excessive loss during the etching of the second sacrificial material layer 5b.

[0153] like Figures 29 to 31 As shown, Figure 29 for Figure 6 The schematic diagram of the structure formed corresponding to step S7 is shown. Figure 30 for Figure 29 The diagram shows a cross-sectional view of the structure formed in step S7 along the first direction X. Figure 31 for Figure 29 The diagram shows a cross-sectional view of the structure formed in step S7 along the second direction Y.

[0154] Step S7 includes: using the barrier layer 83 as a mask, etching the sidewall 70 and the sacrificial layer 82 using a photomask process, so that the channel base layer 72 constituting the sidewall 70 forms the channel 12, the source layer 71 forms the source 11, and the drain layer 73 forms the drain 13. The portion of the isolation layer 40 facing away from the substrate 20 is exposed through the second trench B, and the bit line BL is exposed on the surface of the isolation layer 40. The source 11, the channel 12, and the drain 13 form a columnar structure F.

[0155] Specifically, a photomask process is performed using a barrier layer 83 as a hard mask. The drain layer 73, channel base layer 72, and source layer 71, which are not covered by the barrier layer 83 (i.e., the portion of the sidewall 70 not located in the barrier layer 83 and the bit line BL in the third direction Z), are etched. The etched drain layer 73 forms a drain 13, the etched source layer 71 forms a source 11, and the etched channel base layer 72 forms a channel 12, exposing a portion of the bit line BL. It can be understood that the channel base layer 72, source layer 71, and drain layer 73 connected on the same bit line BL are separated into multiple channels 12 and multiple sources 11 and multiple drains 13 located at both ends of each channel 12. Each channel 12 and the source 11 and drain 13 located at both ends of that channel 12 form a columnar structure F. Multiple columnar structures F form an array. Adjacent columnar structures F are spaced apart along the first direction X and the second direction Y. Then, the remaining sacrificial layer 82 (surrounding the columnar structure F) is removed by wet etching, exposing the isolation layer 40 and part of the bit line BL not covered by the source 11.

[0156] It should be noted that a barrier layer 83, which spaced and connected multiple drains 13 arranged in a row along the second direction Y, helps to establish the columnar structure F during the fabrication of the memory 100, ensuring the stability of two adjacent columnar structures F in subsequent processing. At the same time, the barrier layer 83 separates two adjacent drains 13, thus insulating the two adjacent columnar structures F.

[0157] It should be noted that the protective layer 81 has been completely consumed in the photomask process in this step, so the protective layer 81 is not shown in the figure.

[0158] like Figures 32 to 37 , Figure 32 for Figure 6 The diagram shown is a schematic of the structure formed by depositing the gate oxide material layer in step S8. Figure 33 for Figure 32 The diagram shows a cross-sectional view of the structure of the deposited gate oxide material layer along the first direction X. Figure 34 for Figure 32 The diagram shows a cross-sectional view of the deposited gate oxide material layer along the second direction Y. Figure 35 for Figure 6The diagram shown is a schematic of the structure formed by depositing the gate material layer in step S8. Figure 36 for Figure 35 The diagram shows a cross-sectional view of the deposited gate material layer along the first direction X. Figure 37 for Figure 35 The diagram shows a cross-sectional view of the structure of the deposited gate material layer along the second direction Y.

[0159] Step S8 includes: sequentially forming a gate oxide material layer 7 and a gate material layer 8 on the isolation layer 40. The gate oxide material layer 7 covers the surface of the isolation layer 40 facing away from the insulating layer 30, exposes the ends of multiple bit lines BL of the isolation layer 40, the outer surfaces of multiple pillar structures F, and multiple barrier layers 83. The gate material layer 8 covers the outer surface of the gate oxide material layer 7.

[0160] Specifically, a portion of the gate oxide layer 7 surrounds the outer surface of the columnar structure F, separating and insulating adjacent columnar structures F. The gate oxide layer 7 also separates and insulates the source 11, channel 12, and drain 13 from the gate oxide layer 8. Simultaneously, the gate oxide layer 7 protects the columnar structure F, preventing it from being damaged during subsequent processing. The gate oxide layer 8 surrounds the outer surface of the columnar structure F and is located on the side of the gate oxide layer 7 facing away from the columnar structure F.

[0161] In this embodiment, the gate oxide layer 7 can be made of silicon dioxide or the like. The gate material layer 8 can be made of ruthenium. It should be noted that, as... Figure 37 As shown, along the second direction Y, the surface located between two adjacent channels 12 is covered by a gate oxide material layer 7 and a gate material layer 8, forming a gap H. The cross-section of the gap H can be "O" shaped or "U" shaped.

[0162] like Figure 38 and Figure 39 As shown, Figure 38 for Figure 6 The schematic diagram of the structure formed corresponding to step S9 is shown below. Figure 39 for Figure 38 The diagram shows a cross-sectional view of the structure formed in step S9 along the first direction X.

[0163] Step S9 includes: dry etching the gate material layer 8 on the side opposite to the substrate 20 and the gate material layer 8 located in the second trench B, and partially exposing the gate oxide material layer 7 to form the gate layer 85.

[0164] like Figures 40 to 42 As shown, Figure 40 for Figure 6 The diagram shown is a schematic of the structure formed by depositing the dielectric material layer in step S10. Figure 41 for Figure 40The schematic diagram of the structure formed corresponding to step S10 shown is as follows: Figure 42 for Figure 41 The diagram shows a cross-sectional view of the structure formed in step S10 along the first direction X.

[0165] Step S10 includes: depositing a dielectric material layer 9 on the substrate 20, and planarizing the dielectric material layer 9, the barrier layer 83 and the gate oxide material layer 7 on the side opposite to the substrate 20, so that the barrier layer 83 forms a barrier 50, the gate oxide material layer 7 forms a gate dielectric layer 15, and the planarized dielectric material layer 9 forms an encapsulation layer 60.

[0166] The dielectric material layer 9 can be deposited using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy (EPI), and metal-organic chemical vapor deposition (MOCVD). This application does not impose any restrictions on this method.

[0167] For example, such as Figure 40 As shown, during deposition, the dielectric material layer 9 can fill the gap H of the gate material layer 8 between two adjacent columnar structures F in the second direction Y and the second trench B, and completely cover the gate material layer 8 and the exposed gate dielectric layer 15. In this embodiment, the material of the dielectric material layer 9 can be the same as the material of the gate oxide material layer 7, such as silicon dioxide.

[0168] Using chemical mechanical polishing, the deposited dielectric material layer 9, gate oxide material layer 7, gate material layer 8, and barrier layer 83 are all planarized until they are flush with the end of the drain 13 facing away from the bit line BL, thereby forming a layer as shown in the figure. Figure 41The basic device is shown. Specifically, a planarized dielectric material layer 9 forms an encapsulation layer 60. A planarized barrier layer 83 forms a barrier 50. A planarized gate oxide material layer 7 forms a gate dielectric layer 15. A planarized gate material layer 8 forms a gate layer 85. The encapsulation layer 60 encapsulates the barrier 50, the source 11, the drain 13, and the channel 12, as well as the gap H between two adjacent columnar structures F. The end of the drain 13, a portion of the gate dielectric layer 15, and the gate layer 85 are exposed on the side of the encapsulation layer 60. The gate dielectric layer 15 includes a first dielectric layer 152 and a second dielectric layer 153 located at both ends of the columnar structure F in the height direction. Along the second direction Y, the drain 13 of a columnar structure F is sandwiched between two adjacent barrier elements 50, and the drain 13 is exposed. Along the first direction X, the exposed portion of the gate dielectric layer 15 and the gate layer 85 is located between the barrier 50 and the encapsulation layer 60, that is, the exposed portion of the gate dielectric layer 15 and the gate layer 85 is connected between the barrier 50 and the drain 13 on opposite sides in the first direction X.

[0169] It should be noted that the planarized gate oxide layer 7 is used to form the first dielectric layer 152, the second dielectric layer 153, and the dielectric body 151 of the gate dielectric layer 15 of the memory 100. The first dielectric layer 152 covers the side of the isolation layer 40 facing away from the insulating layer 30, and can be used to separate the gate layer 85 and the isolation layer 40, and to insulate the source 11 from the gate layer 85. The second dielectric layer 153 surrounds the barrier 50 and the drain 13 on the outer side facing the package layer 60. The dielectric body 151 surrounds the outer periphery of the channel 12, and separates and insulates the channel 12 from the gate layer 85.

[0170] like Figures 1 to 4 As shown, step S11 includes: etching a portion of the gate layer 85 located between the gate dielectric layer 15 and the package layer 60, so that the gate layer 85 forms a gate structure 14, and the gate structure 14, the gate dielectric layer 15 and the pillar structure F form a transistor 10.

[0171] Based on existing mature process technologies, this application provides a memory 100 and its fabrication method, which is simple and highly feasible. Directly stacking the bit line material layer 1 and the transistor material layer 2 followed by patterned etching ensures the accuracy of the formation of the first trench A, facilitates the establishment of the channel 12 of the transistor 10, reduces the overall performance fluctuation of the memory 100, and improves the stability of the memory 100. Furthermore, existing methods for fabricating memory 100 often require four or more photomasks or mask plates to complete the etching, resulting in problems with bit line fabrication, alignment accuracy, and channel 12 miniaturization in terms of memory 100 performance. In this application, only two photomasks are required. By using the barrier layer 83 as a photomask in the fabrication of the memory 100, the number of photomasks required for etching the channel base layer 72, drain layer 73, and source layer 71 of the memory 100 is reduced, thus saving the fabrication cost of the memory 100. Furthermore, by fabricating the memory 100 through the self-alignment of the photomask, the problem of overlay misalignment in the photolithography process in the traditional fabrication process of the memory 100 is solved, the alignment accuracy is increased, and the cost of the memory 100 is further reduced, thereby improving the manufacturing yield of the memory 100.

[0172] The above are merely some embodiments and implementation methods of this application. The scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory, characterized in that, include: The system comprises a substrate, multiple bit lines, and N transistors. The bit lines are spaced apart along a first direction on the surface of the substrate. The N transistors are arranged in an array, with each bit line connected to M transistors. Along a second direction, the N transistors are arranged in multiple rows, with each row containing S transistors spaced apart. M multiplied by S equals N, both M and S are greater than 2, and M, S, and N are all integers. The bit lines are connected to the transistors. The transistor includes a channel, a gate dielectric layer, and a gate structure. The gate structure includes a gate body, a first extension, and a second extension. The first extension and the second extension are connected to both ends of the gate body in the height direction and are disposed opposite to each other. Both the first extension and the second extension extend along the first direction. The first extension is close to the bit line. The gate dielectric layer surrounds the outer periphery of the channel and is connected to the outer periphery side of the channel, and the gate body surrounds the gate dielectric layer and faces away from the outer surface of the channel. In the S transistors, in every two adjacent gate structures, the first extension of one gate structure is connected and conducts with the first extension of the other gate structure, and the second extension of one gate structure is connected and conducts with the second extension of the other gate structure. A gap is formed between the gate bodies arranged along the second direction, wherein the first direction and the second direction are perpendicular, and the height direction of the channel and the height direction of the gate body are both perpendicular to the first direction and the second direction.

2. The memory as claimed in claim 1, characterized in that, The transistor includes a source and a drain, which are respectively connected to the two ends of the channel in the height direction. The source is connected to the bit line. The drains of the N transistors are spaced apart. In the S transistors in the same row, a blocking element is connected between every two adjacent drains.

3. The memory as described in claim 2, characterized in that, The gate dielectric layer includes a first dielectric layer and a second dielectric layer. The first dielectric layer covers the peripheral surface of the source electrode. The drains of the S transistors in the same row and the opposite sides of the blocking member are connected to the second dielectric layer. The first extension is connected to the first dielectric layer, and the second extension is connected to the second dielectric layer in a second direction.

4. The memory as described in claim 3, characterized in that, The memory further includes a packaging layer that covers a plurality of the transistors and a plurality of the bit lines, the packaging layer filling the gaps between the gate bodies, the opposite ends of the bit lines being exposed by the packaging layer, the drains being exposed by the packaging layer, and in the first direction, second extensions located in the same row being exposed by the packaging layer, and the ends of the drains of the N transistors facing away from the substrate being exposed by the packaging layer.

5. The memory as claimed in claim 4, characterized in that, The memory further includes an insulating layer and an isolation layer, which are sequentially connected to the side of the substrate where the bit lines are located and insulate the bit lines. The bit lines are exposed on the surface of the isolation layer away from the substrate, and the encapsulation layer is connected to the surface of the isolation layer away from the substrate.

6. A method for manufacturing a memory, characterized in that, include: A substrate is provided, and bit lines, source layers, channel base layers and drain layers are formed on the substrate; the bit lines, source layers, channel base layers and drain layers are stacked sequentially along the height direction of the memory and form sidewalls; a first trench is formed between every two sidewalls along a second direction, and the first trench exposes the surface of the substrate; An insulating layer is formed on the substrate, the insulating layer covering the surface of the substrate located within the first trench and covering a portion of the peripheral side surface of the bit line; An isolation layer is formed on the side of the insulating layer facing away from the substrate, the isolation layer covering the peripheral side surface of the bit line exposed by the insulating layer; along the thickness direction of the substrate, the orthographic projection of the isolation layer coincides with the orthographic projection of the insulating layer; A sacrificial layer is formed on the side of the isolation layer facing away from the substrate, and the drain layer is exposed on the side of the sacrificial layer facing away from the substrate; wherein the sacrificial layer is located in the first trench and covers the periphery of the channel base layer and the source layer; A plurality of spaced-apart barrier layers and a plurality of second trenches are formed on the sacrificial layer, with each pair of barrier layers separated by a second trench; wherein the extension direction of the plurality of barrier layers intersects the extension direction of the bit line, and the barrier layers cover the drain layer and expose the outside of the sacrificial layer; Using multiple barrier layers as masks, the drain layer and the sacrificial layer are etched using a photomask process to form a channel base layer, a source layer, and a drain layer; wherein the isolation layer is exposed through a second trench facing away from the substrate, and the bit line is exposed on the surface of the isolation layer; the source, the channel, and the drain form a columnar structure. A gate oxide layer and a gate material layer are sequentially formed on the isolation layer; wherein, the gate oxide layer covers the surface of the isolation layer facing away from the insulating layer, exposes the ends of the plurality of bit lines of the isolation layer, the outer surfaces of the plurality of columnar structures, and the plurality of barrier layers; the gate material layer covers the outer surface of the gate oxide layer; The gate material layer on the side opposite to the substrate and the gate material layer located in the second trench are etched using a dry etching method, and part of the gate oxide material layer is exposed to form a gate layer. A dielectric material layer is deposited on a substrate, and the dielectric material layer, the barrier layer, and the gate oxide layer are planarized on the side opposite to the substrate, so that the barrier layer forms a barrier, the gate oxide layer forms a gate dielectric layer, and the planarized dielectric material layer forms an encapsulation layer. A portion of the gate layer located between the gate dielectric layer and the packaging layer is etched to form a gate structure, and the gate structure, the gate dielectric layer, and the pillar structure form a transistor.

7. The method for manufacturing a memory as described in claim 6, characterized in that, Before forming an insulating layer on the substrate, the method further includes forming a protective layer on the outer surface of the sidewall; wherein the protective layer covers the outer surface of the sidewall.

8. The method for manufacturing a memory as described in claim 7, characterized in that, The step of forming a bit line, a source layer, a channel base layer and a drain layer on the substrate includes growing a bit line material layer and a transistor material layer sequentially on the surface of the substrate, wherein the transistor material layer is located on the surface of the bit line material layer opposite to the substrate. Through a patterning process, multiple bit lines are formed in the bit line material layer, and the source layer, the channel base layer, and the drain layer are formed in the transistor material layer.

9. The method for manufacturing a memory as described in claim 8, characterized in that, The step of forming a plurality of spaced-apart barrier layers and a plurality of second trenches on the sacrificial layer includes depositing a barrier material layer in the drain layer, the first trench and on the sacrificial layer, and patterning the barrier material layer to form a plurality of barrier layers and a second trench between two barrier layers. In this process, when depositing the barrier material layer, the barrier material layer fills the remaining portion of the first trench and completely covers the side of the sacrificial layer facing away from the isolation layer, and also covers the sidewalls exposed by the sacrificial layer; along the second direction, one barrier layer connects multiple drain layers, and the thickness of the barrier layer is greater than the thickness of the drain layers exposed by the sacrificial layer.

10. The method for manufacturing a memory as described in claim 9, characterized in that, In the step of etching the drain layer and the sacrificial layer using a photomask process with multiple barrier layers as masks... The two adjacent columnar structures are spaced apart. The sacrificial layer surrounding the outside of the columnar structure is removed by wet etching to expose the isolation layer and the bit line partially not covered by the source. Each barrier layer spaced a plurality of drains arranged in a row along the second direction.

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