Monolithic integrated PGaN grid-controlled Cascode structure GaN IGBT (Insulated Gate Bipolar Translator)

Abstract

The invention discloses a monolithic integrated PGaN gate-controlled Cascode structure GaN IGBT, and relates to the technical field of semiconductor devices, a third P-GaN layer on the surface is used as a gate region of an E-mode device, and a trench formed by etching a second P-GaN layer, a barrier layer, a channel layer and a part of a drift layer is used as a gate region of a D-mode device. And etching a trench which is in contact with the second P-GaN layer and the two-dimensional electron gas at the same time to serve as an emitter region of the IGBT, and etching a deep trench at the bottom of the substrate to the first P-GaN layer to serve as a collector region of the IGBT. By moving the grid electrode to the surface, the grid electrode and the collector electrode are prevented from being oppositely placed, and reverse transfer capacitance is greatly reduced.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a monolithically integrated GaN IGBT with a PGaN gate-controlled Cascode structure. Background Technology

[0002] The traditional power device market is mainly dominated by silicon-based power devices. With the continuous development of power semiconductor devices, the performance of silicon-based devices has gradually reached a bottleneck. Therefore, third-generation semiconductor materials such as GaN (gallium nitride) and SiC (silicon carbide) have gradually appeared in the field of power semiconductor devices due to their excellent physical and electrical properties, such as high temperature resistance, radiation resistance, wide bandgap, high breakdown field strength and high electron mobility.

[0003] In the field of power semiconductor devices, metal-oxide-semiconductor field-effect transistors (MOSFETs) offer high switching speeds, high input impedance, and low on-state voltage drop, making them commonly used in low-voltage, high-frequency applications. However, their current handling capability is relatively poor, resulting in suboptimal performance under high-voltage, high-current conditions. Gallium nitride trench-gate MOSFETs (GaN Trench Gate MOSFETs) offer many advantages, but as MOSFETs are unipolar transistors and many-carrier devices, they lack conductivity modulation effects. Furthermore, increasing the reverse withstand voltage of a MOSFET thickens the drift region, leading to increased on-resistance. To overcome this drawback, a PN junction is introduced at the drain of the MOSFET, combining the advantages of MOSFETs and BJTs to obtain an IGBT structure, thereby improving the device's current conduction capability.

[0004] However, in traditional IGBTs, electrons and ionized donors are located in the same layer at the emitter, which greatly increases the influence of scattering effects. In addition, the gate and collector of traditional IGBTs are placed opposite each other, resulting in a large reverse transfer capacitance (Crss) of the device. Summary of the Invention

[0005] To address the aforementioned problems in the prior art, this invention provides a monolithically integrated GaN IGBT with a gate-controlled Cascode structure. The technical problem to be solved by this invention is achieved through the following technical solution: This invention provides a monolithically integrated Cascode GaN IGBT with PGaN gate control, comprising: a substrate, a nucleation layer, a stress adjustment layer, a first P-GaN layer, a buffer layer, a drift layer, a second P-GaN layer, a channel layer, and a barrier layer stacked from bottom to top; ion implantation isolation regions are provided on the drift layer on both sides of the device; The channel layer and the barrier layer are provided with a first trench and a second trench; a third trench is provided between the first trench and the second trench, penetrating the barrier layer, the channel layer and the second P-GaN layer and with its bottom located inside the drift layer; A third P-GaN layer is disposed on the barrier layer between the first trench and the third trench, and on the barrier layer between the second trench and the third trench; a gate metal is disposed on the third P-GaN layer; A first emitter metal is disposed on the inner wall of the first trench and the second trench, a channel metal is disposed on the inner wall of the third trench, and a first dielectric layer is disposed between the channel metal and the inner wall of the third trench. The first emitter metal and the channel metal are connected by a second emitter metal, which is in contact with the inner wall of the groove penetrating the barrier layer near the first trench and the inner wall of the groove penetrating the barrier layer near the second trench. A second dielectric layer is disposed between the second emitter metal and the gate metal; a first dielectric layer and a second dielectric layer are disposed between the second emitter metal and the third P-GaN layer and between the second emitter metal and the barrier layer, stacked from bottom to top; An interconnect metal is disposed on the second emitter metal, and a passivation layer is disposed on the interconnect metal; A fourth trench is provided in the substrate, the nucleation layer and the stress adjustment layer, and a collector metal is provided on the lower surface of the substrate and the inner wall of the fourth trench.

[0006] In one embodiment of the present invention, the substrate is sapphire, SOI, Si, GaN, AlN or diamond.

[0007] In one embodiment of the present invention, the nucleation layer is AlN with a thickness of 200-500 nm.

[0008] In one embodiment of the present invention, the stress-adjusting layer is GaN, AlN or AlGaN, and the thickness is 500-2000 nm.

[0009] In one embodiment of the present invention, the buffer layer is N-GaN with a thickness of 500-1000 nm; the drift layer is GaN with a thickness of 2000-20000 nm.

[0010] In one embodiment of the present invention, the channel layer is GaN with a thickness of 50-500 nm; the barrier layer is AlGaN with a thickness of 10-50 nm.

[0011] In one embodiment of the present invention, the thickness of the first P-GaN layer is 500-1000 nm; the thickness of the second P-GaN layer is 500-1000 nm; and the thickness of the third P-GaN layer is 80-300 nm.

[0012] In one embodiment of the present invention, the first dielectric layer is Al2O3, HfO2, SiO2 or SiNx; the second dielectric layer is Al2O3, SiO2 or Si3N4; and the passivation layer is Al2O3, SiO2 or Si3N4.

[0013] In one embodiment of the present invention, the first emitter metal is in ohmic contact with the second P-GaN layer at the bottom of the first trench and the bottom of the second trench, and the second emitter metal is in ohmic contact with the two-dimensional electron gas between the barrier layer and the channel layer that penetrates the inner wall of the groove of the barrier layer.

[0014] In one embodiment of the present invention, the gate metal is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the channel metal is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the first emitter metal is a Ni / Au multilayer metal or a Ni / Pt multilayer metal; the second emitter metal is a Ti / Al / TiN multilayer metal; and the collector metal is a Ti / Al / TiN multilayer metal.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: The monolithically integrated PGaN-gate-controlled Cascode GaN IGBT of this invention replaces the N+GaN layer in traditional IGBTs with an AlGaN barrier layer / GaN channel layer. The presence of a two-dimensional electron gas significantly reduces scattering effects and improves electron mobility. The third P-GaN layer on the surface is used as the gate region for the E-mode device, and the trench formed by etching the second P-GaN layer, barrier layer, channel layer, and part of the drift layer is used as the gate region for the D-mode device. Simultaneously, trenches contacting the second P-GaN layer and the two-dimensional electron gas are etched to serve as the emitter region of the IGBT. A deep trench is etched at the bottom of the substrate down to the first P-GaN layer to serve as the collector region of the IGBT. By moving the gate to the surface, the gate and collector are avoided from being placed opposite each other, significantly reducing the reverse transfer capacitance (CrSs). Furthermore, the monolithic integration of the entire device reduces packaging costs and improves device performance.

[0016] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings. Attached Figure Description

[0017] Figure 1This is a schematic diagram of a monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT provided in an embodiment of the present invention; Figures 2-23 This is a schematic diagram illustrating the fabrication process of the monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT provided in this embodiment of the invention.

[0018] Icons: 1-Substrate; 2-Nucleation layer; 3-Stress conditioning layer; 4-First P-GaN layer; 5-Buffer layer; 6-Drift layer; 7-Second P-GaN layer; 8-Channel layer; 9-Barrier layer; 10-Third P-GaN layer; 11-First dielectric layer; 12-Ion implantation isolation region; 13-Gate metal; 14-Channel metal; 15-Second dielectric layer; 16-First emitter metal; 17-Second emitter metal; 18-Third dielectric layer; 19-Interconnect metal; 20-Passivation layer; 21-Collector metal. Detailed Implementation

[0019] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following describes in detail a monolithically integrated PGaN gate-controlled Cascode structure GaNIGBT according to the present invention, in conjunction with the accompanying drawings and specific embodiments.

[0020] The foregoing and other technical contents, features, and effects of the present invention will be clearly presented in the following detailed description of specific embodiments in conjunction with the accompanying drawings. Through the description of the specific embodiments, a more in-depth and concrete understanding can be gained of the technical means and effects adopted by the present invention to achieve its intended purpose. However, the accompanying drawings are for reference and illustration only and are not intended to limit the technical solutions of the present invention.

[0021] In a first aspect, embodiments of the present invention provide a monolithically integrated Cascode structure GaNIGBT with a PGaN gate, see [link to relevant documentation]. Figure 1 , Figure 1 This is a schematic diagram of a monolithically integrated PGaN gate-controlled Cascode structure GaNIGBT provided in an embodiment of the present invention, as shown below. Figure 1 As shown, the monolithically integrated PGaN gate-controlled Cascode structure GaNIGBT of this embodiment includes: a substrate 1, a nucleation layer 2, a stress adjustment layer 3, a first P-GaN layer 4, a buffer layer 5, a drift layer 6, a second P-GaN layer 7, a channel layer 8, and a barrier layer 9 stacked from bottom to top; ion implantation isolation regions 12 are provided on the drift layer 6 on both sides of the device.

[0022] The channel layer 8 and the barrier layer 9 are provided with a first trench and a second trench; a third trench is provided between the first trench and the second trench, penetrating the barrier layer 9, the channel layer 8 and the second P-GaN layer 7, and with its bottom located inside the drift layer 6.

[0023] In this embodiment, the first trench and the second trench serve as emitter region trenches, and the third trench serves as channel region trenches.

[0024] A third P-GaN layer 10 is disposed on the barrier layer 9 between the first and third trenches and on the barrier layer 9 between the second and third trenches; a gate metal 13 is disposed on the third P-GaN layer 10. A first emitter metal 16 is disposed on the inner wall of the first and second trenches, and a channel metal 14 is disposed on the inner wall of the third trench. A first dielectric layer 11 is disposed between the channel metal 14 and the inner wall of the third trench. The first emitter metal 16 and the channel metal 14 are connected by a second emitter metal 17, which contacts the inner wall of the groove penetrating the barrier layer 9 near the first trench and the inner wall of the groove penetrating the barrier layer 9 near the second trench. A second dielectric layer 15 is disposed between the second emitter metal 17 and the gate metal 13; a first dielectric layer 11 and a second dielectric layer 15 are stacked from bottom to top between the second emitter metal 17 and the third P-GaN layer 10 and between the second emitter metal 17 and the barrier layer 9.

[0025] That is, the first dielectric layer 11 is disposed on the barrier layer 8, the sidewalls and bottom of the third trench, and the sidewalls of the third P-GaN layer 10, wherein the inner wall of the groove penetrating the barrier layer 9 between the first trench and the third P-GaN layer 10, and the inner wall of the groove penetrating the barrier layer 9 between the second trench and the third P-GaN layer 10 are not covered by the first dielectric layer 11. The second dielectric layer 15 is disposed on the first dielectric layer 11 and the gate metal 13, wherein the first dielectric layer 11 in the third trench is not covered by the second dielectric layer 15. The first emitter metal 16 is disposed on the sidewalls and bottom of the first trench and the second trench, and the channel metal 14 is disposed on the first dielectric layer 11 in the third trench; the second emitter metal 17 is disposed on the second dielectric layer 15, the first emitter metal 16, the channel metal 14, and the inner wall of the groove penetrating the barrier layer 9.

[0026] The second emitter metal 17 is provided with interconnect metal 19, and the interconnect metal 19 is provided with passivation layer 20; a fourth trench is provided in the substrate 1, nucleation layer 2 and stress adjustment layer 3, and collector metal 21 is provided on the lower surface of the substrate 1 and the inner wall of the fourth trench.

[0027] Understandably, due to the fabrication process, a first dielectric layer 11, a second dielectric layer 15, and a second emitter metal 17 are stacked on the ion-implanted isolation region 12. To prevent the interconnect metal 19 from contacting the second emitter metal 17 above the ion-implanted isolation region 12, a third dielectric layer 18 is provided on the second emitter metal 17 in this region. Optionally, the third dielectric layer 17 is Al2O3, SiO2, or Si3N4.

[0028] In an optional embodiment, the substrate 1 is sapphire, SOI, Si, GaN, AlN, or diamond.

[0029] In an optional embodiment, the nucleation layer 2 is AlN with a thickness of 200-500 nm.

[0030] In an optional embodiment, the stress-adjusting layer 3 is GaN, AlN, or AlGaN, with a thickness of 500-2000 nm.

[0031] In an optional embodiment, the buffer layer 5 is N-GaN with a thickness of 500-1000 nm; the drift layer 6 is GaN with a thickness of 2000-20000 nm.

[0032] In an optional embodiment, the channel layer 8 is GaN with a thickness of 50-500 nm; the barrier layer 9 is AlGaN with a thickness of 10-50 nm.

[0033] In an optional embodiment, the thickness of the first P-GaN layer 4 is 500-1000 nm; the thickness of the second P-GaN layer 7 is 500-1000 nm; and the thickness of the third P-GaN layer 10 is 80-300 nm.

[0034] In an optional embodiment, the first dielectric layer 11 is Al2O3, HfO2, SiO2 or SiNx; the second dielectric layer 15 is Al2O3, SiO2 or Si3N4; and the passivation layer 20 is Al2O3, SiO2 or Si3N4.

[0035] In an optional embodiment, the first emitter metal 16 is in ohmic contact with the first trench and the second P-GaN layer 7 at the bottom of the second trench, and the second emitter metal 17 is in ohmic contact with the two-dimensional electron gas between the barrier layer 9 and the channel layer 8 that penetrate the inner wall of the groove of the barrier layer 9.

[0036] In an optional embodiment, the gate metal 13 is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the channel metal 4 is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the first emitter metal 16 is a Ni / Au multilayer metal or a Ni / Pt multilayer metal; the second emitter metal 17 is a Ti / Al / TiN multilayer metal or other Ti / Al-based multilayer metal; and the collector metal 21 is a Ti / Al / TiN multilayer metal or other Ti / Al-based multilayer metal.

[0037] In traditional IGBTs, electrons and ionized donors reside on the same layer at the emitter, significantly increasing the impact of scattering effects. Therefore, in this embodiment of a monolithically integrated PGaN gate-controlled Cascode GaN IGBT, the N+GaN layer in the GaN IGBT is replaced with an AlGaN barrier layer / GaN channel layer. The two-dimensional electron gas is separated from the ionized donors in the barrier layer, thus greatly reducing scattering effects and improving electron mobility.

[0038] A third P-GaN layer is introduced on the surface barrier layer as the gate. Switching of the device is achieved by controlling the generation and depletion of a two-dimensional electron gas, forming an E-mode structure. Additionally, positive ions or N-type impurities are introduced into the channel oxide layer (the first dielectric layer) to form positively charged centers, generating an electric field pointing towards the third P-GaN layer. This connects the channel metal to the emitter metal, allowing a conductive channel to be formed even without an applied voltage, thus forming a D-mode structure. A reverse PN junction formed by the device's drift layer and the second P-GaN layer withstands the high voltage. This significantly increases the distance between the gate and collector, reducing the reverse transfer capacitance (Crss) without affecting the breakdown voltage. Furthermore, the monolithic integration of the entire device reduces packaging costs and improves device performance.

[0039] Furthermore, the specific fabrication process of the monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT in this embodiment will be described.

[0040] Step 1: Provide substrate 1, and sequentially grow the following layers on substrate 1 using MOCVD: nucleation layer 2, stress adjustment layer 3, first P-GaN layer 4, buffer layer 5, drift layer 6, second P-GaN layer 7, channel layer 8, barrier layer 9, and third P-GaN layer 10, as follows. Figure 2 As shown.

[0041] Step 2: Use dry etching (BCl3 / Cl2 / O2) to etch the third P-GaN layer 10 on the barrier layer 9 of the gate region. Add O2 to the etching gas to react with the AlGaN barrier layer during etching to generate Al2O3, which blocks the etching process and achieves self-stopping. Use hydrochloric acid to wash away the surface Al2O3. Figure 3 As shown.

[0042] Step 3: Use dry etching (BCl3 / Cl2) to etch the channel layer 8 and barrier layer 9 of the emitter region to form the first trench and the second trench, as shown below. Figure 4 As shown.

[0043] Step 4: Use dry etching (BCl3 / Cl2) to etch the second P-GaN layer 7, channel layer 8, and barrier layer 9 in the channel region, and over-etch a portion to the drift layer 6 to form the third trench, as shown. Figure 5 As shown.

[0044] Step 5: Use dry etching (BCl3 / Cl2) to etch the channel layer 8 and barrier layer 9 outside the active region to achieve mesa isolation, such as... Figure 6 As shown.

[0045] Step 6: Etch the substrate 1, nucleation layer 2, and stress-adjusting layer 3 from the lower surface of substrate 1 to form the fourth trench, such as... Figure 7 As shown.

[0046] Step 7: Perform high-temperature annealing on the device using an annealing process to activate the H-passivated Mg in the third P-GaN layer 10, the second P-GaN layer 7, and the first P-GaN layer 4.

[0047] Step 8: A first dielectric layer 11 is grown on the upper surface of the device using ALD or PECVD processes to serve as the channel dielectric layer. Positive ions are implanted into the dielectric layer via ion implantation, such as... Figure 8 As shown.

[0048] In this embodiment, the channel dielectric layer, i.e. the first dielectric layer 11, can be grown by ALD or PECVD, and donor impurities can be incorporated into the dielectric layer, or positive ions can be implanted by an ion implantation device.

[0049] Step 9: Ion implantation isolation is performed in the region outside the active region to form ion implantation isolation region 12, such as... Figure 9 As shown.

[0050] Step 10: Use dry etching BCl3 / Cl2 to etch the first dielectric layer 11 of the gate region, such as... Figure 10 As shown.

[0051] Step 11: Deposit gate metal 13 on the third P-GaN layer 10 using an electron beam evaporation process, as shown below. Figure 11As shown.

[0052] Step 12: Deposit the channel metal 14 in the third trench using an electron beam evaporation process, such as... Figure 12 As shown.

[0053] Step 13: Grow a second dielectric layer 15 on the upper surface of the device using PECVD process, such as... Figure 13 As shown.

[0054] Step 14: Use dry etching BCl3 / Cl2 to etch the first dielectric layer 11 and the second dielectric layer 15 within the first and second trenches, as follows: Figure 14 As shown.

[0055] Step 15: Deposit the first emitter metal 16 in the first and second trenches using an electron beam evaporation process, such as... Figure 15 As shown.

[0056] Step 16: Use dry etching BCl3 / Cl2 to etch the second dielectric layer 15, the first dielectric layer 11, and the barrier layer 9 between the first trench and the third P-GaN layer 10, as well as the second dielectric layer 15, the first dielectric layer 11, and the barrier layer 9 between the second trench and the third P-GaN layer 10, to form a groove penetrating the barrier layer 9, such as... Figure 16 As shown.

[0057] Step 17: Use dry etching (BCl3 / Cl2) to etch the second dielectric layer 15 in the channel region, such as... Figure 17 As shown.

[0058] Step 18: Deposit a second emitter metal 17 on the upper surface of the device using an electron beam evaporation process, thereby connecting the first emitter metal 16 and the channel metal 14, as shown below. Figure 18 As shown.

[0059] Step 19: Grow a third dielectric layer 18 on the upper surface of the device using PECVD process, such as... Figure 19 As shown.

[0060] Step 20: Etch the third dielectric layer 18 of the emitter region using a dry etching process, such as... Figure 20 As shown.

[0061] Step 21: Deposit interconnect metal 19 on the upper surface of the device using electron beam evaporation, such as... Figure 21 As shown.

[0062] Step 22: Grow a passivation layer 20 on the upper surface of the device using PECVD process, such as... Figure 22 As shown.

[0063] Step 23: Deposit collector metal 21 on the lower surface of the device using electron beam evaporation, such as... Figure 23 As shown.

[0064] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations are intended to cover non-exclusive inclusion, such that an article or device comprising a list of elements includes not only those elements but also other elements not expressly listed. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the article or device comprising said element. Terms such as "connected" or "linked" are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect. The orientations or positional relationships indicated by terms such as "upper," "lower," "left," and "right" are based on the orientations or positional relationships shown in the accompanying drawings and are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.

[0065] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features or characteristics described may be combined in any suitable manner in one or more embodiments or examples. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.

[0066] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A monolithically integrated GaN IGBT with a PGaN gate-controlled Cascode structure, characterized in that, include: The following layers are stacked from bottom to top: substrate (1), nucleation layer (2), stress adjustment layer (3), first P-GaN layer (4), buffer layer (5), drift layer (6), second P-GaN layer (7), channel layer (8) and barrier layer (9); ion implantation isolation regions (12) are provided on the drift layer (6) on both sides of the device. The channel layer (8) and the barrier layer (9) are provided with a first trench and a second trench; a third trench is provided between the first trench and the second trench, which penetrates the barrier layer (9), the channel layer (8) and the second P-GaN layer (7) and whose bottom is located inside the drift layer (6). A third P-GaN layer (10) is disposed on the barrier layer (9) between the first trench and the third trench and on the barrier layer (9) between the second trench and the third trench; a gate metal (13) is disposed on the third P-GaN layer (10). The inner walls of the first trench and the second trench are provided with a first emitter metal (16), the inner wall of the third trench is provided with a channel metal (14), and a first dielectric layer (11) is provided between the channel metal (14) and the inner wall of the third trench. The first emitter metal (16) and the channel metal (14) are connected by a second emitter metal (17), which is in contact with the inner wall of the groove that penetrates the barrier layer (9) near the first trench and the inner wall of the groove that penetrates the barrier layer (9) near the second trench. A second dielectric layer (15) is disposed between the second emitter metal (17) and the gate metal (13); a first dielectric layer (11) and a second dielectric layer (15) are disposed between the second emitter metal (17) and the third P-GaN layer (10) and between the second emitter metal (17) and the barrier layer (9) stacked from bottom to top. An interconnect metal (19) is disposed on the second emitter metal (17), and a passivation layer (20) is disposed on the interconnect metal (19). A fourth trench is provided in the substrate (1), the nucleation layer (2) and the stress adjustment layer (3), and a collector metal (21) is provided on the lower surface of the substrate (1) and the inner wall of the fourth trench.

2. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The substrate (1) is sapphire, SOI, Si, GaN, AlN or diamond.

3. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The nucleation layer (2) is AlN with a thickness of 200-500 nm.

4. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The stress-adjusting layer (3) is GaN, AlN or AlGaN, with a thickness of 500-2000nm.

5. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The buffer layer (5) is N-GaN with a thickness of 500-1000nm; the drift layer (6) is GaN with a thickness of 2000-20000nm.

6. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The channel layer (8) is GaN with a thickness of 50-500 nm; the barrier layer (9) is AlGaN with a thickness of 10-50 nm.

7. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The thickness of the first P-GaN layer (4) is 500-1000 nm; the thickness of the second P-GaN layer (7) is 500-1000 nm; and the thickness of the third P-GaN layer (10) is 80-300 nm.

8. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The first dielectric layer (11) is Al2O3, HfO2, SiO2 or SiNx; the second dielectric layer (15) is Al2O3, SiO2 or Si3N4; the passivation layer (20) is Al2O3, SiO2 or Si3N4.

9. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The first emitter metal (16) is in ohmic contact with the second P-GaN layer (7) at the bottom of the first trench and the bottom of the second trench, and the second emitter metal (17) is in ohmic contact with the two-dimensional electron gas between the barrier layer (9) and the channel layer (8) that penetrates the inner wall of the groove of the barrier layer (9).

10. The monolithically integrated PGaN gate-controlled Cascode structure GaN IGBT according to claim 1, characterized in that, The gate metal (13) is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the channel metal (4) is a TiN / Ti / Al / Ti multilayer metal or a Ni / Au multilayer metal; the first emitter metal (16) is a Ni / Au multilayer metal or a Ni / Pt multilayer metal; the second emitter metal (17) is a Ti / Al / TiN multilayer metal; and the collector metal (21) is a Ti / Al / TiN multilayer metal.

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