HEMT device and preparation method thereof

Abstract

The invention provides an HEMT device and a preparation method thereof, the HEMT device comprises a semiconductor layer, a gate structure, a source electrode, a drain electrode, a current optimization structure and a field plate, the semiconductor layer comprises a channel layer and a barrier layer; the gate structure is located above the barrier layer; the source electrode and the drain electrode are respectively located at two sides of the gate structure; the current optimization structure comprises first parts and second parts which are located on the two sides of the gate structure in the X direction and are in one-to-one correspondence in the X direction, the two side walls, in the X direction, of the first parts are adjacent to the source electrode and the gate structure respectively, the two side walls, in the X direction, of the second parts are adjacent to the drain electrode structure and the gate structure respectively, and the first parts and the second parts are arranged at intervals in the Y direction; the field plate is located right above the region between the drain electrode and the gate structure, and in the X direction, the size of the field plate right above the second part is larger than the size of the field plate right above the region between two adjacent second parts. Through the arrangement of the current optimization structure, the performance of the device is ensured, and meanwhile, the short-circuit endurance capability of the device is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor integrated circuit manufacturing and relates to a HEMT device and its fabrication method. Background Technology

[0002] The harsh operating environment of motor drives can lead to overcurrent due to faults such as inverter breakdown and motor winding insulation breakdown. Power devices must withstand this overcurrent for the time required for the protection detection circuit to trigger and shut down the motor drive. During overcurrent, the current density in gallium nitride (GaN) devices spikes, causing severe heating during short circuits, leading to rapid temperature increases and device failure. Standard GaN devices can only withstand a few hundredths of a nanosecond during a short circuit, which is far from sufficient for fault detection and safe shutdown operations.

[0003] To improve the short-circuit withstand capability of gallium nitride (GaN) devices, the drain-source voltage Vsense is typically monitored. A comparator compares Vsense with a reference voltage Vref. If Vsense is greater than Vref, a fault signal is pulled high, and an isolator sends the fault signal back to the gate driver circuit, causing a hard shutdown of the gate driver circuit, thus protecting the motor drive circuit. However, this approach requires the design of external short-circuit protection circuits, such as… Figure 1 As shown, it requires complex system design, which greatly increases the cost of the circuit.

[0004] Therefore, there is an urgent need to find a HEMT device that can increase the short-circuit withstand capability and improve the reliability of the device. Summary of the Invention

[0005] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a HEMT device and its fabrication method to solve the problems of poor short-circuit withstand capability and poor reliability of gallium nitride HEMT devices in the prior art.

[0006] To achieve the above and other related objectives, the present invention provides a HEMT device, comprising:

[0007] The semiconductor layer includes at least a channel layer and a barrier layer stacked sequentially.

[0008] A gate structure is located above the barrier layer;

[0009] The source and drain, which are electrically connected to the semiconductor layer, are located on both sides of the gate structure along the X direction and are spaced apart from the gate structure by a predetermined distance.

[0010] The current-optimized structure includes at least a first part and a second part located above the barrier layer on both sides of the gate structure along the X direction. The first part is located on the side of the gate structure near the source and its two side walls along the X direction are respectively adjacent to the source and the gate structure. The second part is located on the side of the gate structure near the drain and its two side walls along the X direction are respectively adjacent to the drain and the gate structure. A plurality of the first parts and a plurality of the second parts are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction form a preset angle.

[0011] A field plate is located directly above the region between the drain and the gate structure and is spaced a predetermined distance from the drain in the X direction. The sidewall of the field plate near the gate structure extends directly above the gate structure. In the X direction, the distance between the field plate directly above the second part and the drain is greater than the distance between the field plate directly above the region between two adjacent second parts and the drain.

[0012] Optionally, the semiconductor layer further includes a substrate structure, and the channel layer is located on the upper surface of the substrate structure.

[0013] Optionally, the substrate structure includes a substrate and a buffer layer stacked sequentially, with the channel layer located on the upper surface of the buffer layer.

[0014] Optionally, the semiconductor layer further includes a dielectric layer covering the upper surface of the barrier layer, the source and the drain penetrating the dielectric layer, the current optimization structure including a groove embedded in the dielectric layer, the gate structure being a gate metal layer covering the upper surface of the dielectric layer, and the bottom surface of the groove being spaced apart from the upper surface of the barrier layer by a predetermined distance.

[0015] Optionally, the distance between the bottom surface of the first part and the upper surface of the barrier layer directly below it is the same as the distance between the bottom surface of the second part and the upper surface of the barrier layer directly below it.

[0016] Optionally, the gate structure includes a cap layer and a gate metal layer stacked sequentially, the cap layer being located on the upper surface of the barrier layer. The device further includes a current enhancement layer that covers at least the exposed surfaces of the barrier layer between the gate structure and the source and between the gate structure and the drain. The current optimization structure includes a groove penetrating the current enhancement layer, the first portion penetrating the current enhancement layer between the source and the cap layer, and the second portion penetrating the current enhancement layer located between the drain and the cap layer.

[0017] Optionally, the current enhancement layer also covers the exposed surface of the gate structure and is in communication with the current enhancement layers on both sides of the gate structure along the X direction.

[0018] Optionally, the first part and the second part have the same dimensions in the Y direction.

[0019] Optionally, the exposed upper surface of the current-optimized structure and the exposed surface of the gate structure are further provided with an isolation dielectric layer, and the field plate is located on the upper surface of the isolation dielectric layer.

[0020] This invention also provides a method for fabricating a HEMT device, comprising the following steps:

[0021] A semiconductor layer is provided, comprising at least a channel layer and a barrier layer stacked sequentially, and a gate structure is formed above the barrier layer, and a source and a drain are respectively located on both sides of the gate structure along the X direction and spaced apart from the gate structure by a predetermined distance, wherein the source and the drain are electrically connected to the semiconductor layer.

[0022] A current-optimized structure is formed, comprising at least a first part and a second part located above the barrier layer on both sides of the gate structure along the X direction. The first part is located on the side of the gate structure near the source and its two side walls along the X direction are respectively adjacent to the source and the gate structure. The second part is located on the side of the gate structure near the drain and its two side walls along the X direction are respectively adjacent to the drain structure and the gate structure. A plurality of the first parts and a plurality of the second parts are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction are at a preset angle.

[0023] A field plate is formed directly above the region between the drain and the gate structure and spaced a predetermined distance from the drain in the X direction. The sidewall of the field plate near the gate structure extends directly above the gate structure. In the X direction, the distance between the field plate directly above the second part and the drain is greater than the distance between the field plate directly above the region between two adjacent second parts and the drain.

[0024] As described above, the HEMT device and its fabrication method of the present invention provide a current optimization structure directly above the semiconductor layer between the gate structure and the source and drain regions. The current optimization structure includes multiple first and second parts spaced apart in the Y direction and corresponding one-to-one in the X direction. By setting the first and second parts, the concentration of two-dimensional electron gas directly below them can be reduced, thereby reducing the saturation current of the device and greatly improving the short-circuit withstand capability of the device. At the same time, a field plate extending to the top of the gate structure is provided directly above the semiconductor layer between the gate structure and the drain. In the X direction, the size of the field plate directly above the second part is larger than the size of the field plate in the area outside the second part, which optimizes the electric field near the drain side of the device, ensures device performance and further improves device reliability, meets the requirements of high temperature and high voltage stress applications, and has high industrial application value. Attached Figure Description

[0025] Figure 1 This is displayed as the peripheral protection circuit for the motor drive circuit.

[0026] Figure 2 The diagram shown is a three-dimensional structural schematic of the HEMT device of the present invention.

[0027] Figure 3 Displayed as Figure 2 A schematic diagram of the structure of the AA screenshot.

[0028] Figure 4 Displayed as Figure 2 Schematic diagram of the BB section.

[0029] Figure 5 This is a schematic diagram of another three-dimensional structure of the HEMT device of the present invention.

[0030] Figure 6 Displayed as Figure 5 A schematic diagram of the CC section.

[0031] Figure 7 Displayed as Figure 5 A schematic diagram of the DD section.

[0032] Figure 8 The diagram shown is a process flow diagram of the fabrication method of the HEMT device of the present invention.

[0033] Figure 9 The diagram shows a cross-sectional structure of the HEMT device fabrication method of the present invention after forming the gate structure, source, and drain.

[0034] Figure 10 This diagram shows another cross-sectional structure of the HEMT device fabrication method of the present invention after forming the gate structure, source, and drain.

[0035] Figure 11 Displayed as Figure 10 A schematic diagram of the cross-sectional structure of the device after the thermal optimization layer is formed.

[0036] Figure 12 The diagram shows a three-dimensional structure of the HEMT device fabrication method of the present invention after thermal optimization.

[0037] Figure 13 This diagram shows another three-dimensional structure of the HEMT device fabrication method of the present invention after thermal optimization.

[0038] Explanation of icon numbers

[0039] 01 First-level soft shutdown protection circuit

[0040] 02 Monitoring Circuit

[0041] 03 Gate driver and secondary hard shutdown protection circuit

[0042] 1 Semiconductor layer

[0043] 11 Substrate

[0044] 12 Buffer Layers

[0045] 13. Channel layer

[0046] 14. Barrier Layer

[0047] 15 Dielectric layers

[0048] 16 Current Enhancement Layer

[0049] 2 Current-optimized structure

[0050] 21 Part 1

[0051] 22 Part Two

[0052] 3 Gate Structure

[0053] 31 Gate metal layer

[0054] 32 cap layers

[0055] 4 Source

[0056] 5 Drain

[0057] 6-board Detailed Implementation

[0058] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0059] Please see Figures 2 to 13 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0060] Example 1

[0061] This embodiment provides a HEMT device; please refer to [link / reference]. Figures 2 to 13 ,like Figures 2 to 9 The diagram shows a three-dimensional structural schematic and cross-sectional schematic of two HEMT devices, including a semiconductor layer 1, a gate structure 3, a source 4, a drain 5, a current optimization structure 2, and a field plate 6. The semiconductor layer 1 includes at least a channel layer 13 and a barrier layer 14 stacked sequentially. The gate structure 3 is located above the barrier layer 14. The source 4 and drain 5, electrically connected to the semiconductor layer 1, are located on opposite sides of the gate structure 3 along the X-direction and are spaced a predetermined distance from the gate structure 3. The current optimization structure 2 includes at least a first part 21 and a second part 22 located above the barrier layers 14 on both sides of the gate structure 3 along the X-direction. The first part 21 is located on the side of the gate structure 3 closest to the source 4 and is divided into two parts along the X-direction. The second part 22 is located on the side of the gate structure 3 near the drain 5 and its two side walls along the X direction are adjacent to the drain 5 structure and the gate structure 3, respectively. Multiple first parts 21 and multiple second parts 22 are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction are at a preset angle. The field plate 6 is located directly above the area between the drain 5 and the gate structure 3 and is spaced at a preset distance from the drain 5 in the X direction. The side wall of the field plate 6 near the gate structure 3 extends to directly above the gate structure 3. In the X direction, the distance between the field plate 6 directly above the second part 22 and the drain 5 is greater than the distance between the field plate 6 directly above the area between two adjacent second parts 22 and the drain 5.

[0062] It should be noted that semiconductor layer 1 is usually the structure of the electrode of the HEMT device to be fabricated, and its specific shape and thickness can be selected according to the actual situation.

[0063] As an example, semiconductor layer 1 also includes a substrate structure, with channel layer 13 located on the upper surface of the substrate structure.

[0064] Specifically, the substrate structure is usually a process platform for forming the trench layer 13, and its specific size, shape, thickness and structure can be selected according to the actual situation.

[0065] As an example, the substrate structure includes a substrate 11 and a buffer layer 12 stacked sequentially, with a channel layer 13 located on the upper surface of the buffer layer 12.

[0066] It should be noted that when the lattice matching between the substrate 11 and the channel layer 13 in the substrate structure is good, the buffer layer 12 may not be necessary in the substrate structure while ensuring device performance.

[0067] Specifically, when a buffer layer 12 is provided in the substrate structure, it is usually because the lattice matching degree between the substrate 11 and the channel layer 13 is not good. Directly forming the channel layer 13 on the substrate 11 will affect the quality of the formed channel layer 13. By providing a buffer layer 12 on the upper surface of the substrate 11, the problem of poor lattice matching degree between the substrate 11 and the channel layer 13 can be alleviated, and the quality of the channel layer 13 formed on the upper surface of the substrate structure can be improved.

[0068] Specifically, when the substrate structure includes a buffer layer 12, the buffer layer 12 can be a single-layer film structure or a multi-layer film structure, provided that the quality of the channel layer 13 on the upper surface of the buffer layer 12 is guaranteed; its thickness can be selected according to the actual situation.

[0069] Specifically, the substrate 11 is made of materials including sapphire, SiC, Si, GaN, diamond, Al2O3 or other suitable materials; when a buffer layer 12 is provided on the upper surface of the substrate 11, the buffer layer 12 is made of materials including AlN, AlGaN, GaN, InN or other suitable materials.

[0070] Specifically, in the device, the channel layer 13 is usually combined with the barrier layer 14 to generate a two-dimensional electron gas (2DEG) layer at their interface, which serves as the conductive channel of the device.

[0071] Specifically, the channel layer 13 is made of GaN, AlGaN, InGaN, or other suitable semiconductor materials; the barrier layer 14 is made of InAlGaN, AlGaN, InAlN, or other suitable materials.

[0072] As an example, the semiconductor layer 1 also includes a dielectric layer 15 covering the upper surface of the barrier layer 14, with the source 4 and drain 5 penetrating through the dielectric layer 15. The current optimization structure 2 includes a groove embedded in the dielectric layer 15. The gate structure 3 is a gate metal layer 31 covering the upper surface of the dielectric layer 15. The bottom surface of the groove is spaced apart from the upper surface of the barrier layer 14 by a predetermined distance. That is, when the device is a depletion-type HEMT device, the current optimization structure 2 is a groove embedded between the gate structure 3 and the source 4 and drain 5. The first part 21 is a groove embedded in the dielectric layer 15 between the gate structure 3 and the source 4, and the second part 22 is a groove embedded in the dielectric layer 15 between the gate structure 3 and the drain 5.

[0073] It should be noted that the X direction is parallel to the arrangement direction of the source 4, drain 5, and gate structure 3 on the upper surface of semiconductor layer 1, and the angle between the Y direction and the X direction can be selected according to the actual situation. Preferably, the angle between the X direction and the Y direction is 90°.

[0074] Specifically, when the device is a depletion-type HEMT device, the thickness of the dielectric layer 15 covering the upper surface of the barrier layer 14 can be selected according to the actual situation, while ensuring the device performance.

[0075] As an example, the distance between the bottom surface of the first part 21 and the upper surface of the barrier layer 14 directly below it is the same as the distance between the bottom surface of the second part 22 and the upper surface of the barrier layer 14 directly below it, that is, the depths of the first part 21 and the second part 22 are the same.

[0076] It should be noted that when the current optimization structure 2 (first part 21 and second part 22) is formed in the dielectric layer 15, the thinning of the dielectric layer 15 directly below the current optimization structure 2 will cause the two-dimensional electron gas concentration directly below it to be lower than the two-dimensional electron gas concentration directly below other regions between the gate structure 3 and the source 4 and drain 5.

[0077] Specifically, when the device is a HEMT device, the depth of the first part 21 can be different from the depth of the second part 22, provided that the device performance is guaranteed; the distance between the bottom surface of the first part 21 and the upper surface of the barrier layer 14 can be selected according to the actual situation; the distance between the bottom surface of the second part 22 and the upper surface of the barrier layer 14 can be selected according to the actual situation; the number of first parts 21 (i.e., second parts 22) in the Y direction can be selected according to the actual situation; the distance between two adjacent first parts 21 (i.e., second parts 22) in the Y direction can be selected according to the actual situation.

[0078] Specifically, when the device is a HEMT device, the dielectric layer 15 is made of silicon oxide, silicon nitride, aluminum nitride, or other suitable dielectric materials. Preferably, a silicon oxide layer is used as the dielectric layer 15.

[0079] As an example, the gate structure 3 includes a cap layer 32 and a gate metal layer 31 stacked sequentially. The cap layer 32 is located on the upper surface of the barrier layer 14. The device also includes a current enhancement layer 16 that covers at least the exposed surfaces of the barrier layer 14 between the gate structure 3 and the source 4 and between the gate structure 3 and the drain 5. The current optimization structure 2 includes a groove penetrating the current enhancement layer 16. A first part 21 penetrates the current enhancement layer 16 between the source 4 and the cap layer 32, and a second part 22 penetrates the current enhancement layer 16 located between the drain 5 and the cap layer 32. That is, the device is an enhancement-mode HEMT device. The first part 21 is a groove penetrating the current enhancement layer 16 between the cap layer 32 and the source 4, and the second part 22 is a groove penetrating the current enhancement layer 16 between the cap layer 32 and the drain 5. The current enhancement layer 16 covering the upper surface of the barrier layer 14 between the cap layer 32 and the source 4 and the drain 5 is in the form of strips spaced apart in the Y direction.

[0080] Specifically, when the device is an enhancement-type HEMT device, the thickness of the strip current enhancement layer 16 located between the source 4 and the cap layer 32 can be selected according to the actual situation, while ensuring device performance; the thickness of the strip current enhancement layer 16 located between the drain 5 and the cap layer 32 can be selected according to the actual situation.

[0081] As an example, the current enhancement layer 16 also covers the exposed surface of the gate structure 3 and is connected to the current enhancement layer 16 on both sides of the gate structure 3 along the X direction.

[0082] It should be noted that the current enhancement layer 16 covering the exposed surface of the gate structure 3 can either cover the entire exposed surface of the gate structure 3, or it can be divided into multiple segments that are spaced apart in the Y direction and connected to the corresponding current enhancement layers 16 on both sides of the gate structure 3 at both ends. Preferably, the current enhancement layers 16 covering the exposed surface of the gate structure 3 are spaced apart in the Y direction and connected to the corresponding current enhancement layers 16 on both sides of the X direction.

[0083] Specifically, when the device is an enhancement-mode HEMT device, the current enhancement layer 16 includes aluminum, nitrogen, or other suitable elements. Preferably, an aluminum nitride layer is used as the current enhancement layer 16.

[0084] It should be noted that the current enhancement layer 16 between the gate structure 3 and the source 4 and between the gate structure 3 and the drain 5 is usually used to increase the concentration of two-dimensional electron gas directly below it. By setting the first part 21 and the second part 22 through the current enhancement layer 16, the concentration of two-dimensional electron gas directly below the first part 21 and the second part 22 can be reduced, thereby reducing the saturation current of the device and improving the device's tolerance while ensuring device performance.

[0085] As an example, the first part 21 and the second part 22 have the same dimensions in the Y direction, that is, the distance between two adjacent first parts 21 in the Y direction is the same as the distance between two second parts 22 corresponding to the first part 21.

[0086] It should be noted that the size of the first part 21 in the X direction is the same as the distance between the gate structure 3 and the source 4; the size of the second part 22 in the X direction is the same as the distance between the gate structure 3 and the drain 5.

[0087] Specifically, while ensuring device performance, the dimensions of each first part 21 in the Y direction can be selected according to the actual situation; the dimensions of each second part 22 in the Y direction can be selected according to the actual situation.

[0088] It should be noted that by adjusting the dimensions of the first part 21 and the second part 22 in the Y direction, as well as the distance between two adjacent first parts 21 and two adjacent second parts 22, the saturation current of the device can be adjusted, thereby achieving the control of the device's tolerance.

[0089] Specifically, the source 4 and drain 5 can be electrically connected to the barrier layer 14 in the semiconductor layer 1, or they can pass through the barrier layer 14 and be electrically connected to the channel layer 13.

[0090] Specifically, while ensuring device performance, the distance between the source 4 and the gate structure 3 can be selected according to the actual situation; the distance between the drain 5 and the gate structure 3 can be selected according to the actual situation.

[0091] Specifically, the source electrode 4 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), or other suitable conductive materials; the drain electrode 5 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum-silicon alloy, aluminum-copper alloy, or other suitable conductive materials; and the gate metal layer 31 is made of titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, aluminum-silicon alloy, aluminum-copper alloy, or other suitable conductive materials.

[0092] Specifically, when the device is an enhancement-mode HEMT device, the material of the cap layer 32 in the gate structure 3 includes P-type GaN, P-type AlGaN, or other suitable semiconductor materials. Preferably, a P-type GaN layer is used as the cap layer 32.

[0093] Specifically, the electric field peak value of the gate structure 3 near the drain 5 is usually high. By setting a field plate 6 electrically connected to the source 4 at the edge of the gate structure 3 near the drain 5, the electric field peak value of the gate structure 3 near the drain 5 can be effectively reduced, thereby improving the breakdown capability of the device. At the same time, since the current optimization structure 2 reduces the concentration of two-dimensional electron gas directly below it, by making the length of the field plate 6 located directly above the second part 22 smaller than the length of the field plate 6 directly above the region between two adjacent second parts 22, that is, the field plate 6 is comb-shaped, the electric field peak value of the gate structure 3 near the drain 5 can be reduced, while the electric field distribution of the gate structure 3 near the drain 5 can be better optimized.

[0094] As an example, the exposed upper surface of the current optimization structure 2 and the exposed surface of the gate structure 3 are also provided with an isolation dielectric layer, and the field plate 6 is located on the upper surface of the isolation dielectric layer.

[0095] It should be noted that when the device is a depletion-type HEMT device, the isolation dielectric layer covers the exposed surfaces of the gate metal layer 31, the current optimization structure 2, the dielectric layer 15, the source 4, and the drain 5. When the device is an enhancement-type HEMT device, the isolation dielectric layer covers the exposed surfaces of the gate structure 3, the current optimization structure 2, the barrier layer 14, the source 4, and the drain 5. The field plate 6 is located on the upper surface of the isolation dielectric layer.

[0096] Specifically, the thickness of the isolation dielectric layer can be selected according to the actual situation, while ensuring device performance.

[0097] Specifically, the material of the isolation dielectric layer includes silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or other suitable dielectric materials; the material of the field plate 6 includes titanium, titanium nitride, silver, gold, copper, aluminum, nickel, tungsten, platinum, or other suitable conductive materials.

[0098] Specifically, while ensuring device performance, the length of the field plate 6 directly above the region between two adjacent second parts 22 in the Y direction in the X direction can be selected according to the actual situation; the length of the field plate 6 directly above the second part 22 in the X direction can be selected according to the actual situation.

[0099] It should be noted that the device is usually equipped with a dielectric protective layer, which covers the exposed upper surface of the isolation dielectric layer and the exposed surface of the field plate 6.

[0100] Specifically, the dielectric protective layer can be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxide, or other suitable dielectric materials; the thickness of the dielectric protective layer can be selected according to the actual situation while ensuring device performance.

[0101] Specifically, by setting a current optimization structure 2 directly above the semiconductor layer 1, the current optimization structure 2 includes multiple first parts 21 and second parts 22 that are spaced apart in the Y direction and correspond one-to-one in the X direction. The first part 21 is located directly above the semiconductor layer 1 between the gate structure 3 and the source 4, and its size in the X direction is the same as the distance between the source 4 and the gate structure 3 in the X direction. The second part 22 is located directly above the semiconductor layer 1 between the gate structure 3 and the drain 5, and its size in the X direction is the same as the distance between the drain 5 and the gate structure 3 in the X direction. By setting the first part 21 and the second part 22, the concentration of two-dimensional electron gas directly below them is lower than the concentration of two-dimensional electron gas in other areas. At the same time, by adjusting the distance between two adjacent first parts 21 and two adjacent second parts 22 in the Y direction, the saturation current capability of the device is adjusted, and the saturation current of the device is reduced, thereby greatly improving the short-circuit withstand capability of the device and reducing the short-circuit protection response sensitivity requirements of the device.

[0102] Specifically, due to the setting of the current optimization structure 2, the concentration of two-dimensional electron gas in local areas of the device is reduced, and the electric field distribution in different areas of the device surface also changes accordingly. By setting a field plate 6 in the area directly above the semiconductor layer 1 on the side of the gate structure 3 near the drain 5, the end of the field plate 6 adjacent to the gate structure 3 is located directly above the gate structure 3. At the same time, the distance between the edge of the field plate 6 directly above the current optimization structure 2 and the drain 5 is greater than the distance between the edge of the field plate 6 directly above the area between the adjacent second part 22 and the drain 5, the sudden change of electric field intensity in the area of ​​the gate structure 3 near the drain 5 is suppressed, the distribution in the area of ​​the gate structure 3 near the drain 5 is made more uniform, the peak electric field in the area of ​​the gate structure 3 near the drain 5 is reduced, the short-circuit withstand capability of the device is improved, and the reliability of the device is improved.

[0103] The HEMT device in this embodiment improves the device structure by setting a current optimization structure 2, which includes multiple first parts 21 and second parts 22 spaced apart in the Y direction, directly above the semiconductor layer 1 between the gate structure 3 and the source 4 and drain region. The first parts 21 and second parts 22 correspond one-to-one in the X direction to reduce the concentration of two-dimensional electron gas directly below them, thereby reducing the saturation current of the device and improving the short-circuit withstand capability of the device. At the same time, a field plate 6 extending to the top of the gate structure 3 is set directly above the semiconductor layer 1 between the gate structure 3 and the drain 5. The distance between the edge of the field plate 6 directly above the second part 22 and the drain 5 is greater than the distance between the edge of the field plate 6 in the area outside the second part 22 and the drain 5, which ensures the device performance and reliability and meets the requirements of high temperature and high voltage stress applications.

[0104] Example 2

[0105] This embodiment also provides a method for fabricating a HEMT device, such as... Figure 8 The diagram shown is a process flow chart of the fabrication method of the HEMT device, including the following steps:

[0106] S1: Provide a semiconductor layer comprising at least a channel layer and a barrier layer stacked sequentially, and form a gate structure above the barrier layer and a source and a drain located on both sides of the gate structure along the X direction and spaced apart from the gate structure by a predetermined distance, wherein the source and the drain are electrically connected to the semiconductor layer.

[0107] S2: Form a current-optimized structure comprising at least a first part and a second part located above the barrier layer on both sides of the gate structure along the X direction. The first part is located on the side of the gate structure near the source and its two side walls along the X direction are respectively adjacent to the source and the gate structure. The second part is located on the side of the gate structure near the drain and its two side walls along the X direction are respectively adjacent to the drain structure and the gate structure. A plurality of first parts and a plurality of second parts are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction are at a preset angle.

[0108] S3: Form a field plate located directly above the region between the drain and the gate structure and spaced a predetermined distance from the drain in the X direction. The sidewall of the field plate near the gate structure extends directly above the gate structure. In the X direction, the distance between the field plate directly above the second part and the drain is greater than the distance between the field plate directly above the region between two adjacent second parts and the drain.

[0109] Please see Figures 9 to 10 Step S1: Provide a semiconductor layer 1 including at least a channel layer 13 and a barrier layer 14 stacked sequentially, and form a gate structure 3 above the barrier layer 14 and a source 4 and a drain 5 located on both sides of the gate structure 3 along the X direction and spaced apart from the gate structure 3 by a predetermined distance. The source 4 and the drain 5 are both electrically connected to the semiconductor layer 1.

[0110] Specifically, the semiconductor layer 1 also includes a substrate structure for forming a process platform for the channel layer 13. The substrate structure can be a single-layer film structure substrate 11 or a multi-layer composite film structure substrate 11 and a stacked structure of buffer layer 12. The selection depends on the channel layer 13 and the material of the channel layer 13.

[0111] Specifically, the channel layer 13 serves as the process platform for forming the barrier layer 14. While ensuring device performance, the thickness of the channel layer 13 can be selected according to the actual situation; the thickness of the barrier layer 14 can also be selected according to the actual situation.

[0112] Specifically, when the device to be fabricated is a depletion-type HEMT device, the semiconductor layer 1 further includes a dielectric layer 15 covering the barrier layer 14 and exposing its upper surface. The gate structure 3 is a gate metal layer 31 located on the upper surface of the dielectric layer 15. The source 4 and drain 5 respectively penetrate the dielectric layer 15 on both sides of the gate metal layer 31 along the X direction. Figure 9 As shown.

[0113] It should be noted that when the device is a depletion-type HEMT device, the gate metal layer 31, source 4 and drain 5 can be formed simultaneously, or the gate metal layer 31, source 4 and drain 5 can be formed step by step. Before forming the gate metal layer 31, source 4 and drain 5 simultaneously, a contact hole penetrating the dielectric layer 15 needs to be formed first, then an electrode material layer filling the contact hole and covering the upper surface of the dielectric layer 15 needs to be formed, and finally the electrode material layer is etched to obtain the source 4 and drain 5 filling the contact hole and the gate metal layer 31 located on the upper surface of the dielectric layer 15 between the source 4 and drain 5.

[0114] Specifically, the methods for forming contact holes through the dielectric layer 15 include dry etching, wet etching, or other suitable methods.

[0115] Specifically, methods for forming electrode material layers include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0116] Specifically, methods for etching the electrode material layer include dry etching, wet etching, or other suitable methods.

[0117] Specifically, when the device to be fabricated is an enhancement-mode HEMT device, the gate structure 3 includes a cap layer 32 and a gate metal layer 31 stacked sequentially. The cap layer 32 is formed on the upper surface of the barrier layer 14, and the gate metal layer 31 is located on the upper surface of the cap layer 32. The size of the gate metal layer 31 is not larger than the size of the cap layer 32. Figure 10 As shown.

[0118] Specifically, forming the cap layer 32 includes the following steps: forming a gate material layer covering the upper surface of the barrier layer 14, and forming a patterned first masking layer on the upper surface of the gate material layer; etching the gate material layer based on the patterned first masking layer to obtain the cap layer 32.

[0119] Specifically, methods for forming the gate material layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0120] Specifically, the method for forming the patterned first masking layer is the commonly used photoresist patterning method, which will not be elaborated here.

[0121] Specifically, methods for etching the gate material layer include dry etching, wet etching, or other suitable methods.

[0122] Specifically, after forming the cap layer 32 and before forming the gate metal layer 31 located on the upper surface of the cap layer 32, the process also includes a step of removing the first masking layer. The method for removing the first masking layer is the commonly used photoresist stripping method, which will not be described in detail here.

[0123] It should be noted that when the device to be fabricated is an enhancement-mode HEMT device, the gate metal layer 31 formed on the upper surface of the cap layer 32 can be formed simultaneously with the source 4 and the drain 5, or it can be formed stepwise with the source 4 and the drain 5. When the gate metal layer 31, the source 4 and the drain 5 are formed simultaneously, an electrode material layer covering the exposed surface of the cap layer 32 and the barrier layer 14 is formed first, and then the electrode material layer is etched to obtain the source 4 and the drain 5, which are electrically connected to the barrier layer 14, and the gate metal layer 31 located on the upper surface of the cap layer 32.

[0124] Please see Figures 11 to 13 Step S2: Form a current optimization structure 2 including at least a first part 21 and a second part 22 located above the barrier layer 14 on both sides of the gate structure 3 along the X direction. The first part 21 is located on the side of the gate structure 3 near the source 4 and its two side walls along the X direction are adjacent to the source 4 and the gate structure 3, respectively. The second part 22 is located on the side of the gate structure 3 near the drain 5 and its two side walls along the X direction are adjacent to the drain structure 5 and the gate structure 3, respectively. A plurality of first parts 21 and a plurality of second parts 22 are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction are at a preset angle.

[0125] Specifically, when the device is a depletion-type HEMT device, the first part 21 located directly above the barrier layer 14 between the gate structure 3 and the source 4 is a groove embedded in the dielectric layer 15 and spaced apart in the Y direction; the second part 22 located directly above the barrier layer 14 between the gate structure 3 and the drain 5 is a groove embedded in the dielectric layer 15 and spaced apart in the Y direction, as shown below. Figure 12 As shown.

[0126] Specifically, when the device is a depletion-type HEMT device, forming the current-optimized structure 2 includes the following steps: forming a patterned second masking layer on the upper surface of the semiconductor structure after forming the gate structure 3, drain 5 and source 4, and etching the dielectric layer 15 based on the second masking layer to obtain a first part 21 embedded in the dielectric layer 15 between the source 4 and the gate structure 3 and a second part 22 embedded in the dielectric layer 15 between the drain 5 and the gate structure 3.

[0127] Specifically, the method for forming the patterned second masking layer is the commonly used photoresist patterning method, which will not be elaborated here.

[0128] Specifically, the method for etching the dielectric layer 15 based on the patterned second masking layer includes dry etching, wet etching, or other suitable methods.

[0129] Specifically, after forming the grooves as the first part 21 and the second part 22, the process also includes a step of removing the second masking layer. The method for removing the second masking layer is the commonly used photoresist layer stripping method, which will not be described in detail here.

[0130] Specifically, when the device is an enhancement-mode HEMT, the upper surface of the barrier layer 14 between the source 4 and the gate structure 3, and between the drain 5 and the gate structure 3, is covered with a current enhancement layer 16 of a predetermined thickness. The first part 21 is a groove that penetrates the current enhancement layer 16 covering the upper surface of the barrier layer 14 between the gate structure 3 and the source 4 and is spaced apart in the Y direction. The second part 22 is a groove that penetrates the current enhancement layer 16 covering the upper surface of the barrier layer 14 between the gate structure 3 and the drain 5 and is spaced apart in the Y direction. Figure 13 As shown.

[0131] Specifically, such as Figure 11 The diagram shows a cross-sectional view of the current enhancement layer 16 after its formation. When the device is an enhancement-mode HEMT, the formation of the current optimization structure 2 includes the following steps: forming a current enhancement layer 16 that covers the exposed upper surface of the barrier layer 14 and the exposed surface of the gate structure 3, and forming a patterned third shielding layer that covers the upper surface of the current enhancement layer 16; etching the current enhancement layer 16 based on the patterned third shielding layer to obtain grooves in the current enhancement layer 16 that penetrate between the gate structure 3 and the source 4 and between the gate structure 3 and the drain 5, thus obtaining the current optimization structure 2 including the first part 21 and the second part 22.

[0132] Specifically, the methods for forming the current enhancement layer 16 include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0133] Specifically, the method for forming the patterned third masking layer is the commonly used photoresist patterning method, which will not be elaborated here.

[0134] Specifically, the etching methods for the current enhancement layer 16 include dry etching, wet etching, or other suitable methods.

[0135] Specifically, step S3 is performed: a field plate 6 is formed directly above the region between the drain 5 and the gate structure 3 and spaced at a predetermined distance from the drain 5 in the X direction. The sidewall of the field plate 6 near the gate structure 3 extends directly above the gate structure 3. In the X direction, the distance between the field plate 6 directly above the second part 22 and the drain 5 is greater than the distance between the field plate 6 directly above the region between two adjacent second parts 22 and the drain 5.

[0136] Specifically, after the current optimization structure 2 and before the field plate 6 is formed, the step of forming an isolation dielectric layer is also included. When the device is a depletion-type HEMT device, the isolation dielectric layer covers the exposed surfaces of the gate metal layer 31, the current optimization structure 2, the dielectric layer 15, the source 4, and the drain 5. When the device is an enhancement-type HEMT device, the isolation dielectric layer covers the exposed surfaces of the gate structure 3, the current optimization structure 2, the barrier layer 14, the source 4, and the drain 5. The field plate 6 is located on the upper surface of the isolation dielectric layer.

[0137] It should be noted that when the device is an enhancement-mode HEMT device, after forming the current-optimized structure 2 and before forming the isolation dielectric layer, there is also a step of removing the third masking layer. The method for removing the third masking layer is the commonly used photoresist layer stripping method, which will not be described in detail here.

[0138] Specifically, methods for forming the isolation medium layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0139] Specifically, forming the field plate 6 includes the following steps: forming a field plate 6 trench in the isolation dielectric layer, located directly above the barrier layer 14 on the side of the gate structure 3 near the drain 5 and near the sidewall of the gate structure 3 at a predetermined distance from the gate structure 3; forming a field plate 6 material layer covering the exposed upper surface of the isolation dielectric layer and the inner wall and bottom surface of the field plate 6 trench; etching the field plate 6 material layer to obtain a field plate 6 located directly above the barrier layer 14 and the gate structure 3 and in a comb-like shape.

[0140] Specifically, the methods for forming the six grooves of the field plate include dry etching, wet etching, or other suitable methods.

[0141] Specifically, while ensuring device performance, the depth of the field plate 6 groove can be selected according to the actual situation; the distance between the side of the field plate 6 groove closest to the gate structure 3 and the gate structure 3 can be selected according to the actual situation.

[0142] Specifically, the methods for forming the field plate 6 material layer include sputtering, physical vapor deposition, chemical vapor deposition, metal compound vapor deposition, molecular beam epitaxy, atomic vapor deposition, atomic layer deposition, or other suitable methods.

[0143] Specifically, the etching methods for the material layer of the field plate 6 include dry etching, wet etching, or other suitable methods.

[0144] It should be noted that the end of the field plate 6 near the drain 5 is usually located on the bottom surface of the field plate 6 trench. While ensuring the quality of the field plate 6, the position of the field plate 6 trench away from the gate structure 3 can be selected according to the actual situation.

[0145] Specifically, after forming the field plate 6, the process also includes forming a dielectric protective layer on the exposed upper surface of the field plate 6 and the exposed surface of the field plate 6, which covers the insulating dielectric layer.

[0146] Specifically, methods for forming a dielectric protective layer include chemical vapor deposition, physical vapor deposition, or other suitable methods.

[0147] Specifically, after forming the electrodes of the device, a current optimization structure 2 is formed directly above the barrier layer 14 between the gate structure 3 and the source 4 and between the gate structure 3 and the drain 5. This improves the two-dimensional electron gas concentration distribution at the interface between the channel layer 13 and the barrier layer 14, reduces the saturation current of the device, and enhances the short-circuit withstand capability of the device.

[0148] The HEMT device fabrication method of this embodiment improves the device fabrication process by forming a current optimization structure 2 directly above the barrier layer 14 located between the gate structure 3 and the source 4 and between the gate structure 3 and the drain 5 after the formation of the electrodes and before the formation of the field plate 6. This reduces the saturation current of the device, improves the short-circuit withstand capability of the device, and enhances the reliability of the device.

[0149] In summary, the HEMT device and its fabrication method of the present invention improve the device structure by setting a current optimization structure directly above the semiconductor layer between the gate structure and the source and drain regions. This current optimization structure includes multiple first and second parts spaced apart in the Y direction and corresponding one-to-one in the X direction. The placement of the first and second parts reduces the concentration of two-dimensional electron gas directly below them, thereby reducing the device's saturation current and improving its short-circuit withstand capability. Simultaneously, a field plate extending to the top of the gate structure is placed directly above the semiconductor layer between the gate and drain regions. The distance between the edge of the field plate directly above the second part and the drain is greater than the distance between the edge of the field plate outside the area directly above the second part and the drain, ensuring device performance and further improving device reliability, meeting the requirements of high-temperature and high-voltage stress applications. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0150] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A HEMT device, characterized in that, include: The semiconductor layer includes at least a channel layer and a barrier layer stacked sequentially. A gate structure is located above the barrier layer; The source and drain, which are electrically connected to the semiconductor layer, are located on both sides of the gate structure along the X direction and are spaced apart from the gate structure by a predetermined distance. The current-optimized structure includes at least a first part and a second part located above the barrier layer on both sides of the gate structure along the X direction. The first part is located on the side of the gate structure near the source and its two side walls along the X direction are respectively adjacent to the source and the gate structure. The second part is located on the side of the gate structure near the drain and its two side walls along the X direction are respectively adjacent to the drain and the gate structure. A plurality of the first parts and a plurality of the second parts are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction form a preset angle. A field plate is located directly above the region between the drain and the gate structure and is spaced a predetermined distance from the drain in the X direction. The sidewall of the field plate near the gate structure extends directly above the gate structure. In the X direction, the distance between the field plate directly above the second part and the drain is greater than the distance between the field plate directly above the region between two adjacent second parts and the drain.

2. The HEMT device according to claim 1, characterized in that: The semiconductor layer further includes a substrate structure, and the channel layer is located on the upper surface of the substrate structure.

3. The HEMT device according to claim 2, characterized in that: The substrate structure includes a substrate and a buffer layer stacked sequentially, and the channel layer is located on the upper surface of the buffer layer.

4. The HEMT device according to claim 1, characterized in that: The semiconductor layer further includes a dielectric layer covering the upper surface of the barrier layer, the source and the drain penetrate the dielectric layer, the current optimization structure includes a groove embedded in the dielectric layer, the gate structure is a gate metal layer covering the upper surface of the dielectric layer, and the bottom surface of the groove is spaced at a predetermined distance from the upper surface of the barrier layer.

5. The HEMT device according to claim 4, characterized in that: The distance between the bottom surface of the first part and the upper surface of the barrier layer directly below it is the same as the distance between the bottom surface of the second part and the upper surface of the barrier layer directly below it.

6. The HEMT device according to claim 1, characterized in that: The gate structure includes a cap layer and a gate metal layer stacked sequentially. The cap layer is located on the upper surface of the barrier layer. The device also includes a current enhancement layer that covers at least the exposed surfaces of the barrier layer between the gate structure and the source and between the gate structure and the drain. The current optimization structure includes a groove penetrating the current enhancement layer. A first portion penetrates the current enhancement layer between the source and the cap layer, and a second portion penetrates the current enhancement layer between the drain and the cap layer.

7. The HEMT device according to claim 6, characterized in that: The current enhancement layer also covers the exposed surface of the gate structure and is in communication with the current enhancement layers on both sides of the gate structure along the X direction.

8. The HEMT device according to claim 1, characterized in that: The first part and the second part have the same dimensions in the Y direction.

9. The HEMT device according to claim 1, characterized in that: The exposed upper surface of the current-optimized structure and the exposed surface of the gate structure are further provided with an isolation dielectric layer, and the field plate is located on the upper surface of the isolation dielectric layer.

10. A method for fabricating a HEMT device, characterized in that, Includes the following steps: A semiconductor layer is provided, comprising at least a channel layer and a barrier layer stacked sequentially, and a gate structure is formed above the barrier layer, and a source and a drain are respectively located on both sides of the gate structure along the X direction and spaced apart from the gate structure by a predetermined distance, wherein the source and the drain are electrically connected to the semiconductor layer. A current-optimized structure is formed, comprising at least a first part and a second part located above the barrier layer on both sides of the gate structure along the X direction. The first part is located on the side of the gate structure near the source and its two side walls along the X direction are respectively adjacent to the source and the gate structure. The second part is located on the side of the gate structure near the drain and its two side walls along the X direction are respectively adjacent to the drain structure and the gate structure. A plurality of the first parts and a plurality of the second parts are arranged at intervals along the Y direction and correspond one-to-one in the X direction. The X direction and the Y direction are at a preset angle. A field plate is formed directly above the region between the drain and the gate structure and spaced a predetermined distance from the drain in the X direction. The sidewall of the field plate near the gate structure extends directly above the gate structure. In the X direction, the distance between the field plate directly above the second part and the drain is greater than the distance between the field plate directly above the region between two adjacent second parts and the drain.

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