A semiconductor structure, a preparation method thereof, and a semiconductor device

Abstract

The application discloses a semiconductor structure and a preparation method and a semiconductor device thereof, and belongs to the technical field of semiconductors. The semiconductor structure comprises a substrate, a recess, a buried oxygen structure, an epitaxial layer and a cavity. The substrate comprises oppositely arranged first and second surfaces. The recess is recessed into the substrate from the first surface, and the interface between the recess and the substrate is in a stepped shape. The buried oxygen structure comprises a first buried oxygen region and a plurality of second buried oxygen regions. The first buried oxygen region extends into the substrate from the bottom of the recess. The second buried oxygen regions extend into the substrate from part of the sidewall of the recess. The epitaxial layer is arranged in the recess on the buried oxygen structure. The cavity is arranged in the substrate between the epitaxial layer, the first buried oxygen region and the second buried oxygen regions. The depth of the cavity is equal to the depth of the second buried oxygen region. The atmosphere in the cavity is the same as the atmosphere when the epitaxial layer is formed. The semiconductor structure, the preparation method and the semiconductor device thereof can reduce the preparation cost of the semiconductor device and improve the performance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a semiconductor structure, a preparation method thereof and a semiconductor device. BACKGROUND

[0002] Compared with bulk silicon, a silicon-on-insulator (SOI) structure can reduce the parasitic capacitance between source / drain and substrate in a metal-oxide-semiconductor (MOS) device, reduce short channel effect and leakage current by introducing a buried oxide layer between the substrate and the top layer of silicon, thereby optimizing the performance, power consumption and reliability of the semiconductor device. However, the current MOS process is based on a bulk silicon substrate, and there are great differences between the substrate structure and the physical characteristics of the device between the MOS process and the SOI process, which leads to the incompatibility between the SOI process and the MOS process, thereby affecting the preparation of the SOI MOS device. SUMMARY

[0003] In view of the above-mentioned shortcomings of the prior art, the present application aims to provide a semiconductor structure, a preparation method thereof and a semiconductor device, which can improve the compatibility of the SOI process and the MOS process, reduce the preparation cost of the SOI MOS device, physically isolate the conductive path in the substrate, improve the resistivity of the substrate, greatly reduce the loss of the substrate, and thereby improve the performance of the semiconductor structure in high frequency, radio frequency, low power consumption and signal integrity.

[0004] To solve the above technical problems, the present application is realized by the following technical scheme.

[0005] The present application provides a semiconductor structure, which at least comprises:

[0006] a substrate comprising a first surface and a second surface arranged oppositely;

[0007] a groove recessed into the substrate from the first surface, and the interface between the groove and the substrate is in a stepped shape;

[0008] a buried oxide structure comprising a first buried oxide region and a plurality of second buried oxide regions, the first buried oxide region extending into the substrate from the bottom of the groove, and the second buried oxide region extending into the substrate from part of the sidewall of the groove;

[0009] an epitaxial layer arranged in the groove on the buried oxide structure; and

[0010] A cavity is formed in the substrate between the epitaxial layer, the first buried oxygen region and the second buried oxygen region, and the depth of the cavity is equal to the depth of the second buried oxygen region, and the atmosphere in the cavity is the same as the atmosphere when the epitaxial layer is formed.

[0011] In an embodiment of the present application, the step structure comprises at least a first step, a second step and a connecting portion, the first step is the bottom of the groove, the second step is arranged on both sides of the first step, the surface of the first step is lower than the surface of the second step, the surface of the second step is lower than the first surface, and the connecting portion connects the first step and the second step.

[0012] In an embodiment of the present application, the second buried oxygen region extends into the substrate from the connecting portion, the first buried oxygen region extends into the substrate from the first step, and the edge of the first buried oxygen region is located in the substrate under the second buried oxygen region.

[0013] The present application also provides a method for manufacturing a semiconductor structure, comprising at least the following steps:

[0014] Providing a substrate, the substrate comprising a first surface and a second surface arranged oppositely;

[0015] Forming a groove in the substrate, the groove is recessed into the substrate from the first surface, and the interface between the groove and the substrate is a step structure, and in the direction from the first surface to the second surface, the size of the groove decreases;

[0016] Forming a buried oxygen structure in the substrate, the buried oxygen structure comprises a first buried oxygen region and a plurality of second buried oxygen regions, the first buried oxygen region extends into the substrate from the bottom of the groove, and the second buried oxygen regions extend into the substrate from the sidewall of the groove near the first buried oxygen region;

[0017] Forming an epitaxial layer in the groove on the buried oxygen structure; and

[0018] Forming a cavity in the substrate between the epitaxial layer, the first buried oxygen region and the second buried oxygen region.

[0019] In an embodiment of the present application, the forming of the groove comprises at least the following steps:

[0020] Forming a pad oxide layer on the first surface;

[0021] Forming a first nitride layer on the pad oxide layer;

[0022] etching part of the first nitride layer, part of the pad oxide layer and part of the substrate to form a recess, the recess being recessed into the substrate from the first nitride layer;

[0023] forming a second nitride layer on the bottom and sidewall of the recess and the first nitride layer; and

[0024] vertically etching the second nitride layer and the substrate in the recess and the first nitride layer and part of the second nitride layer or the first nitride layer, the second nitride layer and part of the pad oxide layer on the first surface to retain the second nitride layer on the sidewall of the recess to form the trench.

[0025] In an embodiment of the present application, the depth of the vertical etching is greater than the thickness of the second nitride layer and less than the sum of the thicknesses of the second nitride layer, the first nitride layer and the pad oxide layer.

[0026] In an embodiment of the present application, the exposed substrate in the trench is subjected to an oxidation process to form the buried oxide structure.

[0027] The present application also provides a semiconductor device comprising at least:

[0028] the semiconductor structure as described above;

[0029] a deep well region extending into the epitaxial layer and the substrate from the first surface and at least to the second buried oxide region;

[0030] at least two shallow trench isolation structures symmetrically arranged in the deep well region on both sides of the cavity;

[0031] a well region arranged in the deep well region between two adjacent shallow trench isolation structures;

[0032] a gate arranged on the well region on the cavity;

[0033] a source doped region arranged in the well region on one side of the gate; and

[0034] a drain doped region arranged in the well region on the other side of the gate.

[0035] In an embodiment of the present application, the orthographic projection of the buried oxide structure and the cavity in the direction of the first surface falls in the well region between the source doped region and the drain doped region.

[0036] In an embodiment of the present application, the orthographic projection of the buried oxide structure and the cavity in the direction of the first surface extends from the well region between the source doped region and the drain doped region to the source doped region and the drain doped region on both sides.

[0037] In summary, the present application provides a semiconductor structure and a preparation method thereof, and a semiconductor device. By improving the semiconductor structure and the preparation method thereof, the present application has the unexpected technical effects of being able to use a conventional bulk silicon substrate to prepare various types of SOI structure, improving the resistivity of the substrate in the SOI structure, greatly reducing the loss of the substrate, improving the compatibility of the SOI process and the MOS process, thereby reducing the preparation cost of the SOI MOS device, reducing the dielectric constant of the substrate, thereby reducing the coupling capacitance of the SOI MOS device and the substrate, and improving the isolation, noise factor, linearity and other performances of the device, and being able to design bulk silicon MOS devices and SOI MOS devices on the same bulk silicon substrate, thereby increasing the diversity of product functions.

[0038] Of course, implementing any of the ways of the present application does not necessarily need to achieve all the advantages described above at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without creative labor on the basis of these drawings.

[0040] Figure 1 A schematic diagram for forming the pad oxide layer, the first nitride layer and the first photoresist layer.

[0041] Figure 2 A schematic diagram for forming the recess.

[0042] Figure 3 A schematic diagram for forming the second nitride layer.

[0043] Figure 4 A schematic diagram for forming the groove.

[0044] Figure 5 A schematic diagram for forming the buried oxygen structure.

[0045] Figure 6 A schematic diagram for forming the epitaxial layer and the cavity.

[0046] Figure 7 A schematic diagram of a semiconductor structure in an embodiment.

[0047] Figure 8 A schematic diagram of a semiconductor structure in another embodiment.

[0048] Figure 9 A schematic diagram for forming the protective layer.

[0049] Figure 10Schematic diagram for forming a deep well region.

[0050] Figure 11 Schematic diagram for forming a third nitride layer.

[0051] Figure 12 Schematic diagram for forming a second photoresist layer.

[0052] Figure 13 Schematic diagram for forming a shallow trench.

[0053] Figure 14 Schematic diagram for forming a repair layer.

[0054] Figure 15 Schematic diagram for forming an insulating medium.

[0055] Figure 16 Schematic diagram for planarizing the third nitride layer and the insulating medium.

[0056] Figure 17 Schematic diagram for forming a well region.

[0057] Figure 18 Schematic diagram for forming a gate oxide layer and a gate.

[0058] Figure 19 Schematic diagram for forming a source lightly doped region and a drain lightly doped region.

[0059] Figure 20 Schematic diagram for forming a side wall.

[0060] Figure 21 Schematic diagram of a semiconductor device in one embodiment.

[0061] Figure 22 Schematic diagram of a semiconductor device in another embodiment.

[0062] Reference Signs List:

[0063] 10. Substrate; 101. First surface; 102. Second surface; 11. Pad oxide layer; 121. First nitride layer; 122. Second nitride layer; 123. First photoresist layer; 1231. First portion; 1232. Second portion; 124. Recess; 13. Groove; 131. First step layer; 132. Second step layer; 133. Connector; 14. Buried oxide structure; 141. First buried oxide region; 142. Second buried oxide region; 15. Cavity; 16. Epitaxial layer; 17. Protective layer; 18. Deep well region; 19. Third nitride layer; 20. Second photoresist layer; 201. Opening; 21. Shallow trench; 22. Repair layer; 23. Shallow trench isolation structure; 231. Insulating dielectric; 24. Well region; 25. Gate oxide layer; 26. Gate; 27. Source doped region; 271. Lightly doped source region; 272. Heavily doped source region; 28. Drain doped region; 281. Lightly doped drain region; 282. Heavily doped drain region; 29. ​​Sidewall; 291. First sidewall; 292. Second sidewall; 293. Third sidewall; 294. Fourth sidewall. Detailed Implementation

[0064] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0065] It should be understood that the invention can be embodied in various forms and should not be construed as being limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0066] The technical solution of the present invention will be further described in detail below with reference to the embodiments and accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0067] Please see Figure 4 , Figure 7 and Figure 8As shown, the present application provides a semiconductor structure, which includes a substrate 10, a groove 13, a buried oxygen structure 14, a cavity 15 and an epitaxial layer 16, etc. Wherein, the substrate 10 includes oppositely arranged first surface 101 and second surface 102, the groove 13 is recessed into the substrate 10 from the first surface 101, and the interface between the groove 13 and the substrate 10 is in a stepped shape, in the direction of the first surface 101 pointing to the second surface 102, the size of the groove 13 decreases, the buried oxygen structure 14 includes a first buried oxygen region 141 and a plurality of second buried oxygen regions 142, the first buried oxygen region 141 extends into the substrate 10 from the bottom of the groove 13, the second buried oxygen region 142 extends into the substrate 10 from the part of the sidewall of the groove 13 close to the first buried oxygen region 141, the epitaxial layer 16 is arranged in the groove 13 on the buried oxygen structure 14, the cavity 15 is arranged in the substrate 10 between the epitaxial layer 16, the first buried oxygen region 141 and the second buried oxygen region 142, and the depth of the cavity 15 is equal to the depth of the second buried oxygen region 142, and the atmosphere in the cavity 15 is the same as the atmosphere when the epitaxial layer 16 is formed. In the semiconductor structure provided by the present application, by introducing the cavity 15 into the substrate 10, the conductive path in the substrate 10 can be physically cut off, the resistivity of the substrate 10 is improved, the loss of the substrate 10 is greatly reduced, thereby improving the performance of the semiconductor structure in high frequency, radio frequency, low power consumption and signal integrity, etc., and increasing the competitiveness of the semiconductor structure in communication, radar or aerospace electronics, etc. applications.

[0068] Please refer to Figure 1 As shown, the present application also provides a preparation method of a semiconductor structure, which is used for preparing various types of SOI structures such as a partially depleted silicon-on-insulator (PD SOI) structure and a fully depleted silicon-on-insulator (FD SOI) structure. In this embodiment, the preparation method of the semiconductor structure is described by taking the PD SOI structure as an example. First, a substrate 10 is provided, which includes oppositely arranged first surface 101 and second surface 102, and the substrate 10 can be any material suitable for forming a semiconductor device, such as silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), indium phosphide (InP), gallium arsenide (GaAs), silicon germanium (GeSi), sapphire, silicon wafer or other III / V compound semiconductor material, etc. Wherein, the substrate 10 can be an intrinsic semiconductor, or ions can be implanted in the substrate 10 to form an N-type semiconductor or a P-type semiconductor. Moreover, the present application does not limit the thickness of the substrate 10. In this embodiment, the preparation method of the semiconductor structure is described by taking a P-type silicon substrate 10 as an example. Wherein, the doping ions in the P-type silicon substrate 10 are, for example, boron (B), boron fluoride (BF2+ P-type ions such as indium (In) or indium (In).

[0069] Please see Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 11 is formed on the first surface 101. The pad oxide layer 11 is, for example, made of a material such as silicon oxide, and the thickness of the pad oxide layer 11 is, for example, 10nm-50nm, specifically, 25nm, 35nm, 40nm, 45nm, or 50nm. The pad oxide layer 11 is formed, for example, by thermal oxidation, in-situ water vapor growth, or chemical vapor deposition. Specifically, for example, after placing the substrate 10 in a furnace tube at a temperature of, for example, 900°C-1150°C, oxygen is introduced, and the substrate 10 reacts with oxygen at a high temperature to generate a dense pad oxide layer 11.

[0070] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad oxide layer 11, a first nitride layer 121 is formed on the pad oxide layer 11. The first nitride layer 121 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide. The thickness of the first nitride layer 121 is, for example, 50nm-120nm, specifically, for example, 60nm, 75nm, 80nm, 100nm, 110nm or 120nm. The first nitride layer 121 is formed, for example, by a method such as low pressure chemical vapor deposition (LPCVD). Specifically, for example, the substrate 10 with the pad oxide layer 11 is placed in a furnace tube filled with dichlorosilane and ammonia, and the reaction is carried out at a pressure of, for example, 2 Torr-10 Torr and a temperature of, for example, 700°C-800°C, to deposit the first nitride layer 121. Among them, the pad oxide layer 11 and the first nitride layer 121 can serve as masks during the subsequent formation of the groove 13, protecting other parts of the substrate 10 from damage when etching the substrate 10.

[0071] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the first nitride layer 121, photoresist is formed on the first nitride layer 121 by, for example, spin coating or spray coating. After exposure and development processes, the photoresist is patterned to form the first photoresist layer 123. The first photoresist layer 123 includes a first portion 1231 and a second portion 1232. The first portion 1231 and the second portion 1232 are disposed at intervals on the first nitride layer 121 and expose a portion of the first nitride layer 121.

[0072] Please see Figures 1-2As shown in the embodiment of the present application, the exposed first nitride layer 121, pad oxide layer 11 and part of the substrate 10 are etched to form a recess 124 using the first photoresist layer 123 as a mask, and then the first photoresist layer 123 is removed, for example, by ashing process, and the polymer residues in the recess 124 during the etching process are removed, for example, by wet cleaning. The recess 124 is recessed from the first nitride layer 121 to the substrate 10, and the present application does not limit the distance between the bottom of the recess 124 and the second surface 102, which can be selected according to the type and requirements of the SOI structure. In the embodiment, the distance between the bottom of the recess 124 and the second surface 102 is, for example, less than the distance between the bottom of the recess 124 and the first surface 101.

[0073] Referring to Figures 2-3 As shown in the embodiment of the present application, after the recess 124 is formed, the second nitride layer 122, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, is formed on the bottom and sidewall of the recess 124 and the first nitride layer 121, and the second nitride layer 122 is formed, for example, by chemical vapor deposition or atomic layer deposition, and the present application does not limit the thickness of the second nitride layer 122, which can be selected according to actual needs.

[0074] Referring to Figures 3-4 As shown in the embodiment of the present application, after the second nitride layer 122 is formed, the second nitride layer 122 in the recess 124 and the substrate 10, and the nitride layer or the nitride layer and part of the pad oxide layer 11 on the first surface 101 are vertically etched from the first surface 101 to the second surface 102, and the second nitride layer 122 on the sidewall of the recess 124 is reserved. The vertical etching depth is, for example, greater than the thickness of the second nitride layer 122, and is, for example, less than the sum of the thicknesses of the second nitride layer 122, the first nitride layer 121 and the pad oxide layer 11. In the embodiment, the vertical etching depth is, for example, greater than the thickness of the second nitride layer 122, and is, for example, less than the sum of the thicknesses of the second nitride layer 122 and the first nitride layer 121.

[0075] Referring to Figure 4As shown in the embodiment of the present application, after the vertical etching of the nitride layer and the substrate 10, the recess 13 is formed in the substrate 10, and the interface between the recess 13 and the substrate 10 is, for example, in a stepped shape, and the size of the recess 13 decreases in the direction from the first surface 101 to the second surface 102. The stepped shape has, for example, at least two layers. In the embodiment, the stepped shape has, for example, two layers, and the stepped shape includes, for example, a first layer of steps 131, a second layer of steps 132, and a connecting portion 133. The first layer of steps 131 is the interface between the bottom of the recess 13 and the substrate 10. The second layer of steps 132 is, for example, symmetrically arranged on both sides of the first layer of steps 131, and the surface of the first layer of steps 131 is lower than the surface of the second layer of steps 132. The surface of the second layer of steps 132 is lower than the first surface 101. The connecting portion 133 connects the first layer of steps 131 and the second layer of steps 132.

[0076] Referring to Figures 4-5 As shown in the embodiment of the present application, after the recess 13 is formed, the exposed substrate 10 in the recess 13 is subjected to an oxidation treatment, for example, by a rapid thermal processing (RTP) and in-situ steam generation (ISSG) process, to obtain a buried oxide structure 14. Specifically, the substrate 10 with the recess 13, the second nitride layer 122, the first nitride layer 121, and the pad oxide layer 11 is placed in an RTP device, and after hydrogen and oxygen are introduced, the substrate 10 in the recess 13 is rapidly heated to, for example, 1000-1500°C, and the silicon in the substrate 10 exposed in the recess 13 is oxidized in-situ to form the buried oxide structure 14. The thickness of the buried oxide structure 14 is, for example, 100-200 nm. The buried oxide structure 14 includes a first buried oxide region 141 and a second buried oxide region 142. The first buried oxide region 141 extends from the bottom of the recess 13, i.e., the first layer of steps 131, to a second depth in the substrate 10. The second buried oxide region 142 is, for example, a plurality of regions, and the second buried oxide region 142 extends from part of the sidewall of the recess 13 to a first depth in the substrate 10. Specifically, in the embodiment, one second buried oxide region 142 is arranged on each side of the first buried oxide region 141, and the second buried oxide region 142 extends from the connecting portion 133 to the first depth in the substrate 10. Further, the edge of the first buried oxide region 141 is located in the substrate 10 below the second buried oxide region 142, i.e., the length of the first buried oxide region 141 is greater than the length of the bottom of the recess 13. The first buried oxide region 141 and the second buried oxide region 142 are arranged continuously, and the first depth and the second depth are equal.

[0077] Referring to Figures 5-6As shown in the embodiment of the present application, after the buried oxygen structure 14 is formed, the first nitrided layer 121 and the second nitrided layer 122 are removed. The nitrided layer is removed by a wet etching method, for example, a hot phosphoric acid solution, for example, at a temperature of 160-180°C and a concentration of 85-90wt%.

[0078] Referring to Figures 4-6 As shown in the embodiment of the present application, after the nitrided layer is removed, a lateral epitaxial growth is performed in the recess 13 to form an epitaxial layer 16, which fills the recess 13 on the second buried oxygen region 142. Specifically, the epitaxial layer 16 extends from the second layer step 132 into the recess 13 on the second buried oxygen region 142 to be flush with the first surface 101 and connects the substrate 10 on both sides of the recess 13, and the thickness of the epitaxial layer 16 is, for example, 50-200nm. In the embodiment, the epitaxial layer 16 is formed by a molecular beam epitaxy (MBE) method, for example. Specifically, the substrate 10 with the buried oxygen structure 14 and the pad oxide layer 11 is placed in an MBE growth chamber, and then the MBE growth chamber is vacuumized so that the atmosphere in the MBE growth chamber is vacuum. Then, a silicon atomic beam is sprayed into the recess 13 to perform a lateral epitaxial growth in the recess 13. In another embodiment of the present application, the epitaxial layer 16 is formed by a vapor phase epitaxy method, for example. Specifically, the substrate 10 with the buried oxygen structure 14 and the pad oxide layer 11 is placed in an epitaxial growth reaction furnace, and then a silicon source gas and a reducing gas are introduced into the epitaxial growth reaction furnace and heated. The silicon source gas is reduced to silicon atoms, and the silicon atoms perform a lateral epitaxial growth in the recess 13. The silicon source gas includes at least one of monosilane and dichlorosilane, for example, and the reducing gas includes hydrogen, for example. The heating temperature is, for example, 800-1200°C.

[0079] Referring to Figure 6As shown, in an embodiment of the present application, after the epitaxial layer 16 is formed, the cavity 15 is naturally formed between the epitaxial layer 16, the first buried oxygen region 141 and the second buried oxygen region 142. The atmosphere in the cavity 15 is the same as that when the epitaxial layer 16 is formed. For example, when the epitaxial layer 16 is formed by the MBE method, the atmosphere in the cavity 15 is vacuum; when the epitaxial layer 16 is formed by the vapor phase epitaxy method, the atmosphere in the cavity 15 is a silicon source gas and a reducing gas. Since the dielectric constant of silicon dioxide is 3.9-4.2, by providing the cavity 15 in the substrate 10 and filling only the gas in the cavity 15 without filling silicon dioxide or other materials, the cavity 15 with a dielectric constant of about 1.006 can be obtained, which is much smaller than the dielectric constant of silicon dioxide, thereby reducing the dielectric constant of the whole semiconductor structure, physically blocking the conductive path in the substrate 10, increasing the resistivity of the substrate 10, reducing the loss of the substrate 10, and improving the performance of the semiconductor structure in high frequency, radio frequency, low power consumption and signal integrity, etc., and increasing the competitiveness of the semiconductor structure in communication, radar or aerospace electronics, etc. Further, the depth of the cavity 15 is equal to the depth of the second buried oxygen region 142, so the volume of the cavity 15 can be adjusted according to the depth of the second buried oxygen region 142, thereby adjusting the filling amount of the atmosphere in the cavity 15, so as to change the degree of reduction of the dielectric constant of the semiconductor structure by the cavity 15, and further optimize the performance of the semiconductor structure in high frequency, radio frequency, low power consumption and signal integrity, etc.

[0080] Referring to Figures 6-7 As shown, in an embodiment of the present application, after the cavity 15 is formed, the pad oxide layer 11 is removed to obtain a PDSOI structure. The pad oxide layer 11 is removed by wet etching, for example. The solution for wet etching includes hydrofluoric acid and water, for example. The volume ratio of hydrofluoric acid to water is 1:(50-100), for example.

[0081] Referring to Figure 8 Based on the preparation method described above, the present application further provides another semiconductor structure, for example, an FDSOI structure. The thickness of the epitaxial layer 16 is 5-10 nm, for example. The thickness of the buried oxygen structure 14 is 10-25 nm, for example. By using the preparation method provided by the present application, various types of SOI structures such as PDSOI and FDSOI can be prepared using a bulk silicon substrate 10, thereby reducing the cost of the SOI structure.

[0082] Referring to Figure 4 , Figure 7 , Figure 8 , Figure 21 and Figure 22 ​As shown, based on the above semiconductor structure, the application further provides a semiconductor device, which comprises the semiconductor structure, the deep well region 18, the shallow trench isolation structure 23, the well region 24, the gate 26, the source doped region 27 and the drain doped region 28, etc. Wherein, the deep well region 18 extends from the first surface 101 to the epitaxial layer 16 and the substrate 10, and at least extends to contact the second buried oxygen region 142, the shallow trench isolation structure 23 is symmetrically arranged in the deep well region 18 on both sides of the cavity 15, the well region 24 is arranged in the deep well region 18 between two adjacent shallow trench isolation structures 23, the gate 26 is arranged on the well region 24 on the cavity 15, the source doped region 27 is arranged in the well region 24 on one side of the gate 26, and the drain doped region 28 is arranged in the well region 24 on the other side of the gate 26. In the semiconductor device provided by the application, the bulk silicon substrate 10 is processed in combination with the SOI process and the MOS process, so that the SOI MOS device can be obtained, thereby improving the compatibility of the SOI process and the MOS process, reducing the preparation cost of the SOI MOS device, and because the semiconductor structure contains the cavity 15, the coupling capacitance between the SOI MOS device and the substrate 10 can be reduced, and the isolation degree, noise coefficient and linearity of the device can be improved. Wherein, the SOI MOS device can be an N-type Metal Oxide Semiconductor (NMOS) device or a P-type Metal Oxide Semiconductor (PMOS) device, etc., and can also be used to manufacture a Complementary Metal Oxide Semiconductor (CMOS) device, etc. In this embodiment, the structure and preparation process of the semiconductor device are described taking the SOI NMOS device as an example.

[0083] As shown in Figure 7 and Figure 8 In an embodiment of the application, the semiconductor structure is, for example, a PD SOI structure or a FDSOI structure, etc. In this embodiment, the semiconductor device is described taking the PD SOI structure as an example.

[0084] As shown in Figure 7 and Figure 9In an embodiment of the present application, a protective layer 17 is formed on the first surface 101 of the semiconductor structure, and the protective layer 17 covers the epitaxial layer 16 and the substrate 10. The protective layer 17 is, for example, a dense silicon oxide or the like, and has a thickness of, for example, 30-60 angstroms, such as 50 angstroms, 55 angstroms or 60 angstroms, and can be formed by, for example, thermal oxidation, in-situ water vapor growth or chemical vapor deposition. In this embodiment, the semiconductor structure is placed in a furnace tube at a temperature of, for example, 900-1150 degrees Celsius, and oxygen is introduced, so that the substrate 10 and the epitaxial layer 16 react with the oxygen at high temperature to form the protective layer 17. By providing the protective layer 17, the surface of the semiconductor structure can be protected from damage in the subsequent ion implantation process.

[0085] Referring to Figures 9-10 In an embodiment of the present application, after the protective layer 17 is formed, first ions are implanted into the semiconductor structure from the first surface 101 to form a deep well region 18, and the deep well region 18 extends from the first surface 101 into the epitaxial layer 16 and the substrate 10, and at least to the second buried oxide region 142. In this embodiment, the interface of the deep well region 18 in the semiconductor structure is in contact with the top of the second buried oxide region 142. The first ions are, for example, N-type ions such as phosphorus (P) or arsenic (As), and the implantation energy of the first ions is, for example, 2-4 MeV, and the implantation dose of the first ions is, for example, 1x1011-1x1013 ions / cm2. 15 2 -2x1012 12 ions / cm2 2 .

[0086] Referring to Figures 10-11 In an embodiment of the present application, after the deep well region 18 is formed, a third nitride layer 19 is formed on the protective layer 17. The third nitride layer 19 is, for example, silicon nitride or a mixture of silicon nitride and silicon oxide, and is formed by, for example, LPCVD. The thickness of the third nitride layer 19 can be selected according to actual needs.

[0087] Referring to Figures 11-12 In an embodiment of the present application, after the third nitride layer 19 is formed, a photoresist is formed on the third nitride layer 19 by, for example, spin coating or spraying. After exposure and development, the photoresist is patterned to form a second photoresist layer 20, and the second photoresist layer 20 covers part of the third nitride layer 19, and openings 201 are formed in the second photoresist layer 20. The openings 201 are, for example, at least two, and are located on both sides of the buried oxide structure 14. In this embodiment, the openings 201 are, for example, two, and are symmetrically arranged, and expose part of the third nitride layer 19 on both sides of the buried oxide structure 14.

[0088] Referring to Figures 12-13 ​As shown, in one embodiment of the present invention, using the second photoresist layer 20 as a mask, the exposed third nitride layer 19, protective layer 17, and part of the deep well region 18 are etched to form shallow trenches 21, and then the second photoresist layer 20 is removed. The shallow trenches 21 may be at least two. In this embodiment, for example, there are two shallow trenches 21, symmetrically arranged on both sides of the buried oxide structure 14, extending from the third nitride layer 19 into the deep well region 18, with the bottom of the shallow trenches 21 located within the deep well region 18.

[0089] Please see Figures 13-14 As shown, in one embodiment of the present invention, after the shallow trench 21 is formed, the inner wall of the shallow trench 21 is oxidized, for example, by an RTP process, to form a repair layer 22, so as to repair the damage to the deep well region 18 caused by etching during the formation of the shallow trench 21. The repair layer 22 may include materials such as silicon oxide, and the thickness of the repair layer 22 can be set according to actual needs.

[0090] Please see Figures 14-15 As shown, in one embodiment of the present invention, after forming the repair layer 22, an insulating medium 231 is deposited on the repair layer 22 until it completely fills the shallow trench 21 and covers the surface of the third nitride layer 19. Then, an annealing treatment is performed to improve the density of the insulating medium 231. The insulating medium 231 is deposited, for example, by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio process chemical vapor deposition (HARP-CVD). The material of the insulating medium 231 can be silicon oxide, which has high adaptability to abrasion, or it can be an insulating material such as fluorosilicone glass.

[0091] Please see Figures 15-16 As shown, in one embodiment of the present invention, after depositing the insulating medium 231, the insulating medium 231 is planarized, for example by using a chemical mechanical polishing (CMP) process to perform non-selective grinding to planarize the insulating medium 231 and the third nitride layer 19, so that the insulating medium 231 and the protective layer 17 have the same height.

[0092] Please see Figure 13 , Figures 16-17As shown, in one embodiment of the present invention, after planarizing the insulating medium 231, a second ion is injected from the first surface 101 into the deep well region 18 between the two shallow trenches 21 to form a well region 24. The well region 24 extends from the first surface 101 into the deep well region 18. The distance between the bottom of the well region 24 and the bottom of the deep well region 18 is, for example, greater than the distance between the bottom of the shallow trenches 21 and the bottom of the deep well region 18. The type of the second ion is, for example, opposite to the type of the first ion, and the second ion is, for example, B or BF2. + Or P-type ions such as In, the second ion is implanted multiple times. In this embodiment, for example, the trap region 24 is formed by implanting the second ion four times. Specifically, during the first implantation, the implantation energy of the second ion is, for example, 100 keV-150 keV, and the implantation dose of the second ion is, for example, 3 × 10⁻⁶. 13 ions / cm 2 -4×10 13 ions / cm 2 During the second implantation, the implantation energy of the second ion is, for example, 50 keV-100 keV, and the implantation dose of the second ion is, for example, 6 × 10⁻⁶. 12 ions / cm 2 -9×10 12 ions / cm 2 During the third implantation, the implantation energy of the second ion is, for example, 20 keV-50 keV, and the implantation dose of the second ion is, for example, 3 × 10⁻⁶. 12 ions / cm 2 -5×10 12 ions / cm 2 During the fourth implantation, the implantation energy of the second ion is, for example, 20 keV-30 keV, and the implantation dose of the second ion is, for example, 6 × 10⁻⁶. 12 ions / cm 2 -7×10 12 ions / cm 2 .

[0093] Please see Figures 17-18 As shown, in one embodiment of the present invention, after forming the well region 24, the insulating medium 231 and the protective layer 17 on the first surface 101 are removed, and the remaining insulating medium 231 is defined as the shallow trench isolation structure 23. The removal of the insulating medium 231 and the protective layer 17 is performed, for example, using CMP processes or etching methods.

[0094] Please see Figure 18As shown in the figure, in an embodiment of the present application, after the shallow trench isolation structure 23 is formed, a layer of oxidation material is deposited on the first surface 101, after the oxidation material covers the first surface 101, a layer of gate material is deposited on the oxidation material, after the gate material covers the oxidation material, a photoresist is formed on the gate material by, for example, spin coating or spray coating, and the like, after the photoresist is exposed and developed, the photoresist is patterned to form a patterned photoresist layer (not shown in the figure), the patterned photoresist layer covers part of the gate material on the cavity 15, and the exposed oxidation material and gate material are etched with the patterned photoresist layer as a mask, the remaining oxidation material is defined as a gate oxide layer 25, and the remaining gate material is defined as a gate 26, and then the patterned photoresist layer is removed. The gate oxide layer 25 and the gate 26 are arranged on part of the well region 24 on the cavity 15, the material of the gate oxide layer 25 includes, for example, silicon oxide, and the like, the material of the gate 26 includes, for example, polysilicon, and the like, the thickness of the gate oxide layer 25 is, for example, 2nm-10nm, and the thickness of the gate 26 is, for example, 200nm-250nm.

[0095] Referring to Figures 18-19 As shown in the figure, in an embodiment of the present application, after the gate 26 is formed, third ions are implanted into the well regions 24 on both sides of the gate 26 from the first surface 101 to form a source light doped region 271 and a drain light doped region 281. The source light doped region 271 is located in the well region 24 between one side wall of the gate 26 and the adjacent shallow trench isolation structure 23, and the drain light doped region 281 is located in the well region 24 between the other side wall of the gate 26 and the adjacent shallow trench isolation structure 23, the type of the third ions is opposite to the type of the second ions, and the third ions are, for example, N-type ions such as P or As.

[0096] Referring to Figures 19-20As shown, in one embodiment of the present invention, after forming the source light doped region 271 and the drain light doped region 281, sidewalls 29 are formed on the first surface 101 on both sides of the gate 26 and the gate oxide layer 25. The sidewalls 29 extend from the sidewalls of the gate 26 and the gate oxide layer 25 to a portion of the source light doped region 271 and a portion of the drain light doped region 281. Specifically, a first layer of material is first deposited on the substrate 10 and the gate 26. Then, a second layer of material is deposited on the first layer of material, a third layer of material is deposited on the second layer of material, and a fourth layer of material is deposited on the third layer of material. After that, the fourth layer of material, the third layer of material, the second layer of material, and the first layer of material on the gate 26 and part of the substrate 10 are removed by processes such as dry etching or wet etching. The four layers of material on both sides of the gate 26 and the gate oxide layer 25 are retained. The retained first layer of material is defined as the first sidewall 291, the second layer of material is defined as the second sidewall 292, the third layer of material is defined as the third sidewall 293, and the fourth layer of material is defined as the fourth sidewall 294. The first sidewall 291, the second sidewall 292, the third sidewall 293, and the fourth sidewall 294 are defined as sidewall 29. The materials of the first sidewall 291 and the third sidewall 293 include, for example, silicon oxide, and the materials of the second sidewall 292 and the fourth sidewall 294 include, for example, silicon nitride. The thicknesses of the first sidewall 291, the second sidewall 292, the third sidewall 293 and the fourth sidewall 294 can be equal or unequal, depending on the actual situation.

[0097] Please see Figures 20-21 As shown, in one embodiment of the present invention, after forming the sidewall 29, a fourth ion is implanted from the first surface 101 into the source lightly doped region 271 and the drain lightly doped region 281 on both sides of the sidewall 29 to form the source heavily doped region 272 and the drain heavily doped region 282. The source lightly doped region 271 and the source heavily doped region 272 are defined as source doped region 27, and the drain lightly doped region 281 and the drain heavily doped region 282 are defined as drain doped region 28. The source heavily doped region 272 extends from the first surface 101 into the source lightly doped region 271, and the drain heavily doped region 282 extends from the first surface 101 into the drain lightly doped region 281. The fourth ion is of the same type as the third ion, for example, an N-type ion such as P or As, and the implantation energy and implantation dose of the fourth ion are greater than those of the third ion.

[0098] Please see Figures 21-22 As shown, the relative positions of the buried oxide structure 14, cavity 15, source doped region 27, and drain doped region 28 are not limited in this invention and can be selected according to actual conditions. Please refer to... Figure 21 As shown, in this embodiment, the orthogonal projection of the buried oxide structure 14 and the cavity 15 in the direction of the first surface 101 extends from the well region 24 between the source doped region 27 and the drain doped region 28 to the source doped region 27 and the drain doped region 28 on both sides. Please refer to...Figure 22 As shown in the drawings, in another embodiment of the present application, the orthographic projection of the buried oxygen structure 14 and the cavity 15 in the direction of the first surface 101 falls within the well region 24 between the source doped region 27 and the drain doped region 28.

[0099] As shown in the drawings, Figures 1-22 As shown in the drawings, in another embodiment of the present application, the orthographic projection of the buried oxygen structure 14 and the cavity 15 in the direction of the first surface 101 falls within the well region 24 between the source doped region 27 and the drain doped region 28.

[0100] In summary, the present application provides a semiconductor structure and a preparation method thereof, and a semiconductor device. By introducing a cavity in the semiconductor structure, the present application unexpectedly improves the resistivity of the substrate, reduces the loss of the substrate, and improves the isolation, noise coefficient, linearity and other performances of the semiconductor device. Moreover, the present application improves the compatibility of the SOI process and the MOS process, and reduces the preparation cost of the SOI MOS device.

[0101] The above disclosed embodiments of the present application are only used to help explain the present application. The embodiments do not describe all the details, nor limit the present application to the specific embodiments. Obviously, according to the content of the present application, many modifications and changes can be made. The present application selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can well understand and utilize the present application. The present application is limited by the claims and their full scope and equivalents.

Claims

1. A semiconductor structure, characterized by, At least comprising: a substrate comprising a first surface and a second surface arranged oppositely; a recess recessed into the substrate from the first surface, and an interface between the recess and the substrate is stepped; a buried oxide structure comprising a first buried oxide region and a plurality of second buried oxide regions, the first buried oxide region extends into the substrate from a bottom of the recess, and the second buried oxide regions extend into the substrate from part of sidewalls of the recess; an epitaxial layer arranged in the recess on the buried oxide structure; and a cavity arranged in the substrate between the epitaxial layer, the first buried oxide region and the second buried oxide regions, and a depth of the cavity is equal to a depth of the second buried oxide regions, and an atmosphere in the cavity is the same as an atmosphere when the epitaxial layer is formed.

2. The semiconductor structure of claim 1, wherein, The step comprises at least a first layer step, a second layer step and a connecting part, the first layer step is the bottom of the recess, the second layer step is arranged on both sides of the first layer step, and a surface of the first layer step is lower than a surface of the second layer step, and the surface of the second layer step is lower than the first surface, and the connecting part connects the first layer step and the second layer step.

3. The semiconductor structure of claim 2, wherein, The second buried oxide regions extend into the substrate from the connecting part, and the first buried oxide region extends into the substrate from the first layer step, and an edge of the first buried oxide region is located in the substrate under the second buried oxide regions.

4. A method of fabricating a semiconductor structure, characterized by, At least comprising the following steps: providing a substrate comprising a first surface and a second surface arranged oppositely; forming a recess in the substrate, the recess is recessed into the substrate from the first surface, and an interface between the recess and the substrate is stepped, and in a direction from the first surface to the second surface, a size of the recess decreases; forming a buried oxide structure in the substrate, the buried oxide structure comprises a first buried oxide region and a plurality of second buried oxide regions, the first buried oxide region extends into the substrate from a bottom of the recess, and the second buried oxide regions extend into the substrate from part of sidewalls of the recess close to the first buried oxide region; forming an epitaxial layer in the recess on the buried oxide structure; and forming a cavity in the substrate between the epitaxial layer, the first buried oxide region and the second buried oxide regions.

5. The preparation method according to claim 4, characterized in that, The forming of the recess comprises at least the following steps: forming a pad oxide layer on the first surface; forming a first nitride layer on the pad oxide layer; etching part of the first nitride layer, part of the pad oxide layer and part of the substrate to form a recessed part, the recessed part is recessed into the substrate from the first nitride layer; forming a second nitride layer on a bottom and sidewalls of the recessed part and the first nitride layer; and vertically etching the second nitride layer and the substrate in the recessed part, and the first nitride layer and part of the second nitride layer or the first nitride layer, the second nitride layer and part of the pad oxide layer on the first surface or the second nitride layer, the first nitride layer and part of the pad oxide layer, to retain the second nitride layer on the sidewalls of the recessed part to form the recess.

6. The production method according to claim 5, characterized by, A depth of the vertical etching is greater than a thickness of the second nitride layer, and less than a sum of thicknesses of the second nitride layer, the first nitride layer and the pad oxide layer.

7. The preparation method according to claim 4, characterized in that, oxidizing the substrate exposed in the recess to form the buried oxide structure.

8. A semiconductor device, characterized by, at least comprising: the semiconductor structure according to any one of claims 1-3; a deep well region extending from the first surface into the epitaxial layer and the substrate, and extending at least to contact the second buried oxide region; at least two shallow trench isolation structures symmetrically disposed in the deep well region on both sides of the cavity; a well region disposed in the deep well region between two adjacent shallow trench isolation structures; a gate disposed on the well region over the cavity; a source doped region disposed in the well region on one side of the gate; and a drain doped region disposed in the well region on another side of the gate. a projection of the buried oxide structure and the cavity in a direction of the first surface falls in the well region between the source doped region and the drain doped region.

9. The semiconductor device of claim 8, wherein, a projection of the buried oxide structure and the cavity in a direction of the first surface extends from the well region between the source doped region and the drain doped region to the source doped region and the drain doped region on both sides.

10. The semiconductor device of claim 8, wherein, ​

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