Semiconductor structure and forming method thereof
By forming an air gap structure in the fin structure and forming a sealing layer on both sides, the problem of germanium atom diffusion is solved, thereby improving the reliability and performance of the device.
Patent Information
- Application Number
- CN202410521621.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-26
- Publication Date
- 2025-10-31
AI Technical Summary
In existing technologies, germanium atoms in silicon-germanium fins diffuse to the substrate silicon layer during the deposition of the interlayer dielectric layer, leading to a decrease in device performance. How can this diffusion be avoided to improve device reliability?
A sacrificial layer is formed on the top surface and sidewalls of the second part of the fin structure, an air gap structure is etched, and a sealing layer is formed on both sides to isolate the liner silicon layer and the silicon-germanium fin to prevent the diffusion of germanium atoms.
By forming an air gap structure between the substrate silicon layer and the silicon-germanium fins, the isolation performance is improved, germanium atom diffusion is avoided, the reliability of the device is enhanced, and the parasitic capacitance between the gate structure and the substrate silicon layer is reduced.
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Figure CN120882076A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Technology
[0002] As the performance requirements of semiconductor integrated circuit devices increase, the miniaturization of semiconductor device cores has shown its limitations. Since the strain provided by the silicon-germanium channel can yield higher mobility, dual-fin structures (i.e., fin structures containing silicon and silicon-germanium fins for PMOS) have been used to improve device performance. The silicon-liner is crucial to fin performance; therefore, its thickness needs precise control. A thicker silicon-liner will leave silicon residue after the interlayer dielectric layer is deposited, reducing the functionality of the silicon-germanium channel. A thinner silicon-liner will generate germanium oxide during the interlayer dielectric layer deposition process, degrading device performance.
[0003] However, even with precise control of the substrate silicon layer thickness, germanium atoms in the silicon-germanium fins can diffuse into the substrate silicon layer during the deposition of the interlayer dielectric layer, forming a germanium oxide layer. Therefore, it is crucial to prevent germanium atoms in the silicon-germanium fins from diffusing into the substrate silicon layer.
[0004] Based on this, this application provides a more effective and reliable technical solution to improve the isolation performance between the substrate silicon layer and the silicon-germanium fin, prevent germanium atoms in the silicon-germanium fin from diffusing to the substrate silicon layer, and thus improve device reliability. Summary of the Invention
[0005] This application provides a semiconductor structure and a method for forming the same, which can improve the isolation performance between the substrate silicon layer and the silicon-germanium fins, prevent germanium atoms in the silicon-germanium fins from diffusing to the substrate silicon layer, and thus improve device reliability.
[0006] One aspect of this application provides a method for forming a semiconductor structure, comprising: providing a semiconductor substrate, the semiconductor substrate including mutually perpendicular x-directions and y-directions and a plurality of fin structures extending along the x-direction, the fin structure including a first portion located on the surface of the semiconductor substrate and a second portion located on the top surface of the first portion; forming a sacrificial layer on the top surface and sidewalls of the second portion of the fin structure; forming a substrate silicon layer on the surface of the sacrificial layer; etching a portion of the second portion of the fin structure and the substrate silicon layer and sacrificial layer on its surface along the y-direction to the top surface of the first portion to form a plurality of partition openings that divide the second portion into a plurality of portions along the x-direction; removing the sacrificial layer to form an air gap structure; and forming a sealing layer sealing the air gap structure on both sides of the air gap structure along the x-direction.
[0007] In some embodiments of this application, a method for forming a sealing layer that seals the air gap structure on both sides of the air gap structure along the x-direction includes: forming a sealing material layer on the semiconductor substrate that covers the isolation structure and the substrate silicon layer and fills the plurality of isolation openings, the sealing material layer extending from the isolation openings to both sides of the air gap structure along the x-direction; removing the sealing material layer located outside the two sides of the air gap structure along the x-direction, and retaining the sealing material layer located on both sides of the air gap structure along the x-direction as the sealing layer.
[0008] In some embodiments of this application, the height of the first portion is 55% to 70% of the height of the fin structure; the height of the second portion is 45% to 30% of the height of the fin structure.
[0009] In some embodiments of this application, the surface of the semiconductor substrate further includes an isolation structure located between adjacent fin structures, the top surface of which is flush with the top surface of the first portion.
[0010] In some embodiments of this application, the etching selectivity ratio for the sacrificial layer and the second portion in the etching process for removing the sacrificial layer to form the air gap structure is greater than 10.
[0011] In some embodiments of this application, the material of the sacrificial layer includes silicon germanium with a germanium atom content greater than 50%, and the material of the second part of the fin structure includes silicon germanium with a germanium atom content less than 45%.
[0012] Another aspect of this application provides a semiconductor structure, comprising: a semiconductor substrate including mutually perpendicular x and y directions and a plurality of fin structures extending along the x direction, the fin structures including a first portion located on the surface of the semiconductor substrate and a second portion located on the top surface of the first portion; an air gap structure located on the top surface and sidewall of the second portion of the fin structure; a liner silicon layer located on the surface of the air gap structure; a plurality of partition openings penetrating the second portion of the fin structure and the liner silicon layer and the air gap structure on its surface and extending along the y direction to partition the second portion into a plurality of portions along the x direction; and a sealing layer located on both sides of the air gap structure along the x direction to seal the air gap structure.
[0013] In some embodiments of this application, the height of the first portion is 55% to 70% of the height of the fin structure; the height of the second portion is 45% to 30% of the height of the fin structure.
[0014] In some embodiments of this application, the surface of the semiconductor substrate further includes an isolation structure located between adjacent fin structures, the top surface of which is flush with the top surface of the first portion.
[0015] In some embodiments of this application, the material of the second part of the fin structure includes silicon germanium with a germanium atom content of less than 45%.
[0016] This application provides a semiconductor structure and a method for forming the same, in which an air gap structure is formed between a substrate silicon layer and a silicon-germanium fin, which can improve the isolation performance between the substrate silicon layer and the silicon-germanium fin, prevent germanium atoms in the silicon-germanium fin from diffusing to the substrate silicon layer, and thus improve device reliability. Attached Figure Description
[0017] The following accompanying drawings describe in detail the exemplary embodiments disclosed in this application. The same reference numerals denote similar structures in several views of the drawings. Those skilled in the art will understand that these embodiments are non-limiting and exemplary, and the drawings are for illustrative purposes only and are not intended to limit the scope of this application. Other embodiments may similarly fulfill the inventive intent of this application. It should be understood that the drawings are not drawn to scale.
[0018] in:
[0019] Figures 1 to 17 This is a schematic diagram of each step in the method for forming a semiconductor structure according to the embodiments of this application. Detailed Implementation
[0020] The following description provides specific application scenarios and requirements for this application, intended to enable those skilled in the art to make and use the content of this application. Various partial modifications to the disclosed embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of this application. Therefore, this application is not limited to the embodiments shown, but rather to the widest scope consistent with the claims.
[0021] The technical solution of the present invention will be described in detail below with reference to the embodiments and accompanying drawings.
[0022] Figures 1 to 17 This is a schematic diagram of each step in the method for forming a semiconductor structure according to an embodiment of this application. The method for forming a semiconductor structure according to an embodiment of this application will be described in detail below with reference to the accompanying drawings.
[0023] refer to Figure 1 , Figure 2 and Figure 3 As shown, where, Figure 1 This is a top view. Figure 2 For along Figure 1 Longitudinal section view at point AA (middle dashed line). Figure 3 For along Figure 1A longitudinal cross-sectional view at the dashed line BB. A semiconductor substrate 100 is provided, the semiconductor substrate 100 including mutually perpendicular x and y directions and a plurality of fin structures 110 extending along the x direction, the fin structure 110 including a first portion 111 located on the surface of the semiconductor substrate 100 and a second portion 112 located on the top surface of the first portion 111.
[0024] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0025] The semiconductor structure described in this application embodiment is a FinFET device with a dual-fin structure. Therefore, the fin structure 110 of this application includes a first portion 111 located on the surface of the semiconductor substrate 100 and a second portion 112 located on the top surface of the first portion 111. The first portion 111 is made of silicon, and can also be referred to as a silicon fin; the second portion 112 is made of silicon-germanium (specifically, the second portion 112 of the fin structure 110 is made of silicon-germanium with a germanium atomic content of less than 45%), and can also be referred to as a silicon-germanium fin.
[0026] In some embodiments of this application, the number of fin structures 110 is multiple. For the sake of brevity, only three fin structures 110 are shown here as an example.
[0027] In some embodiments of this application, the method for forming the fin structure 110 is, for example, to provide a silicon substrate; to epitaxially grow a silicon-germanium layer on the surface of the silicon substrate; and to etch the silicon-germanium layer into the silicon substrate to form the fin structure 110 having silicon-germanium fins and silicon fins.
[0028] In some embodiments of this application, the height of the first portion 111 is 55% to 70% of the height of the fin structure 110; and the height of the second portion 112 is 45% to 30% of the height of the fin structure 110.
[0029] In some embodiments of this application, reference is made to Figure 2 As shown, the surface of the semiconductor substrate 100 also includes an isolation structure 120 located between adjacent fin structures 110, the top surface of the isolation structure 120 being flush with the top surface of the first portion 111. The material of the isolation structure 120 includes silicon oxide or silicon nitride, etc. The isolation structure 120 is used to isolate adjacent fin structures 110.
[0030] refer to Figure 4 , Figure 5 and Figure 6 As shown, where, Figure 4 This is a top view. Figure 5 For along Figure 4 Longitudinal section view at point AA (middle dashed line). Figure 6 For along Figure 4 Longitudinal cross-section at the dashed line BB. A sacrificial layer 130a is formed on the top surface and sidewall of the second part 112 of the fin structure 110.
[0031] In some embodiments of this application, the method of forming the sacrificial layer 130a includes an epitaxial growth process using the second portion 112 of the fin structure 110 as a substrate.
[0032] In some embodiments of this application, the material of the sacrificial layer 130a includes silicon germanium with a germanium atom content of more than 50%.
[0033] In some embodiments of this application, the thickness of the sacrificial layer 130a is 10 to 30 angstroms, for example, 15 angstroms, 20 angstroms or 25 angstroms.
[0034] refer to Figure 7 , Figure 8 and Figure 9 As shown, where, Figure 7 This is a top view. Figure 8 For along Figure 7 Longitudinal section view at point AA (middle dashed line). Figure 9 For along Figure 7 The longitudinal cross-sectional view at the dashed line BB. A silicon-liner 140 is formed on the surface of the sacrificial layer 130a. The addition of a sacrificial layer 130a improves the process window of the silicon-liner 140.
[0035] In some embodiments of this application, the method for forming the substrate silicon layer 140 includes epitaxial growth process or chemical vapor deposition process, etc.
[0036] In some embodiments of this application, the material of the liner silicon layer 140 includes silicon.
[0037] In some embodiments of this application, the thickness of the substrate silicon layer 140 is 10 to 30 angstroms, for example, 15 angstroms, 20 angstroms, or 25 angstroms.
[0038] refer to Figure 10 and Figure 11 As shown, where, Figure 10 This is a top view. Figure 11 For along Figure 10Longitudinal cross-section at the dashed line BB. The second part 112 of the fin structure 110 and its surface of the substrate silicon layer 140 and sacrificial layer 130a are etched along the y-direction to the top surface of the first part 111 to form a plurality of partition openings 150 that divide the second part 112 into a plurality of parts along the x-direction.
[0039] refer to Figure 10 and Figure 11 As shown, after the second part 112 of the fin structure 110 and the liner silicon layer 140 and sacrificial layer 130a on its surface are etched away, a portion of the first part 111 and the isolation structure 120 are exposed.
[0040] In FinFET device manufacturing, different active regions are typically defined by removing portions of the fin structure using fin cutting processes (i.e., fin cut processes, including ARV and ARH). ARV (active region vertical) represents a cut in the vertical direction (i.e., the y-direction in this application), and ARH (active region horizontal) represents a cut in the horizontal direction (i.e., the x-direction in this application). ARV and ARH can divide the fin structure on the semiconductor substrate into several active regions in a grid pattern. In the technical solution of this application, the process of etching a portion of the second part 112 of the fin structure 110 along the y-direction, along with its surface substrate silicon layer 140 and sacrificial layer 130a, up to the top surface of the first part 111, to form several partition openings 150 that divide the second part 112 into several portions along the x-direction, is the ARV process. These partition openings 150 divide the second part 112 of the several fin structures 110 into several portions, i.e., several active regions, in the x-direction.
[0041] It should be noted that, for the sake of brevity, this application only shows the two partition openings 150 and the active region portion located between the two partition openings 150.
[0042] refer to Figure 12 and Figure 13 As shown, the sacrificial layer 130a is removed to form an air gap structure 130.
[0043] In some embodiments of this application, the etching selectivity ratio for the sacrificial layer 130a and the second portion 112 in the etching process for removing the sacrificial layer 130a to form the air gap structure 130 is greater than 10. This avoids damage to the fin structure 110.
[0044] In some embodiments of this application, the etching process for removing the sacrificial layer 130a to form the air gap structure 130 is wet etching.
[0045] refer to Figures 14 to 17As shown, a sealing layer 160 is formed on both sides of the air gap structure 130 along the x-direction to seal the air gap structure 130.
[0046] refer to Figure 14 , Figure 15 and Figure 16 As shown, where, Figure 14 This is a top view. Figure 15 For along Figure 14 Longitudinal section view at point AA (middle dashed line). Figure 16 For along Figure 14 A longitudinal cross-sectional view at the dashed line BB. A sealing material layer 160a is formed on the semiconductor substrate 100, covering the isolation structure 120 and the liner silicon layer 140 and filling the plurality of isolation openings 150. The sealing material layer 160a extends from the isolation openings 150 to both sides of the air gap structure 130 along the x-direction.
[0047] In some embodiments of this application, the method for forming the sealing material layer 160a includes a flowable chemical vapor deposition (FCVD) process. (Reference) Figure 16 As shown, during the FCVD process, due to the fluidity of the sealing material layer 160a, the sealing material layer 160a can extend from the partition opening 150 to both sides of the air gap structure 130 along the x-direction, thereby sealing the air gap structure 130. The extension distance of the sealing material layer 160a can be controlled by controlling the process parameters of the FCVD process.
[0048] refer to Figure 17 As shown, the sealing material layer 160a located on both sides of the air gap structure 130 along the x direction is removed, and the sealing material layer 160a located on both sides of the air gap structure 130 along the x direction is retained to become the sealing layer 160.
[0049] In some embodiments of this application, the material of the sealing layer 160 includes silicon oxide or silicon nitride, etc.
[0050] In the technical solution of this application, an air gap structure 130 is formed between the substrate silicon layer 140 and the second portion 112 of the fin structure 110. This improves the isolation performance between the substrate silicon layer 140 and the second portion 112 of the fin structure 110, preventing germanium atoms in the second portion 112 of the fin structure 110 from diffusing to the substrate silicon layer 140, thereby improving device reliability. The air gap structure 130 can also reduce the parasitic capacitance between the gate structure and the substrate silicon layer.
[0051] In some embodiments of this application, the method for forming the semiconductor structure further includes: forming a gate structure (not shown in the figure) extending in the y direction and covering the isolation structure 120 and the fin structure 110 on the semiconductor substrate 100; and forming an interlayer dielectric layer covering the gate structure, the isolation structure, and the fin structure on the semiconductor substrate 100.
[0052] This application provides a method for forming a semiconductor structure, in which an air gap structure is formed between a substrate silicon layer and a silicon-germanium fin, which can improve the isolation performance between the substrate silicon layer and the silicon-germanium fin, prevent germanium atoms in the silicon-germanium fin from diffusing to the substrate silicon layer, and thus improve device reliability.
[0053] Embodiments of this application also provide a semiconductor structure, referencing Figure 10 , Figure 12 and Figure 17 As shown, the system includes: a semiconductor substrate 100, the semiconductor substrate 100 including mutually perpendicular x and y directions and a plurality of fin structures 110 extending along the x direction, the fin structure 110 including a first portion 111 located on the surface of the semiconductor substrate 100 and a second portion 112 located on the top surface of the first portion 111; an air gap structure 130 located on the top surface and sidewall of the second portion 112 of the fin structure 110; a liner silicon layer 140 located on the surface of the air gap structure 130; a plurality of partition openings 150 penetrating the second portion 112 of the fin structure 110 and the liner silicon layer 140 and the air gap structure 130 on its surface and extending along the y direction to partition the second portion 112 into a plurality of portions along the x direction; and a sealing layer 160 located on both sides of the air gap structure 130 along the x direction to seal the air gap structure 130.
[0054] In some embodiments of this application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium arsenide phosphide or gallium indium phosphide; or (iv) combinations thereof.
[0055] The semiconductor structure described in this application embodiment is a FinFET device with a dual-fin structure. Therefore, the fin structure 110 of this application includes a first portion 111 located on the surface of the semiconductor substrate 100 and a second portion 112 located on the top surface of the first portion 111. The first portion 111 is made of silicon, and can also be referred to as a silicon fin; the second portion 112 is made of silicon-germanium (specifically, the second portion 112 of the fin structure 110 is made of silicon-germanium with a germanium atomic content of less than 45%), and can also be referred to as a silicon-germanium fin.
[0056] In some embodiments of this application, the number of fin structures 110 is multiple. For the sake of brevity, only three fin structures 110 are shown here as an example.
[0057] In some embodiments of this application, the height of the first portion 111 is 55% to 70% of the height of the fin structure 110; and the height of the second portion 112 is 45% to 30% of the height of the fin structure 110.
[0058] In some embodiments of this application, reference is made to Figure 12 As shown, the surface of the semiconductor substrate 100 also includes an isolation structure 120 located between adjacent fin structures 110, the top surface of the isolation structure 120 being flush with the top surface of the first portion 111. The material of the isolation structure 120 includes silicon oxide or silicon nitride, etc. The isolation structure 120 is used to isolate adjacent fin structures 110.
[0059] In some embodiments of this application, the thickness of the air gap structure 130 is 10 to 30 angstroms, for example, 15 angstroms, 20 angstroms or 25 angstroms.
[0060] In some embodiments of this application, the material of the liner silicon layer 140 includes silicon.
[0061] In some embodiments of this application, the thickness of the substrate silicon layer 140 is 10 to 30 angstroms, for example, 15 angstroms, 20 angstroms, or 25 angstroms.
[0062] In FinFET device manufacturing, different active regions are typically defined by removing portions of the fin structure using fin cutting processes (i.e., fin cut processes, including ARV and ARH). ARV (active region vertical) represents a cut in the vertical direction (i.e., the y-direction in this application), and ARH (active region horizontal) represents a cut in the horizontal direction (i.e., the x-direction in this application). ARV and ARH can divide the fin structure on the semiconductor substrate into several active regions in a grid pattern. In the technical solution of this application, the process of etching a portion of the second part 112 of the fin structure 110 along the y-direction, along with its surface substrate silicon layer 140 and sacrificial layer 130a, up to the top surface of the first part 111, to form several partition openings 150 that divide the second part 112 into several portions along the x-direction, is the ARV process. These partition openings 150 divide the second part 112 of the several fin structures 110 into several portions, i.e., several active regions, in the x-direction.
[0063] It should be noted that, for the sake of brevity, this application only shows the two partition openings 150 and the active region portion located between the two partition openings 150.
[0064] In some embodiments of this application, the material of the sealing layer 160 includes silicon oxide or silicon nitride, etc.
[0065] In the technical solution of this application, an air gap structure 130 is formed between the substrate silicon layer 140 and the second portion 112 of the fin structure 110. This improves the isolation performance between the substrate silicon layer 140 and the second portion 112 of the fin structure 110, preventing germanium atoms in the second portion 112 of the fin structure 110 from diffusing to the substrate silicon layer 140, thereby improving device reliability. The air gap structure 130 can also reduce the parasitic capacitance between the gate structure and the substrate silicon layer.
[0066] In some embodiments of this application, the semiconductor structure further includes: a gate structure (not shown in the figure) extending along the y-direction on the semiconductor substrate 100 and covering the isolation structure 120 and the fin structure 110; and an interlayer dielectric layer on the semiconductor substrate 100 covering the gate structure, the isolation structure, and the fin structure.
[0067] This application provides a semiconductor structure and a method for forming the same, in which an air gap structure is formed between a substrate silicon layer and a silicon-germanium fin, which can improve the isolation performance between the substrate silicon layer and the silicon-germanium fin, prevent germanium atoms in the silicon-germanium fin from diffusing to the substrate silicon layer, and thus improve device reliability.
[0068] In summary, after reading this application, those skilled in the art will understand that the foregoing application content is presented by way of example only and is not restrictive. Although not explicitly stated herein, those skilled in the art will understand that this application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of this application.
[0069] It should be understood that the term "and / or" as used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it may be directly connected or coupled to the other element, or there may be an intermediate element.
[0070] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it may be directly on that other element, or there may be intermediate elements present. Conversely, the term "directly" means without intermediate elements. It should also be understood that the terms "comprising," "including," "including," or "comprises," as used in this application, indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.
[0071] It should also be understood that although the terms first, second, third, etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, without departing from the teachings of this application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference signs denote the same elements throughout the specification.
[0072] Furthermore, this application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or perspective views. Therefore, differences from the illustrated shapes are foreseeable due to factors such as manufacturing techniques and / or tolerances. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in shape caused, for example, by manufacturing processes. For instance, etched areas shown as rectangular typically have circular or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to illustrate the actual shape of the regions of the device, nor are they intended to limit the scope of the exemplary embodiments.
Claims
1. A method for forming a semiconductor structure, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate including mutually perpendicular x-direction and y-direction and a plurality of fin structures extending along the x-direction, the fin structures including a first portion located on the surface of the semiconductor substrate and a second portion located on the top surface of the first portion; A sacrificial layer is formed on the top surface and sidewall of the second part of the fin structure; A substrate silicon layer is formed on the surface of the sacrificial layer; The second part of the fin structure and its surface liner silicon layer and sacrificial layer are etched along the y direction to the top surface of the first part to form a number of partition openings that divide the second part into several parts along the x direction; The sacrificial layer is removed to form an air gap structure; A sealing layer is formed on both sides of the air gap structure along the x-direction to seal the air gap structure.
2. The method for forming a semiconductor structure as described in claim 1, characterized in that, A method for forming a sealing layer on both sides of the air gap structure along the x-direction to seal the air gap structure includes: A sealing material layer is formed on the semiconductor substrate, covering the isolation structure and the edge silicon layer and filling the plurality of isolation openings, the sealing material layer extending from the isolation openings to both sides of the air gap structure along the x-direction; The sealing material layer located outside the two sides of the air gap structure along the x direction is removed, and the sealing material layer located in the two sides of the air gap structure along the x direction is retained as the sealing layer.
3. The method for forming a semiconductor structure as described in claim 1, characterized in that, The height of the first part is 55% to 70% of the height of the fin structure; the height of the second part is 45% to 30% of the height of the fin structure.
4. The method for forming a semiconductor structure as described in claim 1, characterized in that, The semiconductor substrate surface also includes an isolation structure located between adjacent fin structures, the top surface of which is flush with the top surface of the first portion.
5. The method for forming a semiconductor structure as described in claim 1, characterized in that, In the etching process for removing the sacrificial layer to form the air gap structure, the etching selectivity ratio between the sacrificial layer and the second part is greater than 10.
6. The method for forming a semiconductor structure as described in claim 1, characterized in that, The material of the sacrificial layer includes silicon germanium with a germanium atom content of more than 50%, and the material of the second part of the fin structure includes silicon germanium with a germanium atom content of less than 45%.
7. A semiconductor structure, characterized in that, include: A semiconductor substrate, the semiconductor substrate including mutually perpendicular x-directions and y-directions and a plurality of fin structures extending along the x-direction, the fin structures including a first portion located on the surface of the semiconductor substrate and a second portion located on the top surface of the first portion; An air gap structure is located on the top surface and sidewall of the second part of the fin structure; A liner silicon layer is located on the surface of the air gap structure; Several openings are provided, penetrating the second part of the fin structure and its surface liner silicon layer and air gap structure, and extending along the y direction to divide the second part into several parts along the x direction; A sealing layer is located on both sides of the air gap structure along the x-direction to seal the air gap structure.
8. The semiconductor structure as described in claim 7, characterized in that, The height of the first part is 55% to 70% of the height of the fin structure; the height of the second part is 45% to 30% of the height of the fin structure.
9. The method for forming a semiconductor structure as described in claim 7, characterized in that, The semiconductor substrate surface also includes an isolation structure located between adjacent fin structures, the top surface of which is flush with the top surface of the first portion.
10. The semiconductor structure as claimed in claim 7, characterized in that, The material of the second part of the fin structure includes silicon germanium with a germanium atom content of less than 45%.