Multi-finger GGNMOS device, manufacturing method and chip

Abstract

The invention provides a multi-finger GGNMOS device, a manufacturing method and a chip, and belongs to the technical field of semiconductor integrated circuits. The multi-finger GGNMOS device comprises a substrate, a body region and a substrate interface which are formed on the substrate, and a plurality of source regions, a plurality of drain regions and a plurality of grids which are formed on the surface of the body region, the source regions, the grids and the substrate interface are all grounded, the source regions, the drain regions and the grids respectively form a plurality of GGNMOS structures, and the GGNMOS structures are connected with the substrate interface. A deep trench isolation region is arranged between every two adjacent source regions and drain regions, and the depth of the deep trench isolation region close to the middle of the substrate is larger than that of the deep trench isolation regions close to the two ends of the substrate. According to the invention, a deep trench isolation region is designed between each source region and each drain region, the source end partial voltage is reduced, and the turn-on voltage of the device is increased, so that the turn-on voltage of the middle and peripheral GGNMs is balanced, the problem of non-uniform turn-on of the multi-finger device is improved, and the middle GGNMs are prevented from being burnt down due to overlarge current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit technology, specifically to a multi-finger GGNMOS device, a method for manufacturing a multi-finger GGNMOS device, and a chip. Background Technology

[0002] With advancements in manufacturing processes, the design challenges of ESD (Electro-Static Discharge) devices have become increasingly significant. The introduction of ultra-shallow junctions, silicides, and epitaxial layers negatively impacts ESD performance. In ultra-deep submicron CMOS processes, due to the low breakdown voltages of thin gate oxides and source / drain components, effective on-chip ESD protection circuitry must be added to clamp over-impact voltages on the device's gate oxides and source / drain components. In ultra-deep submicron processes, NMOS devices are typically used as on-chip ESD protection devices. The most common device for chip-level ESD protection is ESD-NMOS, which is mainly divided into two categories: GGNMOS (Grounded Gate NMOS) and GCNMOS (Gate-coupled NMOS), with GGNMOS being the most prevalent.

[0003] Existing multi-finger GGNMOS devices consist of multiple GGNMOS structures with grounded gates and elongated drains. The internal interface (Bulk) of the device is separated from the substrate by STI (Shallow Trench Isolation). The uniformity of turn-on of each GGNMOS in a multi-finger GGNMOS device significantly affects device performance. In traditional multi-finger GGNMOS devices, the finger near the middle turns on earlier due to the higher voltage division at the source terminal, which is farther from the bulk terminal. This uneven turn-on results in the middle GGNMOS being subjected to excessive current and easily burning out. Summary of the Invention

[0004] To address the aforementioned technical deficiencies, this invention provides a multi-finger GGNMOS device and its manufacturing method.

[0005] The multi-finger GGNMOS device provided by the present invention includes: a substrate, a body region and a substrate interface formed on the substrate, and multiple source regions, multiple drain regions and multiple gates formed on the surface of the body region. The multiple source regions, multiple gates and the substrate interface are all grounded. The multiple source regions, multiple drain regions and multiple gates respectively constitute multiple GGNMOS structures. A deep trench isolation region is provided between every two adjacent source regions and drain regions. The depth of the deep trench isolation region near the middle of the substrate is greater than the depth of the deep trench isolation region near the two ends of the substrate.

[0006] In this embodiment of the invention, the upper end of the deep trench isolation zone is in close contact with the source region, and the lower end of the deep trench isolation zone extends towards the bottom of the body region.

[0007] In this embodiment of the invention, the depth of the deep trench isolation zone is less than the depth of the body zone, or greater than the depth of the body zone.

[0008] In this embodiment of the invention, the depth of the deep trench isolation region in the multiple GGNMOS structures decreases sequentially from the middle of the substrate to both ends of the substrate.

[0009] In this embodiment of the invention, the width of the upper end of the deep trench isolation zone is greater than the width of the lower end, and the shape of the deep trench isolation zone is wedge-shaped or inverted trapezoidal.

[0010] In this embodiment of the invention, a shallow trench isolation region is provided between the substrate interface and the source region near the edge of the substrate, and the depth of the shallow trench isolation region is less than the depth of the deep trench isolation region between the source region and the drain region near the edge of the substrate.

[0011] In this embodiment of the invention, the material filling the deep trench isolation region is silicon oxide or undoped silicon.

[0012] The present invention also provides a method for manufacturing the above-mentioned multi-finger GGNMOS device, comprising: Multiple deep trenches are formed in the substrate, and the depth of the deep trenches near the middle of the substrate is greater than the depth of the deep trenches near the two ends of the substrate. Multiple deep trenches are filled with a medium material to form multiple deep trench isolation zones; A bulk region is formed in the substrate, such that multiple deep trench isolation regions are located within the bulk region; Multiple gates are formed on the surface of the body region; Source and drain regions are formed on both sides of each deep trench isolation region, and substrate interfaces are formed at both ends of the substrate.

[0013] In this embodiment of the invention, the manufacturing method of the multi-finger GGNMOS device further includes: A shallow trench is formed in the region between the source region and the substrate interface near the edge of the substrate; A medium material is filled into the shallow trench to form a shallow trench isolation zone.

[0014] In this embodiment of the invention, a plurality of deep trenches are formed in the substrate, including: Multiple deep trenches are etched at corresponding locations using photolithography and etching processes, with the depth of the trenches decreasing sequentially from the middle of the substrate to both ends.

[0015] In this embodiment of the invention, a dielectric material is filled into multiple deep trenches to form multiple deep trench isolation zones, including: Multiple deep trenches are filled with silicon oxide or undoped silicon, and the filling material on the surface of the deep trenches is smoothed using a chemical mechanical polishing process to form multiple deep trench isolation zones.

[0016] In this embodiment of the invention, forming a body region in the substrate includes: A sacrificial oxide layer is grown on the substrate surface, and the bulk region is defined using photolithography. Ions are implanted into the bulk region to form the bulk region.

[0017] In this embodiment of the invention, a plurality of gates are formed on the surface of the body region, including: A layer of polysilicon is deposited on the surface of the bulk region and etched to form multiple polysilicon gates.

[0018] In this embodiment of the invention, a source region and a drain region are formed on both sides of each deep trench isolation region, and a substrate interface is formed at both ends of the substrate, including: An oxide layer and a silicon nitride layer are deposited on a substrate with multiple gates, and etched to form sidewalls on both sides of each gate. The source and drain regions are defined on both sides of each deep trench isolation region using the sidewalls, and the substrate interface regions are defined at both ends of the substrate. N-type ions are injected into the source and drain regions to form the source and drain regions; P-type ions are implanted into the region of the substrate interface to form the substrate interface.

[0019] In this embodiment of the invention, the manufacturing method of the multi-finger GGNMOS device further includes: After forming the source region, drain region, and substrate interface, a silicide barrier layer is formed on a portion of the surface of the gate and drain regions to elongate the drain region; Form contact lines and metal interconnects that connect to the substrate interface, source region, and gate.

[0020] This invention combines deep trench isolation technology, designing a deep trench isolation region between each source and drain region of a multi-finger GGNMOS device. The deep trench isolation region is close to the source terminal, reducing the voltage drop at the source terminal and increasing the device's turn-on voltage. The deep trench isolation region located in the middle finger is deeper, while the deep trench isolation region located in the outer fingers is shallower. This balances the turn-on voltage between the middle and outer fingers, improving the uneven turn-on problem of multi-finger devices and preventing the middle finger from burning out due to excessive current.

[0021] Other features and advantages of the technical solution of the present invention will be described in detail in the following detailed embodiments section. Attached Figure Description

[0022] The accompanying drawings, which are included to provide a further understanding of the invention and form part of this invention, illustrate exemplary embodiments of the invention and are used to explain the invention, but do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the structure of an existing multi-finger GGNMOS device; Figure 2 This is a schematic diagram of the structure of the multi-finger GGNMOS device provided in an embodiment of the present invention; Figure 3 This diagram illustrates the current conduction path of the intermediate GGNMOS in a multi-finger GGNMOS device during avalanche breakdown, as provided in an embodiment of the present invention. Figure 4 This is a flowchart of a method for manufacturing a multi-finger GGNMOS device according to an embodiment of the present invention; Figure 5 This is a schematic diagram of the shallow trench isolation zone formed in the manufacturing method steps provided in the embodiments of the present invention; Figure 6 , Figure 7 , Figure 8 This is a schematic diagram of the structure of the deep trench isolation zone formed in the manufacturing method steps provided in the embodiments of the present invention; Figure 9 This is a schematic diagram of the structure of the body region formed in the manufacturing method steps provided in the embodiments of the present invention; Figure 10 This is a schematic diagram of the gate structure formed in the manufacturing method steps provided in the embodiments of the present invention; Figure 11 This is a schematic diagram of the source region, drain region, and substrate interface formed in the manufacturing method steps provided in the embodiments of the present invention; Figure 12 This is a schematic diagram of the contact line and metal connection formed in the manufacturing method steps provided in the embodiments of the present invention.

[0023] Explanation of reference numerals in the attached figures 10-Substrate, 11-Body region, 12-Source region, 13-Drain region, 14-Gate, 15-Substrate interface 16-Deep trench isolation zone, 17-Shallow trench isolation zone, 18-Silicide barrier layer, 19-Contact line. Detailed Implementation

[0024] To make the technical solutions and advantages of the embodiments of the present invention clearer, the exemplary embodiments of the present invention will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not an exhaustive list of all embodiments. It should be noted that, unless otherwise specified, the embodiments and features in the embodiments of the present invention can be combined with each other.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0026] In this invention, unless otherwise explicitly specified and limited, the terms "connected," "linked," and "interlocked" should be interpreted broadly, referring to direct connection or indirect connection through an intermediate medium, or the internal connection of two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of these terms in this invention according to the specific circumstances.

[0027] Figure 1 This is a schematic diagram of an existing multi-finger GGNMOS device. (Example:) Figure 1As shown, this multi-finger GGNMOS device includes: a substrate (Psub), a body region (PW) and a substrate interface (P+, Bulk) on the substrate, and multiple source regions (N+, Source), multiple drain regions (N+, Drain), and multiple gates (Poly, Gate) on the surface of the body region. The substrate interface (P+, Bulk), source regions (N+, Source), and gates (Poly, Gate) are all connected to ground via contact lines. The device comprises multiple GGNMOS structures consisting of grounded gates and elongated drains, and the internal components of the device are separated from the substrate interface (Bulk) by STI (Shallow Trench Isolation). The uniformity of the turn-on of each GGNMOS in the multi-finger GGNMOS device significantly affects the device's performance. In existing multi-finger GGNMOS devices, the GGNMOS structures closer to the center have a higher voltage division due to the greater distance between the source and the bulk terminal, resulting in a relatively lower turn-on voltage and earlier turn-on. Conversely, the GGNMOS structures on the periphery have a lower voltage division due to the greater distance between the source and the bulk terminal, resulting in a relatively higher turn-on voltage and later turn-on. This uneven turn-on of the GGNMOS structures leads to uneven power-on. During electrostatic discharge (ESD), not all GGNMOS structures can be fully turned on, causing the central GGNMOS to withstand excessive current and easily burn out.

[0028] To address the aforementioned issues, this invention provides a multi-finger GGNMOS device. It incorporates Deep Trench Isolation (DTI) technology into the traditional GGNMOS structure, designing a deep trench isolation region between each source and drain region. This deep trench isolation region is positioned close to the source terminal, reducing voltage drop at the source and increasing the device's turn-on voltage. The deep trench isolation region in the middle finger is deeper, while the deep trench isolation regions in the outer fingers are shallower. This balances the turn-on voltage between the middle and outer fingers, improving the uneven turn-on performance of the multi-finger and preventing the middle finger from burning out due to excessive current.

[0029] Figure 2 This is a schematic diagram of the structure of the multi-finger GGNMOS device provided in an embodiment of the present invention. Figure 2As shown, the GGNMOS device provided in this embodiment includes: a substrate 10, a body region 11, a substrate interface 15, multiple source regions 12, multiple drain regions 13, and multiple gates 14. The body region 11 is formed in the substrate 10, the substrate interface 15 is formed on the surfaces at both ends of the substrate 10, and the multiple source regions 12, multiple drain regions 13, and multiple gates 14 are formed on the surface of the body region 11. The substrate interface 15, source regions 12, and gates 14 are connected to ground via contact lines 19 and metal interconnects. An adjacent source region 12, a drain region 13, and a gate 14 constitute a GGNMOS structure, and multiple source regions 12, multiple drain regions 13, and multiple gates 14 respectively constitute multiple GGNMOS structures. A deep trench isolation region 16 is provided between every two adjacent source regions 12 and drain regions 13, and the depth of the deep trench isolation region 16 near the middle of the substrate 10 is greater than the depth of the deep trench isolation region 16 near the ends of the substrate 10.

[0030] In a preferred embodiment, the upper end of the deep trench isolation region 16 is close to the source region 12, and the lower end of the deep trench isolation region 16 extends towards the bottom of the body region 11. The depth of the deep trench isolation region 16 is less than the depth of the body region 11.

[0031] In other embodiments, the upper end of the deep trench isolation region 16 may be connected to the source region 12; or, the upper end of the deep trench isolation region 16 may have a certain gap with the source region 12, the gap width between the upper end of the deep trench isolation region 16 and the source region 12 being smaller than the gap width between the upper end of the deep trench isolation region 16 and the drain region 13. In other embodiments, the depth of the deep trench isolation region 16 can be determined according to actual needs. The depth of the deep trench isolation region 16 may be the same as the depth of the body region 11, or the deep trench isolation region 16 may extend into the substrate 10 below the body region 11, that is, the depth of the deep trench isolation region 16 is greater than the depth of the body region 11.

[0032] In this embodiment, the depth of the deep trench isolation region 16 in the multiple GGNMOS structures decreases sequentially from the middle of the substrate 10 to both ends of the substrate 10. That is, the deep trench isolation region in the GGNMOS structure located in the middle of the substrate is the deepest, the deep trench isolation region 16 in the GGNMOS structure located between the middle and both ends of the substrate is shallower, and the deep trench isolation region 16 in the GGNMOS structure located at both ends of the substrate is the shallowest.

[0033] As described in the background section, in traditional multi-finger GGNMOS devices, the GGNMOS closer to the center has a higher voltage division due to the greater distance between the Source (N+) and Bulk (P+) terminals, resulting in a relatively lower turn-on voltage and earlier turn-on. Conversely, the GGNMOS structures on the periphery have a lower voltage division due to the closer distance between the Source and Bulk terminals, resulting in a relatively higher turn-on voltage and later turn-on. This leads to uneven turn-on among the GGNMOS devices. Based on this, the present invention designs a deep trench isolation region between each source region and each drain region. Figure 3 This illustrates the current conduction path of the intermediate GGNMOS in the multi-finger GGNMOS device of the present invention during avalanche breakdown. For example... Figure 3 As shown, the deep trench isolation region in the intermediate GGNMOS increases the distance L1 from the drain (Drain, N+) to the source (Source, N+) in the avalanche breakdown current conduction path, while the distance L2 from the source (Source, N+) to the substrate interface (Bulk, P+) remains unchanged. This reduces the voltage division between the source and body PN junctions of the intermediate GGNMOS, making it more difficult for the PN junction at the PW / Source end of the intermediate GGNMOS to reach the forward turn-on voltage. This makes it harder for the N+ / PW / N+ transistors to turn on, thereby increasing the turn-on voltage of the intermediate GGNMOS. The voltage reduction is greatest in the intermediate GGNMOS, relatively smaller between the intermediate and the two ends, and smallest at the two ends. This balances the turn-on voltage between the intermediate GGNMOS and the peripheral GGNMOS, improving the uneven turn-on problem of multi-finger GGNMOS and preventing the intermediate finger from burning out due to excessive current.

[0034] Furthermore, the multi-finger GGNMOS device of the present invention allows designers to control the magnitude of the turn-on voltage by adjusting the depth of each deep trench isolation region 16. This allows for adjustment of the device's turn-on voltage, for example, by reducing the device's turn-on voltage, to release electrostatic current as early as possible, without affecting the performance of other devices that also use the body region (PW) and without changing the GGNMOS device's holding voltage.

[0035] In an optional embodiment, the upper width of the deep trench isolation region 16 is greater than the lower width, and the shape of the deep trench isolation region is wedge-shaped or inverted trapezoidal. The material filling the deep trench isolation region 16 can be silicon oxide or undoped silicon.

[0036] In an optional embodiment, a shallow trench isolation region 17 is provided between the substrate interface 15 and the source region 12 near the edge of the substrate. The depth of the shallow trench isolation region 17 is less than the depth of the deep trench isolation region 16 between the source region and the drain region near the edge of the substrate.

[0037] In an alternative embodiment, a silicide barrier layer 18 (SAB) is provided on a portion of the surface of the gate 14 and the drain region 13 to elongate the drain region (drain end), which helps carriers flow into the device and out through the parasitic transistor in the body.

[0038] This invention also provides a method for manufacturing the aforementioned multi-finger GGNMOS device. For example... Figure 4 As shown, the manufacturing method of the multi-finger GGNMOS device provided in this embodiment includes the following steps: S401, multiple deep trenches are formed in the substrate, wherein the depth of the deep trenches near the middle of the substrate is greater than the depth of the deep trenches near the two ends of the substrate. S402, multiple deep trenches are filled with dielectric material to form multiple deep trench isolation zones; S403 forms a bulk region in the substrate, so that multiple deep trench isolation regions are located within the bulk region; S404, multiple gates are formed on the surface of the body region; S405 forms source and drain regions on both sides of each deep trench isolation region and substrate interfaces at both ends of the substrate.

[0039] In an optional embodiment, the method further includes: forming a shallow trench in the region between the source region and the substrate interface near the edge of the substrate; filling the shallow trench with a dielectric material to form a shallow trench isolation region. Before step S401, a base oxide layer and silicon nitride are sequentially grown on the substrate 10, and shallow trenches are etched at both ends of the substrate using photolithography and etching processes. The shallow trenches are then filled with oxide to form a shallow trench isolation region. Figure 5 Shallow trench isolation zone 17 is shown.

[0040] In a specific embodiment, in steps S401 and S402 above, a first set of deep trenches is etched near both ends of the substrate using photolithography and etching processes. The depth of the first set of deep trenches is slightly greater than the depth of the shallow trench isolation region 17. Then, silicon oxide or undoped silicon is filled into the first set of deep trenches to form a structure like... Figure 6 The first group of deep trench isolation zones 16 is shown.

[0041] Next, in such Figure 6 A second set of deep trenches is etched inside the first set of deep trench isolation regions 16, as shown. The depth of the second set of deep trenches is slightly greater than the depth of the first set of deep trench isolation regions 16. Then, silicon oxide or undoped silicon is filled into the second set of deep trenches to form a structure like... Figure 7 The second group of deep trench isolation zones 16 is shown.

[0042] Next, in such Figure 7A third set of deep trenches is etched inside the second set of deep trench isolation regions 16, as shown. The depth of the third set of deep trenches is slightly greater than the depth of the second set of deep trench isolation regions 16. Then, silicon oxide or undoped silicon is filled into the third set of deep trenches, meaning the depth of the multiple deep trenches decreases sequentially from the center of the substrate to both ends. Finally, a chemical mechanical polishing process is used to smooth the filler on the surface of each deep trench, forming a... Figure 8 The multiple deep trench isolation zones 16 are shown.

[0043] In a specific embodiment, the method for forming the body region in step S403 above is as follows: a sacrificial oxide layer is grown on the surface of the substrate 10 with multiple deep trench isolation regions 16 (the purpose is to reduce the ion tunneling effect in the subsequent ion implantation process), and then the body region is defined by photolithography. P-type ions are implanted in the body region to form a structure as shown in the figure. Figure 9 The body region 11 is shown. Multiple deep trench isolation zones 16 are located within the body region 11.

[0044] In a specific embodiment, in step S404 above, a layer of polysilicon is deposited on the surface of the body region 11 and etched to form a layer as shown in the figure. Figure 10 The polysilicon gate 14 shown.

[0045] In a specific embodiment, in step S405 above, a source region and a drain region are formed on both sides of each deep trench isolation region, and a substrate interface is formed at both ends of the substrate. Specifically, the process is as follows: First, an oxide layer and a silicon nitride layer are deposited on the substrate with the gate, and etched to form sidewalls on both sides of the gate 14 (not shown in the attached figure); then, the sidewalls are used to define the source and drain regions on both sides of each deep trench isolation region 16, and the substrate interface regions are defined at both ends of the substrate; next, N-type ions are implanted in the source and drain regions to form... Figure 11 As shown, source region 12 and drain region 13 are implanted with P-type ions in the region of the substrate interface to form a structure as shown. Figure 11 The substrate interface 15 is shown.

[0046] After completing steps S401 to S405, as follows Figure 12 As shown, a silicide barrier layer 18 (SAB) is formed on a portion of the surface of the gate and drain regions through a furnace tube, elongating the drain region (Drain end) and facilitating the flow of charge carriers into the device interior, where they flow out through the parasitic transistor within the device. Then, contact lines 19 and metal interconnects are formed to connect to the substrate interface 15, source region 12, and gate 14, connecting the drain region 13 to voltage. The substrate interface 15, source region 12, and gate 14 are all grounded.

[0047] This invention also provides a chip that includes the aforementioned multi-finger GGNMOS device, which constitutes an ESD protection circuit for electrostatic protection of the chip.

[0048] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention. Furthermore, it should be noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. As long as such combination does not violate the spirit of the embodiments of the present invention, it should also be considered as the content disclosed in the embodiments of the present invention.

Claims

1. A multi-finger GGNMOS device, comprising: A substrate, a body region and a substrate interface formed on the substrate, and multiple source regions, multiple drain regions and multiple gates formed on the surface of the body region, wherein the multiple source regions, multiple gates and the substrate interface are all grounded, and the multiple source regions, multiple drain regions and multiple gates respectively constitute multiple GGNMOS structures, characterized in that a deep trench isolation region is provided between every two adjacent source regions and drain regions. The depth of the deep trench isolation region near the middle of the substrate is greater than the depth of the deep trench isolation region near the two ends of the substrate.

2. The multi-finger GGNMOS device according to claim 1, characterized in that, The upper end of the deep trench isolation zone is close to the source region, and the lower end of the deep trench isolation zone extends towards the bottom of the body region.

3. The multi-finger GGNMOS device according to claim 1, characterized in that, The depth of the deep trench isolation zone is either less than or greater than the depth of the body zone.

4. The multi-finger GGNMOS device according to claim 1, characterized in that, In multiple GGNMOS structures, the depth of the deep trench isolation region decreases sequentially from the middle of the substrate to both ends of the substrate.

5. The multi-finger GGNMOS device according to claim 1, characterized in that, The upper width of the deep trench isolation zone is greater than the lower width, and the shape of the deep trench isolation zone is wedge-shaped or inverted trapezoidal.

6. The multi-finger GGNMOS device according to claim 1, characterized in that, A shallow trench isolation region is provided between the substrate interface and the source region near the edge of the substrate. The depth of the shallow trench isolation region is less than the depth of the deep trench isolation region between the source region and the drain region near the edge of the substrate.

7. The multi-finger GGNMOS device according to claim 1, characterized in that, The material filled in the deep trench isolation zone is silicon oxide or undoped silicon.

8. A method for manufacturing a multi-finger GGNMOS device, characterized in that, include: Multiple deep trenches are formed in the substrate, and the depth of the deep trenches near the middle of the substrate is greater than the depth of the deep trenches near the two ends of the substrate. Multiple deep trenches are filled with a medium material to form multiple deep trench isolation zones; A bulk region is formed in the substrate, such that multiple deep trench isolation regions are located within the bulk region; Multiple gates are formed on the surface of the body region; Source and drain regions are formed on both sides of each deep trench isolation region, and substrate interfaces are formed at both ends of the substrate.

9. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, The method further includes: A shallow trench is formed in the region between the source region and the substrate interface near the edge of the substrate; A medium material is filled into the shallow trench to form a shallow trench isolation zone.

10. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, Multiple deep trenches are formed in the substrate, including: Multiple deep trenches are etched at corresponding locations using photolithography and etching processes, with the depth of the trenches decreasing sequentially from the middle of the substrate to both ends.

11. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, Multiple deep trenches are filled with a dielectric material to form multiple deep trench isolation zones, including: Multiple deep trenches are filled with silicon oxide or undoped silicon, and the filling material on the surface of the deep trenches is smoothed using a chemical mechanical polishing process to form multiple deep trench isolation zones.

12. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, A bulk region is formed in the substrate, including: A sacrificial oxide layer is grown on the substrate surface, and the bulk region is defined using photolithography. Ions are implanted into the bulk region to form the bulk region.

13. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, Multiple gates are formed on the surface of the body region, including: A layer of polysilicon is deposited on the surface of the bulk region and etched to form multiple polysilicon gates.

14. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, Source and drain regions are formed on both sides of each deep trench isolation region, and substrate interfaces are formed at both ends of the substrate, including: An oxide layer and a silicon nitride layer are deposited on a substrate with multiple gates, and etched to form sidewalls on both sides of each gate. The source and drain regions are defined on both sides of each deep trench isolation region using the sidewalls, and the substrate interface regions are defined at both ends of the substrate. N-type ions are injected into the source and drain regions to form the source and drain regions; P-type ions are implanted into the region of the substrate interface to form the substrate interface.

15. The method for manufacturing a multi-finger GGNMOS device according to claim 8, characterized in that, The method further includes: After forming the source region, drain region, and substrate interface, a silicide barrier layer is formed on a portion of the surface of the gate and drain regions to elongate the drain region; Form contact lines and metal interconnects that connect to the substrate interface, source region, and gate.

16. A chip, characterized in that, The chip includes the multi-finger GGNMOS device as described in any one of claims 1-7.

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