Magnetoresistive random access memory and manufacturing method thereof

Abstract

The invention discloses a magnetoresistive random access memory (MRAM) and a manufacturing method thereof, and the manufacturing method of the magnetoresistive random access memory (MRAM) mainly comprises the following steps: firstly forming a spin-orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first covering layer beside the MTJ, forming a second covering layer beside the MTJ, and forming a second covering layer beside the MTJ. Forming a second covering layer beside the first covering layer, wherein the thickness of the first covering layer is greater than that of the second covering layer;

Description

Technical Field

[0001] This invention relates to a magnetoresistive random access memory (MRAM) device and its fabrication method. Background Technology

[0002] Magnetoresistance (MR) is the effect of a material's resistance changing with the application of a magnetic field. Its physical quantity is defined as the rate of change of resistance, calculated by dividing the resistance difference (with and without a magnetic field) by the original resistance. Currently, the magnetoresistance effect has been successfully applied in hard drive manufacturing and has significant commercial value. Furthermore, utilizing the characteristic that giant magnetoresistance materials have different resistance values ​​under different magnetization states, magnetic random access memory (MRAM) can also be fabricated, which has the advantage of retaining stored data even when no power is applied.

[0003] The aforementioned magnetoresistive effect is also applied in the field of magnetic field sensing, such as in the electronic compass components of mobile phones that integrate with the Global Positioning System (GPS) to provide users with information such as their location. Currently, various magnetic field sensing technologies are available on the market, such as anisotropic magnetoresistive (AMR) sensing elements, giant magnetoresistive (GMR) sensing elements, and magnetic tunneling junction (MTJ) sensing elements. However, these existing technologies typically have drawbacks, including larger chip area, higher manufacturing costs, higher power consumption, insufficient sensitivity, and susceptibility to temperature changes, necessitating further improvements. Summary of the Invention

[0004] One embodiment of the present invention discloses a method for fabricating a magnetoresistive random access memory (MRAM) element. The method mainly involves first forming a spin orbit torque (SOT) layer on a substrate, then forming a magnetic tunneling junction (MTJ) on the SOT layer, forming a first cover layer next to the MTJ, and then forming a second cover layer next to the first cover layer, wherein the thickness of the first cover layer is greater than the thickness of the second cover layer.

[0005] Another embodiment of the present invention discloses a magnetoresistive random access memory (MRAM) device, which mainly includes a spin-orbit torque (SOT) layer disposed on a substrate, a magnetic tunneling junction (MTJ) disposed on the SOT layer, a first cover layer disposed next to the MTJ, and a second cover layer disposed next to the first cover layer, wherein the thickness of the first cover layer is greater than the thickness of the second cover layer. Attached Figure Description

[0006] Figures 1 to 9 This is a schematic diagram illustrating a method for fabricating an MRAM cell according to an embodiment of the present invention.

[0007] Symbol Explanation

[0008] 12: Base

[0009] 14: MRAM region

[0010] 16: Interlayer dielectric layer

[0011] 18: Metal interconnect structure

[0012] 20: Metal interconnect structure

[0013] 22: Intermetallic dielectric layer

[0014] 24: Metal interconnects

[0015] 26: Stop Layer

[0016] 28: Intermetallic dielectric layer

[0017] 34: Barrier Layer

[0018] 36: Metal layer

[0019] 40: Logical Region

[0020] 42: Lower electrode

[0021] 44: SOT layer

[0022] 46: Free Layer

[0023] 48: Barrier Layer

[0024] 50: Fixed layer

[0025] 60: Covering layer

[0026] 62: Upper electrode

[0027] 64: Dielectric layer

[0028] 66: MTJ stacked structure

[0029] 70:MTJ

[0030] 72: First covering layer

[0031] 74: Intermetallic Dielectric Layer

[0032] 76: Bottom anti-reflective layer

[0033] 78: Patterned Mask

[0034] 80: Second covering layer

[0035] 84: Intermetallic Dielectric Layer

[0036] 86: Metal interconnects

[0037] 88: Stop Layer

[0038] 90: Intermetallic dielectric layer

[0039] 92: Metal interconnects

[0040] 94: Stop Layer Detailed Implementation

[0041] Please refer to Figures 1 to 9 , Figures 1 to 9 This is a schematic diagram illustrating an embodiment of the present invention, showing a method for fabricating a semiconductor element, or more specifically, an MRAM cell, in a direction such as the X direction. Figure 1 As shown, a substrate 12 is first provided, for example, a substrate 12 made of semiconductor material, wherein the semiconductor material may be selected from the group consisting of silicon, germanium, silicon-germanium composite, silicon carbide, gallium arsenide, etc., and an MRAM region 14 and a logic region 40 are preferably defined on the substrate 12.

[0042] The substrate 12 may contain active (active) devices such as metal-oxide-semiconductor (MOS) transistors, passive (passive) devices, conductive layers, and dielectric layers such as interlayer dielectric (ILD) 16 covering it. More specifically, the substrate 12 may contain planar or non-planar (such as fin structure transistors) MOS transistor devices, wherein the MOS transistors may include gate structures (such as metal gates) and source / drain regions, spacers, epitaxial layers, contact hole etch stop layers, and other transistor elements. The interlayer dielectric layer 16 may be disposed on the substrate 12 and cover the MOS transistors, and the interlayer dielectric layer 16 may have multiple contact plugs electrically connecting the gate and / or source / drain regions of the MOS transistors. Since the fabrication processes of planar or non-planar transistors and interlayer dielectric layers are well known in the art, they will not be described in detail here.

[0043] Then, metal interconnect structures 18 and 20 are sequentially formed on the interlayer dielectric layer 16 of the MRAM region 14 to electrically connect the aforementioned contact plugs. The metal interconnect structure 18 includes an intermetallic dielectric layer 22 and metal interconnects 24 embedded in the intermetallic dielectric layer 22. The metal interconnect structure 20 includes a stop layer 26, an intermetallic dielectric layer 28, and multiple metal interconnects (not shown) embedded in the stop layer 26 and the intermetallic dielectric layer 28. It should be noted that, compared to the MRAM region 14 which also has metal interconnects 24, the logic region 40 at this stage only has metal interconnects 24 within the intermetallic dielectric layer 22, but no metal interconnects within the intermetallic dielectric layer 28.

[0044] In this embodiment, each metal interconnect 24 in the metal interconnect structure 18 preferably includes a trench conductor, while the metal interconnects in the metal interconnect structure 20 (not shown) include a via conductor. Furthermore, each metal interconnect 24 in the metal interconnect structures 18 and 20 can be embedded in the inter-metal dielectric layers 22 and 28 and / or the stop layer 26 using a single damascene fabrication process or a double damascene fabrication process and electrically connected to each other. For example, each metal interconnect 24 may further include a barrier layer 34 and a metal layer 36. The barrier layer 34 can be selected from the group consisting of titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN), while the metal layer 36 can be selected from the group consisting of tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc., but is not limited thereto. Since single-damascene or double-damascene fabrication processes are well-known techniques in the art, they will not be described in detail here. In addition, in this example, the metal layer 36 in the metal interconnect 24 preferably includes copper, the intermetallic dielectric layers 22 and 28 preferably include silicon oxide or an ultra-low dielectric constant dielectric layer, and the stop layer 26 includes a nitrogen-doped carbide (NDC), silicon nitride, or silicon carbon nitride (SiCN), but is not limited to these.

[0045] Next, a selective lower electrode 42, a spin orbit torque (SOT) layer 44, an MTJ stack structure 66, a masking layer 60, and a patterned hard mask or upper electrode 62 are formed on the metal interconnect structure 20. In this embodiment, the MTJ stack structure 66 can be formed by sequentially forming a free layer 46, a barrier layer 48, a reference layer (not shown), a spacer layer (not shown), and a pinned layer 50 on the SOT layer 44. The free layer 46 can be made of a ferromagnetic material, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited thereto, and the magnetization direction of the free layer 46 can be "freely" changed by an external magnetic field. The barrier layer 48 can be made of an insulating material containing oxides, such as aluminum oxide (AlO). x It can be magnesium oxide (MgO) or magnesium oxide (MgO), but is not limited to these.

[0046] The reference layer is preferably disposed between the barrier layer 48 and the spacer layer, and may contain ferromagnetic materials, such as iron, cobalt, nickel, or their alloys such as cobalt-iron-boron (CoFeB), but is not limited thereto. The spacer layer contains a non-magnetic layer made of a non-magnetic material, such as a group consisting of ruthenium, iridium, and rhodium.

[0047] The fixing layer 50 may contain ferromagnetic materials such as, but not limited to, cobalt-iron-boron (CoFeB), cobalt-iron (CoFe), iron (Fe), and cobalt (Co). Alternatively, the fixing layer 50 may also be composed of antiferromagnetic (AFM) materials, such as iron-manganese (FeMn), platinum-manganese (PtMn), iridium-manganese (IrMn), and nickel oxide (NiO), to fix or restrict the magnetic moment direction of adjacent layers. In detail, the fixing layer 50 may include a lower synthetic antiferromagnetic (SAF) layer, a coupling layer, and an upper synthetic antiferromagnetic layer. The lower and upper synthetic antiferromagnetic layers may contain the same or different materials, and both may contain ferromagnetic materials such as cobalt (Co), nickel (Ni), platinum (Pt), palladium (Pd), or combinations thereof. The coupling layer preferably contains materials that can provide mechanical and / or lattice structure support for the lower and upper synthetic antiferromagnetic layers, such as ruthenium (Ru), tantalum (Ta), gadolinium (Gd), platinum (Pt), hafnium (Hf), or combinations thereof.

[0048] In this embodiment, the selective electrode 42 preferably comprises a conductive material, such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), platinum (Pt), copper (Cu), gold (Au), and aluminum (Al). The SOT layer 44 preferably serves as a channel for a spinorbit torque (SOT) MRAM, therefore its material may include tantalum (Ta), tungsten (W), platinum (Pt), hafnium (Hf), and bismuth selenide (Bi). x Se 1-x The shielding layer 60 preferably contains a metal such as ruthenium, and the upper electrode 62 may contain a conductive or dielectric material such as, but not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), platinum (Pt), copper (Cu), gold (Au), aluminum (Al), or combinations thereof.

[0049] In addition, in this embodiment, the patterned upper electrode 62 can be formed by forming a dielectric layer 64 made of silicon oxide on the unpatterned upper electrode 62, and then using a patterned mask (not shown), such as a patterned photoresist, to remove part of the dielectric layer 64 and the upper electrode 62 by means of, for example, reactive ion etching (RIE) to form a patterned dielectric layer 64 and a patterned upper electrode 62, and then selectively removing the dielectric layer 64 made of silicon oxide.

[0050] like Figure 2As shown, a patterned dielectric layer 64 or a patterned top electrode 62 can then be used as a mask to remove part of the masking layer 60, part of the MTJ stack structure 66, and even part of the SOT layer 44 of the MRAM region 14 to form the MTJ 70. Then, a first masking layer 72 and an intermetallic dielectric layer 74 are sequentially formed on the MTJ 70. Preferably, the MTJ stack structure 66 of the logic region 40 is completely removed at this stage, and in this embodiment, the etching process parameters are preferably adjusted in the aforementioned patterning process so that the top surface of the top electrode 62 directly above the MTJ 70 has a curved surface. In this embodiment, the first masking layer 72 preferably contains silicon nitride, while the intermetallic dielectric layer 74 contains silicon oxide, such as tetraethoxysilane (TEOS). It should be noted that when the patterned upper electrode 62 is used to pattern the MTJ stack structure 66 to form the MTJ 70 in this stage, a portion of the SOT layer 44 can be selectively removed, so that the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are slightly lower than the top surface of the SOT layer 44 directly below the MTJ 70. According to another embodiment of the present invention, if no SOT layer 44 is removed when forming the MTJ 70, the top surfaces of the remaining SOT layers 44 on both sides of the MTJ 70 are preferably flush with the top surface of the SOT layer 44 directly below the MTJ 70. Furthermore, the first masking layer 72 and the intermetallic dielectric layer 74 formed in this stage are preferably simultaneously disposed on the MRAM region 14 and the logic region 40.

[0051] like Figures 3 to 4 As shown, a bottom anti-reflective coating (BARC) 76 can be formed on the intermetallic dielectric layer 74. Then, an etching process is performed using a patterned mask 78, such as a patterned photoresist mask. For example, an ion beam etching process can be used to remove part of the bottom anti-reflective coating 76 and part of the intermetallic dielectric layer 74 in the MRAM region 14, as well as all of the bottom anti-reflective coating 76 and intermetallic dielectric layer 74 in the logic region 40, exposing the underlying first masking layer 72. This leaves the remaining intermetallic dielectric layer 74 only in the MRAM region 14, but the underlying first masking layer 72 is still simultaneously located in both the MRAM region 14 and the logic region 40. Then, the bottom anti-reflective coating 76 can be removed to expose the intermetallic dielectric layer 74 in the MRAM region 14.

[0052] Subsequently, as Figure 5As shown, an etching process is performed without forming an additional patterned mask. For example, an ion beam etching (IBE) process, different from the one described above, is used to remove all the intermetallic dielectric layers 74, part of the first masking layer 72, part of the SOT layer 44, part of the lower electrode 42, and even part of the intermetallic dielectric layer 28 of the MRAM region 14, as well as all the first masking layer 72, all SOT layers 44, all lower electrodes 42, and part of the intermetallic dielectric layer 28 of the logic region 40. This causes the left and right sidewalls of the first masking layer 72, SOT layer 44, and lower electrode 42 of the MRAM region 14 to be slightly recessed and aligned. The top surface of the remaining intermetallic dielectric layer 28 of the logic region 40 can be selectively slightly lower than the top surface of the intermetallic dielectric layer 28 of the MRAM region 14.

[0053] It should be noted that although the IBE fabrication process performed in this stage removes part of the underlying intermetallic dielectric layer 28 when patterning the first cover layer 72, SOT layer 44, and lower electrode 42, it is not limited to this. According to other embodiments of the present invention, no intermetallic dielectric layer 28 may be removed when patterning the first cover layer 72, SOT layer 44, and lower electrode 42 using the IBE fabrication process. In other words, after patterning the first cover layer 72, SOT layer 44, and lower electrode 42, the top surface of the intermetallic dielectric layer 28 on both sides of the first cover layer 72 or SOT layer 44 can still be aligned with the top surface of the intermetallic dielectric layer 28 directly below the MTJ 70. This variation is also within the scope of the present invention.

[0054] like Figure 6 As shown, a second masking layer 80 is then formed on the first masking layer 72 and the intermetallic dielectric layer 28, wherein the second masking layer 80 preferably covers the top surface of the first masking layer 72, the sidewalls of the first masking layer 72, the sidewalls of the SOT layer 44, the sidewalls of the lower electrode 42, and the top surface of the intermetallic dielectric layer 28. In this embodiment, the first masking layer 72 and the second masking layer 80 preferably contain the same material, for example, both preferably contain silicon nitride.

[0055] Then as Figure 7 As shown, an etching process can be performed without forming a patterned mask to remove part of the second masking layer 80 of the MRAM region 14 and all of the second masking layers 80 of the logic region 40, exposing the top surface of the intermetallic dielectric layer 28. The curved top surface of the second masking layer 80 located on the sidewall of the first masking layer 72 is preferably flush with the curved top surface of the first masking layer 72 or extends continuously and uninterruptedly from the curved top surface of the first masking layer 72 to the curved top surface of the second masking layer 80.

[0056] In this embodiment, the thickness of the first masking layer 72 is preferably greater than the thickness of the second masking layer 80, where "preferably" refers to the maximum distance or width of the first masking layer 72 and the second masking layer 80 extending along the X direction. According to one embodiment of the invention, the thickness of the second masking layer 80 is preferably about 40% to 80% or most preferably about 60% of the thickness of the first masking layer 72. Furthermore, although both the first masking layer 72 and the second masking layer 80 are preferably made of silicon nitride, the silicon concentration of the first masking layer 72 is preferably greater than that of the second masking layer 80, and the refractive index ratio of the first masking layer 72 relative to the second masking layer 80 is preferably between 1.2 and 1.7. According to a preferred embodiment of the invention, this configuration allows for the subsequent filling of a larger intermetallic dielectric layer next to the MTJ, thereby improving the insulation capability between components.

[0057] Subsequently, as Figure 8 As shown, another intermetallic dielectric layer 84 is first formed in the MRAM region 14 and the logic region 40. A planarization process, such as chemical mechanical polishing (CMP), is used to remove part of the intermetallic dielectric layer 84. Then, a pattern transfer process is performed. For example, a patterned mask can be used to remove part of the intermetallic dielectric layer 84, part of the second masking layer 80 and part of the first masking layer 72 in the MRAM region 14, and part of the intermetallic dielectric layer 84, part of the intermetallic dielectric layer 28 and part of the stop layer 26 in the logic region 40 to form contact holes (not shown) and expose the underlying upper electrode 62 and the metal interconnect 24. Then, the contact hole is filled with the desired conductive material, such as a barrier layer containing titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials or combinations thereof, such as tungsten (W), copper (Cu), aluminum (Al), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), etc. Next, a planarization process is performed, for example, by chemical mechanical polishing to remove some of the conductive material to form a metal interconnect 86 electrically connecting the upper electrode 62 and the metal interconnect 24 within the contact hole. A stop layer 88 is then formed on the metal interconnect 86. In this embodiment, the intermetallic dielectric layer 84 and the intermetallic dielectric layer 74 may contain the same or different materials, for example, both containing silicon oxide, while the stop layer 88 may contain silicon dioxide, silicon nitride, or silicon carbide (SiCN), preferably silicon carbide, but is not limited thereto.

[0058] Then as Figure 9As shown, an intermetallic dielectric layer 90 is first formed on the stop layer 88 of the MRAM region 14 and logic region 40. Then, a pattern transfer fabrication process is performed, for example, using a patterned mask (not shown) to remove part of the intermetallic dielectric layer 90 and part of the stop layer 88 to form contact holes (not shown) and expose the underlying metal interconnects 86. The contact holes are then filled with the desired conductive material, such as a barrier layer material including titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), etc., and a low-resistance metal layer selected from low-resistance materials such as tungsten (W), copper (Cu), aluminum (Al), titanium-aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Next, a planarization fabrication process is performed, for example, using a chemical mechanical polishing process to remove part of the metal material to form contact plugs or metal interconnects 92 electrically connecting the metal interconnects 86 within the contact holes. Afterward, a stop layer 94 is selectively formed on the metal interconnects 92. In this embodiment, the intermetallic dielectric layer 90 preferably includes an ultra-low dielectric constant dielectric layer, which may include, for example, a porous dielectric material such as, but not limited to, silicon carbide (SiOC) or silicon carbide hydrogen (SiOCH).

[0059] In summary, this invention mainly discloses a method for fabricating SOT MRAM devices and its related structures. The method primarily involves first forming an SOT layer 44 and an MTJ 70 on a substrate, forming a first masking layer 72 next to the MTJ, and then forming a second masking layer 80 next to the first masking layer. Preferably, the thickness of the first masking layer 72 is greater than the thickness of the second masking layer 80. The top surfaces of both the first and second masking layers 72 and 80 preferably include curved surfaces, with the curved surface of the first masking layer 72 preferably higher than the curved surface of the second masking layer 80. Preferably, the curved surface of the first masking layer 72 extends continuously to the curved surface of the second masking layer 80. Both the first and second masking layers 72 and 80 are preferably composed of silicon nitride, but the silicon concentration of the first masking layer 72 is preferably greater than that of the second masking layer 80. Simultaneously, the refractive index ratio of the first masking layer 72 relative to the second masking layer 80 is preferably between 1.2 and 1.7. According to a preferred embodiment of the present invention, this configuration allows for the subsequent filling of more intermetallic dielectric layers next to the MTJ, thereby improving the insulation capability between components.

[0060] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A method for manufacturing a magnetoresistive random access memory element, characterized in that, Include: A spin-orbit torque layer is formed on the substrate; A magnetic tunneling junction is formed on the spin-orbit torque layer; A first covering layer is formed next to the magnetic tunnel junction; and A second covering layer is formed next to the first covering layer, wherein the thickness of the first covering layer is greater than the thickness of the second covering layer.

2. The method of claim 1, further comprising: An upper electrode is formed on the magnetic tunnel junction; The first covering layer is formed on the magnetic tunneling junction and the spin-orbit torque layer; The first masking layer is patterned using a first etching process. The second covering layer is formed on the first covering layer; The second masking layer is patterned using a second etching process. as well as An intermetallic dielectric layer is formed on the first cover layer and the second cover layer.

3. The method of claim 2, wherein the top surface of the upper electrode comprises a curved surface.

4. The method of claim 1, wherein the width of the magnetic tunnel junction is smaller than the width of the spin-orbit torque layer.

5. The method of claim 1, wherein the bottom surface of the second cover layer is lower than the bottom surface of the first cover layer.

6. The method of claim 1, wherein the silicon concentration of the first masking layer is greater than the silicon concentration of the second masking layer.

7. A magnetoresistive random access memory element, characterized in that, Include: Spin-orbit torque layer, disposed on the substrate; A magnetic tunneling junction is disposed on the spin-orbit torque layer; A first shielding layer is disposed beside the magnetic tunnel junction; and A second covering layer is disposed next to the first covering layer, wherein the thickness of the first covering layer is greater than the thickness of the second covering layer.

8. The magnetoresistive random access memory element as claimed in claim 7, further comprising: The upper electrode is disposed on the magnetic tunnel junction; and A metal-to-metal dielectric layer surrounds the second shielding layer.

9. The magnetoresistive random access memory element of claim 8, wherein the top surface of the upper electrode comprises a curved surface.

10. The magnetoresistive random access memory element of claim 7, wherein the width of the magnetic tunneling junction is smaller than the width of the spin-orbit torque layer.

11. The magnetoresistive random access memory element of claim 7, wherein the bottom surface of the second cover layer is lower than the bottom surface of the first cover layer.

12. The magnetoresistive random access memory element of claim 7, wherein the silicon concentration of the first masking layer is greater than the silicon concentration of the second masking layer.

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