Package including integrated device and metallization portion having variable thickness metallization interconnect on same metal layer

Abstract

A package includes an integrated device and a metallization portion. The metallization part comprises at least one dielectric layer; and a plurality of metallization interconnects. The plurality of metallization interconnects includes a first metallization interconnect on the first metal layer and a second metallization interconnect on the first metal layer. The first metallization interconnect includes a first thickness. The second metallization interconnect includes a second thickness different from the first thickness. The package may include a substrate and / or a bridge. The substrate may include an interposer.

Description

[0001] Cross-references to related applications

[0002] This application claims priority and interest in U.S. Provisional Application S / N. 63 / 491,985, filed March 24, 2023, with the U.S. Patent and Trademark Office, and in accordance with the entire contents of U.S. Provisional Application S / N. 18 / 460,471, filed September 1, 2023, with the U.S. Patent and Trademark Office, the whole contents of which are incorporated herein by reference as fully set forth herein and for all applicable purposes.

[0003] field

[0004] Various features are involved in the packaging, including integrated devices and metallized portions. Background Technology

[0005] A package may include a package substrate and integrated devices. These components are coupled together to provide a package capable of performing various electrical functions. How the integrated devices and the package substrate are coupled together affects the overall performance of the package. There has always been a need to provide packages with better performance.

[0006] Overview

[0007] Various features are involved in the packaging of integrated devices and packaging substrates.

[0008] One example provides a package comprising: an integrated device; a substrate coupled to the integrated device via at least a first plurality of solder interconnects; and a metallized portion coupled to the substrate via at least a second plurality of solder interconnects. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects. The plurality of metallized interconnects includes a first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and a second metallized interconnect located on the first metal layer, wherein the second metallized interconnect includes a second thickness different from the first thickness.

[0009] Another example provides a package including: a first integrated device, a second integrated device, a bridge coupled to the first and second integrated devices; and a metallized portion coupled to the first and second integrated devices. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects. The plurality of metallized interconnects includes a first metallized interconnect located on a first metal layer and a second metallized interconnect located on the first metal layer. The first metallized interconnect includes a first thickness. The second metallized interconnect includes a second thickness different from the first thickness. Brief description of the attached diagram

[0011] The various features, essences, and advantages will become apparent when the following detailed description is understood in conjunction with the accompanying drawings, in which similar reference numerals are used throughout to indicate them accordingly.

[0012] Figure 1 A cross-sectional view of an exemplary package, including integrated devices and metallized portions, is described.

[0013] Figure 2 A cross-sectional view of an exemplary package, including integrated devices and metallized portions, is described.

[0014] Figure 3 A cross-sectional view of an exemplary package, including integrated devices and metallized portions, is described.

[0015] Figure 4 A cross-sectional view of an exemplary package including a first integrated device, a second integrated device, and a metallized portion is described.

[0016] Figures 5A-5H Exemplary processes for manufacturing packages that include integrated devices and metallized portions are explained.

[0017] Figure 6 An exemplary flowchart illustrates a method for manufacturing a package that includes integrated devices and metallized portions.

[0018] Figure 7 A cross-sectional view of an exemplary package, including integrated devices, interposers, and metallized portions, is described.

[0019] Figure 8 A cross-sectional view of an exemplary package including a first integrated device, a second integrated device, a bridge, and a metallized portion is described.

[0020] Figures 9A-9C Exemplary steps for manufacturing a package that includes integrated devices, bridges, and metallized portions are explained.

[0021] Figure 10 An exemplary flowchart illustrates a method for manufacturing a package that includes integrated devices, bridges, and metallized portions.

[0022] Figure 11 This document describes various electronic devices that can integrate the dies, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein.

[0023] Detailed description

[0024] In the following description, specific details are set forth to provide a thorough understanding of various aspects of this disclosure. However, those skilled in the art will understand that these aspects can be practiced without these specific details. For example, circuits may be shown as block diagrams to avoid obscuring these aspects in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these aspects of this disclosure.

[0025] This disclosure describes a package comprising: an integrated device; a substrate coupled to the integrated device via at least a first plurality of solder interconnects; and a metallized portion coupled to the substrate via at least a second plurality of solder interconnects. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects. The plurality of metallized interconnects includes a first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and a second metallized interconnect located on the first metal layer, wherein the second metallized interconnect includes a second thickness different from the first thickness.

[0026] In some implementations, a package includes: a first integrated device, a second integrated device, a bridge coupled to the first and second integrated devices; and a metallized portion coupled to the first and second integrated devices. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects. The plurality of metallized interconnects includes a first metallized interconnect located on a first metal layer and a second metallized interconnect located on the first metal layer. The first metallized interconnect includes a first thickness. The second metallized interconnect includes a second thickness different from the first thickness.

[0027] As will be further described below, the use of metallized interconnects with varying thicknesses in the metallized portion offers several technical advantages, including the ability to customize and optimize the metallized interconnects for the type of signals and / or power that will travel through them, which can help deliver packages with improved performance.

[0028] Exemplary package including integrated devices and metallized portions

[0029] Figure 1 A cross-sectional view of a package 100, including metallized portions of metallized interconnects with varying thicknesses, is illustrated. The package 100 is coupled to a board 108 via a plurality of solder interconnects 110. The board 108 includes at least one board dielectric layer 180 and a plurality of board interconnects 182. The board 108 may include a printed circuit board (PCB).

[0030] Package 100 includes a metallized portion 102, an integrated device 103, and an encapsulation layer 106. The integrated device 103 is coupled to a first surface of the metallized portion 102. The integrated device 103 may be a first integrated device. The integrated device 103 may be a bare die (e.g., a semiconductor bare die). The integrated device 103 is coupled to the metallized portion 102. The front side of the integrated device 103 may face the metallized portion 102. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may be coupled to the first surface of the metallized portion 102. The encapsulation layer (e.g., 106) may include a molding compound, resin, and / or epoxy resin. The encapsulation layer may be a means for encapsulation. The encapsulation layer may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0031] The metallized portion 102 includes at least one dielectric layer 120 and a plurality of metallized interconnects 122. The plurality of metallized interconnects 122 may include a first plurality of metallized interconnects 122a and a second plurality of metallized interconnects 122b. The first plurality of metallized interconnects 122a includes metallized interconnects 122aa, 122ab, 122ac, 122ad, 122ae, 122af, 122ag, and 122ah. The second plurality of metallized interconnects 122b includes metallized interconnects 122ba, 122bb, 122bc, 122bd, 122be, 122bf, 122bg, and 122bh.

[0032] Metallized interconnect 122aa is coupled to metallized interconnect 122ab. Metallized interconnect 122ab is coupled to metallized interconnect 122ac. Metallized interconnect 122ac is coupled to metallized interconnect 122ad. Metallized interconnect 122ad is coupled to metallized interconnect 122ae. Metallized interconnect 122ae is coupled to metallized interconnect 122af. Metallized interconnect 122af is coupled to metallized interconnect 122ag. Metallized interconnect 122ag is coupled to metallized interconnect 122ah. Metallized interconnects 122aa, 122ac, 122ae, and 122ag may include metallized vias (e.g., via interconnects, metallized via interconnects). Metallized interconnects 122ab, 122ad, 122af, and 122ah may include metallized pads and / or metallized traces.

[0033] Metallized interconnect 122ba is coupled to metallized interconnect 122bb. Metallized interconnect 122bb is coupled to metallized interconnect 122bc. Metallized interconnect 122bc is coupled to metallized interconnect 122bd. Metallized interconnect 122bd is coupled to metallized interconnect 122be. Metallized interconnect 122be is coupled to metallized interconnect 122bf. Metallized interconnect 122bf is coupled to metallized interconnect 122bg. Metallized interconnect 122bg is coupled to metallized interconnect 122bh. Metallized interconnects 122ba, 122bc, 122be, and / or 122bg may include metallized vias (e.g., via interconnects, metallized via interconnects). Metallized interconnects 122bb, 122bd, 122bf, and / or 122bh may include metallized pads and / or metallized traces.

[0034] Figure 1 It is explained that some metallized interconnects on the same metal layer (e.g., M1, M2, M3, M4) can have different thicknesses and / or metallized interconnects between the same metal layers can have different heights, widths, and / or diameters. Metallized interconnect 122aa can have a height HA1. Metallized interconnect 122ab can have a thickness TA1. Metallized interconnect 122ac can have a height HA2. Metallized interconnect 122ad can have a thickness TA2. Metallized interconnect 122ae can have a height HA3. Metallized interconnect 122af can have a thickness TA3. Metallized interconnect 122ag can have a height HA4. Metallized interconnect 122ah can have a thickness TA4.

[0035] Metallized interconnect 122ba may have a height HB1. Metallized interconnect 122bb may have a thickness TB1. Metallized interconnect 122bc may have a height HB2. Metallized interconnect 122bd may have a thickness TB2. Metallized interconnect 122be may have a height HB3. Metallized interconnect 122bf may have a thickness TB3. Metallized interconnect 122bg may have a height HB4. Metallized interconnect 122bh may have a thickness TB4.

[0036] Metallized interconnects 122ab and 122bb are located on the same metal layer (e.g., M1). The thickness (TA1) of metallized interconnect 122ab is less than the thickness (TB1) of metallized interconnect 122bb. Metallized interconnects 122ad and 122bd are located on the same metal layer (e.g., M2). The thickness (TA2) of metallized interconnect 122ad is less than the thickness (TB2) of metallized interconnect 122bd. Metallized interconnects 122af and 122bf are located on the same metal layer (e.g., M3). The thickness (TA3) of metallized interconnect 122af is less than the thickness (TB3) of metallized interconnect 122bb. Metallized interconnects 122ah and 122bh are located on the same metal layer (e.g., M4). The thickness (TA4) of metallized interconnect 122ah is approximately the same as the thickness (TB4) of metallized interconnect 122bh.

[0037] Metallized interconnect 122aa may have a height HA1 that is substantially the same as the height HB1 of metallized interconnect 122ba. Metallized interconnect 122aa may have a width and / or diameter that is substantially the same as the width and / or diameter of metallized interconnect 122ba. Metallized interconnect 122ac and metallized interconnect 122bc may be located between the same metal layers (e.g., between M1 and M2). Metallized interconnect 122ac may have a height HA2 that is greater than the height HB2 of metallized interconnect 122bc. Metallized interconnect 122ac may have a width and / or diameter that is smaller than the width and / or diameter of metallized interconnect 122bc. Metallized interconnect 122ae and metallized interconnect 122be may be located between the same metal layers (e.g., between M2 and M3). Metallized interconnect 122ae may have a height HA3 that is greater than the height HB3 of metallized interconnect 122be. Metallized interconnect 122ae may have a width and / or diameter that is smaller than the width and / or diameter of metallized interconnect 122be. Metallized interconnects 122ag and 122bg can be located between the same metal layers (e.g., between M3 and M4). Metallized interconnect 122ag can have a height HA4 greater than the height HB4 of metallized interconnect 122bg. Metallized interconnect 122ag can have a width and / or diameter smaller than the width and / or diameter of metallized interconnect 122bg.

[0038] As examples, in some implementations, the minimum thickness (e.g., TA1, TA2, TA3, TA4) of one or more interconnects (e.g., 122ab, 122ad, 122af) can be in the range of approximately 5-10 micrometers. In some implementations, the minimum height (e.g., HA2, HA3, HA4) of one or more via interconnects (e.g., 122ac, 122ae, 122ag) can be in the range of approximately 7-20 micrometers. In some implementations, the minimum thickness (e.g., TB1, TB2, TB3, TB4) of one or more interconnects (e.g., 122bb, 122bd, 122bf) can be in the range of approximately 7-20 micrometers. In some implementations, the minimum height (e.g., HB2, HB3, HB4) of one or more via interconnects (e.g., 122bc, 122be, 122bg) can be in the range of approximately 5-15 micrometers. In some implementations, one or more interconnects (e.g., trace interconnects) can have a minimum width of approximately 2 micrometers.

[0039] Note that the minimum thickness, minimum height, minimum width, and / or minimum diameter mentioned above are exemplary. Different implementations may have metallized interconnects with different thicknesses, heights, widths, and / or diameters (e.g., different minimum thicknesses, minimum heights, minimum widths, and / or minimum diameters). Furthermore, different implementations may have metallized interconnects with different relative thicknesses, relative heights, relative widths, and / or relative diameters. In some implementations, the thickness of one metallized interconnect on the same metal layer may be at least 1.2 times greater than the thickness of another metallized interconnect on the same layer. For example, metallized interconnect 122bb may have a thickness TB1 at least 1.5 times greater than the thickness TA1 of metallized interconnect 122ab.

[0040] In some implementations, thicker metallized interconnects may be optimal, preferred, and / or more desirable to allow more current to flow through with lower resistance. For example, when a metallized interconnect is configured as an electrical path for power supply, a thicker metallized interconnect may be desirable, resulting in lower resistance in the electrical path, which can allow more power to travel to the integrated device. Conversely, metallized interconnects configured to provide electrical paths for signals (e.g., input / output (I / O) signals) may not need to be as large and / or thick, because input / output signals operate at lower voltages, and therefore their dimensions (e.g., linewidth, line thickness) do not need to be as large as those of metallized interconnects configured to provide electrical paths for power supply.

[0041] Therefore, the thickness and / or height of various metallized interconnects can be configured to be optimized for the type of current traveling through the metallized interconnect in the metallized portion. In one example, a metallized interconnect configured to provide an electrical path for power supply may have a greater thickness and / or a larger width and / or diameter than an interconnect configured to provide an electrical path for signal. In another example, a metallized interconnect configured to provide an electrical path for input / output signals may have the minimum possible thickness, width, and / or diameter, and / or a smaller thickness, width, and / or diameter compared to an interconnect configured to provide an electrical path for power supply and / or ground.

[0042] The integrated device 103 includes die interconnects 130a and 130b. Die interconnects 130a and / or 130b may be die pads for the integrated device 103. Die interconnect 130a is coupled to and contacts metallized interconnect 122aa of metallized portion 102. Die interconnect 130b is coupled to and contacts metallized interconnect 122ba of metallized portion 102.

[0043] Metallized interconnect 122ah can be coupled to and contact solder interconnects from multiple solder interconnects 110. Metallized interconnect 122bh can be coupled to and contact another solder interconnect from multiple solder interconnects 110.

[0044] In some implementations, the electrical path between board 108 and integrated device 103 may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a first plurality of metallized interconnects 122a, and die interconnects 130a.

[0045] In some implementations, the electrical path for input / output signals between board 108 and integrated device 103 may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a first plurality of metallized interconnects 122a, and die interconnects 130a.

[0046] In some implementations, the electrical path between board 108 and integrated device 103 for power supply or grounding may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a first plurality of metallized interconnects 122b, and die interconnects 130a.

[0047] Figure 2 A cross-sectional view of package 200, including metallized portions of metallized interconnects with varying thicknesses, is illustrated. Package 200 is similar to package 100 and includes similar components. However, package 200 includes metallized interconnects with combinations of different thicknesses.

[0048] Package 200 includes a metallized portion 202, an integrated device 103, and an encapsulation layer 106. The integrated device 103 is coupled to a first surface of the metallized portion 202. The integrated device 103 may be a first integrated device. The integrated device 103 is coupled to the metallized portion 202. The front side of the integrated device 103 may face the metallized portion 202. The encapsulation layer 106 may encapsulate the integrated device 103. The encapsulation layer 106 may be coupled to the first surface of the metallized portion 202.

[0049] The metallized portion 202 includes at least one dielectric layer 220 and a plurality of metallized interconnects 222. The plurality of metallized interconnects 222 may include a first plurality of metallized interconnects 222a and a second plurality of metallized interconnects 222b. The first plurality of metallized interconnects 222a includes metallized interconnects 222aa, 222ab, 222ac, 222ad, 222ae, 222af, 222ag, and 222ah. The second plurality of metallized interconnects 222b includes metallized interconnects 222ba, 222bb, 222bc, 222bd, 222be, 222bf, 222bg, and 222bh.

[0050] Metallized interconnect 222aa is coupled to metallized interconnect 222ab. Metallized interconnect 222ab is coupled to metallized interconnect 222ac. Metallized interconnect 222ac is coupled to metallized interconnect 222ad. Metallized interconnect 222ad is coupled to metallized interconnect 222ae. Metallized interconnect 222ae is coupled to metallized interconnect 222af. Metallized interconnect 222af is coupled to metallized interconnect 222ag. Metallized interconnect 222ag is coupled to metallized interconnect 222ah. Metallized interconnects 222aa, 222ac, 222ae, and / or 222ag may include metallized vias. Metallized interconnects 222ab, 222ad, 222af, and / or 222ah may include metallized pads and / or metallized traces.

[0051] Metallized interconnect 222ba is coupled to metallized interconnect 222bb. Metallized interconnect 222bb is coupled to metallized interconnect 222bc. Metallized interconnect 222bc is coupled to metallized interconnect 222bd. Metallized interconnect 222bd is coupled to metallized interconnect 222be. Metallized interconnect 222be is coupled to metallized interconnect 222bf. Metallized interconnect 222bf is coupled to metallized interconnect 222bg. Metallized interconnect 222bg is coupled to metallized interconnect 222bh. Metallized interconnects 222ba, 222bc, 222be, and / or 222bg may include metallized vias. Metallized interconnects 222bb, 222bd, 222bf, and / or 222bh may include metallized pads and / or metallized traces.

[0052] Figure 2 It is explained that some metallized interconnects on the same metal layer (e.g., M1, M2, M3, M4) can have different thicknesses and / or metallized interconnects between the same metal layers can have different heights, widths, and / or diameters. Metallized interconnect 222aa can have a height HA1. Metallized interconnect 222ab can have a thickness TA1. Metallized interconnect 222ac can have a height HA2. Metallized interconnect 222ad can have a thickness TA2. Metallized interconnect 222ae can have a height HA3. Metallized interconnect 222af can have a thickness TA3. Metallized interconnect 222ag can have a height HA4. Metallized interconnect 222ah can have a thickness TA4.

[0053] Metallized interconnect 222ba may have a height HB1. Metallized interconnect 222bb may have a thickness TB1. Metallized interconnect 222bc may have a height HB2. Metallized interconnect 222bd may have a thickness TB2. Metallized interconnect 222be may have a height HB3. Metallized interconnect 222bf may have a thickness TB3. Metallized interconnect 222bg may have a height HB4. Metallized interconnect 222bh may have a thickness TB4.

[0054] Metallized interconnects 222ab and 222bb are located on the same metal layer (e.g., M1). The thickness (TA1) of metallized interconnect 222ab is less than the thickness (TB1) of metallized interconnect 222bb. Metallized interconnects 222ad and 222bd are located on the same metal layer (e.g., M2). The thickness (TA2) of metallized interconnect 222ad is less than the thickness (TB2) of metallized interconnect 222bd. Metallized interconnects 222af and 222bf are located on the same metal layer (e.g., M3). The thickness (TA3) of metallized interconnect 222af is less than the thickness (TB3) of metallized interconnect 222bb. Metallized interconnects 222ah and 222bh are located on the same metal layer (e.g., M4). The thickness (TA4) of metallized interconnect 222ah is approximately the same as the thickness (TB4) of metallized interconnect 222bh.

[0055] Metallized interconnect 222aa may have a height HA1 that is substantially the same as the height HB1 of metallized interconnect 222ba. Metallized interconnect 222aa may have a width and / or diameter that is substantially the same as the width and / or diameter of metallized interconnect 222ba. Metallized interconnect 222ac and metallized interconnect 222bc may be located between the same metal layers (e.g., between M1 and M2). Metallized interconnect 222ac may have a height HA2 that is greater than the height HB2 of metallized interconnect 222bc. Metallized interconnect 222ac may have a width and / or diameter that is smaller than the width and / or diameter of metallized interconnect 222bc. Metallized interconnect 222ae and metallized interconnect 222be may be located between the same metal layers (e.g., between M2 and M3). Metallized interconnect 222ae may have a height HA3 that is greater than the height HB3 of metallized interconnect 222be. Metallized interconnect 222ae may have a width and / or diameter that is smaller than the width and / or diameter of metallized interconnect 222be. Metallized interconnects 222ag and 222bg may be located between the same metal layers (e.g., between M3 and M4). Metallized interconnect 222ag may have a height HA4 greater than the height HB4 of metallized interconnect 222bg. Metallized interconnect 222ag may have a width and / or diameter smaller than the width and / or diameter of metallized interconnect 222bg. As an example, a first via metallized interconnect (e.g., 222ac) may include a first minimum diameter, and a second via metallized interconnect (e.g., 222bc) may include a second minimum diameter greater than the first minimum diameter.

[0056] Figure 2The explanation states that the relative thickness of a metallized interconnect to another metallized interconnect on the same metallized layer can differ for different metallized layers. For example, for the first metallized layer of metallized portion 202 (e.g., M1), metallized interconnect 222bb may have a thickness TB1 that is at least 1.2 times thicker than the thickness TA1 of metallized interconnect 222ab. In another example, for the second metallized layer of metallized portion 202 (e.g., M2), metallized interconnect 222bd may have a thickness TB2 that is at least 1.5 times thicker than the thickness TA2 of metallized interconnect 222ad. In another example, for the third metallized layer of metallized portion 202 (e.g., M3), metallized interconnect 222bf may have a thickness TB3 that is at least 2 times thicker than the thickness TA3 of metallized interconnect 222af. In another example, for the fourth metallized layer of metallized portion 202 (e.g., M4), metallized interconnect 222bh may have a thickness TB4 that is approximately the same as the thickness TA4 of metallized interconnect 222ah. However, note that the thickness, height, width, and / or diameter described above are exemplary. Different implementations may have metallized interconnects with different thicknesses, heights, widths, and / or diameters. Furthermore, different implementations may have metallized interconnects with different relative thicknesses, relative heights, relative widths, and / or relative diameters.

[0057] Figure 3 Exemplary electrical paths for package 200 are explained. For example, Figure 3 The electrical paths 302, 304, and 306 between integrated device 103 and board 108 are explained. Electrical path 302 between integrated device 103 and board 108 may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a first plurality of metallized interconnects 222a, and die interconnects 130a. Electrical path 302 can be configured to provide electrical paths for input / output signals.

[0058] The electrical path 304 between the integrated device 103 and the board 108 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallized interconnects 222b, and a die interconnect 130b. The electrical path 304 may be configured to provide an electrical path for power supply or grounding.

[0059] The electrical path 306 between the integrated device 103 and the board 108 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a third plurality of metallized interconnects 222c, and a die interconnect 130c. The electrical path 306 may be configured to provide an electrical path for power supply or grounding. The third plurality of metallized interconnects 222c may be similar to the second plurality of metallized interconnects 222b because they have metallized interconnects of different thicknesses on the same metal layer.

[0060] Figure 4 The package described includes metallized portions of metallized interconnects with varying thicknesses. Package 400 includes a metallized portion 402, an integrated device 403, an integrated device 405, and an encapsulation layer 106. Integrated device 403 is coupled to a first surface of the metallized portion 402. Integrated device 405 is coupled to the first surface of the metallized portion 402. Integrated device 403 may be a bare die (e.g., a semiconductor die). Integrated device 405 may be a bare die (e.g., a semiconductor die). Integrated device 403 may be a first integrated device (e.g., a first die), and integrated device 405 may be a second integrated device (e.g., a second die). Integrated devices 403 and 405 are coupled to and contact the metallized portion 402. The front side of integrated device 403 may face the metallized portion 402. The front side of integrated device 405 may face the metallized portion 402. Encapsulation layer 106 may encapsulate integrated device 403 and integrated device 405. Encapsulation layer 106 may be coupled to a first surface of metallization portion 402. Integrated device 403 may be configured to perform a first plurality of functions and / or operations. Integrated device 405 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations.

[0061] The metallized portion 402 includes at least one dielectric layer 420 and a plurality of metallized interconnects 422. The plurality of metallized interconnects 422 may include a first plurality of metallized interconnects 422a, a second plurality of metallized interconnects 422b, a third plurality of metallized interconnects 422c, and a fourth plurality of metallized interconnects 422d.

[0062] The first plurality of metallized interconnects 422a may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The third plurality of metallized interconnects 422c may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The second plurality of metallized interconnects 422b may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b. The fourth plurality of metallized interconnects 422d may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b.

[0063] Figure 4 Exemplary electrical paths for packaging, such as electrical path 401, electrical path 404, electrical path 412, and electrical path 414, are described. An electrical path between integrated device 403 and board 108 may include electrical path 401. Electrical path 401 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallized interconnects 422a, and a first die interconnect from integrated device 403. Electrical path 401 may be configured to provide electrical paths for input / output signals.

[0064] The electrical path between integrated device 403 and board 108 may include electrical path 404. Electrical path 404 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallized interconnects 422b, and a second die interconnect from integrated device 403. Electrical path 404 may be configured to provide an electrical path for power supply or grounding.

[0065] The electrical path between integrated device 405 and board 108 may include electrical path 412. Electrical path 412 may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a third plurality of metallized interconnects 422c, and a first die interconnect from integrated device 405. Electrical path 412 may be configured to provide an electrical path for input / output signals.

[0066] The electrical path between integrated device 405 and board 108 may include electrical path 414. Electrical path 414 may include another board interconnect from multiple board interconnects 182, another solder interconnect from multiple solder interconnects 110, a fourth plurality of metallized interconnects 422d, and a second die interconnect from integrated device 405. Electrical path 414 may be configured to provide an electrical path for power supply or grounding.

[0067] The electrical path 416 between integrated device 405 and integrated device 403 may include die interconnects from integrated device 405, at least one metallized interconnect from a plurality of metallized interconnects 422, and die interconnects from integrated device 403.

[0068] The metallized portion may include a redistribution portion, which includes a redistribution interconnect (e.g., a redistribution layer (RDL) interconnect). The redistribution interconnect may include portions having a U-shape or a V-shape. The terms "U-shape" and "V-shape" should be used interchangeably. The terms "U-shape" and "V-shape" may refer to the side profile shape of the interconnect and / or redistribution interconnect. U-shaped interconnects (e.g., U-shaped side profile interconnects) and V-shaped interconnects (e.g., V-shaped side profile interconnects) may have a top and a bottom. The bottom of a U-shaped interconnect (or V-shaped interconnect) may be coupled to the top of another U-shaped interconnect (or V-shaped interconnect).

[0069] Integrated devices (e.g., 103, 403, 405) may include dies (e.g., bare semiconductor dies). Integrated devices may include power management integrated circuits (PMICs). Integrated devices may include application processors. Integrated devices may include modems. Integrated devices may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memories, power management processors, and / or combinations thereof. Integrated devices (e.g., 103, 403, 405) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). Integrated devices may include transistors. Integrated devices may be examples of electrical components and / or electrical devices. In some implementations, integrated devices may be chips. Chips can be manufactured using processes that offer better yields compared to other processes used to manufacture other types of integrated devices, which can reduce the overall cost of manufacturing chips. Different chips can have different sizes and / or shapes. Different chips can be configured to provide different functions. Different chips can have different interconnect densities (e.g., interconnects with different widths and / or spacings). In some implementations, several chips can be used to perform the functionality of one or more chips (e.g., one or more integrated devices). As mentioned above, using several chips that perform several functions can reduce the overall cost of the package compared to using a single chip to perform all the functions of the package. In some implementations, the same technology node or two or more different technology nodes can be used to manufacture one or more chips and / or one or more integrated devices (e.g., 103, 403, 405) as described in this disclosure. For example, an integrated device (e.g., 403) can be manufactured using a first technology node, and a chip (e.g., 405) can be manufactured using a second technology node that is less advanced than the first technology node. In such examples, an integrated device (e.g., 403) may include components (e.g., interconnects, transistors) having a first minimum size, and a die (e.g., 405) may include components (e.g., interconnects, transistors) having a second minimum size, wherein the second minimum size is greater than the first minimum size. In some implementations, the packaged integrated device 403 and integrated device 405 may be manufactured using the same or different technology nodes. In some implementations, one die and another die may be manufactured using the same or different technology nodes.

[0070] A technology node can refer to a specific manufacturing process and / or technology used to manufacture integrated devices and / or dies. A technology node can specify the minimum possible size that can be manufactured (e.g., minimum size) (e.g., transistor size, trace width, gap between two transistors). Different technology nodes can have different yield losses. Different technology nodes can have different costs. Technology nodes that produce components with finer details (e.g., traces, transistors) are more expensive and can have higher yield losses compared to technology nodes that produce components with less fine detail (e.g., traces, transistors). Therefore, more advanced technology nodes can be more expensive and can have higher yield losses compared to less advanced technology nodes. When all the functions of a package are implemented in a single integrated device, the same technology node is used to manufacture the entire integrated device, even if some functions of the integrated device do not require manufacturing using that specific technology node. Thus, the integrated device is locked into a single technology node. To optimize packaging costs, some functions can be implemented in different integrated devices and / or dies, where different technology nodes can be used to manufacture different integrated devices and / or dies to reduce overall costs. For example, functionality requiring state-of-the-art technology nodes can be implemented in an integrated device, while functionality achievable with less advanced technology nodes can be implemented in another integrated device and / or one or more dies. An example would be an integrated device configured to provide computing applications, manufactured using a first technology node (e.g., the most advanced technology node), and at least one die manufactured using a second technology node configured to provide additional functionality, wherein the second technology node is less expensive than the first technology node, and wherein the minimum size of the component manufactured using the second technology node is greater than the minimum size of the component manufactured using the first technology node. Examples of computing applications could include high-performance computing and / or high-performance processing, which can be achieved by manufacturing and packaging as many transistors as possible in the integrated device. This is why the integrated device configured for computing applications can be manufactured using the most advanced technology nodes available, while other dies can be manufactured using less advanced technology nodes, since those dies may not require as many transistors to be manufactured in the die. Therefore, using combinations of different technology nodes (which may have different associated yield losses) for different integrated devices and / or dies can reduce the overall cost of the package compared to using a single integrated device to perform all the functionality of the package.

[0071] Another advantage of breaking down functionality into several integrated devices and / or dies is that it allows for improvements in package performance without requiring the redesign of each individual integrated device and / or die. For example, if a package configuration uses a first integrated device and a first die, package performance can be improved by changing the design of the first integrated device while keeping the design of the first die the same. Therefore, the first die can be reused with improved and / or differently configured first integrated devices. This saves costs by eliminating the need to redesign the first die when manufacturing a package with improved integrated devices.

[0072] Exemplary process for manufacturing a package including integrated devices and metallized portions.

[0073] Figures 5A-5H Exemplary steps for providing or manufacturing a package comprising integrated devices and metallized portions of metallized interconnects with varying thicknesses are described. In some implementations, Figures 5A-5H The process can be used to provide or manufacture Figure 2 Package 200, or any package described in this disclosure.

[0074] It should be noted that Figures 5A-5H The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. Figures 5A-5H The process can be used to manufacture one package or several packages (as part of a chip) at a time.

[0075] like Figure 5A As shown, stage 1 illustrates the state after the carrier 500 and adhesive coating 501 are provided. Adhesive coating 501 may be an adhesive layer located on the surface of the carrier 500.

[0076] Phase 2 describes the state of integrated device 103 after it has been placed on carrier 500 and adhesive coating 501. Pick-and-place processes can be used to place integrated devices. The front side of integrated device 103 can be placed on carrier 500 and adhesive coating 501. In some implementations, more than one integrated device (e.g., 403, 405) can be placed on carrier 500 and adhesive coating 501.

[0077] Phase 3 describes the state after the encapsulation layer 106 is formed over the carrier 500, adhesive coating 501, and integrated device 103. The encapsulation layer 106 encapsulates the integrated device 103. The encapsulation layer 106 may include molding materials, resin, and / or epoxy resin. The encapsulation layer 106 may be a device for encapsulation. The encapsulation layer 106 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 can be removed. For example, a polishing process can be used to remove the top of the encapsulation layer 106 and / or the back side of the integrated device 103.

[0078] Phase 4 describes the state after the carrier 500 and adhesive coating 501 are decoupled from the integrated device 103 and encapsulation layer 106. The carrier 500 and adhesive coating 501 can be separated from the integrated device 103 and encapsulation layer 106.

[0079] like Figure 5B As shown, stage 5 explains the integrated device 103 and encapsulation layer 106 placed on the carrier 502. The back side of the integrated device 103 can be placed and coupled to the carrier 502. An adhesive coating similar to adhesive coating 501 may be present on the carrier 502. A pick-and-place process can be used to place the integrated device 103 and encapsulation layer 106 on the carrier 502.

[0080] Phase 6 describes the state after the dielectric layer 510 is formed on the integrated device 103 and the encapsulation layer 106. The dielectric layer 510 can be formed using deposition and / or lamination processes. The dielectric layer 510 can be formed on the front side of the integrated device 103.

[0081] Phase 7 describes the state after the plurality of cavities 511 are formed in the dielectric layer 510. The plurality of cavities 511 can be formed using an etching process (e.g., a photolithography process). Masking processes, exposure processes, and / or development processes can be used to form the plurality of cavities 511. The plurality of cavities 511 can be formed over a plurality of die interconnects 130 of the integrated device 103, such that the plurality of die interconnects 130 are exposed (or at least a portion of the plurality of die interconnects 130 are exposed).

[0082] Phase 8 describes the state after metallized interconnects are formed in and on the dielectric layer 510 and in the plurality of cavities 511. A plurality of metallized interconnects 512 may be formed on the first surface of the dielectric layer 510 and on (e.g., above) the plurality of cavities 511. The plurality of metallized interconnects 512 may be formed using masking processes, plating processes, exposure processes, developing processes, and / or etching processes.

[0083] like Figure 5CAs shown, stage 9 illustrates the state after the photoresist layer 513 is formed on the dielectric layer 510. Deposition and / or lamination processes can be used to form the photoresist layer 513. The photoresist layer 513 may include openings on some of the metallization interconnects from the plurality of metallization interconnects 512.

[0084] Phase 10 describes the state after some of the metallized interconnects from multiple metallized interconnects 512 are thickened to form multiple metallized interconnects 514. Multiple metallized interconnects 514 can be formed using masking processes, plating processes, exposure processes, development processes, and / or etching processes. As a result, some metallized interconnects on the same metal layer can have different thicknesses.

[0085] Stage 11 describes the state after the photoresist layer 513 has been removed. An etching process can be used to remove the photoresist layer 513.

[0086] Phase 12 describes the state after dielectric layer 520 is formed over dielectric layer 510, multiple metallized interconnects 512, and multiple metallized interconnects 514. Dielectric layer 520 can be formed using deposition and / or lamination processes. Dielectric layer 520 may resemble dielectric layer 510.

[0087] Stage 13 describes the state after the formation of multiple cavities 521 in the dielectric layer 520. Etching processes (e.g., photolithography) can be used to form the multiple cavities 521. Masking processes, exposure processes, and / or development processes can be used to form the multiple cavities 521.

[0088] Phase 14 describes the state after metallized interconnects are formed in and on the dielectric layer 520 and in the plurality of cavities 521. A plurality of metallized interconnects 522 may be formed on the first surface of the dielectric layer 520 and on (e.g., above) the plurality of cavities 521. The plurality of metallized interconnects 522 may be formed using masking processes, plating processes, exposure processes, developing processes, and / or etching processes.

[0089] Stage 15 describes the state after the photoresist layer 523 is formed on the dielectric layer 520. Deposition and / or lamination processes can be used to form the photoresist layer 523. The photoresist layer 523 may include openings on some of the metallization interconnects from the plurality of metallization interconnects 522.

[0090] Phase 16 describes the state after some of the metallized interconnects 522 from multiple metallized interconnects 522 are thickened to form multiple metallized interconnects 524. Multiple metallized interconnects 524 can be formed using masking processes, plating processes, exposure processes, development processes, and / or etching processes. As a result, some metallized interconnects on the same metal layer can have different thicknesses.

[0091] like Figure 5EAs shown, stage 17 illustrates the state after the removal of photoresist layer 523. An etching process can be used to remove photoresist layer 523.

[0092] Phase 18 describes the state after dielectric layer 530 is formed over dielectric layer 520, multiple metallized interconnects 522, and multiple metallized interconnects 524. Dielectric layer 530 can be formed using deposition and / or lamination processes. Dielectric layer 530 may resemble dielectric layer 520.

[0093] Phase 19 describes the state after the formation of multiple cavities 531 in the dielectric layer 530. Etching processes (e.g., photolithography) can be used to form the multiple cavities 531. Masking processes, exposure processes, and / or development processes can be used to form the multiple cavities 531.

[0094] like Figure 5F As shown, stage 20 illustrates the state after metallized interconnects are formed in and above the dielectric layer 530 and in the plurality of cavities 531. A plurality of metallized interconnects 532 may be formed on the first surface of the dielectric layer 530 and above (e.g., above) the plurality of cavities 531. The plurality of metallized interconnects 532 may be formed using masking processes, plating processes, exposure processes, developing processes, and / or etching processes.

[0095] Phase 21 describes the state after the photoresist layer 533 is formed on the dielectric layer 530. Deposition and / or lamination processes can be used to form the photoresist layer 533. The photoresist layer 533 may include openings on some of the metallization interconnects from the plurality of metallization interconnects 532.

[0096] Phase 22 describes the state after some of the metallized interconnects 532 from multiple metallized interconnects 532 are thickened to form multiple metallized interconnects 534. Multiple metallized interconnects 534 can be formed using masking processes, plating processes, exposure processes, development processes, and / or etching processes. As a result, some metallized interconnects on the same metal layer can have different thicknesses.

[0097] like Figure 5G As shown, stage 23 illustrates the state after the removal of photoresist layer 533. An etching process can be used to remove photoresist layer 533.

[0098] Phase 24 describes the state after dielectric layer 540 is formed over dielectric layer 530, multiple metallized interconnects 532, and multiple metallized interconnects 534. Dielectric layer 540 can be formed using deposition and / or lamination processes. Dielectric layer 540 may be similar to dielectric layer 530.

[0099] Phase 25 describes the state after the formation of multiple cavities 541 in the dielectric layer 540. Etching processes (e.g., photolithography) can be used to form the multiple cavities 541. Masking processes, exposure processes, and / or development processes can be used to form the multiple cavities 541.

[0100] like Figure 5H As shown, stage 26 illustrates the state after metallized interconnects are formed in and on the dielectric layer 540 and in the plurality of cavities 541. A plurality of metallized interconnects 542 may be formed on the first surface of the dielectric layer 540 and on (e.g., above) the plurality of cavities 541. The plurality of metallized interconnects 542 may be formed using masking processes, plating processes, exposure processes, developing processes, and / or etching processes.

[0101] Phase 27 describes the state after the carrier 502 is decoupled from the integrated device 103 and the encapsulation layer 106. The carrier 502 can be separated from the integrated device 103 and the encapsulation layer 106. At least one dielectric layer 220 may represent dielectric layer 510, dielectric layer 520, dielectric layer 530 and / or dielectric layer 540. A plurality of metallized interconnects 222 may represent a plurality of metallized interconnects 512, a plurality of metallized interconnects 514, a plurality of metallized interconnects 522, a plurality of metallized interconnects 524, a plurality of metallized interconnects 532, a plurality of metallized interconnects 534, a plurality of metallized interconnects 542 and / or a plurality of metallized interconnects 544. The plurality of metallized interconnects 222 may include a first plurality of metallized interconnects 222a and a second plurality of metallized interconnects 222b, as at least in this disclosure. Figure 2 and 3 As described in [the text].

[0102] Phase 28 describes the state after the multiple solder interconnects 110 are coupled to the metallization portion 202. The multiple solder interconnects 110 can be coupled to the multiple metallization interconnects 222 of the metallization portion 202 using a solder reflow process.

[0103] An exemplary flowchart of a method for manufacturing a package including integrated devices and metallized portions.

[0104] In some implementations, manufacturing the package involves several processes. Figure 6 An exemplary flowchart of a method 600 for providing or manufacturing a package is illustrated. In some implementations, Figure 6 Method 600 can be used to provide or manufacture any package disclosed herein. For example, Figure 6 Method 600 can be used to manufacture package 200.

[0105] It should be noted that method 600 of Figure 13 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. Figure 6 Method 600 can be used to manufacture one or more packages (as part of a chip) at a time.

[0106] This method (in 605) provides a carrier. In some implementations, the carrier may be provided with an adhesive. Figure 5A Phase 1 explains and describes an example of providing a carrier 500 and an adhesive coating 501. The adhesive coating 501 may be an adhesive layer located on the surface of the carrier 500.

[0107] This method (in 610) places the front side of the integrated device on a carrier. In some implementations, the front side of the integrated device is placed on a carrier including an adhesive. In some implementations, more than one integrated device may be placed on the carrier. Figure 5A Phase 2 explains and describes an example of an integrated device 103 placed on a carrier 500 and an adhesive coating 501. A pick-and-place process can be used to place the integrated device. The front side of the integrated device 103 can be placed on the carrier 500 and the adhesive coating 501. In some implementations, more than one integrated device (e.g., 403, 405) can be placed on the carrier 500 and the adhesive coating 501.

[0108] This method (at 615) forms an encapsulation layer for encapsulating the integrated device. The encapsulation layer can be coupled to the integrated device and the carrier. Figure 5A Phase 3 explains and describes an example of an encapsulation layer 106 formed over a carrier 500, an adhesive coating 501, and an integrated device 103. The encapsulation layer 106 encapsulates the integrated device 103. The encapsulation layer 106 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 106 may be a device for encapsulation. The encapsulation layer 106 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 can be removed. For example, a polishing process can be used to remove the top of the encapsulation layer 106 and / or the back side of the integrated device 103.

[0109] This method (at 620) decouples the carrier from the encapsulation layer and the integrated device. Figure 5A Phase 4 explains and describes an example of carrier 500 and adhesive coating 501 decoupled from integrated device 103 and encapsulation layer 106. Carrier 500 and adhesive coating 501 can be separated from integrated device 103 and encapsulation layer 106.

[0110] The method (at 625) places the back side of the integrated device and the encapsulation layer on top of another carrier (e.g., a second carrier). The carrier may include an adhesive. Figure 5B Phase 5 explains and describes an example of an integrated device 103 and an encapsulation layer 106 placed on a carrier 502. The back side of the integrated device 103 can be placed and coupled to the carrier 502. An adhesive coating similar to adhesive coating 501 may be present on the carrier 502. A pick-and-place process can be used to place the integrated device 103 and the encapsulation layer 106 on the carrier 502.

[0111] The method (at 630) forms a metallized portion coupled to the front side and encapsulation layer of an integrated device. The metallized portion may include at least one dielectric layer and a plurality of metallized interconnects. The plurality of metallized interconnects may include a first metallized interconnect on a first metal layer and a second metallized interconnect on the first metal layer, wherein the second interconnect has a second thickness different from the first metallized interconnect's first thickness. Forming the metallized portion may include forming at least one dielectric layer, forming the first metallized interconnect on the first metal layer, and forming the second metallized interconnect on the first metal layer. The second interconnect may have a second thickness different from the first metallized interconnect's first thickness. Figure 5B Stage 6 to Figure 5H Stage 26 illustrates an example of forming a metallization portion coupled to at least one integrated device. Different implementations may have different numbers of metal layers. Once the metallization portion is formed (at 630), the method can decouple the second carrier from the integrated device and the encapsulation layer. Figure 5H Phase 27 explains an example of decoupling the second carrier.

[0112] This method (in 635) couples multiple solder interconnects to the metallized interconnects of the metallized portion. Figure 5H Phase 28 explains and describes an example of multiple solder interconnects 110 coupled to the metallization portion 202. A solder reflow process can be used to couple the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0113] Exemplary packages including integrated devices, metallized portions, bridges, and / or intermediaries

[0114] Figure 7A package including an interposer and metallized portions of metallized interconnects with different thicknesses is described. Package 700 includes a metallized portion 402, an interposer 702, an integrated device 403, and an integrated device 405. Integrated device 403 is coupled to a first surface of interposer 702 via a plurality of solder interconnects 730. Integrated device 405 is coupled to the first surface of interposer 702 via a plurality of solder interconnects 750. Interposer 702 may be a substrate. Interposer 702 includes at least one dielectric layer 720 (e.g., a substrate dielectric layer, an interposer dielectric layer) and a plurality of interposer interconnects 722 (e.g., substrate interconnects). Interposer 702 may include silicon. For example, the at least one dielectric layer 720 may include silicon. Integrated device 403 may be a bare die (e.g., a semiconductor bare die). Integrated device 405 may be a bare die (e.g., a semiconductor bare die). Integrated device 403 may be a first integrated device (e.g., a first die), and integrated device 405 may be a second integrated device (e.g., a second die). Note that instead of the intermediate 702, a laminated substrate, such as an embedded trace substrate comprising at least one dielectric layer and multiple substrate interconnects, can be used.

[0115] Integrated device 403 may be configured to perform a first plurality of functions and / or operations. Integrated device 405 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations.

[0116] The metallized portion 402 is coupled to the second surface of the dielectric 702 via a plurality of solder interconnects 740. The metallized portion 402 includes at least one dielectric layer 420 and a plurality of metallized interconnects 422. The plurality of metallized interconnects 422 may include a first plurality of metallized interconnects 422a, a second plurality of metallized interconnects 422b, a third plurality of metallized interconnects 422c, and a fourth plurality of metallized interconnects 422d.

[0117] The first plurality of metallized interconnects 422a may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The third plurality of metallized interconnects 422c may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The second plurality of metallized interconnects 422b may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b. The fourth plurality of metallized interconnects 422d may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b.

[0118] Figure 7Exemplary electrical paths for packaging, such as electrical path 701, electrical path 704, electrical path 712, and electrical path 714, are described. Electrical paths between integrated device 403 and board 108 may include electrical path 701. Electrical path 701 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallized interconnects 422a, solder interconnects from a plurality of solder interconnects 740, intermediate interconnects from a plurality of intermediate interconnects 722 (e.g., substrate interconnects from a plurality of substrate interconnects), solder interconnects from a plurality of solder interconnects 730, and a first die interconnect from integrated device 403. Electrical path 701 may be configured to provide electrical paths for input / output signals.

[0119] The electrical path between integrated device 403 and board 108 may include electrical path 704. Electrical path 704 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallized interconnects 422b, solder interconnects from a plurality of solder interconnects 740, intermediate interconnects from a plurality of intermediate interconnects 722 (e.g., substrate interconnects from a plurality of substrate interconnects), solder interconnects from a plurality of solder interconnects 730, and a second die interconnect from integrated device 403. Electrical path 704 may be configured to provide an electrical path for power supply or grounding.

[0120] The electrical path between integrated device 405 and board 108 may include electrical path 712. Electrical path 712 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a third plurality of metallized interconnects 422c, solder interconnects from a plurality of solder interconnects 740, intermediate interconnects from a plurality of intermediate interconnects 722 (e.g., substrate interconnects from a plurality of substrate interconnects), solder interconnects from a plurality of solder interconnects 750, and a first die interconnect from integrated device 405. Electrical path 712 may be configured to provide electrical paths for input / output signals.

[0121] The electrical path between integrated device 405 and board 108 may include electrical path 714. Electrical path 714 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a fourth plurality of metallized interconnects 422d, solder interconnects from a plurality of solder interconnects 740, intermediate interconnects from a plurality of intermediate interconnects 722 (e.g., substrate interconnects from a plurality of substrate interconnects), solder interconnects from a plurality of solder interconnects 750, and a second die interconnect from integrated device 405. Electrical path 714 may be configured to provide an electrical path for power supply or grounding.

[0122] The electrical path between integrated device 405 and integrated device 403 may include die interconnects from integrated device 405, at least one intermediate interconnect from a plurality of intermediate interconnects 722, and die interconnects from integrated device 403.

[0123] In some implementations, package 700 can be fabricated by coupling integrated devices 403 and 405 to a medium 702 via multiple solder interconnects (e.g., 730, 750). The medium 702 can then be coupled to a metallization portion 402 via multiple solder interconnects 740. The metallization portion 402 can then be coupled to a board 108 via multiple solder interconnects 110. However, different implementations may use different processes to fabricate package 700. Medium 702 can be used when there is a significant difference between the size and / or spacing of the pad interconnects of the integrated devices (e.g., 403, 405) and the interconnects of the metallization portion 402.

[0124] Figure 8 The description includes a package comprising a bridge and metallized portions of metallized interconnects with varying thicknesses. Package 800 includes a metallized portion 402, integrated devices 403 and 405, and a bridge 808. Bridge 808 may include a silicon-based bridge. Package 800 is similar to... Figure 4 The package size is 400.

[0125] Integrated device 403 is coupled to a first surface of metallization portion 402. Integrated device 405 is coupled to the first surface of metallization portion 402. Integrated device 403 may be a bare die (e.g., a semiconductor die). Integrated device 405 may be a bare die (e.g., a semiconductor die). Integrated device 403 may be a first integrated device (e.g., a first die), and integrated device 405 may be a second integrated device (e.g., a second die). Integrated devices 403 and 405 are coupled to and in contact with metallization portion 402. The front side of integrated device 403 may face metallization portion 402. The front side of integrated device 405 may face metallization portion 402. Encapsulation layer 106 may encapsulate integrated device 403 and integrated device 405. Encapsulation layer 106 may be coupled to the first surface of metallization portion 402. Integrated device 403 may be configured to perform a first plurality of functions and / or operations. Integrated device 405 may be configured to perform a second plurality of functions and / or operations. The second plurality of functions and / or operations includes at least one function and / or operation that is different from the first plurality of functions and / or operations.

[0126] Bridge 808 is at least partially located in metallized portion 402. Bridge 808 is coupled to integrated device 403 and integrated device 405. Bridge 808 can be coupled to integrated device 403 and / or integrated device 405 via hybrid bonding (e.g., copper-to-copper bonding, interconnect-to-interconnect bonding). In some implementations, bridge 808 can be coupled to integrated device 403 and / or integrated device 405 via at least a plurality of solder interconnects (not shown). The front side of integrated device 403 and the front side of integrated device 405 may face bridge 808. Bridge 808 may include bridge substrate 880 and a plurality of bridge interconnects 882. Bridge 808 may include at least one dielectric layer 884. In some implementations, bridge 808 may be a silicon-based bridge. Bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to die pads (e.g., 430) of integrated device 403 and die pads (e.g., 450) of integrated device 405. Figure 8 The electrical path 816 between integrated device 403 and integrated device 405 is explained. Electrical path 816 can be configured to provide at least one electrical path between integrated device 403 and integrated device 405 for input / output signals.

[0127] Electrical path 816 includes die interconnects from integrated device 403, at least one bridge interconnect from a plurality of bridge interconnects 882 from bridge 808, and die interconnects from integrated device 405.

[0128] The metallized portion 402 includes at least one dielectric layer 420 and a plurality of metallized interconnects 422. A bridge 808 may be at least partially located within the metallized portion 402. The plurality of metallized interconnects 422 may include a first plurality of metallized interconnects 422a, a second plurality of metallized interconnects 422b, a third plurality of metallized interconnects 422c, and a fourth plurality of metallized interconnects 422d.

[0129] The first plurality of metallized interconnects 422a may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The third plurality of metallized interconnects 422c may be similar to the first plurality of metallized interconnects 122a and / or the first plurality of metallized interconnects 222a. The second plurality of metallized interconnects 422b may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b. The fourth plurality of metallized interconnects 422d may be similar to the second plurality of metallized interconnects 122b and / or the second plurality of metallized interconnects 222b.

[0130] Figure 8Exemplary electrical paths for packaging, such as electrical path 401, electrical path 404, electrical path 412, and electrical path 414, are described. An electrical path between integrated device 403 and board 108 may include electrical path 401. Electrical path 401 may include board interconnects from a plurality of board interconnects 182, solder interconnects from a plurality of solder interconnects 110, a first plurality of metallized interconnects 422a, and a first die interconnect from integrated device 403. Electrical path 401 may be configured to provide electrical paths for input / output signals.

[0131] The electrical path between integrated device 403 and board 108 may include electrical path 404. Electrical path 404 may include another board interconnect from a plurality of board interconnects 182, another solder interconnect from a plurality of solder interconnects 110, a second plurality of metallized interconnects 422b, and a second die interconnect from integrated device 403. Electrical path 404 may be configured to provide an electrical path for power supply or grounding.

[0132] The electrical path between integrated device 405 and board 108 may include electrical path 412. Electrical path 412 may include board interconnects from multiple board interconnects 182, solder interconnects from multiple solder interconnects 110, a third plurality of metallized interconnects 422c, and a first die interconnect from integrated device 405. Electrical path 412 may be configured to provide an electrical path for input / output signals.

[0133] The electrical path between integrated device 405 and board 108 may include electrical path 414. Electrical path 414 may include another board interconnect from multiple board interconnects 182, another solder interconnect from multiple solder interconnects 110, a fourth plurality of metallized interconnects 422d, and a second die interconnect from integrated device 405. Electrical path 414 may be configured to provide an electrical path for power supply or grounding.

[0134] In some implementations, the electrical path between integrated device 405 and integrated device 403 may include die interconnects from integrated device 405, at least one metallized interconnect from a plurality of metallized interconnects 422, and die interconnects from integrated device 403.

[0135] Note that different portions of the metallized portion of the package may have different minimum interconnect thicknesses, minimum line and space dimensions, and minimum pitches. In one example, the metallized portion may have a global set of the same minimum interconnect thickness, minimum line and space dimensions, and / or minimum pitch. In another example, the metallized portion includes (i) a first set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches, and (ii) a second set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches. For example, the second set of minimum interconnect thicknesses, minimum line and space dimensions, and / or minimum pitches may be located in a region of the metallized portion that perpendicularly overlaps with one or more integrated devices. Some minimum dimensions may be local minimum dimensions of the metallized portion. Some of these minimum dimensions may be global dimensions of the metallized portion. Therefore, different portions of the metallized portion may have different minimum interconnect thicknesses, different minimum line and space dimensions, and / or different minimum pitches.

[0136] Exemplary process for manufacturing a package including integrated devices and metallized portions.

[0137] Figures 9A-9C Exemplary steps for providing or manufacturing a package comprising integrated devices and metallized portions of metallized interconnects with varying thicknesses are described. In some implementations, Figure 9A -9C processes can be used for supplying or manufacturing. Figure 8 The package 800, or any package described in this disclosure.

[0138] It should be noted that Figures 9A-9C The processes may be combined in one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. Figures 9A-9C The process can be used to manufacture one package or several packages (as part of a chip) at a time.

[0139] like Figure 9A As shown, stage 1 illustrates the state after the carrier 500 and adhesive coating 501 are provided. Adhesive coating 501 may be an adhesive layer located on the surface of the carrier 500.

[0140] Phase 2 describes the state of integrated devices 403 and 405 after they have been placed on the carrier 500 and the adhesive coating 501. Pick-and-place processes can be used to place the integrated devices. The front sides of integrated devices 403 and 405 can be placed on the carrier 500 and the adhesive coating 501.

[0141] Phase 3 describes the state after the encapsulation layer 106 is formed over the carrier 500, adhesive coating 501, integrated device 403, and integrated device 405. The encapsulation layer 106 encapsulates the integrated device 103. The encapsulation layer 106 may include molding materials, resin, and / or epoxy resin. The encapsulation layer 106 may be a device for encapsulation. The encapsulation layer 106 can be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 can be removed. For example, a polishing process can be used to remove the top of the encapsulation layer 106, the back side of the integrated device 403, and / or the back side of the integrated device 405.

[0142] Phase 4 describes the state after the carrier 500 and adhesive coating 501 are decoupled from the integrated device 403, integrated device 405 and encapsulation layer 106. The carrier 500 and adhesive coating 501 can then be separated from the integrated device 403, integrated device 405 and encapsulation layer 106.

[0143] like Figure 5B As shown, stage 5 explains that integrated device 403, integrated device 405, and encapsulation layer 106 are placed on carrier 502. The back sides of integrated device 403 and integrated device 405 can be placed and coupled to carrier 502. An adhesive coating similar to adhesive coating 501 may be present on carrier 502. Pick-and-place processes can be used to place integrated device 403, integrated device 405, and encapsulation layer 106 on carrier 502.

[0144] Phase 6 describes the state after bridge 808 is coupled to integrated devices 403 and 405. Bridge 808 can be coupled to integrated devices 403 and / or 405 via hybrid bonding (e.g., copper-to-copper bonding, interconnect-to-interconnect bonding, metal-to-metal bonding). In some implementations, bridge 808 can be coupled to integrated devices 403 and / or 405 via at least a plurality of solder interconnects (not shown). The front side of integrated device 403 and the front side of integrated device 405 may face bridge 808. Bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. Bridge 808 may include at least one dielectric layer 884. In some implementations, bridge 808 may be a silicon bridge. Bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to die pads (e.g., 430) of integrated device 403 and die pads (e.g., 450) of integrated device 405.

[0145] Phase 7 describes the state after the metallization portion 402 is formed over integrated device 403, integrated device 405, bridge 808, and encapsulation layer 106. The metallization portion 402 may include at least one dielectric layer 420 and a plurality of metallized interconnects 422. Bridge 808 may be at least partially located in the metallization portion 402 and / or at least partially surrounded by at least one dielectric layer 420 of the metallization portion 402. Figure 5B Stage 6 to Figure 5H Stage 26 explains and describes an example of the process of forming the metallized part.

[0146] Phase 8 explains the state after the carrier 502 is decoupled from the integrated device 403, integrated device 405 and encapsulation layer 106. The carrier 502 can then be separated from the integrated device 403, integrated device 405 and encapsulation layer 106.

[0147] Phase 9 describes the state after multiple solder interconnects 110 are coupled to the metallization portion 402. A solder reflow process can be used to couple the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0148] An exemplary flowchart of a method for manufacturing a package including integrated devices and metallized portions.

[0149] In some implementations, manufacturing the package involves several processes. Figure 10 An exemplary flowchart of a method 1000 for providing or manufacturing a package is illustrated. In some implementations, Figure 10 Method 1000 can be used to provide or manufacture any package disclosed herein. For example, Figure 10 Method 1000 can be used to manufacture package 800.

[0150] It should be noted that Figure 10 Method 1000 may combine one or more processes to simplify and / or clarify the methods used to provide or manufacture the package. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this disclosure. Figure 10 Method 1000 can be used to manufacture one or more packages at a time (as part of a wafer and / or panel).

[0151] This method (in 1005) provides a carrier. In some implementations, the carrier may be provided with an adhesive. Figure 9A Phase 1 explains and describes an example of providing a carrier 500 and an adhesive coating 501. The adhesive coating 501 may be an adhesive layer located on the surface of the carrier 500.

[0152] The method (in 1010) places the front sides of the first integrated device and the front sides of the second integrated device on a carrier. In some implementations, the front sides of the integrated devices are placed on a carrier comprising an adhesive. In some implementations, two or more integrated devices may be placed on the carrier. Figure 9A Phase 2 explains and describes examples of integrated devices 403 and 405 placed on carrier 500 and adhesive coating 501. Pick-and-place processes can be used to place integrated devices. The front sides of integrated devices 403 and 405 can be placed on carrier 500 and adhesive coating 501.

[0153] This method (at 1015) forms an encapsulation layer for encapsulating the integrated device. The encapsulation layer can be coupled to the integrated device and the carrier. Figure 9A Phase 3 explains and describes an example of an encapsulation layer 106 formed over a carrier 500, an adhesive coating 501, an integrated device 403, and an integrated device 405. The encapsulation layer 106 may encapsulate the integrated devices 403 and 405. The encapsulation layer 106 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 106 may be a device for encapsulation. The encapsulation layer 106 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes. In some implementations, once the encapsulation layer 106 is provided, portions of the encapsulation layer 106 may be removed. For example, a polishing process may be used to remove the top of the encapsulation layer 106, the back side of the integrated device 403, and / or the back side of the integrated device 405.

[0154] This method (in 1020) decouples the carrier from the encapsulation layer and the integrated device. Figure 9A Phase 4 explains and describes an example of carrier 500 and adhesive coating 501 decoupled from integrated device 403, integrated device 405 and encapsulation layer 106. Carrier 500 and adhesive coating 501 can be separated from integrated device 403, integrated device 405 and encapsulation layer 106.

[0155] The method (in 1025) places the back side of the integrated device and the encapsulation layer on top of another carrier (e.g., a second carrier). The carrier may include an adhesive. Figure 9B Phase 5 explains and describes examples of integrated devices 403, 405, and encapsulation layer 106 placed on carrier 502. The back sides of integrated devices 403 and 405 can be placed and coupled to carrier 502. An adhesive coating similar to adhesive coating 501 may be present on carrier 502. Pick-and-place processes can be used to place integrated devices 403, 405, and encapsulation layer 106 on carrier 502.

[0156] This method (at 1030) couples a bridge to an integrated device. For example, bridge 808 is coupled to integrated devices 403 and 405. Bridge 808 can be coupled to integrated devices 403 and / or 405 via hybrid bonding (e.g., copper-to-copper bonding, interconnect-to-interconnect bonding, metal-to-metal bonding). In some implementations, bridge 808 can be coupled to integrated devices 403 and / or 405 via at least a plurality of solder interconnects. The front side of integrated device 403 and the front side of integrated device 405 may face bridge 808. Bridge 808 may include a bridge substrate 880 and a plurality of bridge interconnects 882. Bridge 808 may include at least one dielectric layer 884. In some implementations, bridge 808 may be a silicon bridge. Bridge substrate 880 may include silicon. The plurality of bridge interconnects 882 may be coupled to die pads (e.g., 430) of integrated device 403 and die pads (e.g., 450) of integrated device 405. Figure 9B Phase 6 explains and describes an example of coupling a bridge to an integrated device.

[0157] The method (at 1035) forms a metallized portion coupled to the front side and encapsulation layer of an integrated device. The metallized portion may at least partially surround and / or encapsulate a bridge. The metallized portion may include at least one dielectric layer and a plurality of metallized interconnects. The plurality of metallized interconnects may include a first metallized interconnect on a first metal layer and a second metallized interconnect on the first metal layer, wherein the second interconnect has a second thickness different from the first metallized interconnect's first thickness. Forming the metallized portion may include forming at least one dielectric layer, forming the first metallized interconnect on the first metal layer, and forming the second metallized interconnect on the first metal layer. The second interconnect may have a second thickness different from the first metallized interconnect's first thickness. Figure 9C Phase 7 explains and describes examples of the process for forming metallized portions on integrated devices and bridges (e.g., 808). Figure 5B Stage 6 to Figure 5H Stage 26 illustrates an example of forming a metallization portion coupled to at least one integrated device. Different implementations may have different numbers of metal layers. Once the metallization portion is formed (at 1035), the method can decouple the second carrier from the integrated device and the encapsulation layer.

[0158] This method (in 1040) couples multiple solder interconnects to the metallized interconnects of the metallized portion. Figure 9C Phase 9 explains and describes an example of multiple solder interconnects 110 coupled to the metallization portion 202. A solder reflow process can be used to couple the multiple solder interconnects 110 to the multiple metallization interconnects 222 of the metallization portion 202.

[0159] Exemplary electronic devices

[0160] Figure 11This describes various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, PoP (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 1102, laptop computer device 1104, fixed-location terminal device 1106, wearable device 1108, or motor vehicle 1110 may include device 1100 as described herein. Device 1100 can be any of the devices and / or integrated circuit (IC) packages described herein. Figure 11 The devices 1102, 1104, 1106, and 1108, as well as vehicle 1110, described herein are merely exemplary. Other electronic devices may also feature device 1100, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0161] Figure 1-4 One or more of the components, processes, features, and / or functions described in 5A-5H, 6-8, 9A-9C, and / or 10-11 may be rearranged and / or combined into a single component, process, feature, or function, or implemented in several components, processes, or functions. Additional elements, components, processes, and / or functions may also be added without departing from this disclosure. It should also be noted that... Figure 1-4 5A-5H, 6-8, 9A-9C and / or 10-11, and their corresponding descriptions in this disclosure, are not limited to dies and / or ICs. In some implementations, Figure 1-4 5A-5H, 6-8, 9A-9C and / or 10-11 and their corresponding descriptions may be used to manufacture, create, provide, and / or produce devices and / or integrated devices. In some implementations, devices may include dies, integrated devices, integrated passive devices (IPDs), die packages, integrated circuit (IC) devices, device packages, integrated circuit (IC) packages, wafers, semiconductor devices, stacked package (PoP) devices, thermal devices and / or interposers.

[0162] It should be noted that the accompanying drawings in this disclosure may represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all components and / or parts are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various parts and / or components in the drawings may be exemplary. In some implementations, the various components and / or parts in the drawings may be optional.

[0163] The term “exemplary” is used herein to mean “serving as an example, instance, or illustration.” Any implementation or aspect described herein as “exemplary” is not necessarily to be construed as superior to or better than other aspects of this disclosure. Similarly, the term “aspect” does not require that all aspects of this disclosure include the features, advantages, or modes of operation discussed. The term “coupled” is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A is physically in contact with object B, and object B is in contact with object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. The term “electrically coupled” can mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power supply, ground) can be transmitted between the two objects. Electrically coupled objects may or may not have current transmitted between them. The use of the terms “first,” “second,” “third,” and “fourth” (and / or anything above fourth) is arbitrary. Any component described can be a first component, a second component, a third component, or a fourth component. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. The term “enclosing” means that an object may partially enclose or completely enclose another object. A first component “located” within a second component can mean that the first component is “partially located” within or “completely located” within the second component. A first component “embedded” within a second component can mean that the first component is “partially embedded” within or “completely embedded” within the second component. The terms “top” and “bottom” are arbitrary. A component located at the top can be on top of a component located at the bottom. A top component can be considered a bottom component, and vice versa. As described in this disclosure, a first component located “above” a second component can mean that the first component is located above or below the second component, depending on how bottom or top is arbitrarily defined. In another example, a first component may be located above (e.g., above) a first surface of a second component, while a third component may be located above (e.g., below) a second surface of a second component, where the second surface is opposite the first surface. It should be further noted that the term “above,” as used in this application in the context of one component being above another, can be used to mean that a component is on and / or within another component (e.g., on the surface of a component or embedded within a component). Thus, for example, the first component being on the second component can mean: (1) the first component is on the second component but does not directly contact the second component; (2) the first component is on the second component (e.g., on the surface of the second component); and / or (3) the first component is in the second component (e.g., embedded in the second component). A first component located “in” the second component may be partially or completely located in the second component. As used in this disclosure, the terms “about 'value X'” or “approximately value X” mean within ten percent of 'value X'.For example, a value of approximately 1 or roughly 1 would mean a value in the range of 0.9-1.1.

[0164] In some implementations, an interconnect is a element or component in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, solder pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or component. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0165] It should also be noted that the various disclosures contained herein can be described as processes depicted as flowcharts, flow diagrams, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. A process terminates when its operations are completed.

[0166] Further examples are described below to facilitate understanding of the invention.

[0167] Aspect 1: A package comprising: an integrated device; a substrate coupled to the integrated device via at least a first plurality of solder interconnects; and a metallized portion coupled to the substrate via at least a second plurality of solder interconnects. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects including a first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and a second metallized interconnect located on the first metal layer, wherein the second metallized interconnect includes a second thickness different from the first thickness.

[0168] Aspect 2: The package as described in aspect 1, wherein the second thickness is greater than the first thickness.

[0169] Aspect 3: The package as in aspect 2, wherein the second thickness is at least 1.2 times greater than the first thickness.

[0170] Aspect 4: The package as described in Aspects 1 to 3, wherein the plurality of metallized interconnects includes a third metallized interconnect located on a second metal layer; a fourth metallized interconnect located on a second metal layer; a first via metallized interconnect coupled to the first metallized interconnect and the third metallized interconnect, wherein the first via metallized interconnect includes a first via height; and a second via metallized interconnect coupled to the second metallized interconnect and the fourth metallized interconnect, wherein the second via metallized interconnect includes a second via height different from the first via height.

[0171] Aspect 5: The package as described in aspect 4, wherein the second thickness is greater than the first thickness, and wherein the height of the first through-hole is greater than the height of the second through-hole.

[0172] Aspect 6: The package as described in aspects 4 to 5, wherein the second metal layer is adjacent to the first metal layer.

[0173] Aspect 7: Packages as described in Aspects 4 to 6, wherein a first through-hole metallized interconnect includes a first minimum diameter, and wherein a second through-hole metallized interconnect includes a second minimum diameter greater than the first minimum diameter.

[0174] Aspect 8: Packages as described in aspects 4 to 7, wherein the third metallization interconnect includes a third thickness, and wherein the fourth metallization interconnect includes a fourth thickness greater than the third thickness.

[0175] Aspect 9: The package as described in Aspects 4 to 8, wherein the plurality of metallized interconnects includes a fifth metallized interconnect located on a third metal layer, wherein the fifth metallized interconnect includes a fifth thickness; a sixth metallized interconnect located on the third metal layer, wherein the sixth metallized interconnect includes a sixth thickness greater than the fifth thickness; a third via metallized interconnect coupled to the fifth metallized interconnect and the third metallized interconnect, wherein the third via metallized interconnect includes a third via height; and a fourth via metallized interconnect coupled to the sixth metallized interconnect and the fourth metallized interconnect, wherein the fourth via metallized interconnect includes a fourth via height different from the third via height.

[0176] Aspect 10: Packages as described in Aspects 4 to 9, wherein the first metallized interconnect, the first through-hole metallized interconnect, and the third metallized interconnect are part of an electrical path for input / output signals to and / or from the integrated device, and wherein the second metallized interconnect, the second through-hole metallized interconnect, and the fourth metallized interconnect are part of an electrical path for supplying power to the integrated device.

[0177] Aspect 11: Packages as described in aspects 1 to 10, wherein the substrate includes an interposer comprising a plurality of interconnected interposers.

[0178] Aspect 12: The package as described in aspects 1 to 11 further includes: a second integrated device coupled to the substrate via at least a third plurality of solder interconnects, wherein the integrated device is a first chip and wherein the second integrated device is a second chip.

[0179] Aspect 13: The package of aspect 12, wherein the plurality of metallized interconnects includes a first plurality of metallized interconnects, the first plurality of metallized interconnects including a first minimum thickness, a first minimum spacing, a first minimum pitch and / or a first minimum width, wherein the first plurality of metallized interconnects includes interconnects perpendicularly overlapping with a first integrated device and a second integrated device; and a second plurality of metallized interconnects, the second plurality of metallized interconnects including a second minimum thickness, a second minimum spacing, a second minimum pitch and / or a second minimum width, wherein the metallized portion includes a redistributed portion, wherein the first metallized interconnect includes a first redistributed interconnect, and wherein the second metallized interconnect includes a second redistributed interconnect.

[0180] Aspect 14: A package comprising: a first integrated device, a second integrated device, a bridge coupled to the first integrated device and the second integrated device; and a metallized portion coupled to the first integrated device and / or the second integrated device. The metallized portion includes at least one dielectric layer; and a plurality of metallized interconnects including a first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and a second metallized interconnect located on the first metal layer, wherein the second metallized interconnect includes a second thickness different from the first thickness.

[0181] Aspect 15: Package as in aspect 14, wherein the second thickness is greater than the first thickness.

[0182] Aspect 16: The package as described in aspect 15, wherein the second thickness is at least 1.2 times greater than the first thickness.

[0183] Aspect 17: The package as described in Aspects 14 to 16, wherein the plurality of metallized interconnects includes a third metallized interconnect located on a second metal layer; a fourth metallized interconnect located on a second metal layer; a first via metallized interconnect coupled to the first metallized interconnect and the third metallized interconnect, wherein the first via metallized interconnect includes a first via height; and a second via metallized interconnect coupled to the second metallized interconnect and the fourth metallized interconnect, wherein the second via metallized interconnect includes a second via height different from the first via height.

[0184] Aspect 18: The package as in aspect 17, wherein the second thickness is greater than the first thickness, and wherein the height of the first through-hole is greater than the height of the second through-hole.

[0185] Aspect 19: The package as described in Aspects 17 to 18, wherein the first through-hole metallized interconnect includes a first maximum diameter, and wherein the second through-hole metallized interconnect includes a second maximum diameter smaller than the first maximum diameter.

[0186] Aspect 20: Package as described in aspects 14 to 19, wherein the bridge is located in the metallized portion.

[0187] Aspect 21: Package as in aspect 20, wherein the bridge comprises a silicon-based bridge.

[0188] Aspect 22: The package as described in aspects 20 to 21, wherein the first integrated device and the second integrated device are configured to be electrically coupled to each other via an electrical path including a bridge.

[0189] Aspect 23: Packages as described in Aspects 20 to 22, wherein the bridge includes a silicon-based bridge, wherein the first integrated device includes a first technology node, and wherein the second integrated device includes a second technology node.

[0190] Aspect 24: The package as described in aspects 14 to 23, wherein the plurality of metallized interconnects includes a first plurality of metallized interconnects, the first plurality of metallized interconnects including a first minimum thickness, a first minimum spacing, a first minimum pitch and / or a first minimum width; and a second plurality of metallized interconnects, the second plurality of metallized interconnects including a second minimum thickness, a second minimum spacing, a second minimum pitch and / or a second minimum width.

[0191] Aspect 25: Package as in aspect 24, wherein the first plurality of metallized interconnects includes interconnects that vertically overlap with the first integrated device and the second integrated device.

[0192] Aspect 26: The package as described in aspects 14 to 25, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0193] The various features of this disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of aspects of this disclosure is intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings of this disclosure can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

Claims

1. A package, comprising: Integrated devices; The substrate of the integrated device is coupled to it via at least a first plurality of solder interconnects; as well as Metallized portions coupled to the substrate via at least a second plurality of solder interconnects, the metallized portions comprising: At least one dielectric layer; and Multiple metallized interconnects, the multiple metallized interconnects including: A first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and A second metallized interconnect located on the first metal layer, wherein the second metallized interconnect has a second thickness different from the first thickness.

2. The package as claimed in claim 1, wherein the second thickness is greater than the first thickness.

3. The package of claim 2, wherein the second thickness is at least 1.2 times greater than the first thickness.

4. The package of claim 1, wherein the plurality of metallized interconnects comprises: The third metallization interconnect is located on the second metal layer; The fourth metallized interconnect is located on the second metal layer; A first via metallized interconnect coupled to the first metallized interconnect and the third metallized interconnect, wherein the first via metallized interconnect includes a first via height; as well as A second via metallized interconnect coupled to the second metallized interconnect and the fourth metallized interconnect, wherein the second via metallized interconnect includes a second via height different from the first via height.

5. The packaging as described in claim 4, Wherein the second thickness is greater than the first thickness, and The height of the first through hole is greater than the height of the second through hole.

6. The package of claim 4, wherein the second metal layer is adjacent to the first metal layer.

7. The packaging as described in claim 4, The first through-hole metallized interconnect includes a first minimum diameter, and The second through-hole metallization interconnect includes a second minimum diameter that is larger than the first minimum diameter.

8. The packaging as described in claim 4, The third metallized interconnect includes a third thickness, and The fourth metallized interconnect includes a fourth thickness greater than the third thickness.

9. The package of claim 4, wherein the plurality of metallized interconnects comprises: A fifth metallized interconnect located on a third metal layer, wherein the fifth metallized interconnect includes a fifth thickness; A sixth metallized interconnect located on the third metal layer, wherein the sixth metallized interconnect includes a sixth thickness greater than the fifth thickness; A third via metallized interconnect coupled to the fifth metallized interconnect and the third metallized interconnect, wherein the third via metallized interconnect includes a third via height; as well as A fourth via metallized interconnect coupled to the sixth metallized interconnect and the fourth metallized interconnect, wherein the fourth via metallized interconnect includes a fourth via height different from the height of the third via.

10. The packaging as described in claim 4, The first metallized interconnect, the first through-hole metallized interconnect, and the third metallized interconnect are part of the electrical path for input / output signals to and / or from the integrated device, and The second metallized interconnect, the second through-hole metallized interconnect, and the fourth metallized interconnect are part of an electrical path for supplying power to the integrated device.

11. The package of claim 1, wherein the substrate includes an interposer comprising a plurality of interconnected interposers.

12. The packaging as claimed in claim 1, further comprising: A second integrated device is coupled to the substrate via at least a third or more solder interconnects. The integrated device is the first chip, and The second integrated device is the second chip.

13. The package of claim 12, wherein the plurality of metallized interconnects comprises: A first plurality of metallized interconnects, the first plurality of metallized interconnects including a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width, wherein the first plurality of metallized interconnects includes interconnects perpendicularly overlapping with the first integrated device and / or the second integrated device; and The second plurality of metallized interconnects includes a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width. The metallized portion includes a redistribution portion. The first metallized interconnect includes a first redistributed interconnect, and The second metallized interconnect includes a second redistributed interconnect.

14. A package comprising: First integrated device; Second integrated device; A bridge coupled to the first integrated device and the second integrated device; as well as Metallization portions coupled to the first integrated device and the second integrated device, wherein the metallization portions include: At least one dielectric layer; and Multiple metallized interconnects, the multiple metallized interconnects including: A first metallized interconnect located on a first metal layer, wherein the first metallized interconnect includes a first thickness; and A second metallized interconnect located on the first metal layer, wherein the second metallized interconnect has a second thickness different from the first thickness.

15. The package of claim 14, wherein the second thickness is greater than the first thickness.

16. The package of claim 15, wherein the second thickness is at least 1.2 times greater than the first thickness.

17. The package of claim 14, wherein the plurality of metallized interconnects comprises: The third metallization interconnect is located on the second metal layer; The fourth metallized interconnect is located on the second metal layer; A first via metallized interconnect coupled to the first metallized interconnect and the third metallized interconnect, wherein the first via metallized interconnect includes a first via height; as well as A second via metallized interconnect coupled to the second metallized interconnect and the fourth metallized interconnect, wherein the second via metallized interconnect includes a second via height different from the first via height.

18. The packaging as described in claim 17, Wherein the second thickness is greater than the first thickness, and The height of the first through hole is greater than the height of the second through hole.

19. The packaging as described in claim 17, The first through-hole metallized interconnect includes a first maximum diameter, and The second via metallized interconnect includes a second maximum diameter smaller than the first maximum diameter.

20. The package of claim 14, wherein the bridge is located in the metallized portion.

21. The package of claim 20, wherein the bridge comprises a silicon-based bridge.

22. The package of claim 20, wherein the first integrated device and the second integrated device are configured to be electrically coupled to each other via an electrical path including the bridge.

23. The package of claim 20, wherein the bridge comprises a silicon-based bridge. The first integrated device includes a first technology node, and The second integrated device includes a second technology node.

24. The package of claim 14, wherein the plurality of metallized interconnects comprises: The first plurality of metallized interconnects includes a first minimum thickness, a first minimum spacing, a first minimum pitch, and / or a first minimum width; as well as The second plurality of metallized interconnects includes a second minimum thickness, a second minimum spacing, a second minimum pitch, and / or a second minimum width.

25. The package of claim 24, wherein the first plurality of metallized interconnects includes interconnects that perpendicularly overlap with the first integrated device and the second integrated device.

26. The package of claim 14, wherein the package is implemented in a device selected from the group consisting of: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptop computers, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

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