Semiconductor package and manufacturing method thereof

Abstract

The present invention relates to a semiconductor package comprising: a first substrate; a plurality of semiconductor chips disposed above the first substrate; and a connection structure disposed between at least one of the plurality of semiconductor chips and the first substrate and electrically connecting at least two or more semiconductor chips arranged in a horizontal direction among the plurality of semiconductor chips. The connection structure includes a conductive layer directly connected to the semiconductor chip, a plurality of connection members electrically connected to the first substrate, and a wiring layer disposed between the conductive layer and the plurality of connection members.

Description

Technical Field

[0001] This invention relates to semiconductor packaging and manufacturing methods thereof, and more specifically, to semiconductor packaging and manufacturing methods thereof that enable miniaturization and further reduce manufacturing costs. Background Technology

[0002] A semiconductor chip is an integrated circuit made of semiconductors with conductivity higher than that of insulators but lower than that of conductors.

[0003] Typically, after a semiconductor chip is separated from its single-crystal substrate, i.e., a wafer, a packaging process is required. This is to protect the semiconductor chip from physical impact and to mitigate integration differences between the semiconductor chip and the substrate to be mounted, thereby improving ease of installation. The finished product of this packaged semiconductor chip is called a semiconductor package.

[0004] This type of semiconductor package can house multiple semiconductor chips. Based on the arrangement of the installed semiconductor chips, it can be classified as 2D, 2.5D, 3D, etc. Among them, 2.5D semiconductor packaging refers to a package in which logic chips are arranged horizontally and memory chips are stacked vertically.

[0005] In addition, in 2.5D semiconductor packaging, to improve the connectivity between the substrate and the semiconductor chip (i.e., the die), an interposer or a bridge die can be placed between the substrate and the semiconductor chip. In this case, the semiconductor chip can be electrically connected to the substrate through the interposer or the bridge die.

[0006] However, existing interposers or bridging dies are expensive to manufacture and hinder the miniaturization of semiconductor packages. Therefore, methods to address these issues are needed. Summary of the Invention

[0007] The problem the invention aims to solve

[0008] The purpose of this invention is to solve the above-mentioned problems and other problems. Another purpose is to provide a miniaturized semiconductor package and a method for manufacturing the same.

[0009] Another objective is to provide a semiconductor package and its manufacturing method that can simplify the manufacturing process.

[0010] Another objective is to provide a semiconductor package and its manufacturing method that can reduce manufacturing costs.

[0011] means for solving problems

[0012] To achieve the above or other objectives, according to one aspect of the present invention, a semiconductor package is provided, characterized in that it comprises: a first substrate; a plurality of semiconductor chips disposed above the first substrate; and a connection structure disposed between at least one of the plurality of semiconductor chips and the first substrate, electrically connecting at least two or more of the plurality of semiconductor chips arranged in a horizontal direction; the connection structure includes a conductive layer, a plurality of connection members, and a wiring layer, the conductive layer being directly connected to the semiconductor chips, the plurality of connection members being electrically connected to the first substrate, and the wiring layer being disposed between the conductive layer and the plurality of connection members.

[0013] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, comprising: a step of disposing of a plurality of first posts on a first substrate; a step of mounting a connection structure in adjacent regions of the plurality of first posts; a step of disposing of a molding member on the first substrate, the plurality of first posts, and the connection structure; a step of removing an upper region of the molding member and a second substrate of the connection structure, thereby exposing the conductive layers of the plurality of first posts and the connection structure to the outside; a step of mounting a plurality of semiconductor chips on the plurality of first posts and the connection structure; a step of disposing of a protective member above the plurality of semiconductor chips; and a step of attaching an external connection member to the bottom surface of the first substrate.

[0014] According to another aspect of the present invention, a method for manufacturing a semiconductor package is provided, comprising: mounting a connection structure on a first substrate; disposing a molding member on the first substrate and the connection structure; removing an upper region of the molding member and a second substrate of the connection structure to expose a conductive layer of the connection structure to the outside; mounting a plurality of semiconductor chips on the connection structure exposing the conductive layer; disposing a protective member above the plurality of semiconductor chips; and attaching an external connection member to the bottom surface of the first substrate.

[0015] Invention Effects

[0016] The effects of the semiconductor packaging and manufacturing method of the present invention are explained below.

[0017] According to at least one embodiment of the present invention, more than one semiconductor chip can be protected from physical impact, and the integration difference between the semiconductor chip and the substrate on which it is to be mounted can be mitigated, thereby increasing the ease of installation.

[0018] Furthermore, according to at least one embodiment of the present invention, by configuring a plurality of first post and small-scale connection structures between the first substrate and the semiconductor chip, not only can the miniaturization of the semiconductor package be achieved, but the manufacturing process of the semiconductor package can also be simplified, thereby reducing manufacturing costs.

[0019] Furthermore, according to at least one embodiment of the present invention, by configuring a large-scale interconnect structure between the first substrate and the semiconductor chip, the manufacturing process of the semiconductor package can be simplified to reduce manufacturing costs and improve the wiring integration of the semiconductor package.

[0020] In addition, according to at least one embodiment of the present invention, a connection structure is provided using fan-out technology. The connection structure not only realizes the electrical connection between a plurality of semiconductor chips arranged in a horizontal direction, but also realizes the electrical connection between a first substrate arranged in a vertical direction and the semiconductor chips, thereby enabling easy transfer of power and signal between the first substrate and the plurality of semiconductor chips, and improving the power efficiency of the semiconductor package.

[0021] The technical effects achieved by this invention are not limited to those mentioned above. Those skilled in the art to which this invention pertains can clearly understand other technical effects not mentioned from the following description. Attached Figure Description

[0022] Figure 1a This is a diagram illustrating the structure of a semiconductor package according to a first embodiment of the present invention.

[0023] Figure 1b It is shown Figure 1a The diagram shows the structure of the connecting structure.

[0024] Figure 2 This is a flowchart illustrating a semiconductor package manufacturing method according to a first embodiment of the present invention.

[0025] Figures 3a to 3g This is a reference figure used to illustrate the manufacturing method of a semiconductor package according to the first embodiment of the present invention.

[0026] Figure 4a This is a diagram illustrating the structure of a semiconductor package according to a second embodiment of the present invention.

[0027] Figure 4b It is shown Figure 4a The diagram shows the structure of the connecting structure.

[0028] Figure 5 This is a flowchart illustrating a semiconductor package manufacturing method according to a second embodiment of the present invention.

[0029] Figures 6a to 6g This is a reference figure used to illustrate the manufacturing method of a semiconductor package according to the second embodiment of the present invention.

[0030] Figure 7 This is a diagram illustrating the structure of a semiconductor package according to a third embodiment of the present invention.

[0031] Figure 8 This is a diagram illustrating the structure of a semiconductor package according to a fourth embodiment of the present invention.

[0032] Figure 9 This is a diagram illustrating the structure of a semiconductor package according to a fifth embodiment of the present invention.

[0033] Figure 10 This is a flowchart illustrating a method for manufacturing a connection structure according to an embodiment of the present invention.

[0034] Figures 11a to 11h This is a reference figure used to illustrate a method for manufacturing a connection structure according to an embodiment of the present invention.

[0035] Figure 12 This is a flowchart illustrating a method for manufacturing a connection structure according to another embodiment of the present invention.

[0036] Figures 13a to 13g This is a reference figure used to illustrate a method for manufacturing a connection structure according to another embodiment of the present invention. Detailed Implementation

[0037] Hereinafter, embodiments disclosed in this specification will be described in detail with reference to the accompanying drawings. However, unlike the reference numerals, the same or similar structural elements are given the same reference numerals, and repeated descriptions thereof are omitted. In describing embodiments according to the present invention, when referring to layers (films), regions, patterns, or structures formed on a substrate, layers (films), regions, pads, or patterns as "on" or "under," "on" and "under" include all cases of formation "directly" or "indirectly" via other layers. Furthermore, the references to the above / above or below / under each layer are explained with reference to the accompanying drawings. The thickness or size of each layer in the drawings is exaggerated, omitted, or shown approximated for ease of explanation and clarity. Furthermore, the sizes of the constituent elements do not perfectly reflect the actual dimensions. The same reference numerals refer to the same constituent elements.

[0038] In this specification, when it is mentioned that a constituent element (or region, layer, part, etc.) is located "on" or "connected" or "combined" with other constituent elements, it means that a third constituent element can be directly configured / connected / combined with other constituent elements or configured between them. Furthermore, in this specification, terms such as "comprising" or "having" are intended to specify the presence of features, numbers, steps, actions, constituent elements, components, or combinations thereof described in the specification, rather than pre-excluding the presence or additional possibilities of more than one other feature, number, step, action, constituent element, component, or combination thereof.

[0039] The terms "first," "second," etc., can be used to describe various constituent elements, but the constituent elements are not limited to these terms. These terms are used only to distinguish one constituent element from another. For example, without departing from the scope of this invention, a first constituent element may be named a second constituent element, and similarly, a second constituent element may be named a first constituent element. Unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0040] Furthermore, when describing the embodiments disclosed in this specification, if it is determined that the specific description of relevant prior art may obscure the main idea of ​​the embodiments disclosed in this specification, its detailed description will be omitted. In addition, the accompanying drawings are only for the purpose of facilitating the understanding of the embodiments disclosed in this specification. The technical ideas disclosed in this specification should not be limited by the accompanying drawings, and should be understood to include all modifications, equivalents, and even substitutions that fall within the scope of the inventive concept and technology.

[0041] This invention proposes a semiconductor package capable of miniaturization and a method for manufacturing the same. Furthermore, this invention proposes a semiconductor package and a method for manufacturing the same that simplifies the manufacturing process. Additionally, this invention proposes a semiconductor package and a method for manufacturing the same that reduces manufacturing costs.

[0042] Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0043] Figure 1a This is a diagram illustrating the structure of a semiconductor package according to a first embodiment of the present invention. Figure 1b It is shown Figure 1a The diagram shows the structure of the connecting structure.

[0044] Reference Figure 1a and Figure 1b The semiconductor package 100 of the first embodiment of the present invention may include a first substrate 110, a first guide post 120, a connecting structure 130, a reinforcing plate 140, a molding component 150, a semiconductor chip 160, a protective component 170, and an external connecting component 180. Figure 1aThe components shown are not essential for realizing a semiconductor package. The semiconductor package described in this specification may have more or fewer components than those listed above.

[0045] The first substrate 110 can serve to mount various electronic components. The first substrate 110 can be a printed circuit board (PCB), a flexible PCB substrate, an IC substrate, etc., but is not limited to these. In the following embodiment, the case where a PCB substrate is used as the first substrate 110 will be described as an example.

[0046] The printed circuit board 110 can be formed from an organic PCB. Electronic components such as integrated circuits, resistors, or switches can be mounted on this printed circuit board 110.

[0047] The printed circuit board 110 may include wiring circuitry for electrical connections between electronic components. Additionally, one or more passive components may be mounted on the upper and / or lower surfaces of the printed circuit board 110.

[0048] On the other hand, although not illustrated, the printed circuit board 110 may have an integrated passive device (IPD) built into it. Additionally, the printed circuit board 110 may have a cavity structure for mounting the connection structure 130. The depth of the cavity structure can be from 50µm to 200µm. The connection structure can be mounted and electrically connected to the conductive layer of the printed circuit board 110 located at the lower part of the cavity structure. The upper part of the conductive layer of the connection structure mounted in the cavity structure can be directly connected to the semiconductor chip in an exposed state, without any additional circuit layers or redistribution layers in between.

[0049] The first guide post 120 can be disposed on one side of the first substrate 110. As an example, a plurality of first guide posts 120 can be formed on the wiring circuit of the first substrate 110.

[0050] The first guide post 120 can be formed to extend vertically from the top surface of the first substrate 110. In this case, the first guide post 120 can be formed to have a constant width of cross-sectional area or to have a gradually increasing width of cross-sectional area in the upward direction.

[0051] The first guide post 120 can be formed to have a predetermined height. Additionally, the upper end of the first guide post 120 can be formed by a grinding process. The first guide post 120 can be formed on the first substrate 110 to have a diameter of 20µm to 100µm, a height of 50µm to 300µm, and a pitch of 50µm to 200µm.

[0052] The first guide post 120 can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). An insulating material can be coated around the first guide post 120. The first guide post 120 can be directly formed on the first substrate 110 in the form of a Cu post, Cu pin, or TMV (Through Mold Via), or it can be first formed in the form of a Cu post, Cu pin, or TMV (Through Mold Via) and then disposed on the first substrate 110.

[0053] The first guide post 120 can be configured to contact the wiring circuit of the first substrate 110 for electrical connection. Alternatively, the first guide post 120 can be configured to contact the semiconductor chip 160 for electrical connection. Thus, the first substrate 110 can be electrically connected to the semiconductor chip 160 via the first guide post 120. In particular, the semiconductor chip 160 can be directly electrically connected to the first substrate 110 via the first guide post 120, and there is no additional circuit layer or redistribution layer between the first guide post 120 and the semiconductor chip 160.

[0054] The connecting structure 130 can be disposed on one side of the first substrate 110. The connecting structure 130 can be single or multiple.

[0055] The connecting structure 130 can be configured among a plurality of first guide posts 120. The height of the connecting structure 130 can be equal to or slightly lower than the height of the first guide posts 120.

[0056] The connection structure 130 can be formed from a silicon wafer, an active die, or an IPD, etc. The connection structure 130 can be formed to enable electrical connection in the vertical and / or horizontal directions.

[0057] The connection structure 130 can be mounted on the first substrate 110 in a flip-chip configuration. After the connection structure 130 is mounted on the first substrate 110, it can be filled with underfill.

[0058] The connection structure 130 may include a wiring layer 30, a conductive layer 20 disposed on the upper part of the wiring layer 30, and a plurality of connecting members (i.e., bumps) 40 disposed on the lower part of the wiring layer 30. Here, the conductive layer 20 may include a plurality of second guide posts 21 spaced apart from each other and a first insulating material 22 coated between the plurality of second guide posts 21. The wiring layer 30 may include wiring circuits 31 and a second insulating material 32 coated on the wiring circuits 31. The plurality of connecting members 40 may be configured as metal balls or metal bumps.

[0059] The second guide post 21 can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). The second guide post 21 can be configured to contact and be electrically connected to the semiconductor chip 160.

[0060] The second guide post 21 can be formed to have a predetermined height. In addition, the second guide post 21 can be formed to have a constant width of cross-sectional area or to have a gradually increasing width of cross-sectional area in the upward direction.

[0061] The height of the second guide post 21 can be less than the height of the first guide post 120. Additionally, the diameter of the second guide post 21 can be less than the diameter of the first guide post 120. Furthermore, the spacing between the plurality of second guide posts 21 can be less than the spacing between the plurality of first guide posts 120. The second guide posts 21 can be formed on the connecting structure 130 with a diameter of 5µm to 100µm, a height of 10µm to 50µm, and a pitch of 10µm to 150µm.

[0062] The first insulating material 22 and the second insulating material 32 can be formed of dielectric or polymer materials. The polymer materials can be EMC (Epoxy Molding Compound), PI (Polyimide), ABF (Ajinomoto Build-up Film), etc., but are not limited to these.

[0063] The wiring circuit 31 of the wiring layer 30 can be configured to have a wiring circuit density greater than that of the first substrate 110. The line width / space of the wiring layer 30 can be formed to be 2um / 2um or less.

[0064] The connecting structure 130 can electrically connect a plurality of semiconductor chips 160 that are different from each other. At this time, the connecting structure 130 can electrically connect semiconductor chips of the same type or semiconductor chips of different types. For this purpose, the top surface of the connecting structure 130 can be formed to contact the plurality of semiconductor chips 160. The connecting structure 130 can be connected to the plurality of semiconductor chips 160 to enable them to conduct electricity to each other.

[0065] The connecting structure 130 can electrically connect the first substrate 110 and the semiconductor chip 160. For this purpose, the top surface of the connecting structure 130 can be formed to contact the semiconductor chip 160, and the bottom surface of the connecting structure 130 can be formed to contact the first substrate 110.

[0066] A direct electrical connection structure can be formed between the lower surface of the semiconductor chip 160 and the upper surface of the connection structure 130, and between the lower surface of the connection structure 130 and the upper surface of the first substrate 110, without any additional circuit layer or redistribution layer in between.

[0067] On the other hand, although not shown in the figure, the lower part of the semiconductor chip 160 mounted on the first substrate 110 and the connecting structure 130 may be filled with underfill or molded underfill (MUF).

[0068] The connection structure 130 does not need to be disposed on the entire top surface of the first substrate 110, but only needs to be disposed on at least a portion of the overlapping area between the first substrate 110 and the plurality of semiconductor chips 160. In the illustrated embodiment, the overall area of ​​the connection structure 130 can be smaller than the sum of the areas of the plurality of semiconductor chips (160) coupled to the connection structure 130. Therefore, the area of ​​the connection structure 130 can be further reduced, thereby achieving the effect of reducing the manufacturing cost of the connection structure 130 and the semiconductor package 100.

[0069] Furthermore, the reduced area of ​​the connection structure 130 facilitates its miniaturization. Therefore, as the space occupied by the connection structure 130 decreases, the overall miniaturization of the semiconductor package becomes possible for high-performance semiconductor packaging.

[0070] The reinforcing plate 140 can be disposed in the edge region of the first substrate 110 to support the protective member 170.

[0071] The molded component (or insulating component) 150 may be coated on one side of the first substrate 110 to provide electrical insulation between the components mounted on the first substrate 110.

[0072] The molded component 150 can be formed from an insulating material. As an example, the molded component 150 can be formed from a dielectric or a polymer material. EMC, PI, ABF, etc., can be used as the polymer material, but are not limited to these.

[0073] The semiconductor chip 160 can be disposed on the upper part of the first substrate 110. More specifically, the semiconductor chip 160 can be disposed on the first guide post 120 and the connection structure 130.

[0074] The semiconductor chip 160 can be provided as a single unit or a plurality of units. In this embodiment, the plurality of semiconductor chips 160 have a structure stacked in both the horizontal and vertical directions.

[0075] Semiconductor chip 160 may include one or more logic chips and one or more memory chips. Here, the logic chips may be arranged horizontally, and the memory chips may be arranged vertically. In this embodiment, the plurality of semiconductor chips stacked vertically are memory chips, and the semiconductor chips disposed between the stacked plurality of semiconductor chips are logic chips.

[0076] A chip connection member (not shown) for electrical connection to the first post 120 and / or the connection structure 130 can be formed on the bottom surface of the semiconductor chip 160. The upper end of the chip connection member can be formed by a grinding process.

[0077] On the other hand, although not illustrated, a first connecting member may be disposed between the semiconductor chip 160 and the first post 120, and a second connecting member may be disposed between the semiconductor chip 160 and the connecting structure 130. The first and second connecting members may be formed of a conductive metallic material. The first and second connecting members may be formed in the form of bumps. As pathways solely for electrical connection, such as bumps or posts, the structure and function of the first and second connecting members differ from the wiring layers constituting the circuit.

[0078] Additionally, although not illustrated, a heat dissipation die or an active die may be added and stacked on the upper side of the semiconductor chip 160. When an active die is stacked on the upper side of the semiconductor chip 160, a conductive connection means for electrical connection between the semiconductor chip 160 and the active die may be added.

[0079] Additionally, although not illustrated, a thermal interface material (TIM) can be added and stacked on top of the semiconductor chip 160. In this case, the thermal interface material (TIM) can be disposed between the semiconductor chip 160 and the heat dissipation die (or active die). Alternatively, the thermal interface material (TIM) can also be disposed on the top surface of the heat dissipation die (or active die).

[0080] A heat transfer material (TIM) can be disposed on the upper part of the semiconductor chip 160 to dissipate the heat generated on the semiconductor chip 160 to the outside. For this purpose, the heat transfer material (TIM) can be formed of a material with high thermal conductivity.

[0081] By configuring heat dissipation dies and / or heat transfer material (TIM) on the upper side of the semiconductor chip 160, the heat generated by the semiconductor chip 160 can be dissipated more easily, thereby preventing the semiconductor chip 160 from overheating. Furthermore, damage to the semiconductor package 100 due to overheating can be prevented, and the maintenance costs incurred when the semiconductor package is damaged can be reduced.

[0082] Furthermore, as shown in the figure, since multiple semiconductor chips are controlled and mounted separately, it is not necessary to include the structure and process of surrounding the semiconductor chips with molding layers and other insulating materials, thus simplifying the overall process and reducing costs. Additionally, the ability to add subsequent processes increases process flexibility. Moreover, because the semiconductor chips are handled individually, package warpage control is very easy to perform.

[0083] This is because, compared to the wafer-level fan-out process or TBDB (Temporary Bonding and Debonding) process widely used in advanced packaging processes, which must include a process of wrapping multiple semiconductor chips at once using EMC (Epoxy Molding Compound), the packaging of the present invention produces structural differences and effects by processing semiconductor chips individually.

[0084] On the other hand, although not illustrated, after configuring a plurality of semiconductor chips, additional processes can be selectively performed to surround the spaces between and around the semiconductor chips with a specific material. As this specific material, there are no limitations; not only EMC, PI (Polyimide), and other insulating materials can be used, but also materials with high or low thermal conductivity, as well as combinations thereof. Alternatively, the semiconductor chips can be left exposed to air without surrounding them with a specific material. In particular, the material used to fill the spaces around or between the semiconductor chips can be freely selected based on the thermal characteristics of the semiconductor chips, thereby increasing the degree of process freedom and facilitating improvements in the overall thermal characteristics of the package.

[0085] For the specific material mentioned above, EMC can be used first, as it is the most common and widely used material in general semiconductor packaging processes. EMC has a thermal conductivity of approximately 1 W / mK, which is not high, making it a relatively disadvantageous material for heat dissipation. However, in this invention, as a specific material usable in advanced packaging processes, materials with thermal conductivity ranging from tens to hundreds of W / mK, such as SiO2, Si3N4, SiC, Al, Au, Cu, and mixtures thereof, can be used. These materials are well-known for their excellent heat dissipation performance. Compared to other advanced packaging methods, the specific material mentioned above can be more easily used in the process for the reasons described above, thus, high heat dissipation performance can be expected in advanced semiconductor packaging where high temperatures may occur.

[0086] As an example, in the case of memory chips, since they cannot function in environments above a predetermined temperature, blocking externally generated heat becomes important. Due to the characteristics of advanced packaging, chips such as processors that generate high temperatures may be positioned close to memory chips at a distance of tens to hundreds of micrometers. Therefore, it is necessary to use materials with low thermal conductivity to fill the spaces between the chips to prevent high-temperature heat from moving towards the memory chip, thus allowing the memory chip to maintain its function. According to the advanced packaging process of the present invention, specific materials with low thermal conductivity can be freely and without restriction placed between the chips, or a low thermal conductivity air state, i.e., an airgap, can be maintained between the chips without placing specific materials. Therefore, unlike other packages, thermal blocking between chips becomes very easy.

[0087] As another example, when processor chips such as CPUs (Central Processing Units) or NPUs (Neural Processing Units) are positioned close together, unlike the embodiments described above, free heat exchange facilitates the control of overall package heat generation. In this case, specific materials between the semiconductor chips are filled with the aforementioned high thermal conductivity material, thereby improving the package's thermal characteristics.

[0088] The packaging process of the present invention, which has the aforementioned features of easy encapsulation and warpage control and the ability to freely control thermal properties, is particularly effective in advanced semiconductor packaging processes that mount multiple semiconductor chips of multiple types at intervals of tens to hundreds of micrometers.

[0089] The protective member (or pin) 170 may be disposed on the upper part of the first substrate 110 and the semiconductor chip 160. As an example, the protective member 170 may be formed to surround at least a portion of the first substrate 110, the semiconductor chip 160, the heat dissipation dies, and the heat transfer material.

[0090] The protective member 170 can protect the components mounted on the first substrate 110 from physical impacts, while also assisting in the fixation between the semiconductor chip 160, the heat dissipation die, and the heat transfer material, preventing these components from detaching arbitrarily. Therefore, the protective member 170 can be formed in a shape corresponding to the structure that integrates with the semiconductor chip 160, the heat dissipation die, and the heat transfer material.

[0091] The protective component 170 may be made of steel can material, but is not limited to it.

[0092] The edge region of the protective member 170 may form a defined step with the central portion. The edge region of the protective member 170 may be configured to contact the reinforcing plate 140.

[0093] An external connecting member 180 can be attached to the bottom surface of the first substrate 110, serving to electrically connect the first substrate 110 to an external member (not shown). The external connecting member 180 can be formed in the form of a solder ball or a metal ball.

[0094] The semiconductor package 100, with these components, protects one or more semiconductor chips 160 from physical impact and mitigates the integration differences between the semiconductor chip 160 and the substrate on which it is mounted, thereby increasing ease of installation. Furthermore, since a plurality of first post 120s and small-scale connection structures 130 are disposed between the first substrate 110 and the semiconductor chip 160 in the semiconductor package 100, not only can the miniaturization of the semiconductor package be achieved, but the manufacturing process of the semiconductor package can also be simplified, thereby reducing manufacturing costs.

[0095] Figure 2 This is a flowchart illustrating a semiconductor package manufacturing method according to a first embodiment of the present invention. Figures 3a to 3g This is a reference figure used to illustrate a semiconductor package manufacturing method according to a first embodiment of the present invention. In the illustrated flowchart, the semiconductor package manufacturing method is divided into a plurality of steps and described, but at least some steps may be performed in a different order, or combined with other steps and performed simultaneously, or omitted, or subdivided into a plurality of steps, or one or more steps not shown may be added and performed.

[0096] Reference Figures 2 to 3g First, a first substrate 110 is set (S210). The first substrate 110 can be a PCB substrate or an F-PCB substrate.

[0097] A plurality of first guide posts 120 are disposed on the first substrate 110 (S220). At this time, the plurality of first guide posts 120 can be disposed on one side of the first substrate 110 and spaced apart from each other. In addition, the plurality of first guide posts 120 can be configured to be connected to the wiring circuit of the first substrate 110.

[0098] A connecting structure 130 is mounted on the first substrate 110 (S230). At this time, the connecting structure 130 can be disposed among a plurality of first guide posts 120. Furthermore, the connecting structure 130 can be formed to enable electrical connection in the vertical and / or horizontal directions. A method for manufacturing the connecting structure 130 will be described later.

[0099] A stiffener 140 is mounted on the edge region of the first substrate 110.

[0100] Subsequently, a molding member 150 is disposed (coated) on the upper part of the first substrate 110, the first guide post 120, the connecting structure 130, and the reinforcing plate 140 (S240). At this time, the molding member 150 is coated to completely cover the first substrate 110, the first guide post 120, the connecting structure 130, and the reinforcing plate 140.

[0101] If this coating operation is completed, the first guide post 120 and the conductive layer 20 of the connecting structure 130 are exposed to the outside by removing the upper region of the molding member 150 and the second substrate 10 disposed on the upper part of the connecting structure 130 (S250). The removal process can be performed by a grinding process.

[0102] One or more semiconductor chips 160 (S260) are mounted on the first guide post 120 and the connecting structure 130. The semiconductor chips 160 may be stacked in the horizontal and / or vertical directions.

[0103] A plurality of bumps may be formed on the lower part of the semiconductor chip 160. These bumps, as heterogeneous bumps, may be formed to correspond respectively to the first guide post 120 mounted on the first substrate 110 and the second guide post 21 of the connection structure 130 (described later). More specifically, the plurality of bumps may include high-density bumps directly connected to the conductive layer 20 of the connection structure 130 and low-density bumps directly connected to the first guide post 120.

[0104] A protective member 170 is disposed on the upper part of the first substrate 110 and the semiconductor chip 160 (S270). The protective member 170 may be formed to surround at least a portion of the first substrate 110, the semiconductor chip 160, the heat dissipation grains, and the heat transfer material.

[0105] Then, an external connecting member 180 is attached to the bottom surface of the first substrate 110.

[0106] Through the above process, the semiconductor package 100 of the first embodiment of the present invention can be formed.

[0107] On the other hand, as another embodiment, the first guide post 120 can be formed by a TMV (Through Mold Via) process. The TMV process can be performed after the connecting structure 130, the reinforcing plate 140, and the molding member 150 are stacked on the first substrate 110. The TMV process is a process in which a plurality of holes are formed in the molding member 150 and a plurality of first guide posts 120 are inserted into a plurality of said holes.

[0108] Figure 4a This is a diagram illustrating the structure of a semiconductor package according to a second embodiment of the present invention. Figure 4b It is shown Figure 4a The diagram shows the structure of the connecting structure.

[0109] Reference Figure 4a and Figure 4b The semiconductor package 200 of the second embodiment of the present invention may include a first substrate 210, a connecting structure 220, a reinforcing plate 230, a molding component 240, a semiconductor chip 250, a heat transfer material 260, a protective component 270, and an external connecting component 280. Figure 4a The components shown are not essential for realizing a semiconductor package; therefore, the semiconductor package described in this specification may have more or fewer components than those listed above.

[0110] Unlike the semiconductor package 100 of the first embodiment described above, the semiconductor package 200 of this embodiment has a structure that extends the dimensions of the connection structure 220 in the horizontal direction, instead of mounting a plurality of conductive posts on the first substrate 210.

[0111] The first substrate 210, connecting structure 220, reinforcing plate 230, molding component 240, semiconductor chip 250, heat transfer material 260, protective component 270, and external connecting component 280 of the semiconductor package 200 in this embodiment are the same as or similar to the first substrate 110, connecting structure 130, reinforcing plate 140, molding component 150, semiconductor chip 160, heat transfer material (not shown), protective component 170, and external connecting component 180 of the semiconductor package 100 in the first embodiment described above. Therefore, detailed descriptions of these components are omitted, and the description focuses on the differences.

[0112] The first substrate 210 can be used to mount various electronic components. The first substrate 210 can be a PCB substrate or an F-PCB substrate, but is not limited to these.

[0113] The connecting structure 220 can be disposed on one side of the first substrate 210. A plurality of connecting structures 220 can be provided.

[0114] The connection structure 220 can be formed from a silicon wafer, an active die, or an IPD, etc. The connection structure 220 can be configured to provide electrical connections in both vertical and horizontal directions.

[0115] The connection structure 220 can be mounted on the first substrate 210 in a flip-chip configuration. After being mounted on the first substrate 210, the connection structure 220 can be filled with underfill.

[0116] The connection structure 220 may include a wiring layer 30, a conductive layer 20 disposed on the upper part of the wiring layer 30, and a plurality of connecting members (i.e., bumps) 40 disposed on the lower part of the wiring layer 30. Here, the conductive layer 20 may include a plurality of second guide posts 21 spaced apart from each other and a first insulating material 22 coated between the plurality of second guide posts 21. The wiring layer 30 may include wiring circuits 31 and a second insulating material 32 coated on the wiring circuits 31. The plurality of connecting members 40 may be configured as metal balls or metal bumps.

[0117] The connecting structure 220 enables electrical connection between a plurality of semiconductor chips 250 that are different from each other. In this case, the connecting structure 220 can electrically connect a plurality of semiconductor chips of the same type or a plurality of semiconductor chips of different types. For this purpose, the top surface of the connecting structure 220 can be formed to contact the plurality of semiconductor chips 250. The connecting structure 220 can be connected to the plurality of semiconductor chips 250 to enable them to conduct electricity to each other.

[0118] The connecting structure 220 can electrically connect the first substrate 210 and the semiconductor chip 250. For this purpose, the top surface of the connecting structure 220 can be formed to contact the semiconductor chip 250, and the bottom surface of the connecting structure 220 can be formed to contact the first substrate 210.

[0119] The connection structure 220 can be disposed between the first substrate 210 and the semiconductor chip 250, and can be configured to cover the entire overlapping area between the first substrate 210 and the semiconductor chip 250. In the illustrated embodiment, the overall area of ​​the connection structure 220 can be equal to or slightly larger than the sum of the areas of the plurality of semiconductor chips 250 coupled to the connection structure 220. Therefore, it is not necessary to provide a plurality of guide pillars on the first substrate 210, thus achieving the effect of reducing the manufacturing cost of the connection structure 220 and the semiconductor package 200.

[0120] The reinforcing plate 230 can be disposed in the edge region of the first substrate 210 to support the protective member 270.

[0121] The molded component (or insulating component) 240 may be coated on one side of the first substrate 210 to provide electrical insulation between the components mounted on the first substrate 210.

[0122] Semiconductor chip 250 can be disposed on connection structure 220. Semiconductor chip 250 may include one or more logic chips and one or more memory chips. Here, the one or more logic chips may be arranged horizontally, and the one or more memory chips may be arranged vertically. In this embodiment, the plurality of semiconductor chips stacked vertically are memory chips, and the semiconductor chips disposed between the stacked plurality of semiconductor chips are logic chips.

[0123] On the other hand, although not shown in the figure, a connecting member can be disposed between the semiconductor chip 250 and the connecting structure 220. Additionally, a heat dissipation die or an active die can be added and stacked on top of the semiconductor chip 250.

[0124] The heat transfer material 260 (TIM) can be disposed on the upper part of the semiconductor chip 250 to dissipate the heat generated by the semiconductor chip 250 to the outside. In this case, the heat transfer material 260 (TIM) can be disposed between the semiconductor chip 250 and the heat dissipation die (or active die). Alternatively, the heat transfer material 260 (TIM) can also be disposed on the top surface of the heat dissipation die (or active die).

[0125] The protective member (or pin) 270 may be disposed on the upper part of the first substrate 210 and the semiconductor chip 250. The protective member 270 can protect the components mounted on the first substrate 210 from physical impact, while assisting in the fixation between the semiconductor chip 250, the heat dissipation die, and the heat transfer material, preventing these components from detaching arbitrarily.

[0126] The external connecting member 280 can be attached to the bottom surface of the first substrate 210, serving to electrically connect the first substrate 210 with the external member (not shown).

[0127] The semiconductor package 200, having the components described above, can protect one or more semiconductor chips 250 from physical impacts and mitigate integration differences between the semiconductor chip 250 and the substrate to be mounted, thereby increasing installation convenience. Furthermore, by configuring a large-scale interconnect structure 220 between the first substrate 210 and the semiconductor chip 250 in the semiconductor package 200, the manufacturing process of the semiconductor package is simplified, thereby reducing manufacturing costs and improving the wiring integration of the semiconductor package.

[0128] Figure 5 This is a flowchart illustrating a semiconductor package manufacturing method according to a second embodiment of the present invention. Figures 6a to 6g This is a reference figure used to illustrate a semiconductor package manufacturing method according to a second embodiment of the present invention. Although the semiconductor package manufacturing method is described in the flowchart shown as a plurality of steps, at least some of the steps may be performed in a different order, or in combination with other steps and performed simultaneously, or omitted, or subdivided into a plurality of steps, or one or more steps not shown may be added.

[0129] Reference Figures 5 to 6g First, a first substrate 210 (S510) is set. The first substrate 210 can be a PCB substrate or an F-PCB substrate.

[0130] A connection structure 220 is mounted on the first substrate 210 (S520). At this time, the connection structure 220 can be configured to be electrically connected in both the vertical and horizontal directions. The manufacturing method of the connection structure 220 will be described later.

[0131] A stiffener 230 is mounted on the edge region of the first substrate 210.

[0132] Then, a molding member 240 is coated on the upper part of the first substrate 210, the connecting structure 220 and the reinforcing plate 230 (S530). At this time, the molding member 240 can be coated to completely cover the first substrate 210, the connecting structure 220 and the reinforcing plate 230.

[0133] If this coating operation is completed, the conductive layer 20 of the connecting structure 220 is exposed to the outside by removing the upper region of the molding member 240 and the second substrate 10 disposed on the upper part of the connecting structure 220 (S540).

[0134] One or more semiconductor chips 250 (S550) are mounted on the upper surface of the exposed conductive layer 20 of the connecting structure 220. The semiconductor chips 250 may be stacked in the horizontal and / or vertical directions.

[0135] A plurality of bumps may be formed on the lower part of the semiconductor chip 250. The bumps, as heterogeneous bumps, may be formed to correspond to the second guide post 21 of the connection structure 220 described later.

[0136] A heat transfer material 260 (TIM) is disposed on the upper part of the semiconductor chip 250 (S560). On the other hand, although not shown, a heat dissipation die or an active die can be disposed between the semiconductor chip 250 and the heat transfer material 260 (TIM).

[0137] A protective member 270 is disposed on the upper part of the first substrate 210 and the heat transfer material 260 (TIM). The protective member 270 may be formed to surround at least a portion of the first substrate 210, the semiconductor chip 250, the heat dissipation dies, and the heat transfer material 260.

[0138] Finally, an external connecting member 280 is attached to the bottom surface of the first substrate 210 (S570).

[0139] Through the above process, the semiconductor package 200 of the second embodiment of the present invention can be formed.

[0140] Figure 7 This is a diagram illustrating the structure of a semiconductor package according to a third embodiment of the present invention.

[0141] Reference Figure 7 The semiconductor package 300 of the third embodiment of the present invention may include a first substrate 310, a vertical wire 320, a connecting structure 330, a reinforcing plate 340, a molding component 350, a semiconductor chip 360, a heat transfer material 370, a protective component 380, and an external connecting component 390. Figure 7 The components shown are not essential for realizing a semiconductor package; therefore, the semiconductor package described in this specification may have more or fewer components than those listed above.

[0142] Unlike the semiconductor package 100 of the first embodiment described above, the semiconductor package 300 of this embodiment has a structure in which a plurality of vertical wires are mounted on a first substrate 310 to replace a plurality of conductive posts. This structure simplifies the manufacturing process of the semiconductor package 300 and reduces manufacturing costs. Furthermore, the plurality of vertical wires 320 can form a fine pitch.

[0143] The vertical conductor 320 can be disposed on one side of the first substrate 310. As an example, a plurality of vertical conductors 320 may also be formed on the wiring circuit of the first substrate 310.

[0144] The vertical conductor 320 can be formed to extend vertically from the top surface of the first substrate 310. The vertical conductor 320 can be formed to have a predetermined height.

[0145] The vertical conductor 320 can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al). An insulating material can be coated around the vertical conductor 320.

[0146] The vertical conductor 320 has a wide range of processable diameters, heights, and pitches, thus offering high process flexibility. It can accommodate not only the pitches of existing conductive posts such as the first post, but also finer pitches. Therefore, it is more suitable for high-performance semiconductor packaging processes, including high-density wiring, without requiring additional structures such as redistribution layers. Furthermore, even with smaller diameters and pitches, the vertical conductor 320 can still achieve a higher height. For example, the vertical conductor 320 can be formed on the first substrate 310 with a diameter of 10µm to 50µm, a height of 50µm to 500µm, and a pitch of 20µm.

[0147] The vertical lead 320 has a simple manufacturing process, which results in a shorter manufacturing time and ultimately reduces the total production time of the package, thereby improving productivity.

[0148] The vertical conductor 320 can be configured to directly contact the wiring circuitry of the first substrate 310 for electrical connection. Alternatively, the vertical conductor 320 can be configured to contact the semiconductor chip 360 for electrical connection. Thus, the first substrate 310 can be directly electrically connected to the semiconductor chip 360 via the vertical conductor 320. As an example, the vertical conductor 320 can be formed on a PCB substrate and configured to contact the semiconductor chip 360, allowing direct electrical connection between the semiconductor chip 360 and the PCB substrate without any additional wiring layers between them.

[0149] As an example, the process of directly connecting a semiconductor chip 360 with a high-density bump pitch of approximately 50µm to a first substrate (i.e., PCB) 310 is difficult due to pitch limitations. However, since the vertical conductor 320 can accommodate high-density bump pitch, the corresponding process can be achieved. That is, the vertical conductor 320 is more advantageous than other conductive posts for the process of high-performance semiconductor packaging with high-density wiring.

[0150] The first substrate 310, connecting structure 330, reinforcing plate 340, molding component 350, semiconductor chip 360, heat transfer material 370, protective component 380, and external connecting component 390 of the semiconductor package 300 in this embodiment are the same as or similar to the first substrate 110, connecting structure 130, reinforcing plate 140, molding component 150, semiconductor chip 160, heat transfer material (not shown), protective component 170, and external connecting component 180 of the semiconductor package 100 in the first embodiment described above, therefore detailed descriptions thereof are omitted.

[0151] Figure 8 This is a diagram illustrating the structure of a semiconductor package according to a fourth embodiment of the present invention.

[0152] Reference Figure 8 The semiconductor package 400 of the fourth embodiment of the present invention may include a first substrate 410, a first guide post 420, a connecting structure 430, a reinforcing plate 440, a molding component 450, a semiconductor chip 460, a heat transfer material 470, a protective component 480, and an external connecting component 490. Figure 8 The components shown are not essential for realizing a semiconductor package; therefore, the semiconductor package described in this specification may have more or fewer components than those listed above.

[0153] Unlike the semiconductor package 100 of the first embodiment described above, the semiconductor package 400 of this embodiment is provided with a first substrate 410 having a cavity structure. A connecting structure 430 can be mounted in the cavity region formed on the upper part of the first substrate 410. The cavity region can be formed to correspond to the shape of the connecting structure 430.

[0154] This cavity structure allows for a lower height of the first guide post 420 to be mounted on the first substrate 410, thus reducing manufacturing complexity and improving signal characteristics. Furthermore, by not forming the first guide post 420 on the first substrate 410, or by replacing it with solder balls or solder bumps, manufacturing complexity and processing time can be reduced. Additionally, miniaturization of the semiconductor package 400 is achieved by reducing its thickness.

[0155] The first guide post 420, connecting structure 430, reinforcing plate 440, molding component 450, semiconductor chip 460, heat transfer material 470, protective component 480, and external connecting component 490 of the semiconductor package 400 in this embodiment are the same as or similar to the first guide post 120, connecting structure 130, reinforcing plate 140, molding component 150, semiconductor chip 160, heat transfer material (not shown), protective component 170, and external connecting component 180 of the semiconductor package 100 in the first embodiment described above, therefore detailed descriptions thereof are omitted.

[0156] Figure 9 This is a diagram illustrating the structure of a semiconductor package according to a fifth embodiment of the present invention.

[0157] Reference Figure 9 The semiconductor package 500 of the fifth embodiment of the present invention may include a first substrate 510, a connecting structure 520, a reinforcing plate 530, a molding component 540, a semiconductor chip 550, a heat transfer material 560, a protective component 570, and an external connecting component 580. Figure 9 The components shown are not essential for realizing a semiconductor package; therefore, the semiconductor package described in this specification may have more or fewer components than those listed above.

[0158] Unlike the semiconductor package 200 of the second embodiment described above, the semiconductor package 500 of this embodiment is provided with a first substrate 510 having a cavity structure. A connecting structure 520 can be mounted in the cavity region formed on the upper part of the first substrate 510. The cavity region can be formed to correspond to the shape of the connecting structure 520.

[0159] This cavity structure allows for a reduction in the thickness of the semiconductor package 500, thereby enabling miniaturization of the semiconductor package 500.

[0160] The connection structure 520, reinforcing plate 530, molding component 540, semiconductor chip 550, heat transfer material 560, protective component 570, and external connection component 580 of the semiconductor package 500 in this embodiment are the same as or similar to the connection structure 220, reinforcing plate 230, molding component 240, semiconductor chip 250, heat transfer material 260, protective component 270, and external connection component 280 of the semiconductor package 200 in the second embodiment described above, therefore, detailed descriptions thereof are omitted.

[0161] Figure 10 This is a flowchart illustrating a method for manufacturing a connection structure according to an embodiment of the present invention. Figures 11a to 11hThis is a reference figure illustrating a method for manufacturing a connecting structure according to an embodiment of the present invention. The flowchart shown divides the manufacturing method of the connecting structure into a plurality of steps, but at least some of these steps may be performed in a different order, or in combination with other steps and performed simultaneously, or omitted, or subdivided into a plurality of steps, or one or more steps not shown may be added.

[0162] Reference Figures 10 to 11h First, a second substrate 10 is provided, and then a plurality of second guide posts 21 are disposed on the second substrate 10 (S1010). At this time, the plurality of second guide posts 21 can be configured to be spaced apart from each other. The spacing between the plurality of second guide posts 21 can be varied according to various embodiments of the present invention.

[0163] The second substrate 10 can be formed of silicon (Si), glass, or polymer materials. Additionally, the second guide post 21 can be formed of a conductive metal material such as copper (Cu), silver (Ag), gold (Au), or aluminum (Al).

[0164] A conductive layer 20 is formed by distributing a first insulating material 22 between a plurality of second conductive posts 21 (S1020). More specifically, as Figure 11b and Figure 11c As shown, after coating the first insulating material 22 to cover the plurality of second guide posts 21, the upper region of the first insulating material 22 is removed until the plurality of second guide posts 21 are exposed to the outside, thereby forming a conductive layer 20.

[0165] Next, a wiring layer 30 is disposed on the conductive layer 20 (S1030). At this time, the wiring layer 30 can be manufactured by electroplating copper (Cu) using a damascene process, or printed as a redistribution layer (RDL).

[0166] The connection structures 130 and 220 (S1040) are formed by arranging a plurality of connection members 40 on one side of the wiring layer 30. At this time, although the plurality of connection members 40 are illustrated to have the form of weld bumps, it is not limited to this.

[0167] After the connecting structures 130 and 220 are flipped, they are installed on the first substrates 110 and 210 (S1050). At this time, the connecting structures 130 and 220 are installed on the wiring circuit of the first substrates 110 and 210 so that the bump 40 contacts the wiring circuit of the first substrates 110 and 210.

[0168] Then, by removing the second substrate 10 located on the upper part of the connecting structures 130, 220, the conductive layer 20 of the connecting structures 130, 220 is exposed to the outside (S1060). More specifically, as... Figure 11g and Figure 11h As shown, after molding components 150 and 240 are coated on the first substrates 110 and 210 and the connecting structures 130 and 220, the second substrate 10 is removed together with a portion of the molding components 150 and 240, so that the conductive layer 20 of the connecting structures 130 and 220 is exposed to the outside.

[0169] Through the above process, the connection structures 130 and 220 of an embodiment of the present invention can be manufactured.

[0170] Figure 12 This is a flowchart illustrating a method for manufacturing a connection structure according to another embodiment of the present invention. Figures 13a to 13g This is a reference figure used to illustrate a method for manufacturing a connecting structure according to another embodiment of the present invention. Although the flowchart shown in the figure describes the method for manufacturing a connecting structure in a plurality of steps, at least some of the steps may be performed in a different order, or in combination with other steps and performed simultaneously, or may be omitted, or may be subdivided into a plurality of steps, or may be additionally performed one or more steps not shown in the figure.

[0171] Reference Figures 12 to 13g First, a second substrate 60 is provided, and then a plurality of recessed grooves 61 are formed on one side of the second substrate 60 (S1210). At this time, the plurality of recessed grooves 61 can be configured to be spaced apart from each other. The spacing between the recessed grooves 61 can be varied according to various embodiments of the present invention.

[0172] The second substrate 60 can be formed of silicon, glass, or polymer materials. When the second substrate 60 is made of silicon, the plurality of recesses 61 can be coated with an insulating material.

[0173] A conductive layer 20 is formed by arranging a plurality of second guide pillars 21 within a recess 61 in the second substrate 60 (S1220). Similar to the above... Figure 10 Unlike the connection structure in this embodiment, in the case of the connection structure, the protrusion between the plurality of recessed grooves 61 formed on the upper part of the second substrate 60 acts as an insulating material.

[0174] Subsequently, a wiring layer 30 is formed on the conductive layer 20 (S1330). At this time, the wiring layer 30 can be manufactured by electroplating copper (Cu) using a damascene process, or printed as a redistribution layer (RDL).

[0175] The connection structures 130 and 220 (S1240) are formed by arranging a plurality of connection members 40 on one side of the wiring layer 30. At this time, it is exemplified that the plurality of connection members 40 have a solder bump shape, but it is not limited to this.

[0176] After flipping the connecting structures 130 and 220, they are installed on the first substrates 110 and 210 (S1250). At this time, the wiring circuit of the first substrates 110 and 210 is installed with the connecting structures 130 and 220 so that the bump 40 contacts the wiring circuit of the first substrates 110 and 210.

[0177] Then, by removing the second substrate 60 located on the upper part of the connecting structures 130, 220, the conductive layer 20 of the connecting structures 130, 220 is exposed to the outside (S1260). More specifically, as Figure 13f and Figure 13g As shown, after molding components 150 and 240 are coated on the first substrates 110 and 210 and the connecting structures 130 and 220, the upper region of the second substrate 10 is removed together with a portion of the molding components 150 and 240, so that the conductive layer 20 of the connecting structures 130 and 220 is exposed to the outside.

[0178] Through the above process, the connection structures 130 and 220 of another embodiment of the present invention can be manufactured.

[0179] As described above, the present invention utilizes fan-out technology to provide connection structures 130 and 220, which not only realize electrical connections between a plurality of semiconductor chips 160 and 250 arranged in the horizontal direction, but also realize electrical connections between the first substrate 110 and 210 arranged in the vertical direction and the semiconductor chips 160 and 250. Furthermore, the connection structures 130 and 220 of the present invention facilitate the transfer of power and signals between the first substrate 110 and 210 and the semiconductor chips 160 and 250, thereby improving power efficiency. In addition, the connection structures 130 and 220 are easily adjustable in size, offering excellent design flexibility.

[0180] On the other hand, although specific embodiments of the present invention have been described above, it is self-evident that various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the present invention is not limited to the described embodiments, but should be determined by the scope of the patent claims described below and equivalents thereof.

Claims

1. A semiconductor package, characterized in that, include: First substrate; A plurality of semiconductor chips are disposed above the first substrate; as well as A connecting structure is disposed between at least one of the plurality of semiconductor chips and the first substrate, electrically connecting at least two semiconductor chips arranged in a horizontal direction among the plurality of semiconductor chips. The connection structure includes a conductive layer, a plurality of connection members, and a wiring layer. The conductive layer is directly connected to the semiconductor chip, the plurality of connection members are electrically connected to the first substrate, and the wiring layer is disposed between the conductive layer and the plurality of connection members.

2. The semiconductor package according to claim 1, characterized in that, The conductive layer includes a plurality of second conductive posts arranged spaced apart from each other and a first insulating material coated between the plurality of second conductive posts.

3. The semiconductor package according to claim 2, characterized in that, The wiring layer includes wiring circuitry and a second insulating material coated on the wiring circuitry.

4. The semiconductor package according to claim 3, characterized in that, The first insulating material and the second insulating material are formed of dielectric or polymer materials.

5. The semiconductor package according to claim 1, characterized in that, The wiring layer is manufactured by electroplating copper using a damascus inlay process, or printed as a redistribution layer.

6. The semiconductor package according to claim 1, characterized in that, The connection structure is formed from silicon wafers, active chips, or integrated passive devices.

7. The semiconductor package according to claim 1, characterized in that, The connection structure electrically connects the first substrate to at least one of the plurality of semiconductor chips.

8. The semiconductor package according to claim 1, characterized in that, The connection structure is mounted on the top surface of the first substrate in a flip-chip configuration.

9. The semiconductor package according to claim 1, characterized in that, The area of ​​the connecting structure is less than the sum of the areas of the plurality of semiconductor chips coupled to the connecting structure.

10. The semiconductor package according to claim 9, wherein, It also includes a plurality of first posts, which are disposed between the first substrate and at least one of the plurality of semiconductor chips, electrically connecting the first substrate and the at least one semiconductor chip.

11. The semiconductor package according to claim 10, characterized in that, Each first guide post is formed with a constant width of cross-sectional area or with the width of cross-sectional area gradually increasing upwards.

12. The semiconductor package according to claim 9, wherein, It also includes a plurality of vertical wires disposed between the first substrate and at least one of the plurality of semiconductor chips, electrically connecting the first substrate and the at least one semiconductor chip.

13. The semiconductor package according to claim 1, characterized in that, The area of ​​the connecting structure is equal to or slightly larger than the sum of the areas of the plurality of semiconductor chips coupled to the connecting structure.

14. The semiconductor package according to claim 1, characterized in that, The first substrate has a cavity structure for mounting the connecting structure.

15. The semiconductor package according to claim 1, wherein, It also includes heat dissipation dies, which are disposed on at least one of the plurality of semiconductor chips.

16. The semiconductor package of claim 15, wherein, It also includes a heat transfer material disposed between the at least one semiconductor chip and the heat dissipation grain or disposed on the top surface of the heat dissipation grain.

17. The semiconductor package according to claim 1, characterized in that, The plurality of semiconductor chips includes one or more logic chips and one or more memory chips.

18. A method for manufacturing a semiconductor package, wherein, include: The step of configuring a plurality of first guide pillars on a first substrate; The step of installing the connecting structure in the adjacent areas of a plurality of the first guide posts; The step of configuring molded components on the first substrate, the plurality of first guide posts, and the connecting structure; The step of removing the upper region of the molded component and the second substrate of the connecting structure to expose the plurality of first guide posts and the conductive layer of the connecting structure to the outside; The step of mounting a plurality of semiconductor chips on a plurality of first guide posts and the connecting structure; The step of configuring a protective member above the plurality of said semiconductor chips; as well as The step of attaching an external connecting member to the bottom surface of the first substrate.

19. A method for manufacturing a semiconductor package, wherein, include: The step of mounting the connecting structure on the first substrate; The step of configuring molded components on the first substrate and the connecting structure; The step of removing the upper region of the molded component and the second substrate of the connecting structure to expose the conductive layer of the connecting structure to the outside; The step of mounting a plurality of semiconductor chips on a connection structure that exposes the conductive layer; The step of configuring a protective member above the plurality of said semiconductor chips; as well as The step of attaching an external connecting member to the bottom surface of the first substrate.

20. The method for manufacturing a semiconductor package according to claim 18 or 19, characterized in that, It also includes the step of manufacturing the connecting structure. The steps for manufacturing the connection structure further include: The step of forming a conductive layer on the second substrate; The step of forming a wiring layer on the conductive layer; and The step of configuring a plurality of connection members on the wiring layer.

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