Multi-mode current mode control for PWM converters

Abstract

The techniques and circuits described herein include a solution for multi-mode current control of pulse width modulation (PWM) converters. In some aspects, a slope control circuit (116) is used to simulate a current through an inductor (102) as a voltage across a switched capacitor (144) during a discharge phase. A slope control voltage (134) is used to modify a slope of the simulated current waveform relative to the actual inductor current waveform. The converter may selectively operate in a continuous conduction mode (CCM), a discontinuous conduction mode (DCM), or a transition mode (TM), respectively, depending on whether the magnitude of the modified slope is greater than, less than, or equal to the actual slope.

Description

Background Technology

[0001] A DC-DC converter can be used to perform various functions in electronic circuits, such as voltage stepping / shaving and voltage regulation. Typically, a DC-DC converter contains one or more switches, and a pulse-width modulation (PWM) signal can be used to control the operation of these switches to control the switching frequency. The switching frequency and input voltage of a DC-DC converter affect its output voltage. Summary of the Invention

[0002] In one example, a circuit includes an inductor arranged along a first current path. The inductor includes a first terminal and a second terminal. A current sensing circuit is arranged in series with the inductor along the first current path. A first switch is coupled between the inductor and the current sensing circuit. A voltage sensing circuit includes first and second inputs coupled to the first and second terminals of the inductor, respectively. A feedback path extends from the output of the voltage sensing circuit to a control terminal of the first switch. A slope control circuit is arranged along the feedback path and coupled to the output of the voltage sensing circuit, and the slope control circuit includes a switch output. A peak current control circuit is coupled to the output of the current sensing circuit, and the peak current control circuit includes a switch output. A switch control circuit includes a first input coupled to the switch output of the slope control circuit, a second input coupled to the switch output of the peak current control circuit, and a first output coupled to the control terminal of the first switch.

[0003] In another example, a circuit includes a voltage sensing circuit with first and second inputs coupled to first and second terminals of an inductor. A current sensing circuit is arranged in series with the inductor, and a first switch is arranged between the inductor and the current sensing circuit. A peak current control circuit is coupled to the output of the current sensing circuit and is configured to selectively open the first switch via a switch control circuit based on a sensed current and a peak current control voltage. A slope control circuit is coupled to the output of the voltage sensing circuit and is configured to selectively close the first switch via the switch control circuit based on a sensed voltage and a slope control voltage.

[0004] In another example, a method for controlling a pulse width modulation (PWM) converter includes: during a first discharge phase: sensing a voltage across an inductor and charging a sampling capacitor based on the sensed voltage; discharging a switched capacitor at a certain rate based on a voltage stored on the sampling capacitor and a slope control voltage; and initiating a charging phase in response to a voltage drop on the switched capacitor below a threshold, wherein the operating mode of the PWM converter is based on the slope control voltage. Attached Figure Description

[0005] Figure 1This is a circuit diagram of a pulse width modulation (PWM) controller including slope control circuitry and peak current control circuitry, according to some aspects of this disclosure.

[0006] Figure 2 This is a circuit diagram of a flyback converter including a PWM controller with slope control circuitry and peak current control circuitry, according to some aspects of this disclosure.

[0007] Figure 3 The diagram illustrates a waveform of a flyback converter operating in discontinuous conduction mode (DCM) according to some aspects of this disclosure, the flyback converter including a PWM controller with slope control circuitry and peak current control circuitry.

[0008] Figure 4 The diagram illustrates a waveform of a flyback converter operating in transition mode (TM) according to some aspects of this disclosure, the flyback converter including a PWM controller with slope control circuitry and peak current control circuitry.

[0009] Figure 5 This is a waveform diagram illustrating continuous conduction mode (CCM) operation of a flyback converter according to some aspects of this disclosure, the flyback converter including a PWM controller with slope control circuitry and peak current control circuitry.

[0010] Figure 6 This is a waveform diagram illustrating the transition between DCM and CCM operation of a flyback converter according to some aspects of this disclosure, the flyback converter including a PWM controller with slope control circuitry and peak current control circuitry.

[0011] Figure 7 This is a circuit diagram of a mode selection circuit system for a PWM controller, which includes slope control circuitry and peak current control circuitry, according to some aspects of this disclosure.

[0012] Figure 8 This is a circuit diagram of a PWM controller including a slope control circuit and a peak current control circuit according to some aspects of this disclosure. Detailed Implementation

[0013] The diagram was not drawn to scale.

[0014] DC-DC converters (such as pulse-width modulation (PWM) converters) are used in a wide variety of electronic circuits due to their ability to step up / down and regulate DC voltage. A PWM converter may include a voltage input, an inductor, a capacitor, a diode, and one or more switches. During operation, the one or more switches open and close at a high frequency; the operation of the one or more switches in combination with the diodes controls the current path within the PWM converter and charges / discharges the inductor and capacitor. An output voltage is generated across the capacitor based on the switching frequency and the topology of the PWM converter. PWM converters can present various topologies, such as buck, boost, buck-boost, flyback, etc., which provide various relationships between the input and output voltages. The placement of the voltage input, inductor, capacitor, diode, and one or more switches can vary based on the topology.

[0015] Figure 1 A PWM controller 100 is shown, which can be coupled to / used to control a PWM converter. The PWM controller 100 can be used with any PWM topology, and the PWM controller 100 is already... Figure 1 This is generalized to be applicable to any PWM topology.

[0016] An inductor 102 and a first switch 104 of a PWM converter arranged along a first current path 105 are shown. The switching operation of the PWM converter can generally be divided into two phases: a charging phase and a discharging phase. During the charging phase, the first switch 104 is closed. A voltage 106 "Va" (e.g., through a voltage input) is applied across the inductor 102, and the inductor 102 begins to charge. Finally, the PWM converter switches to the discharging phase, in which the first switch 104 is opened and current flows from the inductor 102 through the diode 110. More specifically, the difference "Va-Vb" between the voltage 106 "Va" and the voltage 108 "Vb" (e.g., based on the voltage input and / or voltage output of the PWM converter) is applied across the inductor 102, and the inductor 102 begins to discharge. Depending on the value of the current present in the inductor 102 at the end of the discharging phase, the PWM converter can be defined to operate in continuous conduction mode (CCM), discontinuous conduction mode (DCM), or transition mode (TM). In CCM, the discharge phase ends before inductor 102 is fully discharged, so the current through inductor 102 will never be zero. In DCM, the discharge phase ends after inductor 102 has been fully discharged, so the current through inductor 102 reaches zero during the discharge phase and remains zero until the next charging phase. In TM, the discharge phase ends after inductor 102 is fully discharged, so the current through inductor 102 is only temporarily zero. Note that voltages 106"Va" and 108"Vb" have been generalized to apply to any PWM topology. The exact relationship between voltages 106"Va", 108"Vb" and the input / output voltages of the PWM converter will vary based on the specific PWM topology.

[0017] In an ideal scenario, the output load of the PWM converter will remain perfectly stable. However, in reality, the load on the PWM converter will vary depending on actual conditions. For example, the power draw of the load may vary accordingly if the system is in an idle state compared to an active state. To maintain a regulated DC output for varying loads, an intelligent method of switching control for the PWM converter is required. One such method is peak current mode control. During peak current control, the current through the inductor (e.g., 102) is monitored during the charging phase and compared to a reference. Once the current through the inductor exceeds the reference, the discharging phase is initiated. The switching between the charging and discharging phases is controlled, for example, by a clock, where the frequency of the clock controls the operating mode (e.g., CCM, DCM, or TM). Therefore, both the peak current through the inductor and the output of the PWM converter are regulated.

[0018] However, peak current mode control has several drawbacks. For example, when operating in CCM, subharmonic oscillations may occur when the clock duty cycle exceeds 50%. A compensation slope can be added to the current signal to suppress these oscillations; however, this adversely affects the converter's current-limiting characteristics and increases circuit complexity. Furthermore, to switch between CCM, DCM, and TM in a peak current mode control circuit, the clock frequency must be changed, which can lead to undesirable effects such as transients and the need for time for the circuit to adjust.

[0019] Accordingly, this disclosure provides circuitry and corresponding techniques for regulating a PWM converter using hysteresis regulation of inductor current (flux) to eliminate noise and achieve seamless transitions between DC-DC converter operating modes. In some aspects, voltage sensing circuitry 114 is used to monitor the voltage across inductor 102 during the discharge phase, and slope control circuitry 116 coupled to voltage sensing circuitry 114 is used to simulate the current flowing through inductor 102. Based on the control voltage V_slope_ctrl provided to slope control circuitry 116, the slope of the simulated current can be adjusted, and the charging phase can be initiated before, after, or momentarily before inductor 102 is fully discharged. This allows for precise control to selectively operate the converter in CCM, DCM, or TM, respectively.

[0020] The PWM controller 100 further includes a current sensing circuit 112 arranged in series with the inductor 102 for measuring the current passing through the inductor 102 during the charging phase. When the measured current exceeds the peak current value V_Ipk_ctrl, the peak current control circuit 118 can initiate the discharging phase. The charging and / or discharging phases can be initiated via a switch control circuit 120, which controls a first switch 104, a second switch 122, and a third switch 124. A first output 126 of the switch control circuit 120 provides a first signal "A" to the first switch 104 and the second switch 122. A second output 128 of the switch control circuit 120 provides a second signal "B" to the third switch 124.

[0021] Feedback path 130 extends from the output of voltage sensing circuit 114 to the control terminal of first switch 104. Slope control circuit 116 is arranged along feedback path 130 and includes a first voltage input terminal 132, a slope control voltage input terminal 134, a first discharge terminal 136, a second discharge terminal 138, and a switch output 140. The first voltage input terminal 132 is coupled to the output of voltage sensing circuit 114 via a third switch 124 and further coupled to sampling capacitor 142. The first discharge terminal 136 and the second discharge terminal 138 are coupled to switched capacitor 144. A second switch 122 is coupled between the output of current sensing circuit 112 and the first discharge terminal 136.

[0022] The peak current control circuit 118 includes a first voltage input terminal 146, a peak current control voltage input terminal 148, and a switch output 150. The first voltage input terminal 146 is coupled to the output of the current sensing circuit 112.

[0023] The switch control circuit 120 further includes a first input coupled to the switch output 140 of the slope control circuit 116 and a second input coupled to the switch output 150 of the peak current control circuit 118.

[0024] In some respects, the slope control circuit 116 and the peak current control circuit 118 are configured to set the voltage across the switched capacitor 144 based on the current flowing through the inductor 102. Therefore, the voltage across 144 can “track” the current flowing through the inductor. For simplicity and ease of explanation, the current sensing circuit 112 and the voltage sensing circuit 114 will be described as having a gain equal to 1 (e.g., the current sensing circuit 112 outputs a voltage in volts numerically equal to the sensed current in amperes, and the voltage sensing circuit 114 outputs a voltage numerically equal to the voltage across the inductor 102). However, it should be understood that other gain values ​​(e.g., less than 1, greater than 1) may be used without departing from the scope of this disclosure.

[0025] During the charging phase, the first switch 104 and the second switch 122 are closed, and the third switch 124 is open. The inductor is charged with a voltage 106 "Va". The current sensing circuit 112 outputs a voltage in volts at 146, which is equal to the current in amperes flowing through the current sensing circuit 112 (e.g., the same current flowing through inductor 102). Because the second switch 122 is closed, the switched capacitor 144 is charged through the output of the current sensing circuit 112 as inductor 102 is charged. Therefore, the voltage across the switched capacitor 144 (in volts) is numerically equal to the current through inductor 102 (in amperes). The current through inductor 102 increases as inductor 102 is charged. Ultimately, the peak current control circuit 118 will detect that the voltage at the first voltage input terminal 146 exceeds the voltage V_Ipk_ctrl at the peak current control voltage input terminal 148 (e.g., the current through the inductor has exceeded a certain peak current, where the peak current is controlled / set by V_Ipk_ctrl). The peak current control circuit 118 indicates to the switch control circuit 120 via the switch output 150 that the peak current has been exceeded. In response, the switch control circuit 120 switches to the discharge phase.

[0026] At the start of the discharge phase, the switch control circuit 120 disconnects the first switch 104 and the second switch 122, and closes the third switch 124 for the sampling duration. During the sampling duration, the voltage across inductor 102 is provided to sampling capacitor 142 by voltage sensing circuit 114. Slope control circuit 116 is configured to discharge switched capacitor 144 via first discharge terminal 136 and second discharge terminal 138 based on the voltage at first voltage input terminal 132 (e.g., the voltage of sampling capacitor 142) and the voltage V_slope_ctrl at slope control voltage input terminal 134. The voltage across sampling capacitor 142 is the sampled voltage of inductor 102, which provides information about the discharge rate of the inductor (e.g., the rate of change of current), because the relationship between inductor voltage and discharge rate follows... The voltage at the first voltage input terminal 132 serves as a baseline for discharging the switched capacitor 144 at the same rate as the inductor 102. The switched capacitor 144 and the inductor 102 will discharge completely simultaneously, such that the current through the inductor 102 tracks the voltage across the switched capacitor 144. Additionally, the voltage V_slope_ctrl is used to modify the discharge rate of the switched capacitor 144. For example, if V_slope_ctrl is 1, the switched capacitor 144 discharges at the same rate as the inductor 102; if V_slope_ctrl < 1, the switched capacitor 144 discharges at a slower rate than the inductor 102; and if V_slope_ctrl > 1, the switched capacitor 144 discharges at a faster rate than the inductor 102. After the switched capacitor 144 is fully discharged, the slope control circuit 116 sends a signal to the switch control circuit 120 via the switch output 140, and the switch control circuit 120 switches back to the charging phase.

[0027] Because the voltage across switched capacitor 144 simulates the current flowing through inductor 102, the PWM controller 100 controls in a known manner when the charging phase begins relative to the actual current flowing through inductor 102 by controlling the slope of the voltage change across switched capacitor 144. For example, if V_slope_ctrl > 1, the voltage across 144 reaches a predetermined value (e.g., 0) before the actual inductor current, thus initiating the charging phase before the actual inductor current reaches the predetermined value (e.g., 0), and the converter operates in CCM. If V_slope_ctrl < 1, the voltage across 144 reaches the predetermined value (e.g., 0) after the actual inductor current, thus initiating the charging phase after the actual inductor current reaches the predetermined value (e.g., 0), and the converter operates in DCM. If V_slope_ctrl = 1, the voltage across 144 reaches the predetermined value (e.g., 0) simultaneously with the actual inductor current, thus initiating the charging phase when the actual inductor current reaches the predetermined value (e.g., 0), and the converter operates in TM. Although a value of 1 is used as an instance, alternative thresholds can also be used. The use of V_slope_ctrl allows for precise control of the PWM converter's operating mode by modeling the inductor current as a voltage across the capacitor used for switch control. Furthermore, the voltage on the 144 (and therefore the operating mode) can be seamlessly adjusted by changing V_slope_ctrl without causing unwanted subharmonic oscillations, transients, etc.

[0028] The exact placement of the inductor 102, first switch 104, diode 110, capacitor (not shown), and voltage input (not shown, represented by Va and Vb) within the PWM converter can vary based on the topology of the PWM converter. Furthermore, the placement of the current sensing circuit 112 allows it to measure the current through the inductor 102 during the charging phase, and the placement of the voltage sensing circuit 114 allows it to measure the voltage across the inductor 102 during the discharging phase. The placement of the current sensing circuit 112 and the voltage sensing circuit 114 can vary accordingly based on the topology.

[0029] Figure 2 This is shown within the context of a flyback converter. Figure 1 The circuit 200 of the PWM controller. The flyback converter includes a voltage input 202, an inductor 102, a transformer 204, a diode 110, and an output capacitor 206. The inductor 102 is shown for illustrative purposes only and represents the magnetizing inductance of the transformer 204.

[0030] The current sensing circuit 112 is connected in series with the inductor 102. The voltage sensing circuit 114 is connected across the output capacitor 206, which is connected to... Figure 1Slight variations are made to maintain a 1:1 ratio between the measured current and measured voltage used for charging / discharging the switched capacitor 144, respectively. For example, if the transformer 204 has a turns ratio of 1:10, the voltage ratio of the transformer will be 1:10, and the current ratio of the transformer will be 10:1. By placing the current sensing circuit 112 on the first side of the transformer 204 and the voltage sensing circuit 114 on the second side of the transformer 204 opposite to the first side, the ratio of the charging rate to the discharging rate of the switched capacitor 144 is unaffected by the presence of the transformer 204, and the functionality of the circuit is consistent with the reference... Figure 1 The descriptions are largely the same. Alternatively, the current sensing circuit 112 and the voltage sensing circuit 114 can be placed on the same side of the transformer 204; however, the gain ratio of the current sensing circuit 112 and the voltage sensing circuit 114 must be 1:10 (or 10:1, depending on the side of the transformer). The gain ratio can be adjusted accordingly for different turns ratios.

[0031] In some aspects, circuit 200 further includes an error amplifier 208. Error amplifier 208 has a first input, a second input, and an output. The first input is coupled to the output voltage 210Vout appearing on the output capacitor 206. The second input is coupled to a reference voltage 212, and the output is coupled to a slope control voltage input terminal 134 and a peak current control voltage input terminal 148. Error amplifier 208 is configured to compare the output voltage 210 with the reference voltage 212 and adjust the slope control and peak current control accordingly to regulate the output voltage 210. For example, a change in load may cause a drop in the output voltage 210. In response, the output of error amplifier 208 increases, thereby increasing the peak current via peak current control voltage input terminal 148 and causing the converter to operate in CCM via slope control voltage input terminal 134. The increased peak current and operation in CCM increase power delivery to the load, which compensates for the voltage drop at the output. Similarly, an increase in output voltage 210 reduces the output of error amplifier 208, thereby reducing the peak current and allowing the converter to operate in DCM to deliver less power to the load and compensate for the voltage increase at the output. While the current example includes converter switching between DCM and CCM, alternative examples may not include converter switching between DCM and CCM. For example, the converter may already be in CCM and "further enter" CCM by initiating a charging phase earlier in response to an increase in power drawn by the load (e.g., when the inductor current is high).

[0032] Figure 3Examples of switching current waveforms 302, diode current waveforms 304, inductor current waveforms 306, and combined inductor current waveforms 308 for a flyback converter operating in a DCM, according to some aspects of this disclosure, are shown. In some aspects, the combined inductor current waveform 308 represents the voltage across the switched capacitor 144. In some aspects, the flyback converter is a reference... Figure 2 The flyback converter is described.

[0033] During the charging phase, the switching current waveform 302 mirrors the inductor current waveform 306. Additionally, the switching current waveform 302 may mirror the synthesized inductor current waveform 308 during the charging phase. For ease of explanation, the synthesized inductor current waveform 308 is shown / described in the following figures as being identical to the inductor current waveform 306 during the charging phase; however, the synthesized inductor current waveform 308 and the inductor current waveform 306 may also be proportional but have different magnitudes (e.g., based on the gains of the current sensing circuit 112 and the voltage sensing circuit 114). At a first time point 309, the switch is turned off, thereby initiating the discharge phase. This may occur, for example, in response to the current passing through the switch (and therefore the inductor) exceeding a peak current value set by V_Ipk_ctrl.

[0034] During the discharge phase, diode current waveform 304 mirrors inductor current waveform 306. The magnitude of the slope of the synthesized inductor current waveform 308 is less than the magnitude of the slope of inductor current waveform 306. This can be, for example, in response to V_slope_ctrl having a value less than 1. Therefore, after inductor current waveform 306 reaches 0 at the second time point 312, synthesized inductor current waveform 308 reaches 0 at the third time point 310. At time 310, the charging phase begins again. The switch turns on and the inductor charges, as shown by switch current waveform 302 and inductor current waveform 306, respectively. Because the current through the inductor has been 0 for a period of time at the second time point 310, the converter operates in DCM.

[0035] Figure 4 This illustrates a flyback converter (e.g., from) operating in a TM according to some aspects of this disclosure. Figure 2 Examples of switching current waveform 402, diode current waveform 404, inductor current waveform 406, and combined inductor current waveform 408 of a flyback converter. In some aspects, the combined inductor current waveform 408 is represented as the voltage across the switched capacitor 144. Note that the inductor current waveform 406 and the combined inductor current waveform 408 overlap in this example and are therefore shown as a single waveform.

[0036] During the charging phase, the switching current waveform 402 mirrors the inductor current waveform 406 and the combined inductor current waveform 408. During the discharging phase, the diode current waveform 404 mirrors the inductor current waveform 406 and the combined inductor current waveform 408. The inductor current waveform 406 and the combined inductor current waveform 408 reach 0 at the same time point 410, marking the start of the charging phase. Therefore, the charging phase begins approximately at the precise time point 410 when the inductor is fully discharged, and the converter can be considered to be operating in TM.

[0037] Figure 5 This illustrates a flyback converter (e.g., from) operating in a CCM according to some aspects of this disclosure. Figure 2 Examples of switching current waveform 502, diode current waveform 504, inductor current waveform 506, and combined inductor current waveform 508 for a flyback converter. In some respects, the combined inductor current waveform 508 is represented as the voltage across the switched capacitor 144.

[0038] During the charging phase, the switching current waveform 502 mirrors the inductor current waveform 506 and the synthesized inductor current waveform 508. During the discharging phase, the diode current waveform 504 mirrors the inductor current waveform 506. The magnitude of the slope of the synthesized inductor current waveform 508 is greater than the magnitude of the slope of the inductor current waveform 506. This can be, for example, in response to V_slope_ctrl having a value greater than 1. Therefore, the synthesized inductor current waveform 508 reaches 0 at the first time point 510, and the charging phase restarts. The charging phase begins before the inductor current waveform 506 reaches 0; in fact, the inductor current waveform 506 never reaches 0. Therefore, the converter can be considered to be operating in CCM.

[0039] Figure 6 This disclosure illustrates a flyback converter (e.g., from) some aspects of the present disclosure for switching between DCM and CCM. Figure 2 Examples of switching current waveform 602, diode current waveform 604, inductor current waveform 606, and composite inductor current waveform 608 for a flyback converter. In some aspects, the composite inductor current waveform 608 is represented as the voltage across the switched capacitor 144.

[0040] At the first time point 610, the converter is operating in the DCM, for example, as referenced. Figure 3 As described. At the second time point 612, the converter switches to CCM operation. This can occur in response to a change in load, for example, as described in the reference. Figure 2The error amplifier 208 is described. At the third time point 614, the converter switches back to DCM operation, for example, in response to the load returning to its original state. The transition between DCM and CCM can occur relatively seamlessly in response to changing loads. The first switch 104 selectively opens and closes in response to reaching the peak current value and the combined current reaching 0, respectively. Therefore, the circuit does not require time to adjust when transitioning between CCM and DCM, and the transition between CCM and DCM is transient-free.

[0041] Figure 7 This is a circuit diagram of a mode selection circuit system 701 for a PWM controller 100, comprising slope control circuitry 116 and peak current control circuitry 118, according to some aspects of this disclosure. In some aspects, the mode selection circuit system 701 is configured to control mode selection (e.g., CCM, DCM, TM) of the PWM converter. The mode selection circuit system 701 includes a maximum slope control voltage input 702 having a voltage V_slope_max, a minimum peak current control voltage input 704 having a voltage V_Ipk_min, and a maximum peak current control voltage input 706 having a voltage V_Ipk_max. The maximum slope control voltage input 702 is coupled to a slope control voltage input terminal 134 via a first diode 708. The minimum peak current control voltage input 704 is coupled to a peak current control voltage input terminal 148 via a second diode 710, and the maximum peak current control voltage input 706 is coupled to a peak current control voltage input terminal 148 via a third diode 712. The circuit further includes an error amplifier 714 having a first input coupled to an output voltage 716 and a second input coupled to a reference voltage 718. The output voltage 716 may be the output voltage of a PWM converter. The output of the error amplifier 714 is coupled to a slope control voltage input terminal 134 via a first resistor 720 and to a peak current control voltage input terminal 148 via a second resistor 722.

[0042] In some aspects, V_Ipk_min < V_Ipk_max < V_slope_max. When the output voltage of error amplifier 714 drops below V_Ipk_min, the peak current control voltage V_Ipk_ctrl is clamped to V_Ipk_min, and only the slope control voltage V_slope_ctrl is allowed to decrease, thereby forcing DCM operation. When the output voltage of error amplifier 714 increases above V_Ipk_max, the peak current control voltage V_Ipk_ctrl is clamped to V_Ipk_max, and only the slope control voltage V_slope_ctrl is allowed to increase, thereby forcing CCM operation. When the output voltage of error amplifier 714 increases above V_slope_max, the peak current control voltage V_Ipk_ctrl is clamped to V_Ipk_max, and the slope control voltage V_slope_ctrl is clamped to V_slope_max, and the converter enters current limit. The current configuration is merely exemplary for the purpose of more detailed explanation of the functions of PWM controller 100. Other variations of the mode selection circuitry 701 may be used without departing from the scope of the present disclosure.

[0043] Figure 8 illustrates a PWM controller 100 according to some aspects of the present disclosure, which includes a slope control circuit 116, a peak current control circuit 118, and a switch control circuit 120. Figure 1 from

[0044] In some aspects, the slope control circuit 116 includes a voltage multiplier 802, a transconductance amplifier 804, and a first comparator 806. A first voltage input terminal 132 and a slope control voltage input terminal 134 are coupled to the input of the voltage multiplier 802. The output of the voltage multiplier is coupled to the input of the transconductance amplifier 804, and the output of the transconductance amplifier 804 is coupled to the first and second terminals of a switched capacitor 144. The transconductance amplifier 804 discharges the switched capacitor at a certain rate based on the voltage provided at the first voltage input terminal 132 multiplied by V_slope_ctrl. The first comparator 806 includes first and second inputs coupled to the first and second terminals of the switched capacitor 144. When the voltage across the switched capacitor 144 reaches 0 (e.g., the switched capacitor 144 is fully discharged), the first comparator 806 sets the switch output 140 to high. As previously described, V_slope_ctrl can be modified to operate the converter in CCM, DCM, or TM.

[0045] In some aspects, the peak current control circuit 118 includes a second comparator 808. The second comparator 808 includes a first input coupled to the output of the current sensing circuit 112 and a second input coupled to the peak current control voltage input terminal 148. The second comparator is configured to set the switch output 150 high when the sensed current exceeds the peak current indicated by V_Ipk_ctrl.

[0046] In some aspects, the switch control circuit 120 includes an SR latch 810, a first edge-triggered pulse generator 812 (e.g., monostable), and a second edge-triggered pulse generator 814. The set input of the SR latch 810 is coupled to the switch output 140, and the reset input of the SR latch is coupled to the switch output 150. When the peak current control circuit 118 sets the switch output 150 high, the SR latch 810 is reset, causing the first switch 104 and the second switch 122 to open (e.g., in start-up discharge mode). Furthermore, when the SR latch 810 is reset, a falling edge triggers the first edge-triggered pulse generator 812. The second edge-triggered pulse generator 814 is triggered, causing the third switch 124 to close for the duration of the pulse. The voltage provided by the output of the voltage sensing circuit 114 is "sampled" when the third switch 124 closes during the pulse and is "held" after the third switch 124 opens after the pulse. When the slope control circuit 116 sets the switch output 140 high (e.g., when the switch capacitor 144 is fully discharged), the charging phase is initiated by closing the first switch 104 and the second switch 122.

[0047] The foregoing description and illustration of the method is a series of operations or events, but the order in which such operations or events are described is not restrictive. For example, some operations or events may occur in a different order and / or simultaneously with other operations or events besides those described and / or illustrated herein. Furthermore, some of the described operations or events may be optional for implementing one or more aspects or instances of this specification. Additionally, one or more of the operations or events depicted herein may be performed in one or more separate operations and / or phases. In some instances, the method described above may be implemented in a computer-readable medium using instructions stored in memory.

[0048] In this specification, the term "coupling" may encompass a connection, link, or signal path that achieves a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0049] A device “configured to” perform a task or function can be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform a function and / or can be configured (or reconfigured) by the user after manufacturing to perform a function and / or other additional or alternative functions. Configuration can be done via firmware and / or software programming of the device, via the construction and / or layout of the device’s hardware components and interconnections, or a combination thereof.

[0050] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to interconnections or terminations between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0051] A circuit or device described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may substantially contain only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0052] While this document describes the use of specific transistors, other transistors (or equivalent devices) can actually be used with little or no alteration to the remaining circuitry. For example, field-effect transistors, bipolar junction transistors (BJTs, such as NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) can be used in place of or in combination with the devices described herein. The transistors can be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices can be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0053] While some elements in the described examples are contained within the integrated circuit, and others are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Furthermore, some or all features shown as being external to the integrated circuit may be contained within the integrated circuit, and / or some features shown as being internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0054] The use of the phrase "grounding" in the foregoing description includes chassis grounding, earth grounding, floating grounding, virtual grounding, digital grounding, common grounding, and / or any other form of grounding connection applicable to or suited to the teachings of this specification. Unless otherwise stated, the words "about," "approximately," or "substantially" preceding a value mean + / - 10% of the parameter. Modifications to the described examples are possible within the scope of the claims, and other embodiments are possible.

Claims

1. A circuit comprising: First current path; An inductor arranged along the first current path, the inductor including a first terminal and a second terminal; A current sensing circuit is arranged in series with the inductor along the first current path; A first switch is coupled between the inductor and the current sensing circuit; A voltage sensing circuit includes a first input and a second input respectively coupled to the first terminal and the second terminal of the inductor; A feedback path extends from the output of the voltage sensing circuit to the control terminal of the first switch; A slope control circuit, which is arranged along the feedback path and coupled to the output of the voltage sensing circuit, the slope control circuit including a switching output; A peak current control circuit coupled to the output of the current sensing circuit, the peak current control circuit including a switching output; as well as A switch control circuit includes a first input coupled to the switch output of the slope control circuit, a second input coupled to the switch output of the peak current control circuit, and a first output coupled to the control terminal of the first switch.

2. The circuit of claim 1, further comprising a sampling capacitor having a first terminal coupled to the output of the voltage sensing circuit.

3. The circuit of claim 2, further comprising a switched capacitor arranged along the feedback path, wherein the slope control circuit further comprises: A first voltage input terminal is coupled to the first terminal of the sampling capacitor; Slope control voltage input terminal; as well as The first and second discharge terminals are respectively coupled to the first and second terminals of the switched capacitor.

4. The circuit according to claim 3, wherein the peak current control circuit further comprises: A first voltage input terminal, wherein the first voltage input terminal is coupled to the output of the current sensing circuit; as well as Peak current control voltage input terminal.

5. The circuit of claim 4, further comprising a second switch coupled between the output of the current sensing circuit and the first discharge terminal of the slope control circuit, wherein the control terminal of the second switch is coupled to the first output of the switch control circuit.

6. The circuit of claim 5, further comprising a third switch coupled between the output of the voltage sensing circuit and the first voltage input terminal of the slope control circuit, wherein the control terminal of the third switch is coupled to a second output of the switch control circuit.

7. The circuit according to claim 6, wherein the switch control circuit further comprises: A set-reset (SR) latch includes a set input coupled to a first input of the switch control circuit, a reset input coupled to a second input of the switch control circuit, and an output coupled to a first output of the switch control circuit; A first edge-triggered pulse generator includes an edge-triggered input coupled to the output of the SR latch, and an output; as well as The second edge-triggered pulse generator includes an edge-triggered input coupled to the output of the first edge-triggered pulse generator, and an output coupled to the second output of the switch control circuit.

8. The circuit according to claim 7, wherein the slope control circuit further comprises: A voltage multiplier includes a first input coupled to the first voltage input terminal of the slope control circuit, a second input coupled to the slope control voltage input terminal, and an output; A transconductance amplifier, comprising an input coupled to the output of the voltage multiplier, and first and second outputs coupled to the first and second discharge terminals; as well as The first comparator includes a first input coupled to the first discharge terminal, a second input coupled to a voltage reference, and an output coupled to the switching output of the slope control circuit.

9. The circuit of claim 8, wherein the peak current control circuit further comprises: The second comparator includes a first input coupled to the first voltage input terminal of the peak current control circuit, a second input coupled to the peak current control voltage input terminal, and an output coupled to the switch output of the peak current control circuit.

10. The circuit of claim 4, further comprising an error amplifier, wherein the output of the error amplifier is coupled to the slope control voltage input terminal and the peak current control voltage input terminal.

11. The circuit of claim 10, wherein the circuit is part of a pulse width modulation (PWM) converter, wherein the output of the PWM converter is coupled to a first input of the error amplifier, and wherein a reference output voltage is coupled to a second input of the error amplifier.

12. The circuit of claim 11, wherein the output of the error amplifier is coupled to the slope control voltage input terminal via a first resistor, wherein the output of the error amplifier is coupled to the peak current control voltage input terminal via a second resistor, and wherein the circuit further comprises: A first diode is coupled between the peak current control voltage input terminal and the minimum peak current voltage; The second diode is coupled between the peak current control voltage input terminal and the maximum peak current voltage. as well as A third diode is coupled between the slope control voltage input terminal and the maximum slope voltage.

13. A circuit comprising: A voltage sensing circuit includes first and second inputs coupled to first and second terminals of an inductor; A current sensing circuit, which is arranged in series with the inductor; A first switch is arranged between the inductor and the current sensing circuit; A peak current control circuit coupled to the output of the current sensing circuit, wherein the peak current control circuit is configured to selectively disconnect the first switch via a switch control circuit based on the sensed current and the peak current control voltage. as well as A slope control circuit coupled to the output of the voltage sensing circuit, wherein the slope control circuit is configured to selectively close the first switch via the switch control circuit based on the sensed voltage and the slope control voltage.

14. The circuit of claim 13, wherein the inductor and the first switch are included in a pulse width modulation (PWM) converter, wherein the PWM converter operates in discontinuous conduction mode (DCM) when the slope control voltage is less than a threshold, wherein the PWM converter operates in continuous conduction mode (CCM) when the slope control voltage is greater than the threshold, and wherein the PWM converter operates in transition mode (TM) when the slope control voltage is equal to the threshold.

15. The circuit of claim 13, further comprising a switched capacitor having first and second terminals coupled to the slope control circuit, wherein the slope control circuit is configured to: The switched capacitor is discharged based on the sensed voltage and the slope control voltage; and In response to the voltage of the switched capacitor dropping below a threshold, the first switch is selectively closed via the switch control circuit.

16. The circuit of claim 15, further comprising a second switch disposed between the output of the current sensing circuit and the first terminal of the switched capacitor, wherein a control terminal of the first switch is coupled to a control terminal of the second switch.

17. A method for controlling a pulse width modulation (PWM) converter, comprising: During the first discharge phase: The voltage across the inductor is sensed and the sampling capacitor is charged based on the sensed voltage; Based on the voltage and slope control voltage stored on the sampling capacitor, the switched capacitor is discharged at a certain rate; as well as The charging phase begins in response to a drop in voltage across the switched capacitor below a threshold. The operating mode of the PWM converter is based on the slope control voltage.

18. The method of claim 17, wherein the operating mode is one of the following: discontinuous conduction mode (DCM), continuous conduction mode (CCM), or transition mode (TM).

19. The method of claim 17, further comprising: During the charging phase: The current passing through the inductor is sensed and the switched capacitor is charged based on the sensed current; as well as The second discharge phase is initiated in response to the sensed current exceeding the peak current threshold.

20. The method of claim 19, wherein the peak current threshold is based on the peak current control voltage.

Images