Improved power-like nonlinear function implementation method

Abstract

The invention relates to an improved power-like nonlinear function implementation method. According to the method, through calculation of sign bits, exponent bits and mantissa bits of decoupling function values, intervals required by a lookup table are remarkably compressed. Firstly, index bits and sign bits of function values are directly determined through index bits and sign bits of input values through a mathematical formula; the input mantissa bits are constructed into new input values, and the new input values are mapped to a preset compression interval; an LUT is established on the interval, and a mantissa digit approximate value is calculated through linear interpolation; and finally combining the three parts to obtain a final result. The method is suitable for functions such as square root, reciprocal and reciprocal square root, and supports IEEE 754 format floating-point number processing. The method has the advantages that the LUT storage overhead is greatly reduced, interpolation errors are reduced, and operation overflow is avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of digital circuit, in particular to an improved implementation method of a class of power-like nonlinear function. BACKGROUND

[0002] Nonlinear functions play an irreplaceable role in mathematical modeling, signal processing, artificial intelligence, and engineering control. They can describe the dynamic behavior of complex systems, such as activation functions in neural networks that introduce expressive power through nonlinear transformations, enabling models to fit highly nonlinear data relationships. However, the calculation of nonlinear functions often involves complex operations such as exponentials, logarithms, and trigonometric functions, and direct real-time calculation can consume a large amount of computing resources, increase system latency and hardware cost. To balance the accuracy and efficiency of the calculation, look-up table (LUT) has become a widely used efficient method.

[0003] The core idea of LUT is to pre-store a series of sampling points of the nonlinear function, and to quickly look up the table by the input value during actual calculation, and to calculate the approximate result using interpolation method. In the prior art, the input value is usually queried in the left and right adjacent two sampling points on the x-axis, a linear function is constructed using the two sampling points, and the input value is substituted into the linear function to calculate the approximate value of the nonlinear function.

[0004] This method significantly reduces the resources required for nonlinear function calculation, especially suitable for resource-constrained scenarios such as FPGA or embedded systems, but also introduces additional storage overhead and certain approximation error. The more sampling points LUT stores, the smaller the distance between sampling points, and the smaller the approximation error introduced; vice versa.

[0005] In addition, for nonlinear functions with very large domain or very steep variation in a certain interval, it is very difficult to balance the storage overhead and the approximation error, because a small number of sampling points cannot capture the characteristics of the entire nonlinear function.

[0006] Therefore, there is an urgent need for an implementation method to reduce the approximation error of the LUT result of the class of power-like nonlinear function in hardware with limited storage resources. SUMMARY

[0007] To solve the above technical problems, an improved implementation method of a class of power-like nonlinear function, in hardware circuit, efficiently implements a class of power-like nonlinear function by decoupling the calculation of the sign bit, the exponent bit and the mantissa bit of the function value; comprising the following steps: Step S1: receiving a floating-point input value conforming to IEEE 754 standard, separating its sign bit, exponent bit and mantissa bit; Step S2: calculating the exponent bits of the function value directly according to the exponent bits of the input value and determining the sign bits of the function value according to the sign bits of the input value through mathematical formula derivation; Step S3: based on the mantissa bits of the input value, constructing a new input value within a predetermined compression interval through splicing a fixed prefix or logical shifting; Step S4: searching for two adjacent sampling points and their corresponding function values in a lookup table (LUT) constructed in advance on the predetermined compression interval; Step S5: calculating the approximate value of the mantissa bits of the function value according to the new input value and the two adjacent sampling points using the linear interpolation method; Step S6: combining the calculated sign bits, exponent bits and approximate value of the mantissa bits of the function value to form the final function approximation result; Wherein, the predetermined compression interval is much smaller than the original domain of the power-like nonlinear function.

[0008] In an embodiment of the present application, the power-like nonlinear function includes the reciprocal function , square root function and reciprocal square root function , wherein x is the input value.

[0009] In an embodiment of the present application, the operation of calculating the exponent bits of the function value in step S2 is realized by an adder and a shifter.

[0010] In an embodiment of the present application, in step S3, the method of constructing the new input value is to splice a prefix value of a fixed bit width determined by the parity of the exponent bits before the mantissa bits of the input value.

[0011] In an embodiment of the present application, the lookup table (LUT) is stored in a RAM, the depth of the RAM is the number N of sampling points, and the width of the RAM is the bit width of the mantissa bits of the function value.

[0012] In an embodiment of the present application, the process of searching for adjacent sampling points in step S4 is realized by a judgment logic circuit, which determines the interval segment where the new input value is located by comparing the new input value with the stored interval boundary values, and outputs the addresses of the two end sampling points in the RAM.

[0013] In an embodiment of the present application, the read logic of the RAM is to read out the two adjacent sampling points and their corresponding function values according to the addresses output by the judgment logic circuit, and input them to the linear interpolation operation module.

[0014] In an embodiment of the present application, in step S5, the linear interpolation formula is as follows: wherein is a new input value, , are respectively two adjacent sampling points, and ≥ , .

[0015] In one embodiment of the present application, the operation module performing the linear interpolation comprises: a divider for calculating a slope: ; a multiplier for calculating the product of the slope and an offset: ; at least one adder for calculating the function value difference, the sampling point difference, and the final sum product: ， ， ， .

[0016] In one embodiment of the present application, it is applicable to handle the regular number, irregular number and zero input value, and avoids overflow or underflow in the calculation process through the way of constructing the new input value.

[0017] The above technical solution of the present application has the following advantages compared with the prior art: the implementation method of the power-like nonlinear function of the present application maps the entire definition domain of the nonlinear function to a smaller subset by decoupling the calculation of the sign bit, the exponent bit and the mantissa bit of the nonlinear function, which can more effectively realize the LUT; and only the mantissa bit of the input value and an additional bit are needed for table lookup when calculating the mantissa bit approximation of the nonlinear function, which reduces the address bit width; the mantissa bit of the input value is constructed as a new input value, which is certainly located in the interval for realizing the LUT, avoiding the scenarios of input overflow or underflow. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to make the content of the present application more easily understood, the present application will be further described in detail below according to specific embodiments of the present application and in conjunction with the accompanying drawings.

[0019] Figure 1 is a flowchart of the improved power-like nonlinear function implementation method of the present application.

[0020] Figure 2 is a specific implementation schematic flowchart of the present application. ​

[0021] Figure 3 A specific embodiment hardware structure diagram of the present application.

[0022] Figure 4 Absolute error distribution comparison diagram of the power function of the present application.

[0023] Figure 5 Relative error distribution comparison diagram of the power function of the present application.

[0024] Figure 6 Absolute error distribution comparison diagram of the power function of the present application.

[0025] Figure 7 Relative error distribution comparison diagram of the power function of the present application.

[0026] Figure 8 FP32 floating point number format classification diagram of the present application.

[0027] Figure 9 Error value comparison diagram of the present application about .

[0028] Figure 10 Error comparison diagram of the present application about . DETAILED DESCRIPTION

[0029] As shown in Figures 1-3 , the embodiment provides an improved power-like nonlinear function implementation method, which comprises the following steps: The present embodiment will be implemented by using the power function , and the data type is FP32. The FP32 type data is composed of 1-bit sign bit S, 8-bit exponent bit E and 23-bit mantissa bit M.

[0030] Specifically, as shown in Figure 8 , there are ten different classifications of FP32; wherein, the representation formula of the non-normal number is , and the representation formula of the normal number is .

[0031] The present embodiment is only for the scenarios of input value being 0, non-normal number and normal number. In these three scenarios, the function value of the power function is certainly greater than or equal to 0, that is, S is 0. Therefore, the subsequent part will ignore the sign bit to simplify the description.

[0032] Scenario one, input value is 0: .

[0033] Scenario 2, input value is the number of specifications: Input value function value At this time, the function value This refers to the number of specifications.

[0034] Assumption , .

[0035] make ,but , .in, , .

[0036] When the exponent is odd .because , , ,so , .therefore , .

[0037] At this point, the function value sign bit =0; function value exponent By input values exponent Add a constant 127 and then shift right by one bit to obtain the result; by inputting the value mantissa A new input value is constructed by extending the input with a nine-bit binary number 0b001111111. Then to The results were obtained using a lookup table-based method and linear interpolation. , The last 23 bits of the binary representation are the function value. mantissa Therefore, it is only necessary to... range Implement the power function LUT.

[0038] When the exponent is even .because , , ,so , .therefore , .

[0039] At this point, the function value sign bit =0; function value exponent By input values exponent Add a constant 126 and then shift right by one bit to obtain the result; by inputting the value mantissa A new input value is constructed by extending the input with a nine-bit binary number 0b010000000. Then to The results were obtained using a lookup table-based method and linear interpolation. , The last 23 bits of the binary representation are the function value. mantissa Therefore, it is only necessary to... range Implement the power function LUT.

[0040] In summary, in scenario two, it is only necessary to be within the range... Implement the power function LUT, not input value range This greatly reduces the lookup range of the LUT.

[0041] Scenario 3, Input value is a non-standard number: Input value function value At this time, the function value This refers to the number of specifications.

[0042] Assumption , .

[0043] at this time, In order to construct the form of the specification number representation formula, it is necessary to ensure that Even number and ,Right now The specific implementation method is as follows: first, Initialize to 0; then, input value mantissa Perform a left shift; each left shift... The value is incremented by 1; when When the highest bit 1 is shifted left to the 24th bit, a judgment is made. Is it an even number?

[0044] if is even, then , and a new input value can be constructed by extending a nine-bit binary number 0b001111111 in front of the low 23 bits of after shifting , i.e. , and an intermediate result is obtained by a method based on a lookup table and linear interpolation, and the low 23 bits of the intermediate result are ; if is odd, then needs to be transformed into , so as to meet the format of the specification number, at this time, , and a new input value can be constructed by extending a nine-bit binary number 0b010000000 in front of the low 23 bits of after shifting , i.e. , and an intermediate result is obtained by a method based on a lookup table and linear interpolation, and the low 23 bits of the intermediate result are .

[0045] In summary, in scenario three, only the LUT of the power function in the range interval needs to be implemented, rather than the range interval of the input value , which coincides with the LUT lookup interval in scenario two.

[0046] According to the analysis and summary of the above three scenarios, the LUT lookup interval of the power function is reduced from to , and in the LUT table with the same depth, the lookup step is less than one percent of the original, which greatly improves the fitting accuracy.

[0047] Figure 4 and Figure 5 respectively compare the absolute error curve and the relative error curve of the power function calculated by the present application and the traditional lookup table, and the results are shown in Figure 9 . From Figure 9 , it can be concluded that the calculation error of the power function is reduced by more than three orders of magnitude, which greatly improves the calculation accuracy; and as shown in Figure 9 , the error of .

[0048] For the power function , the implementation is described as follows: the power function The function value must be greater than 0, meaning S is 0. Therefore, the sign bit will be ignored in the following sections to simplify the explanation.

[0049] Scenario 1, input value is the number of specifications: Input value function value At this time, the function value This refers to the number of specifications.

[0050] Assumption , .

[0051] make ,but , .in, , .

[0052] When the exponent is odd and hour, .because , ,so , .therefore , .

[0053] At this point, the function value sign bit =0; function value exponent By subtracting the input value from a constant 381 exponent Then shift right by one position to obtain the function value. mantissa It is 0.

[0054] When the exponent is odd and hour, .because , , ,so , .therefore , .

[0055] At this point, the function value sign bit =0; function value exponent By subtracting the input value from a constant 379 exponent Then shift right by one bit to obtain the result; by inputting the value... mantissa a new input value is constructed by extending one nine-bit binary number 0b001111101 in front of the exponent bits of the input value Then, the LUT-based method and linear interpolation method are used to calculate the binary of the last 23 bits of , is the mantissa of the function value . Therefore, only the LUT of the power function needs to be implemented in the range interval .

[0056] When the exponent bits are even, Because , , , so , Therefore , .

[0057] At this time, the sign bit of the function value is 0; the exponent bits of the function value are obtained by subtracting a constant 380 from the exponent bits of the input value and then right shifting one bit; a new input value is constructed by extending one nine-bit binary number 0b001111110 in front of the mantissa bits of the input value , and then is calculated using the LUT-based method and linear interpolation method , the binary of the last 23 bits of is the mantissa of the function value . Therefore, only the LUT of the power function needs to be implemented in the range interval . In summary, in scenario one, only the LUT of the power function

[0058] needs to be implemented in the range interval , not the range interval of the input value , which greatly compresses the lookup interval of the LUT.

[0059] Scenario two, the input value is a non-canonical number: the input value ​​function value At this time, the function value This refers to the number of specifications.

[0060] Assumption , .

[0061] at this time, In order to construct the form of the specification number representation formula, it is necessary to ensure that Even number and ,Right now The specific implementation method is as follows: first, Initialize to 0; then, input value mantissa Perform a left shift; each left shift... The value is incremented by 1; when When the most significant 1 is shifted left to the 24th bit, a judgment is made. Is it an even number?

[0062] if Even number and after shift If the lower 23 are all 0, then and ,Right now , ;if Even number and after shift If the lower 23 are not all zero, then Therefore, it is necessary to Transform into Thus ,at this time, And after the shift By extending the lower 23 bits with a nine-bit binary number 0b001111101, a new input value can be constructed. The new input value is then processed using a lookup table-based method and linear interpolation to obtain an intermediate result, the lower 23 bits of which are the input value. ;if If it is an odd number, then it is necessary to... Transform into This satisfies the format of the specification number. And after the shift A new input value can be constructed by extending the lower 23 bits with a nine-bit binary number 0b001111110. ,Right now The new input value is then processed using a lookup table-based method and linear interpolation to obtain an intermediate result, the lower 23 bits of which are the input value. .

[0063] In the second scenario, only the LUT of the power function in the range interval needs to be implemented, instead of the range interval of the input value , which coincides with the LUT lookup interval in the first scenario.

[0064] According to the analysis and summary of the above three scenarios, the LUT lookup interval of the power function is reduced from to , and in the LUT table with the same depth, the lookup step is less than one hundredth of the original, greatly improving the fitting accuracy.

[0065] Figure 6 and Figure 7 respectively compare the absolute error curve and the relative error curve (for easy comparison, only the interval with larger error is shown) of the power function calculated by the present application and the traditional lookup table, and the results are shown in Figure 10 . From Figure 10 , it can be concluded that the calculation error of the power function is reduced by more than seven orders of magnitude, greatly improving the calculation accuracy; the error in Figure 10 can be seen.

[0066] In summary, the method described in this embodiment is applicable to functions such as square root, reciprocal and reciprocal square root, and supports IEEE754 format floating point number processing. Its advantages lie in greatly reducing LUT storage overhead, reducing interpolation error, and avoiding operation overflow.

[0067] Obviously, the above embodiments are only examples for clear illustration, and are not a limitation on the implementation. For ordinary skilled persons in the art, other different forms of changes or variations can be made on the basis of the above description. Here, it is not necessary and impossible to exhaust all the implementations. The obvious changes or variations derived therefrom are still within the protection scope of the present application.​

Claims

1. An improved method for implementing a power-like nonlinear function, the method being implemented in FPGA or ASIC hardware circuits, characterized in that, In hardware circuits, power-like nonlinear functions are efficiently implemented by decoupling the calculation of the sign bit, exponent bit, and mantissa bit of the function value; this includes the following steps: Step S1: Receive a floating-point input value conforming to the IEEE 754 standard and separate its sign bit, exponent bit, and mantissa bit; Step S2: Through mathematical formula derivation, the exponent of the function value is directly calculated based on the exponent of the input value, and the sign of the function value is determined based on the sign of the input value; in step S2, the operation of calculating the exponent of the function value is implemented by an adder and a shifter; Step S3: Based on the last few digits of the input value, construct a new input value located within a predetermined compression range by concatenating a fixed prefix or logical shifting; Step S4: In the lookup table pre-built on the predetermined compression interval, find two sampling points adjacent to the new input value and their corresponding function values; the process of finding adjacent sampling points in step S4 is implemented by a judgment logic circuit, which determines the interval segment in which the new input value is located by comparing the new input value with the stored interval boundary value, and outputs the addresses of the sampling points at both ends of the interval segment in RAM; Step S5: Using linear interpolation, calculate the approximate value of the function value's last digits based on the new input value and two adjacent sampling points; Step S6: Combine the approximate values ​​of the sign bit, exponent bit, and mantissa bit of the calculated function value to form the final function approximation result; The predetermined compression interval is much smaller than the original domain of the power-like nonlinear function.

2. The method for implementing a power-like nonlinear function according to claim 1, characterized in that: The power-like nonlinear function includes the reciprocal function. Square root function and the reciprocal square root function , where x is the input value.

3. The method for implementing a power-like nonlinear function according to claim 1, characterized in that: In step S3, the method for constructing the new input value is to append a prefix value with a fixed width determined by the parity of the exponent of the input value to the last few digits of the input value.

4. The method for implementing an exponential nonlinear function according to claim 1, characterized in that: The lookup table is stored in a RAM with a depth equal to the number of sampling points N and a width equal to the mantissa of the function value.

5. The method for implementing a power-like nonlinear function according to claim 1, characterized in that: The read logic of the RAM is as follows: based on the address output by the judgment logic circuit, the two adjacent sampling points and their corresponding function values ​​are read out simultaneously and input to the linear interpolation operation module.

6. The method for implementing a power-like nonlinear function according to claim 1, characterized in that: In step S5, the linear interpolation formula is as follows: ,in For the new input value, , These are two adjacent sampling points, and ≥ , < .

7. The method for implementing a power-like nonlinear function according to claim 6, characterized in that: The computation module for performing the linear interpolation includes: A divider for calculating the slope: ; A multiplier is used to calculate the product of the slope and the offset: ; At least three adders are used to calculate the difference in function values, the difference in sample points, and the final sum-product: ， ， ， .

8. The method for implementing a power-like nonlinear function according to claim 1, characterized in that: It is suitable for handling standard numbers, non-standard numbers, and zero input values, and avoids overflow or underflow during the calculation process by constructing the new input value.

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