A signal processor access method and computer device

Abstract

The application relates to the technical field of device communication management, in particular to a signal processor access method and a computer device. The method comprises the following steps: in response to system power-on, a first controller sets an access enable signal to an invalid state to limit a management controller from accessing a signal processor; the model of the signal processor is acquired, and a fixed delay is determined according to the model of the signal processor; in response to detecting that the signal processor is loaded, a timer is started; the environmental parameters of the signal processor are acquired, and a compensation delay is determined according to the environmental parameters; a target delay is determined according to the fixed delay and the compensation delay; in response to the target delay time reaching, the management controller accesses the signal processor; by the method, the chip access timeliness can be improved, and the influence range of chip communication interruption can be reduced.

Description

Technical Field

[0001] This application relates to the field of device communication management technology, and in particular to a signal processor access method and a computer device. Background Technology

[0002] With the widespread deployment of PCIe buses in high-performance computing, enterprise servers, and data centers, signal processors are integrated into motherboard designs as key components to enhance signal quality and extend transmission distances. Signal processors ensure the stability and reliability of PCIe links during high-speed transmission by retiming and reshaping signals. During system startup, the Baseboard Management Controller (BMC), as the underlying management controller, is responsible for automatically identifying, scanning, and initializing PCIe devices, which includes accessing and configuring signal processors.

[0003] To avoid conflicts caused by the BMC accessing the signal processor before it has completed internal initialization or firmware loading, existing technologies mainly employ two strategies to control the access timing: First, a delay time is preset in the BMC firmware, and the signal processor is accessed only after the system is powered on, thus avoiding its firmware loading phase. Second, the BMC periodically reads the signal processor's status register to determine whether it has completed initialization, thereby deciding when to initiate the access and configuration process.

[0004] While the methods described above mitigate access conflicts to some extent, they still have significant limitations. Fixed-delay strategies lack adaptability, easily leading to insufficient latency or resource waste when faced with variations in signal processor loading times across different models or operating environments. Polling mechanisms, while possessing some dynamic judgment capabilities, increase system communication load, and status determination may result in misjudgments due to signal fluctuations or interface instability. If the BMC accesses the signal processor before firmware loading is complete, it can cause firmware loading interruptions, configuration conflicts, or link training failures, and in severe cases, even lead to "card drop," affecting the integrity of the system's device identification and consequently reducing overall system stability and operational efficiency. Therefore, existing mechanisms still suffer from insufficient reliability in practical deployments and urgently require optimization. Summary of the Invention

[0005] Therefore, it is necessary to provide a signal processor access method and computer device that can improve the timeliness of signal processor access and reduce the impact of communication interruptions, in order to address the above-mentioned technical problems.

[0006] On the one hand, a signal processor access method is provided, including:

[0007] In response to system power-on, the first controller sets the access enable signal to an invalid state to restrict the management controller's access to the signal processor;

[0008] Obtain the signal processor model and determine the fixed delay based on the signal processor model;

[0009] A timer is started in response to the detection that the signal processor has finished loading;

[0010] Obtain the environmental parameters of the signal processor and determine the compensation delay based on the environmental parameters;

[0011] The target delay is determined based on the fixed delay and the compensated delay;

[0012] In response to the delay in reaching the target, the management controller is triggered to access the signal processor.

[0013] On the other hand, a computer device is also provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the signal processor access method described in the first aspect.

[0014] By implementing the aforementioned signal processor access method, device, computer device, and storage medium, this method, after the system is powered on, has a first controller take over and control the communication link between the management controller and the signal processor. Firstly, the access enable signal is set to an invalid state, disconnecting the communication connection between the management controller and the signal processor during the loading phase, ensuring that the signal processor is not interfered with during loading at the hardware level. The first controller, through its pin interface connected to the signal processor, can collect key pin information to determine the chip type or manufacturer category, providing a basis for subsequent loading status identification. Based on the category information, the first controller uses a matching status identification method to monitor the loading process of the signal processor, obtaining real-time information on whether firmware loading has been completed. Once it is determined that the signal processor has completed the loading operation, the logic device switches the access enable signal back to valid, allowing the management controller to re-establish the communication connection with the signal processor. Through hardware-level isolation of the communication link, logical control of the status judgment process, and unified management of communication access permissions, access protection and precise timing control of communication access during the signal processor loading phase are achieved, thereby ensuring the integrity of the chip loading process and the reliability of the system's identification link. Attached Figure Description

[0015] Figure 1 This is a flowchart of a signal processor access method in one embodiment.

[0016] Figure 2 This is a structural diagram of a signal processor access method in one embodiment.

[0017] Figure 3 This is a control flowchart of a signal processor access method in one embodiment.

[0018] Figure 4 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0020] In one embodiment, such as Figure 1 As shown, a signal processor access method is provided, including:

[0021] S100: In response to system power-on, the first controller sets the access enable signal to an invalid state to restrict the management controller from accessing the signal processor;

[0022] S200: Obtain the signal processor model and determine the fixed delay based on the signal processor model;

[0023] S300: In response to detecting that the signal processor has finished loading, a timer is started;

[0024] S400: Acquires the environmental parameters of the signal processor and determines the compensation delay based on the environmental parameters;

[0025] S500: Determine the target delay based on the fixed delay and the compensated delay;

[0026] S600: In response to the delay time in reaching the target, the management controller is triggered to access the signal processor.

[0027] The system comprises the following components: a signal processor (used for signal shaping and delay compensation in high-speed interfaces to improve link stability and signal integrity, applicable to high-speed interconnect channels such as PCIe, USB, and SAS); a first controller (Programmable Logic Device, PLD, FPGA or CPLD) for implementing specific control logic; a baseboard management controller (BMC) for monitoring the signal processor's loading status and controlling access; a communication enable signal (issued by the control logic to control whether the communication link is open, determining whether the management controller can access the signal processor); and an access enable signal controlled by the first controller for managing the communication connection.

[0028] Specifically, by integrating a signal processor, a first controller (PLD), and a management controller (BMC) onto the motherboard and establishing connections between them, the first controller can not only monitor the loading status of the signal processor in real time but also actively control the communication status between the BMC and the signal processor during the loading incomplete phase, enabling or disabling access. This design prevents problems such as loading interruption, link training failure, or card drop during the firmware loading phase due to premature access by the BMC, significantly improving system stability and device identification integrity during startup. Furthermore, because the control logic is integrated into the PLD, it possesses excellent configurability and hardware isolation characteristics, allowing flexible adaptation to different signal processor chip models and complex system deployment scenarios, enhancing system reliability and maintainability.

[0029] By disabling the access enable signal during the initial power-up of the system, access permissions to the management controller are restricted, providing secure timing protection for the stable loading of the signal processor. Building upon this, the system further determines a fixed delay based on the actual signal processor model being connected, ensuring sufficient coverage of loading time differences for different device models. Simultaneously, this solution calculates a corresponding compensation delay by real-time acquisition of environmental parameters of the signal processor, such as temperature and voltage, making delay control more refined and adaptable. Once the system detects that the signal processor has completed loading, a timing mechanism is initiated, and the target delay time is determined by combining the fixed delay and the compensation delay. Finally, the management controller's access operation is triggered at this target time. This delayed access mechanism considers not only the static differences in chip models but also the dynamic fluctuations of the operating environment, significantly improving the system's compatibility and robustness under multi-chip and multi-environment conditions. The overall solution achieves autonomous judgment of the signal processor's loading status and access timing control without relying on external synchronization signals, effectively improving the system's stability and reliability.

[0030] In one embodiment, such as Figure 2 As shown, the motherboard also includes a temperature sensor and a voltage monitor. The temperature sensor is connected to the first controller to monitor the system temperature, and the voltage monitor is connected to the first controller to monitor the power supply voltage of the signal processor.

[0031] The system includes a temperature sensor for real-time monitoring of the system or key chip temperature and transmitting the collected data to the control unit. In this solution, the temperature sensor is connected to the first controller, enabling it to sense changes in the system's ambient temperature and assisting in determining the signal processor's operating status or risk conditions. A voltage monitor is used to detect whether the supply voltage of the target device is stable or has reached a specified threshold, typically used for power-on detection, fault detection, or power protection. In this embodiment, the voltage monitor is connected to the first controller to monitor the signal processor's power supply status and assist in determining whether it meets the preconditions for loading.

[0032] Specifically, by further installing temperature sensors and voltage monitors on the motherboard and connecting them to the first controller, the first controller can comprehensively determine whether the system ambient temperature and the signal processor's power supply voltage are within a reasonable range before controlling the management controller to access the signal processor. This not only avoids signal processor loading failure or malfunction due to excessive temperature or unstable voltage, but also improves the accuracy of access control and the safety of system operation. This structure expands the original loading status judgment mechanism, upgrading it from single signal status recognition to a multi-dimensional judgment strategy that integrates environmental parameters and electrical status, thereby achieving more refined access control and anomaly avoidance, and improving the overall system's stability, reliability, and fault tolerance.

[0033] In one embodiment, determining the fixed delay based on the signal processor model includes:

[0034] Determine whether the signal processor has a hardware identification bit based on the signal processor model;

[0035] In response to the presence of a hardware identification bit, the state change of the hardware identification bit is detected, and the access status of the management controller and signal processor is determined based on the state change;

[0036] If no hardware identification bit is found, a fixed delay is determined based on the processor model.

[0037] Among them, the hardware identification bit refers to a specific physical pin signal in the pin configuration of a signal processor chip that is used to characterize the chip's identity category. It is usually a predefined level bit (such as high level or low level) that can be detected by external logic circuits to determine the chip type.

[0038] Specifically, during the initial power-up phase of the system, the first controller actively disables the access enable signal, physically blocking the communication connection between the management controller and the signal processor at the hardware level. This prevents access before the signal processor has completed firmware loading, avoiding issues such as link training failure, configuration interruption, or device loss caused by incorrect access timing, thus ensuring the stability and consistency of the system initialization process. The method identifies the signal processor's pin information to determine its category, enabling the first controller to recognize and adapt to various models and manufacturers of signal processor chips. This classification and identification mechanism makes subsequent loading status judgments targeted and flexible, providing a technical foundation for system compatibility and avoiding misjudgments or failures caused by a general method's inability to adapt to all chips. Based on the identified signal processor category, the first controller calls the matching loading status acquisition method to accurately extract its loading status information. Different signal processor chips may characterize their loading status through different registers, pin levels, or communication protocols. This method has the ability to flexibly switch status detection strategies based on the category, improving the accuracy and real-time performance of status judgment. After confirming that the signal processor has completed loading, the first controller resets the access enable signal to be valid, restoring the communication connection between the management controller and the signal processor. This ensures that communication is established when the signal processor is ready and safe to access. This dynamically enabled communication mechanism provides a high degree of controllability and security for access operations, effectively reducing the probability of system-level anomalies.

[0039] By dynamically taking over communication links, automatically identifying devices, accurately sensing loading status, and intelligently controlling access permissions, a complete, closed-loop, and scalable access control mechanism has been built. This not only significantly improves the system's startup stability and device identification success rate, but also enhances its adaptability to complex heterogeneous hardware environments.

[0040] In one embodiment, determining the access status of the management controller and the signal processor based on state changes includes:

[0041] When the hardware identification bit is high, indicating that the signal processor has finished loading, the management controller is triggered to access the signal processor.

[0042] If the hardware identification bit is at a low level, indicating that the signal processor has not finished loading, the status of the hardware identification bit will be checked after a preset interval.

[0043] High level / low level: These are two voltage levels used in digital circuits to represent logic states. A high level typically represents logic "1", and a low level represents logic "0". In this embodiment, the signal processor can be determined to have completed loading by detecting the level state of the hardware identification bit.

[0044] Specifically, when the hardware identification bit is detected to be high, the system can determine that the signal processor has completed loading and promptly trigger the management controller to access it, ensuring that system resources are fully scheduled and utilized when available. Conversely, when the hardware identification bit is low, it indicates that the signal processor has not yet completed loading, and the system will not immediately initiate access. Instead, it will poll the identification bit status again after a preset interval, thus avoiding accidental access in an incomplete state, which could lead to data anomalies or communication failures. This solution, through the linkage mechanism of hardware status awareness and access control, achieves the timing rationality and stability of signal processor access, improving the system's compatibility in asynchronous loading or delayed initialization scenarios.

[0045] In one embodiment, before initiating timing in response to detecting that the signal processor has finished loading, the following steps are included:

[0046] In response to the absence of a hardware identification bit, the status of the signal processor's reset signal is used to determine whether the signal processor has completed the loading operation.

[0047] If the signal processor is detected to be inactive, it indicates that the signal processor has completed the loading operation.

[0048] If the signal processor's reset signal is detected as active, it indicates that the signal processor has not completed the loading operation.

[0049] Specifically, the reset signal is a control signal indicating whether the signal processor is currently in the reset phase. It is typically active during the reset phase and inactive after loading is complete. By determining the activation or deactivation of this reset signal, the system can reliably identify whether the signal processor has completed initialization loading in the absence of other auxiliary hardware flags. When the reset signal is inactive, the system considers loading complete and promptly initiates subsequent processing flows related to loading completion; conversely, when the reset signal is still active, it indicates that loading is not yet complete, and the system can delay entering subsequent phases, thereby avoiding access anomalies or system errors caused by incomplete loading. This solution does not rely on additional hardware resources, possesses good adaptability and versatility, and is particularly suitable for low-cost or lightweight system designs, helping to improve the stability and control accuracy of the system initialization phase.

[0050] In one embodiment, in response to the absence of a hardware identification bit, determining whether the signal processor has completed the loading operation based on the state of the signal processor's reset signal includes:

[0051] In response to the detection that the reset signal of the signal processor is inactive, the load timeout timer is started;

[0052] If the loading timeout reaches the preset timeout period and the reset signal is still in an inactive state, the signal processor loading is determined to be abnormal.

[0053] In response to a signal processor loading error, a soft reset operation is performed on the signal processor, and the loading judgment is re-executed after the soft reset operation is completed.

[0054] If the reload still fails, the first controller switches to the backup signal processor via control logic.

[0055] Among them, soft reset operation refers to the reset operation of the signal processor through software, which is used to replace hardware reset to restart the processor and restore its function; control logic refers to the logic module composed of hardware circuits or firmware programs, which is used to perform control operations such as judgment and switching in the abnormal handling process; backup signal processor is a processing module that is preset in the system to replace the main signal processor and take over when the main processor fails or loads abnormally.

[0056] Specifically, during the signal processor loading process, the system first determines the loading completion status through a reset signal, and then introduces timeout logic to identify abnormal situations such as false exit reset or potential loading deadlock, thereby improving the accuracy and timeliness of loading status determination. When a loading abnormality is confirmed, the system can immediately perform a soft reset operation to attempt to restore processor functionality, preventing the system from entering an irreversible error state due to a single loading failure. In extreme cases where multiple recovery attempts still fail, the first controller can automatically switch to the backup signal processor, enabling rapid reconfiguration of processing resources and business continuity, effectively improving the system's operational reliability and availability in critical scenarios.

[0057] In one embodiment, the environmental parameters include: ambient temperature; acquiring the environmental parameters and determining the compensation delay based on the environmental parameters includes:

[0058] The ambient temperature of the system is monitored in real time during the timing process;

[0059] In response to the detection that the ambient temperature exceeds the temperature threshold, a first delay is determined based on the difference between the ambient temperature and the temperature threshold, and the first delay is used as a compensation delay.

[0060] Among them, environmental parameters refer to external physical quantities that affect the operating status of the system. In this embodiment, they mainly refer to ambient temperature, that is, the real-time temperature value of the physical environment in which the signal processor in the system is located.

[0061] Specifically, by introducing ambient temperature as a dynamic influencing factor, the system senses the current temperature status in real time during timing and determines whether to perform compensation delay adjustment accordingly. This effectively addresses issues such as decreased circuit response speed and timing deviation under high-temperature conditions. When the temperature exceeds a preset threshold, it can dynamically generate compensation time by calculating the temperature difference, achieving more precise timing control and ensuring the reliability and stability of critical operations (such as loading, communication, and detection).

[0062] In one embodiment, the environmental parameters further include: power supply voltage; acquiring the environmental parameters and determining the compensation delay based on the environmental parameters further includes:

[0063] Monitor the system's power supply voltage in real time during the timing process;

[0064] In response to the detection that the supply voltage exceeds the voltage range threshold, a second delay is determined based on the offset of the supply voltage, and the second delay is used as a compensation delay.

[0065] Among them, the power supply voltage refers to the voltage value that provides working power to the system, which is usually output through the power supply module; the compensation delay is a delay control parameter introduced by the changes in environmental parameters (such as temperature and voltage), which is used to correct the system response deviation caused by changes in external conditions.

[0066] Specifically, real-time monitoring of the supply voltage is introduced, and delay compensation is performed based on the degree of voltage deviation, thereby enhancing the system's robustness to power fluctuations. In actual operation, abnormal supply voltage may lead to changes in device response time, internal oscillator frequency deviation, and other problems, which in turn affect the reliability of the system's accurate timing, communication synchronization, or timing-sensitive operations. By dynamically adjusting the second delay based on the voltage deviation, the system can maintain a relatively stable operating sequence under voltage fluctuation conditions, reducing the risk of malfunctions and system inconsistencies.

[0067] In one embodiment, such as Figure 3 As shown, the target delay is determined based on the fixed delay and the compensated delay, including:

[0068] In response to the triggering of a compensation delay during the timing process, at least one of the second delay or the first delay is obtained as the compensation delay;

[0069] The target delay is obtained by summing the fixed delay and the compensated delay.

[0070] Among them, the target delay is the final delay control amount obtained by adding the fixed delay to the currently triggered compensation delay (first or second delay).

[0071] Specifically, by adding the fixed delay to the compensated delay dynamically derived from the actual operating environment to form the final target delay, a more flexible, precise, and environmentally adaptive time control mechanism is achieved. Under normal system conditions, the fixed delay is sufficient to meet operational requirements; however, when abnormal temperature or voltage is detected, the system automatically introduces the corresponding compensated delay, effectively eliminating problems such as hardware timing drift, inconsistent response, or abnormal function triggering caused by changes in the external environment.

[0072] In one embodiment, in response to reaching the target delay time, the management controller is triggered to access the signal processor, which then includes:

[0073] In response to the management controller accessing the signal processor, the first controller monitors the communication status between the management controller and the signal processor, wherein the communication status includes at least one of the following: normal communication and abnormal communication;

[0074] If the number of consecutive data verification failures between the management controller and the signal processor reaches the failure threshold, it indicates that the communication between the management controller and the signal processor is abnormal, and the access enable signal is set to an invalid state, restricting the management controller from accessing the signal processor.

[0075] If the number of consecutive data verification failures between the management controller and the signal processor does not reach the failure threshold, it indicates that the communication between the management controller and the signal processor is normal, and the current access enable signal state is maintained.

[0076] The access enable signal controls whether the management controller can access the signal processor. A valid signal allows communication, while an invalid signal blocks communication. Communication status refers to the data transmission status between the management controller and the signal processor, typically determined by analyzing data verification results during communication to identify any anomalies. The failure threshold is a system-preset limit on the number of failed data verification attempts to determine if communication is abnormal. When the number of consecutive failures reaches or exceeds this threshold, the system considers communication abnormal.

[0077] Specifically, once communication is restored, the first controller begins real-time monitoring of data verification during the communication process between the two parties. If the number of consecutive verification failures reaches a preset failure threshold, the system determines that the communication is abnormal and immediately sets the access enable signal to an invalid state, thereby actively blocking the communication link and preventing data interaction from continuing under abnormal conditions. If the number of consecutive failures does not reach the threshold, it indicates that the communication is still in a stable state, and the access enable signal remains in its current state, ensuring uninterrupted communication. This mechanism can provide timely feedback control when non-transient anomalies occur in communication, possessing a certain degree of self-recovery judgment and fault tolerance capabilities. This helps improve the reliability of data transmission during the operation of the signal processor and reduces the risk of system failures caused by communication anomalies.

[0078] Suppose that after a 43ms delay, a signal processor's access enable signal is enabled, allowing the management controller to establish a communication connection. After communication is restored, the first controller continuously monitors the communication status. The system has a preset failure threshold of 5 times; five consecutive data verification failures are considered a communication anomaly. If, at a certain stage, three consecutive data verification failures occur between the management controller and the signal processor, the system considers communication to be normal since the preset threshold of 5 has not been reached, and the access enable signal remains enabled, allowing communication to continue. However, if two more verification failures subsequently occur, accumulating to five consecutive failures, the system determines a communication anomaly and automatically switches the access enable signal to an invalid state, thus blocking the communication connection between the management controller and the signal processor to avoid data mistransmission and control command errors caused by the abnormal communication status. This state switching is automatically completed by the first controller, possessing real-time and independent operation, requiring no external intervention.

[0079] In one specific embodiment, if the signal processor is identified as lacking a hardware identification bit, the first controller retrieves the corresponding delay parameter (assumed to be 25 milliseconds) from the parameter database based on the signal processor's model and starts the delay timing accordingly. During the delay timing process, the system simultaneously monitors environmental factors in real time: the signal processor's power supply voltage is detected to be 0.91V, while the recommended power supply voltage range is 0.95V to 1.05V (set range), which is below the lower limit, with an offset of 0.04V; the system ambient temperature is 70℃, which exceeds the set temperature threshold of 60℃ (assumed to be more than 10℃). According to the second delay rule (assumed to increase the delay by 2 milliseconds for every 0.01V deviation), the second delay is 0.04V ÷ 0.01V × 2ms = 8ms; according to the first delay rule (set to increase the delay by 1 millisecond for every 1℃ increase), the first delay is 10ms. Finally, the first controller adds the second delay to the first delay and then to the initial delay parameter, resulting in a final delay of 25ms + 8ms + 10ms = 43ms. Only after the delay reaches 43ms does the system set the access enable signal to be valid, allowing the management controller and signal processor to establish a communication connection. This ensures that the chip has sufficient loading time under the current power supply and temperature conditions, improving the stability and reliability of the system operation.

[0080] In one embodiment, according to:

[0081] Determine the target delay, where T target T represents the final delay time. fixed This indicates the standard initialization time, or fixed delay, corresponding to the processor model. This represents the positive difference between the current ambient temperature and the set temperature threshold. k1 represents the offset between the current supply voltage and the target voltage, k3 represents the linear sensitivity coefficient of temperature to loading time, k2 represents the quadratic nonlinear coefficient of temperature compensation, and k3 represents the linear delay coefficient corresponding to the voltage deviation.

[0082] By combining fixed logic with dynamic environmental states, both compatibility and the ability to handle loading time fluctuations caused by complex environments can be ensured. Performance optimization can be achieved for different chips and scenarios by finely adjusting three coefficients (k1, k2, k3).

[0083] Setting parameters:

[0084] parameter meaning numerical values Tfixed Default initialization time for processor model 300 ms Tenv Current temperature 85℃ Tthresh Temperature threshold 60℃ δT Temperature deviation 25℃ Venv Current voltage 4.6 V Vnominal nominal voltage 5.0 V Voltage threshold range [4.8V, 5.2V], the current voltage is below the lower limit. Compensation trigger δV Voltage deviation 0.4 V

[0085] Setting coefficients:

[0086]

[0087] Calculate the first compensation delay:

[0088] ;

[0089] Calculate the second compensation delay:

[0090] ;

[0091] Calculate the target delay:

[0092] T target =300+55+3.2=358.2ms.

[0093] By extending the fixed delay and superimposing linear and nonlinear deviation processing on two types of environmental parameters, the system gains the ability to dynamically adapt to environmental changes. The three coefficients are the key parameters controlling the compensation accuracy and amplitude, and can be flexibly adjusted based on actual chip test results, avoiding wasted time and ensuring access security.

[0094] In one embodiment, in response to the first controller setting the access enable signal to an invalid state, a retry counter is started, and after a preset retry waiting time, the access enable signal is set to an valid state again to retry establishing the communication connection between the management controller and the signal processor; in response to the number of retries reaching the maximum retry threshold, the access enable signal is kept in an invalid state, and a communication abnormality alarm message is generated.

[0095] Specifically, by introducing an automatic retry mechanism after communication anomalies, the system can automatically recover communication under non-permanent faults (such as transient interference or incomplete temporary loading) without manual intervention, improving the stability and self-healing capability of the communication link. Combined with a maximum retry limit and alarm mechanism, it prevents unlimited retries under abnormal conditions, enhancing the system's robustness and resource controllability. This solution enhances the intelligence of signal processor communication control without introducing additional hardware complexity, further improving the reliability and management friendliness of the signal processor access method in complex operating environments.

[0096] In one embodiment, in response to the first controller detecting a communication anomaly and setting the access enable signal to an invalid state, the control signal processor re-enters the loading state, and after reloading is completed, repeats the delay timing and communication status detection process.

[0097] Specifically, by proactively reloading the signal processor in the event of a communication anomaly, and in conjunction with existing delay control and communication status monitoring processes, a complete "closed-loop self-recovery mechanism" for the communication link is constructed. Compared to simple communication blocking or retries, this solution not only considers the possibility of communication failure due to abnormal signal processor loading, but also "pulls" it back to a controllable state through the control device logic, ensuring that the entire link, from the underlying chip to the upper-level control, is always in a "controlled and recoverable" state. This mechanism improves the system's fault tolerance and operational stability, and is particularly suitable for complex application scenarios such as data center servers and network switching equipment where communication reliability requirements are extremely high.

[0098] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above-described signal processor access method embodiments when it is run.

[0099] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0100] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above-described signal processor access method embodiments.

[0101] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both, such as Figure 4 As shown, to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been generally described in terms of functionality in the above description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0102] The signal processor access method provided in this application has been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only intended to help understand the method and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.

Claims

1. A signal processor access method, characterized in that, include: In response to system power-on, the first controller sets the access enable signal to an invalid state to restrict the management controller from accessing the signal processor; Obtain the model number of the signal processor, and determine the fixed delay based on the model number of the signal processor; In response to the detection that the signal processor has finished loading, a timer is started; Obtain the environmental parameters of the signal processor and determine the compensation delay based on the environmental parameters; The target delay is determined based on the fixed delay and the compensated delay; In response to the time delay in reaching the target, the management controller is triggered to access the signal processor; The environmental parameters include: ambient temperature. Acquiring the environmental parameters and determining the compensation delay based on the environmental parameters includes: The ambient temperature of the system is monitored in real time during the timing process; In response to the detection that the ambient temperature exceeds a temperature threshold, a first delay is determined based on the difference between the ambient temperature and the temperature threshold, and the first delay is used as the compensation delay; The environmental parameters also include: power supply voltage; acquiring environmental parameters and determining compensation delay based on the environmental parameters also includes: The system's power supply voltage is monitored in real time during the timing process; In response to detecting that the supply voltage exceeds the voltage range threshold, a second delay is determined based on the offset of the supply voltage, and the second delay is used as the compensation delay; Determining the target delay based on the fixed delay and the compensated delay includes: In response to the compensation delay being triggered during the timing process, at least one of the second delay or the first delay is obtained as the compensation delay; The target delay is obtained by summing the fixed delay and the compensated delay.

2. The signal processor access method according to claim 1, characterized in that, Determining the fixed delay based on the model of the signal processor includes: Determine whether the signal processor has a hardware identification bit based on the model number of the signal processor; In response to the presence of the hardware identification bit, a change in the state of the hardware identification bit is detected, and the access state of the management controller and the signal processor is determined based on the change in state. In response to the absence of a hardware identification bit, a fixed delay is determined based on the model of the signal processor.

3. The signal processor access method according to claim 2, characterized in that, Determining the access status between the management controller and the signal processor based on the state changes includes: When the hardware identification bit is at a high level, indicating that the signal processor has finished loading, the management controller is triggered to access the signal processor. If the hardware identification bit is at a low level, indicating that the signal processor loading is not complete, the state of the hardware identification bit will be detected after a preset interval.

4. The signal processor access method according to claim 2, characterized in that, Before initiating timing in response to the detection that the signal processor has finished loading, the following steps are included: In response to the absence of the hardware identification bit, the state of the reset signal of the signal processor is used to determine whether the signal processor has completed the loading operation; If the signal processor is detected to be in an inactive state, it indicates that the signal processor has completed the loading operation; If the reset signal of the signal processor is detected to be active, it indicates that the signal processor has not completed the loading operation.

5. A signal processor access method according to claim 4, characterized in that, In response to the absence of the hardware identification bit, determining whether the signal processor has completed the loading operation based on the state of the signal processor's reset signal includes: In response to detecting that the reset signal of the signal processor is in an inactive state, a load timeout timer is started; If the loading timeout reaches the preset timeout period and the reset signal is still in an inactive state, then the signal processor is determined to be abnormally loaded. In response to the signal processor loading abnormality, a soft reset operation is performed on the signal processor, and the loading operation is re-executed after the soft reset operation is completed; If the reload still fails, the first controller switches to the backup signal processor via control logic.

6. The signal processor access method according to claim 1, characterized in that, The response to reaching the target delay time triggers the management controller to access the signal processor, followed by: In response to the management controller accessing the signal processor, the first controller monitors the communication status between the management controller and the signal processor, wherein the communication status includes at least one of the following: normal communication and abnormal communication; If the number of consecutive data verification failures between the management controller and the signal processor reaches a failure threshold, it indicates that the communication between the management controller and the signal processor is abnormal, and the access enable signal is set to an invalid state to restrict the management controller from accessing the signal processor. If the number of consecutive data verification failures between the management controller and the signal processor does not reach the failure threshold, it indicates that the communication between the management controller and the signal processor is normal, and the current access enable signal state is maintained.

7. A computer device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

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