A cache coherency domain adjustment method, apparatus, device, medium and product

Abstract

The application discloses a cache consistency domain adjustment method and device, equipment, medium and product, and relates to the technical field of cache, and comprises the following steps: monitoring access requests of a target core to a shared memory in a heterogeneous core architecture to obtain access behaviors; judging whether the target core meets a preset active condition based on the access behaviors; if the target core meets the preset active condition and the target core is not currently located in a preset cache consistency domain, the target core is included in the cache consistency domain; if the target core does not meet the preset active condition and the target core is currently located in the preset cache consistency domain, the target core is removed from the cache consistency domain; wherein each core in the cache consistency domain maintains access consistency to the shared memory based on a cache consistency protocol, and receives consistency transaction requests of the remaining cores in the cache consistency domain. The application can dynamically adjust the cache consistency domain to reduce communication redundancy.

Description

Technical Field

[0001] This invention relates to the field of caching technology, and in particular to a method, apparatus, device, medium, and product for adjusting cache consistency domains. Background Technology

[0002] In existing chiplet architecture multiprocessor systems, multiple chips are combined into a heterogeneous computing platform via high-speed interconnect protocols. Some of these chips have independent cache systems, while others share a unified physical memory address space. To ensure consistency in access to shared data across multiple chips, the system typically introduces a cache coherence protocol and constructs cache coherence domains among the chips to ensure consistent results when chips within a domain access shared data.

[0003] In traditional architectures, most mainstream multiprocessor systems employ statically configured consistency domain schemes. This means that during the system design phase, it's predetermined which cores will participate in the cache consistency protocol as fixed members of the consistency domain. This static partitioning method is simple and effective in homogeneous scenarios with fixed computing patterns. However, with the development of heterogeneous computing, especially AI computing, the computational tasks of systems exhibit highly dynamic and diverse characteristics. Taking AI cores as an example, when performing offline model training or read-only inference tasks, they primarily access local weight parameters, with extremely low or even zero demand for accessing shared data; while when performing interactive neural networks or edge sensing tasks, they may need to frequently read and write data in shared memory.

[0004] Because the task types of AI chips change dynamically during system operation, it is impossible to accurately determine whether they need to participate in consistency maintenance in the long term during the design phase. If a static domain partitioning strategy is adopted, when an AI chip performs a read-only task, it still needs to receive failure requests broadcast by other chips, which will significantly increase the communication overhead and power consumption between chips, causing unnecessary resource burden.

[0005] In summary, how to dynamically adjust the cache consistency domain during system operation to reduce communication redundancy is a problem that needs to be solved. Summary of the Invention

[0006] In view of this, the purpose of this invention is to provide a method, apparatus, device, medium, and product for adjusting the cache consistency domain, which can dynamically adjust the cache consistency domain during system operation to reduce communication redundancy. The specific solution is as follows:

[0007] Firstly, this application discloses a cache consistency domain adjustment method, including:

[0008] Monitor the target chip's access requests to shared memory in a heterogeneous chip architecture to obtain access behavior;

[0009] Determine whether the target core meets the preset activity conditions based on access behavior;

[0010] If the target kernel meets the preset active condition and the target kernel is not currently in the preset cache consistency domain, then the target kernel will be included in the cache consistency domain.

[0011] If the target kernel does not meet the preset active condition, and the target kernel is currently in the preset cache consistency domain, then the target kernel will be moved out of the cache consistency domain.

[0012] Each core in the cache consistency domain maintains consistent access to shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain.

[0013] Optionally, the access behavior includes at least the range of access addresses, the type of access operation, and the access frequency;

[0014] Accordingly, the determination of whether a target chip meets preset activity conditions based on access behavior includes:

[0015] Determine whether the access address range belongs to a pre-defined shared data field in shared memory;

[0016] If the access address range belongs to the shared data domain, the target core is judged to meet the preset active conditions based on the access operation type and access frequency.

[0017] If the access address range does not belong to the shared data domain, the target core is directly determined not to meet the preset active conditions.

[0018] Optionally, the heterogeneous chip architecture includes at least two chips of different functional types, and the shared memory is pre-divided into multiple data domains; wherein, the multiple data domains include at least a shared data domain and a private data domain corresponding to each functional type of chip; the shared data domain allows access by all chips, and the private data domain only allows access by chips of the corresponding functional type.

[0019] Optionally, the heterogeneous chip architecture includes master chips and non-master chips. Master chips include CPU chips, and non-master chips include AI chips, IO chips and GPU chips. The master chips are always located in the cache consistency domain, and the target chips are non-master chips.

[0020] Optionally, the target core is determined to meet preset activity conditions based on the access operation type and access frequency, including:

[0021] If the access operation type is a write operation for a shared data domain, the target core is directly determined to meet the preset active conditions.

[0022] If the access operation type is a read operation for a shared data domain, and the target core is determined to be in a continuously active state based on the access frequency, then the target core is determined to meet the preset active conditions.

[0023] If the access operation type is a read operation for a shared data domain, and the target kernel is determined to be in an inactive state based on the access frequency, then the target kernel is determined not to meet the preset active condition.

[0024] Optionally, determining that the target core is in a continuously active state based on the access frequency includes:

[0025] If, based on the access frequency, it is determined that the target core has accessed the shared data domain more than a first preset threshold number of times within a consecutive first preset number of time periods, then the target core is determined to be in a continuously active state.

[0026] Optionally, determining that a target core is in an inactive state based on access frequency includes:

[0027] If, based on the access frequency, the target core particle has accumulated more than a second preset threshold number of times it has not accessed the shared data domain within a consecutive second preset number of time periods, then the target core particle is determined to be in an inactive state.

[0028] Optionally, the cache consistency domain adjustment method of this application further includes:

[0029] When an update to the cache consistency domain is detected, the information of each directory entry in the preset directory is updated. The directory entry information is used to record the status information of each cache line in shared memory. The directory entry information includes an address tag, a replica bit, and a status field. The address tag is used to identify the target cache line corresponding to the directory entry. The replica bit is used to identify the distribution information of the target cache line in each kernel. The status field is used to identify the consistency status of the target cache line in each kernel. The consistency status includes shared status, modified status, exclusive status, and invalid status.

[0030] Optionally, update the information for each directory entry in the preset directory, including:

[0031] After the target kernel is included in the cache consistency domain, the directory entry information in the preset directory is updated according to the latest access behavior of the target kernel; the latest access behavior includes the latest access address and the latest access operation type.

[0032] After removing the target kernel from the cache consistency domain, all directory entries in the preset directory are traversed to remove information related to the target kernel from the directory entries.

[0033] Optionally, the directory entry information in the preset directory can be updated based on the latest access behavior of the target core, including:

[0034] Determine cache line information based on the latest access address of the target core;

[0035] The target directory entry information corresponding to the cache line information is determined in the preset directory, and the replica bit corresponding to the target core in the target directory entry information is marked with a preset value; the default state of the replica bit is zero.

[0036] The corresponding target consistency status is determined based on the latest access operation type of the target core, and the corresponding state field segment of the target core is updated in the target directory entry information based on the target consistency status.

[0037] Optionally, remove information related to the target chip from the catalog entry information, including:

[0038] In the catalog entry information, the replica bit corresponding to the target core is cleared to zero; the default state of the replica bit is zero.

[0039] In the directory entry information, the status field is updated based on the copy bits after the clearing process.

[0040] Optionally, after clearing the replica bit corresponding to the target core, the process also includes:

[0041] If all copies of any directory entry are zero, then that directory entry will be cleared in the default directory.

[0042] Optionally, the cache consistency domain adjustment method of this application further includes:

[0043] Upon receiving a consistency transaction request from any target particle in the cache consistency domain, determine the current set of particles in the cache consistency domain;

[0044] Send a consistency transaction request to each core in the current core set.

[0045] Optionally, a consistent transaction request can be a failed transaction request.

[0046] Accordingly, the method of this application also includes:

[0047] When any target kernel performs a write operation on the first memory address, it sends an invalidation transaction request to each kernel in the current kernel set, so that each kernel in the current kernel set marks the cache line copy corresponding to the first memory address held locally as invalid.

[0048] Optionally, a consistent transaction request can be a read-shared transaction request;

[0049] Accordingly, the method of this application also includes:

[0050] When any target kernel performs a read operation on the second memory address, a read shared transaction request is sent to each kernel in the current kernel set to determine whether each kernel in the current kernel set holds a copy of the cache line corresponding to the second memory address;

[0051] If held, obtain a copy of the cache line from the kernels in the current kernel set;

[0052] If not held, data is read from the second memory address.

[0053] Optionally, a consistency transaction request can be a write-back transaction request.

[0054] Accordingly, the method of this application also includes:

[0055] When any target kernel performs a modification operation on the data at the local cache address, it writes the modified data back to the shared memory and sends a write-back transaction request to each kernel in the current kernel set so that each kernel in the current kernel set can update the corresponding data.

[0056] Secondly, this application discloses a cache consistency domain adjustment device, comprising:

[0057] The monitoring module is used to monitor the access requests of target chips to shared memory in a heterogeneous chip architecture in order to obtain access behavior;

[0058] The condition judgment module is used to determine whether the target core meets the preset activity conditions based on the access behavior;

[0059] The inclusion module is used to include the target core into the cache consistency domain if the target core meets the preset active conditions and the target core is not currently located in the preset cache consistency domain.

[0060] The removal module is used to remove the target core from the cache consistency domain if the target core does not meet the preset active conditions and the target core is currently located in the preset cache consistency domain.

[0061] Each core in the cache consistency domain maintains consistent access to shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain.

[0062] Thirdly, this application discloses an electronic device, including:

[0063] Memory, used to store computer programs;

[0064] A processor for executing a computer program to implement the steps of the aforementioned disclosed cache coherency domain adjustment method.

[0065] Fourthly, this application discloses a computer-readable storage medium for storing a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the aforementioned disclosed cache coherence domain adjustment method.

[0066] Fifthly, this application discloses a computer program product, including a computer program that, when executed by a processor, implements the steps of the aforementioned disclosed cache coherence domain adjustment method.

[0067] As can be seen, this application obtains access behavior by monitoring the access requests of target particles to shared memory in a heterogeneous particle architecture; it determines whether the target particle meets the preset active conditions based on the access behavior; if the target particle meets the preset active conditions and is not currently located in the preset cache consistency domain, the target particle is included in the cache consistency domain; if the target particle does not meet the preset active conditions and is currently located in the preset cache consistency domain, the target particle is removed from the cache consistency domain; wherein, each particle in the cache consistency domain maintains the access consistency of shared memory based on the cache consistency protocol, and receives consistency transaction requests from other particles in the cache consistency domain.

[0068] Beneficial Effects: This application monitors the target kernel's access behavior to shared memory and determines whether it meets the liveness condition. This allows the target kernel to participate in the cache consistency domain on demand, ensuring that the kernel only participates in the domain protocol when consistency maintenance is required, accurately matching the dynamic needs of heterogeneous scenarios. When the target kernel does not meet the liveness condition, it is removed from the cache consistency domain, preventing it from receiving consistency transaction requests from kernels within the domain. This mechanism significantly reduces invalid communication and lowers the computational consumption of kernels processing redundant transactions, thereby reducing the overall power consumption of the system. In this way, by dynamically adjusting the cache consistency domain, this application ensures efficient collaboration of active kernels while avoiding resource waste from inactive kernels, improving the resource utilization of heterogeneous kernel architecture and optimizing system operating efficiency and energy efficiency. Attached Figure Description

[0069] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0070] Figure 1 This is a flowchart of a cache consistency domain adjustment method disclosed in this application;

[0071] Figure 2 This is a schematic diagram of the data structure of a catalog item information disclosed in this application;

[0072] Figure 3 This application discloses a specific flowchart of a cache consistency domain adjustment method.

[0073] Figure 4 This is a schematic diagram of a dynamic adjustment process for cache consistency domains disclosed in this application;

[0074] Figure 5 This is a system architecture diagram of a heterogeneous chip architecture disclosed in this application;

[0075] Figure 6 A comparison diagram of dynamic consistency domain monitoring transaction pruning disclosed in this application;

[0076] Figure 7 This is a schematic diagram of a cache consistency domain adjustment device disclosed in this application;

[0077] Figure 8 This is a structural diagram of an electronic device disclosed in this application. Detailed Implementation

[0078] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of the present invention.

[0079] In traditional architectures, most mainstream multiprocessor systems employ statically configured consistency domain schemes. This means that during the system design phase, it is pre-determined which cores will participate in the cache consistency protocol as fixed members of the consistency domain. This static partitioning method is simple and effective in homogeneous scenarios with fixed computing patterns. However, with the development of heterogeneous computing, especially AI computing, the computational tasks of systems exhibit highly dynamic and diverse characteristics. Therefore, this application discloses a cache consistency domain adjustment method, apparatus, device, medium, and product that can dynamically adjust the cache consistency domain during system operation to reduce communication redundancy.

[0080] See Figure 1 As shown in the figure, this application discloses a cache consistency domain adjustment method, which includes:

[0081] Step S11: Monitor the target chip's access requests to shared memory in the heterogeneous chip architecture to obtain access behavior.

[0082] In this embodiment, an access monitoring module can be pre-deployed on the heterogeneous chip architecture according to system deployment requirements to monitor the target chip's access requests to shared memory and thus obtain access behavior. The access monitoring module can be located inside the chip, near the package interface, or in the SoC (System on a Chip) interconnect module. It is used to detect the shared memory access behavior of the target chip. Specifically, the access monitoring module adopts a modular design and can be regarded as an independent module, connecting to the chip through a standard interface.

[0083] Step S12: Determine whether the target chip meets the preset active conditions based on the access behavior.

[0084] In this embodiment, the access monitoring module reports the monitored access behaviors to the consistency domain control module, which then determines whether the target kernel meets the preset activity conditions based on the access behaviors. The consistency domain control module can periodically or based on event triggering to acquire access behaviors from the access monitoring module.

[0085] Step S13: If the target kernel meets the preset active condition and the target kernel is not currently located in the preset cache consistency domain, then the target kernel is included in the cache consistency domain.

[0086] In this embodiment, if the target kernel meets the preset active condition and is not currently located in the preset cache consistency domain, then the target kernel is included in the cache consistency domain, enabling it to participate in the cache consistency protocol. It should be noted that each kernel in the cache consistency domain maintains consistent access to shared memory based on the cache consistency protocol, and receives consistency transaction requests from other kernels in the cache consistency domain.

[0087] Step S14: If the target kernel does not meet the preset active condition and the target kernel is currently located in the preset cache consistency domain, then the target kernel is moved out of the cache consistency domain.

[0088] In this embodiment, if the target kernel does not meet the preset active condition and the target kernel is currently located in the preset cache consistency domain, the target kernel will be moved out of the cache consistency domain so that it will no longer participate in the cache consistency protocol, thereby reducing unnecessary communication overhead.

[0089] In other words, this application monitors the target kernel's access behavior to shared memory and determines whether it meets the liveness condition. This enables the target kernel to participate in the cache consistency domain on demand, ensuring that the kernel only participates in the domain protocol when consistency maintenance is required, thus accurately matching the dynamic needs in heterogeneous scenarios. When the target kernel does not meet the liveness condition, it is removed from the cache consistency domain, preventing it from receiving consistency transaction requests from kernels within the domain. This mechanism significantly reduces invalid communication and lowers the computational cost of kernels processing redundant transactions, thereby reducing the overall power consumption of the system.

[0090] Furthermore, the above method also includes: when an update to the cache consistency domain is detected, updating the information of each directory entry in the preset directory; wherein, the directory entry information is used to record the status information of each cache line in shared memory, and the directory entry information includes an address tag, a replica bit, and a status field segment; the address tag is used to identify the target cache line corresponding to the directory entry, the replica bit is used to identify the distribution information of the target cache line in each kernel, and the status field segment is used to identify the consistency status of the target cache line in each kernel; the consistency status includes shared status, modified status, exclusive status, and invalid status.

[0091] It should be noted that this application also includes a directory management module for tracking and maintaining the information structure of the cache consistency state in the system, i.e., a preset directory. When a consistency domain member changes, the consistency domain control module notifies the directory management module to update the directory, ensuring that the consistency protocol state is consistent with the actual cache state, and limiting the target scope for subsequent cache consistency transaction broadcasts.

[0092] The preset directory contains multiple directory entries, each recording the status information of each cache line in shared memory. Specifically, it includes address tags, replica bits, and status fields, with the following data structure: Figure 2 As shown, it is important to note that Figure 2 This section provides a detailed structural description using a heterogeneous chip architecture, including CPU chips, AI chips, IO chips, and GPU chips. The chip types can be dynamically modified when they change, are added, or removed. The address label identifies the target cache line corresponding to the directory entry, i.e., the specific memory address in shared memory. The replica bit identifies the distribution information of the target cache line in each chip, i.e., which chips the cache copy of that memory address is currently distributed in, including the CPU replica bit, GPU replica bit, AI replica bit, and IO replica bit. If a chip contains the corresponding cache copy, the corresponding replica bit is set to 1; otherwise, it is the default value of 0. Furthermore, the state field identifies the consistency state (i.e., cache state) of the target cache line in each chip. The consistency state specifically includes Shared, Modified, Exclusive, and Invalid states.

[0093] Therefore, by using a pre-defined directory, it is possible to know whether a cache line is currently cached in any kernel, its consistency status, and the kernel identifiers to which the replicas are distributed. When a kernel is dynamically added to or removed from the cache consistency domain based on access behavior, the directory management module can dynamically update the status entries of the relevant cache lines to ensure the correctness of the global consistency relationship.

[0094] Specifically, the information of each directory entry in the preset directory is updated, including: after the target kernel is included in the cache consistency domain, the information of the directory entries in the preset directory is updated according to the latest access behavior of the target kernel; wherein, the latest access behavior includes the latest access address and the latest access operation type; after the target kernel is removed from the cache consistency domain, all directory entry information in the preset directory is traversed to remove information related to the target kernel from the directory entry information.

[0095] In one specific implementation, when a target kernel is included in the cache consistency domain due to accessing shared data and meeting preset active conditions, the directory entry information in the preset directory is updated based on its latest access behavior, which specifically includes the latest access address and the latest access operation type. For example, when it subsequently accesses a shared address or modifies the corresponding data, the target kernel cache generates a new copy and records it in the preset directory. It is understood that the preset directory records the actual physical location of the data copy, not domain membership. Therefore, the directory update is triggered by data movement, not by changes in membership. Thus, including a target kernel in the cache consistency domain itself typically does not immediately trigger a large-scale update to the directory content; the directory update is performed synchronously when the target kernel subsequently performs specific cache access behavior.

[0096] In another specific implementation, once the target kernel is removed from the cache consistency domain, it is no longer governed by the consistency protocol. All information recorded in its preset directory must be cleared to prevent the system from sending messages to a kernel that no longer responds to consistency requests. Therefore, this embodiment needs to traverse all directory entries in the preset directory to remove information related to the target kernel, thereby ensuring that only currently valid replicas maintained by the consistency protocol are retained in the preset directory. This prevents transaction processing anomalies and data inconsistencies caused by expired member replicas.

[0097] Specifically, updating the directory entry information in the preset directory based on the latest access behavior of the target core includes: determining cache line information based on the latest access address of the target core; determining the target directory entry information corresponding to the cache line information in the preset directory, and marking the replica bit in the target directory entry information corresponding to the target core with a preset value; wherein the default state of the replica bit is zero; determining the corresponding target consistency state based on the latest access operation type of the target core, and updating the state field segment corresponding to the target core in the target directory entry information based on the target consistency state.

[0098] In other words, when a target kernel begins accessing shared memory, the cache line information is first determined based on the latest access address of the target kernel. Then, the target directory entry information corresponding to the cache line information is determined in the preset directory, thereby updating the replica bit corresponding to the target kernel in the target directory entry information from the default value of 0 to the preset value of 1. Furthermore, the consistency status of the cache line is updated according to the latest access operation type of the target kernel. For example, if the target kernel performs a write operation, the status is marked as modified; if it performs a read-only operation, it is marked as shared. This ensures that the cache line replica distribution and consistency status recorded in the directory can accurately reflect the cache status of kernels in the current domain, guaranteeing global consistency.

[0099] The process of clearing information related to the target kernel from the directory entry information includes: clearing the replica bit corresponding to the target kernel in the directory entry information; the default state of the replica bit is zero; and updating the state field based on the cleared replica bit in the directory entry information. It is understood that after removing the target kernel from the cache consistency domain, all records related to the target kernel will be cleared from the preset directory. This application iterates through all target entry information and clears the replica bit corresponding to the target kernel. For example, removing a GPU kernel sets the GPU replica bit of all cache lines to 0, indicating that the kernel no longer caches the corresponding data. Secondly, the state field in the directory entry information is updated based on the cleared replica bit. Specifically, it checks whether the cache line still has valid replicas of kernels in other domains. If other replicas exist, the consistency state is updated according to the access status of the remaining replicas. If only CPU replicas remain, they are marked as exclusive.

[0100] Furthermore, after clearing the replica bits corresponding to the target kernel, the process also includes: if all replica bits of any directory entry are zero, then that directory entry is cleared from the preset directory. That is, if the target kernel is the sole replica holder of a cache line, clearing the replica bits corresponding to the target kernel will reveal that all replica bits of that cache line are zero. In this case, the directory entry information for the entire cache line can be directly cleared to avoid subsequent transaction processing anomalies due to expired replica records, ensuring that only cached information of valid kernels within the current consistency domain is retained in the preset directory.

[0101] Furthermore, the above method also includes: upon receiving a consistency transaction request from any target granule in the cache consistency domain, determining the current set of granules in the cache consistency domain; and sending consistency transaction requests to each granule in the current set. First, it should be noted that in cache consistency protocols, a consistency transaction refers to a series of standardized messages or operations initiated, transmitted, and processed to maintain the consistency of data replicas across multiple caches. These transactions are the core of inter-granule communication, ensuring that any modification made to data by any granule is known and responded to by other granules holding that data replica. Consistency transactions include, but are not limited to, invalidation transactions, read-shared transactions, and write-back transactions. An invalidation transaction means that before initiating a write operation, a granule must send an invalidation request to other granules holding that data replica, invalidating the old replica and avoiding data inconsistency. A read-shared transaction means that before reading a shared data replica, a granule must confirm whether other granules have a valid replica of the data; if so, it reads it directly instead of directly reading from the slow shared memory. A write-back transaction means writing locally modified data back to shared memory.

[0102] In traditional solutions, a global broadcast is required for a consistency transaction, meaning all kernels must accept and process the listener request. However, most kernels may not have a copy of the data and would need to interrupt their current tasks to process the broadcast message, consuming computational resources and power, and increasing communication redundancy. Therefore, this application, upon receiving a consistency transaction request from any target kernel in the cache consistency domain, needs to determine the current set of kernels in the cache consistency domain and then send the consistency transaction request only to each kernel in that current set. If there are no other relevant members in the cache consistency domain, the broadcast process can be omitted, avoiding invalid listening and redundant transmission.

[0103] In the first specific implementation, the consistency transaction request is a failure transaction request; correspondingly, the above method further includes: when any target kernel performs a write operation on the first memory address, sending a failure transaction request to each kernel in the current kernel set, so that each kernel in the current kernel set marks its locally held cache line copy corresponding to the first memory address as invalid. That is, when any target kernel performs a write operation on the first memory address, it is necessary to send a failure transaction request to invalidate other kernels holding the cache line copy. This application sends the request only to kernels within the cache consistency domain, and not to kernels outside the domain, so that the kernel receiving the failure transaction request marks its locally held cache line copy corresponding to the first memory address as invalid, thereby avoiding data corruption caused by multiple people modifying the cache line simultaneously.

[0104] In the second specific implementation, the consistency transaction request is a read shared transaction request. Accordingly, the method further includes: when any target kernel performs a read operation on the second memory address, a read shared transaction request is sent to each kernel in the current kernel set to determine whether each kernel in the current kernel set holds a copy of the cache line corresponding to the second memory address; if it does, the cache line copy is obtained from the kernel in the current kernel set; if it does not, the data is read from the second memory address. That is, when a kernel needs to read shared data from the second memory address of shared memory, it needs to confirm whether other kernels have a valid copy of the data. If so, it reads directly, reducing main memory access latency. For example, when a CPU kernel reads shared data, it needs to confirm whether other kernels cache the data. By querying the current kernel set and finding only the AI ​​kernel, a read shared transaction request is sent only to the AI ​​kernel currently within the domain, without sending it to other kernels outside the domain. If the AI ​​kernel holds a copy of the cache line corresponding to the second memory address, the data can be read from the AI ​​kernel; otherwise, the corresponding data is read from the second memory address of shared memory.

[0105] In the third specific implementation, the consistency transaction request is a write-back transaction request; correspondingly, the above method further includes: when any target particle performs a modification operation on the data at its local cache address, it writes the modified data back to the shared memory and sends a write-back transaction request to each particle in the current particle set, so that each particle in the current particle set can update the corresponding data. That is, after a particle modifies the shared data in its local cache, it needs to write the modified data back to the shared memory and synchronize it with other particles.

[0106] In other words, the consistency domain control module is the core of consistency management, responsible for real-time control and transaction routing management of cache consistency relationships between kernels. It can dynamically adjust consistency domain members based on feedback from the access monitoring module, and optimize the routing path of consistency transactions accordingly. For cache consistency transactions generated in the system, it can dynamically determine whether the target kernel set needs to send a listening request based on the current state of the domain members, avoiding unnecessary global broadcasts. This effectively reduces transaction response redundancy between kernels and improves the energy efficiency and bandwidth utilization of system consistency maintenance.

[0107] As can be seen, this application monitors the target particle's access behavior to shared memory and determines whether it meets the activity condition, enabling the target particle to participate in the cache consistency domain on demand. This ensures that the particle only participates in the domain protocol when consistency maintenance is required, accurately matching the dynamic needs of heterogeneous scenarios. When the target particle does not meet the activity condition, it is removed from the cache consistency domain, preventing it from receiving consistency transaction requests from other particles within the domain. This mechanism significantly reduces invalid communication and lowers the computational consumption of particles processing redundant transactions, thereby reducing the overall power consumption of the system. In this way, by dynamically adjusting the cache consistency domain, this application ensures efficient collaboration among active particles while avoiding resource waste from inactive particles, improving the resource utilization of heterogeneous particle architectures and optimizing system operating efficiency and energy efficiency.

[0108] See Figure 3 and Figure 4 As shown, this application discloses a specific method for adjusting cache consistency domains. Compared to the previous embodiment, this embodiment further explains and optimizes the technical solution. Specifically, it includes:

[0109] Step S21: Monitor the target chip's access requests to shared memory in the heterogeneous chip architecture to obtain access behavior; the access behavior includes at least the access address range, access operation type, and access frequency.

[0110] In this embodiment, the access monitoring module primarily monitors the target chip's access requests to shared memory during system operation to obtain access behavior. This access behavior mainly includes the access address range, access operation type, and access frequency.

[0111] Step S22: Determine whether the access address range belongs to the pre-divided shared data field in the shared memory.

[0112] In this embodiment, when determining whether a target chip meets the preset active conditions based on access behavior, it is first necessary to determine whether the corresponding access address range belongs to the pre-divided shared data domain in the shared memory.

[0113] It should be noted that the heterogeneous core architecture includes at least two cores with different functional types, and the shared memory is pre-divided into multiple data domains; among them, the multiple data domains include at least a shared data domain and a private data domain corresponding to each functional type of core; the shared data domain allows access by all cores, while the private data domain only allows access by cores of the corresponding functional type.

[0114] In other words, the heterogeneous chip architecture contains multiple functionally heterogeneous chip units, including but not limited to CPU chips, GPU chips, AI chips, and I / O chips. Furthermore, shared memory is used to enable data interaction or shared access between multiple chips. To achieve efficient data access management, shared memory can be divided into multiple data domains, each including at least a shared data domain and a private data domain corresponding to each functional type of chip. The private data domains include CPU-specific domains, GPU-specific domains, AI-specific domains, and I / O-specific domains; the shared data domains can be accessed by all chips, while the private data domains are only accessible to chips of the corresponding functional type. For example, the CPU-specific domain stores the processor core's private runtime data, accessible only to the CPU core; access by other cores is restricted, and this area does not participate in cache consistency maintenance. The GPU-specific domain stores intermediate variables required by the GPU core for tasks such as graphics rendering and parallel computing; it is accessible only to the GPU core and does not participate in cache consistency maintenance. The AI-specific domain stores model weights and network structure parameters loaded by the AI ​​core; access is read-only, and it is not modified by other cores during inference tasks, thus not participating in cache consistency maintenance. Shared data domains are used for intermediate results exchanged between multiple cores and shared cache data; access behavior needs to be maintained by the consistency domain control module, which dynamically maintains cache consistency. Therefore, by analyzing the access address range, it is possible to identify whether the address accessed by the core belongs to the system-defined shared data domain, thus excluding access to the dedicated private data domain.

[0115] In addition, the shared memory can be divided into different domains according to needs. For example, there are control and synchronization domains, which are used to store task scheduling flags, control information, status synchronization signals, etc. between cores, support read and write access by multiple cores, and need to support cache consistency protocols.

[0116] Furthermore, the heterogeneous chip architecture includes master control chips and non-master control chips. Master control chips include CPU chips, and non-master control chips include AI chips, IO chips, and GPU chips. The master control chips are always located in the cache consistency domain, while the target chips are non-master control chips. It is understood that the CPU chip is the system's master control unit, responsible for system scheduling and main memory access; therefore, in this embodiment, it is always in the cache consistency domain. The GPU chip is used to execute highly parallel computing tasks, and its access frequency to shared data fluctuates depending on the task type; therefore, it supports dynamically joining the cache consistency domain according to the scheme of this application. The AI ​​chip is used to run inference, neural networks, and other tasks, exhibiting highly dynamic access behavior, and also supports dynamically joining the cache consistency domain. IO chips, such as network interfaces and DMA controllers, may access shared areas in some tasks, and also need to support dynamically joining the cache consistency domain. Therefore, the target chips monitored in this application belong to non-master control chips, namely AI chips, IO chips, and GPU chips. Therefore, this application requires the deployment of access monitoring modules in the AI, IO, and GPU cores to monitor their access behavior to shared memory in real time. The CPU core, as the system's main control core, does not have an access monitoring module deployed. Since the CPU typically has the highest access rights and scheduling control, it always defaults to being in the consistency domain, and its behavior is not subject to access behavior monitoring and control. The specific system architecture is as follows: Figure 5 As shown, the system architecture includes an access monitor module, a consistency domain control module, a directory management module, and shared memory, which can dynamically determine whether a core should participate in the cache consistency protocol based on its actual access behavior, thereby reducing redundant communication overhead and improving system energy efficiency and consistency management efficiency.

[0117] Step S23: If the access address range belongs to the shared data domain, determine whether the target kernel meets the preset active conditions based on the access operation type and access frequency; if the access address range does not belong to the shared data domain, directly determine that the target kernel does not meet the preset active conditions.

[0118] In one specific implementation, if the access address range of the target core belongs to the shared data domain, then the target core is further judged based on the access operation type and access frequency to determine whether it meets the preset active conditions.

[0119] In another specific implementation, if the access address range of the target kernel does not belong to the shared data domain, it is directly determined that the target kernel does not meet the preset active condition, which means that the request will not involve other kernels and can be completed directly through the kernel's local cache or main memory, without the system needing to trigger the cache consistency protocol maintenance process.

[0120] The method of determining whether a target kernel meets the preset active conditions based on the access operation type and access frequency includes: if the access operation type is a write operation to the shared data domain, the target kernel is directly determined to meet the preset active conditions; if the access operation type is a read operation to the shared data domain, and the target kernel is determined to be in a continuously active state based on the access frequency, the target kernel is determined to meet the preset active conditions; if the access operation type is a read operation to the shared data domain, and the target kernel is determined to be in an inactive state based on the access frequency, the target kernel is determined not to meet the preset active conditions.

[0121] In other words, if the access operation is a write operation targeting a shared data domain, the write operation will affect the cached copies of other granules in the system, requiring consistency protocol maintenance. It's understandable that when the target granule performs a write operation on the shared data domain, it changes the data content. The core function of the cache consistency domain is to ensure consistency in access to shared data by granules within the domain. If the granule performing the write operation is not within the cache consistency domain, the system cannot notify other granules within the domain to clear old copies through the consistency protocol. This will cause other granules to retrieve the old value when subsequently reading the data, leading to calculation errors. Therefore, if the target granule performs a write operation, it indicates that other granules may have cached copies and need to be reintegrated into the cache consistency domain.

[0122] If the access operation type is a write operation targeting a shared data domain, since it only reads shared data and does not change the data content, theoretically there is no need to trigger strong consistency operations such as invalidation requests. However, it is necessary to determine whether the access is frequent to decide whether to add it to the domain. That is, if it is a read-only access, the consistency domain control module needs to determine whether it constitutes continuous activity based on the access rate. If the target particle is not currently in the consistency domain and its behavior is in a continuous active state, then the target particle is determined to meet the preset active condition and is included in the cache consistency domain. If the target particle is in the cache consistency domain and the target particle is determined to be in an inactive state based on the access frequency, then the target particle is determined not to meet the preset active condition and is removed from the cache consistency domain.

[0123] In a specific implementation, determining that a target kernel is in a continuously active state based on access frequency includes: if, based on access frequency, the target kernel's cumulative number of accesses to the shared data domain within a first preset number of time periods exceeds a first preset threshold, then the target kernel is determined to be in a continuously active state. That is, if the target kernel's cumulative number of accesses to the shared data domain exceeds the first preset threshold within N consecutive time periods, then the target kernel is considered to be in a continuously active state. For example, if the shared domain is accessed more than 5 times within 10 consecutive periods, it is determined to be active.

[0124] In a specific implementation, determining that a target core is in an inactive state based on access frequency includes: if, based on access frequency, the target core has accumulated more than a second preset threshold number of times it has not accessed the shared data domain within a second preset number of consecutive time periods, then the target core is determined to be in an inactive state. That is, if the target core has accumulated more than the second preset threshold number of times it has not accessed the shared data domain within M time periods, then the target core is determined to be in an inactive state. For example, if the number of times the shared domain has not been accessed is 15 within 20 consecutive periods, then it is determined to be inactive. Alternatively, if the target core has accessed the shared data domain 0 times within 15 consecutive periods, then it is determined to be inactive.

[0125] Step S24: If the target kernel meets the preset active condition and the target kernel is not currently located in the preset cache consistency domain, then the target kernel is included in the cache consistency domain.

[0126] Step S25: If the target core does not meet the preset active condition and the target core is currently located in the preset cache consistency domain, then the target core is moved out of the cache consistency domain.

[0127] Each core in the cache consistency domain maintains consistent access to shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain.

[0128] For more detailed processing of steps S24 and S25, please refer to the relevant content disclosed in the foregoing embodiments, which will not be repeated here.

[0129] As can be seen, this application deploys access monitoring modules in GPU, AI, IO and other components to perceive their access behavior status in shared memory in real time. This is used to detect whether each component accesses the shared data domain, performs write operations, and whether the access frequency reaches a set threshold. The status behavior is periodically reported to the consistency domain control module, thereby achieving a dynamic management mechanism for on-demand participation in cache consistency maintenance. This can effectively reduce communication overhead, improve system energy efficiency, and reduce traditional consistency redundancy operations.

[0130] The following three examples illustrate the solution proposed in this application in detail:

[0131] Example 1: The dynamic consistency domain mechanism prunes the listening transactions during the read request process when the directory is not hit, avoiding the communication redundancy caused by global broadcast in traditional solutions.

[0132] During system operation, when a CPU core initiates a read request to shared memory, since the address is not currently recorded in the directory module, according to the traditional cache consistency maintenance scheme, the listen request should be broadcast to all cores in the system to confirm whether the copy exists in other cores.

[0133] Figure 6 The improved process of this solution is demonstrated. Through dynamic consistency domains, the system avoids global broadcasting and instead first queries the current member status of the cache consistency domain. It determines that only the AI ​​core is in the cache consistency domain, while the GPU and IO cores are not. Therefore, a listening request is sent only to the AI ​​core. This mechanism avoids invalid broadcast requests and reduces the response overhead of other cores, significantly improving cache consistency maintenance efficiency, especially in high-concurrency, multi-request scenarios.

[0134] Example 2: The process of adding AI chips to a consistency domain due to frequent access to shared memory.

[0135] Assume that the AI ​​chip is not initially a member of the cache consistency domain. During task execution, the access monitoring module detects that it frequently accesses shared data over multiple consecutive periods and performs multiple write operations. This behavior satisfies the preset active condition of the cache consistency domain. The consistency domain control module determines that the AI ​​chip should be added to the cache consistency domain and notifies the directory to perform subsequent member updates.

[0136] The AI ​​chip performs a write operation on the shared memory address 0x8800_1234. According to the cache coherence protocol, the system needs to ensure that the AI ​​chip has exclusive access to this address throughout the system. Therefore, the control module sends invalidation requests to other chips, invalidating the cache lines corresponding to other chips (such as the CPU) that hold copies of this address. Once all other copies have invalidated, the AI ​​chip creates a copy of this address in its local cache and marks it as "modified." The directory module synchronously updates the copy bit and status field, marking the AI ​​chip as the sole copy holder.

[0137] Example 3: The process of dynamically removing a GPU chip from the cache consistency domain and clearing its copy record in the directory after the access does not meet the preset active conditions.

[0138] During system operation, the GPU chip participated in image processing tasks and frequently read shared data domain addresses. The access monitoring module included it in the cache consistency domain. However, subsequently, the GPU chip's related tasks ended, and access activity decreased. The access monitoring module monitored for several consecutive cycles without detecting any GPU access to the shared memory domain. The consistency domain control module determined that the GPU chip no longer met the active condition and removed it from the cache consistency domain. Simultaneously, the directory module cleared the GPU-related replicas, that is, cleared the cache status field and replica bit flag corresponding to the GPU in the address directory entry. If the chip was the sole replica holder for that address, the entire directory was cleared.

[0139] See Figure 7As shown in the figure, this application discloses a cache consistency domain adjustment device, which includes:

[0140] The monitoring module 11 is used to monitor the access requests of the target chip to the shared memory in the heterogeneous chip architecture in order to obtain the access behavior;

[0141] Condition judgment module 12 is used to determine whether the target core meets the preset active conditions based on the access behavior;

[0142] The inclusion module 13 is used to include the target core into the cache consistency domain if the target core meets the preset active conditions and the target core is not currently located in the preset cache consistency domain.

[0143] The removal module 14 is used to remove the target core from the cache consistency domain if the target core does not meet the preset active conditions and the target core is currently located in the preset cache consistency domain.

[0144] Each core in the cache consistency domain maintains consistent access to shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain.

[0145] As can be seen, this application monitors the target particle's access behavior to shared memory and determines whether it meets the activity condition, enabling the target particle to participate in the cache consistency domain on demand. This ensures that the particle only participates in the domain protocol when consistency maintenance is required, accurately matching the dynamic needs of heterogeneous scenarios. When the target particle does not meet the activity condition, it is removed from the cache consistency domain, preventing it from receiving consistency transaction requests from other particles within the domain. This mechanism significantly reduces invalid communication and lowers the computational consumption of particles processing redundant transactions, thereby reducing the overall power consumption of the system. In this way, by dynamically adjusting the cache consistency domain, this application ensures efficient collaboration among active particles while avoiding resource waste from inactive particles, improving the resource utilization of heterogeneous particle architectures and optimizing system operating efficiency and energy efficiency.

[0146] Since the embodiments of the device part correspond to the embodiments described above, please refer to the embodiments described in the method part for the embodiments of the device part, and will not be repeated here.

[0147] Figure 8 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Specifically, it may include: at least one processor 21, at least one memory 22, a power supply 23, a communication interface 24, an input / output interface 25, and a communication bus 26. The memory 22 stores a computer program, which is loaded and executed by the processor 21 to implement the relevant steps in the cache consistency domain adjustment method performed by the electronic device as disclosed in any of the foregoing embodiments.

[0148] In this embodiment, the power supply 23 is used to provide operating voltage for each hardware device on the electronic device 20; the communication interface 24 can create a data transmission channel between the electronic device 20 and external devices, and the communication protocol it follows can be any communication protocol applicable to the technical solution of this application, and is not specifically limited here; the input / output interface 25 is used to acquire external input data or output data to the outside world, and its specific interface type can be selected according to specific application needs, and is not specifically limited here.

[0149] The processor 21 may include one or more processing cores, such as a quad-core processor or an octa-core processor. The processor 21 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 21 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, the processor 21 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, the processor 21 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0150] In addition, the memory 22, as a carrier for resource storage, can be a read-only memory, random access memory, disk or optical disk, etc. The resources stored on it include operating system 221, computer program 222 and data 223, etc., and the storage method can be temporary storage or permanent storage.

[0151] The operating system 221 manages and controls the various hardware devices and computer programs 222 on the electronic device 20 to enable the processor 21 to perform calculations and processing on the massive amounts of data 223 in the memory 22. The operating system 221 can be Windows, Unix, Linux, etc. The computer program 222, in addition to including a computer program capable of performing the cache coherence domain adjustment method executed by the electronic device 20 as disclosed in any of the foregoing embodiments, may further include computer programs capable of performing other specific tasks. The data 223 may include data received by the electronic device from external devices, as well as data collected by its own input / output interface 25.

[0152] Furthermore, embodiments of this application also disclose a computer-readable storage medium storing a computer program. When the computer program is loaded and executed by a processor, it implements the cache consistency domain adjustment method steps disclosed in any of the foregoing embodiments.

[0153] This invention also discloses a computer program product, including a computer program / instruction that, when executed by a processor, implements the steps of the cache coherence domain adjustment method disclosed in any of the foregoing embodiments.

[0154] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.

[0155] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0156] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, compact disc read-only memory (CD-ROM), or any other form of storage medium known in the art.

[0157] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0158] The foregoing has provided a detailed description of a cache consistency domain adjustment method, apparatus, device, medium, and product provided by the present invention. Specific examples have been used to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only intended to help understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A method for adjusting cache consistency domains, characterized in that, include: Monitor the target chip's access requests to shared memory in a heterogeneous chip architecture to obtain access behavior; Based on the access behavior, determine whether the target core meets the preset activity conditions; If the target kernel meets the preset active condition and the target kernel is not currently located in the preset cache consistency domain, then the target kernel will be included in the cache consistency domain. If the target kernel does not meet the preset active condition, and the target kernel is currently located in the preset cache consistency domain, then the target kernel will be moved out of the cache consistency domain. Each core in the cache consistency domain maintains the consistency of access to the shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain. The access behavior includes at least the access address range, access operation type, and access frequency; Accordingly, determining whether the target chip meets the preset activity condition based on the access behavior includes: Determine whether the access address range belongs to a pre-defined shared data domain in the shared memory; If the access address range belongs to the shared data domain, then it is determined whether the target core meets the preset active conditions based on the access operation type and the access frequency; If the access address range does not belong to the shared data domain, then the target core is directly determined not to meet the preset active conditions.

2. The cache consistency domain adjustment method according to claim 1, characterized in that, The heterogeneous chip architecture includes at least two chips of different functional types, and the shared memory is pre-divided into multiple data domains; wherein, the multiple data domains include at least the shared data domain and a private data domain corresponding to each functional type of chip; the shared data domain allows access by all chips, and the private data domain only allows access by chips of the corresponding functional type.

3. The cache consistency domain adjustment method according to claim 2, characterized in that, The heterogeneous chip architecture includes master control chips and non-master control chips. The master control chips include CPU chips, and the non-master control chips include AI chips, IO chips, and GPU chips. The master control chips are always located in the cache consistency domain, and the target chips are the non-master control chips.

4. The cache consistency domain adjustment method according to claim 1, characterized in that, The step of determining whether the target chip meets the preset activity conditions based on the access operation type and the access frequency includes: If the access operation type is a write operation for the shared data domain, then the target core is directly determined to meet the preset active condition; If the access operation type is a read operation for the shared data domain, and the target core is determined to be in a continuously active state based on the access frequency, then the target core is determined to meet the preset active condition. If the access operation type is a read operation for the shared data domain, and the target kernel is determined to be in an inactive state based on the access frequency, then the target kernel is determined not to meet the preset active condition.

5. The cache consistency domain adjustment method according to claim 4, characterized in that, The step of determining that the target chip is in a continuously active state based on the access frequency includes: If, based on the access frequency, it is determined that the target core has accessed the shared data domain more than a first preset threshold number of times within a consecutive first preset number of time periods, then the target core is determined to be in a continuously active state.

6. The cache consistency domain adjustment method according to claim 5, characterized in that, The step of determining that the target core is in an inactive state based on the access frequency includes: If, based on the access frequency, it is determined that the target core has not accessed the shared data domain more than a second preset threshold number of times within a consecutive second preset number of time periods, then the target core is determined to be in an inactive state.

7. The cache consistency domain adjustment method according to any one of claims 1 to 6, characterized in that, Also includes: When an update to the cache consistency domain is detected, the information of each directory entry in the preset directory is updated. The directory entry information records the status information of each cache line in the shared memory. The directory entry information includes an address tag, a replica bit, and a status field. The address tag identifies the target cache line corresponding to the directory entry. The replica bit identifies the distribution information of the target cache line in each kernel. The status field identifies the consistency status of the target cache line in each kernel. The consistency status includes shared status, modified status, exclusive status, and invalid status.

8. The cache consistency domain adjustment method according to claim 7, characterized in that, The step of updating the information of each directory item in the preset directory includes: After the target kernel is included in the cache consistency domain, the directory entry information in the preset directory is updated according to the latest access behavior of the target kernel; wherein, the latest access behavior includes the latest access address and the latest access operation type; After removing the target core from the cache consistency domain, all directory entries in the preset directory are traversed to remove information related to the target core from the directory entries.

9. The cache consistency domain adjustment method according to claim 8, characterized in that, The step of updating the directory item information in the preset directory based on the latest access behavior of the target chip includes: Determine cache line information based on the latest access address of the target core; In a preset directory, the target directory entry information corresponding to the cache line information is determined, and the replica bit in the target directory entry information corresponding to the target core is marked with a preset value; wherein, the default state of the replica bit is zero. The corresponding target consistency status is determined based on the latest access operation type of the target core, and the state field segment corresponding to the target core is updated in the target directory entry information based on the target consistency status.

10. The cache consistency domain adjustment method according to claim 8, characterized in that, The step of removing information related to the target chip from the catalog entry information includes: In the catalog entry information, the replica bit corresponding to the target core is cleared to zero; the default state of the replica bit is zero. In the directory entry information, the status field is updated based on the copy bits after the clearing process.

11. The cache consistency domain adjustment method according to claim 10, characterized in that, After clearing the replica bit corresponding to the target core, the process further includes: If all copy bits of any directory entry information are zero, then that directory entry information is cleared in the preset directory.

12. The cache consistency domain adjustment method according to claim 7, characterized in that, Also includes: Upon receiving a consistency transaction request from any target particle in the cache consistency domain, determine the current set of particles in the cache consistency domain; Send the consistency transaction request to each core in the current core set.

13. The cache consistency domain adjustment method according to claim 12, characterized in that, The consistency transaction request is a failed transaction request; Accordingly, the method further includes: When any target kernel performs a write operation on the first memory address, the invalidation transaction request is sent to each kernel in the current kernel set so that each kernel in the current kernel set marks the cache line copy corresponding to the first memory address held locally as invalid.

14. The cache consistency domain adjustment method according to claim 12, characterized in that, The consistency transaction request is a read shared transaction request; Accordingly, the method further includes: When any target kernel performs a read operation on the second memory address, the read shared transaction request is sent to each kernel in the current kernel set to determine whether each kernel in the current kernel set holds a cache line copy corresponding to the second memory address; If held, the cache line copy is obtained from the kernel of the current kernel set; If not held, data is read from the second memory address.

15. The cache consistency domain adjustment method according to claim 12, characterized in that, The consistency transaction request is a write-back transaction request; Accordingly, the method further includes: When any target kernel performs a modification operation on the data at its local cache address, it writes the modified data back to the shared memory and sends the write-back transaction request to each kernel in the current kernel set so that each kernel in the current kernel set can update the corresponding data.

16. A cache consistency domain adjustment device, characterized in that, include: The monitoring module is used to monitor the access requests of target chips to shared memory in a heterogeneous chip architecture in order to obtain access behavior; The condition judgment module is used to determine whether the target chip meets the preset activity conditions based on the access behavior; The inclusion module is used to include the target core into the cache consistency domain if the target core meets the preset active condition and the target core is not currently located in the preset cache consistency domain. The removal module is used to remove the target particle from the cache consistency domain if the target particle does not meet the preset active condition and the target particle is currently located in the preset cache consistency domain. Each core in the cache consistency domain maintains the consistency of access to the shared memory based on the cache consistency protocol, and receives consistency transaction requests from other cores in the cache consistency domain. The access behavior includes at least the access address range, access operation type, and access frequency; Accordingly, the condition judgment module is specifically used to determine whether the access address range belongs to a pre-divided shared data domain in the shared memory; if the access address range belongs to the shared data domain, then based on the access operation type and the access frequency, it is determined whether the target core meets the preset active condition; if the access address range does not belong to the shared data domain, then it is directly determined that the target core does not meet the preset active condition.

17. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing the computer program to implement the steps of the cache coherence domain adjustment method as described in any one of claims 1 to 15.

18. A computer-readable storage medium, characterized in that, Used to store a computer program; wherein, when the computer program is executed by a processor, it implements the steps of the cache coherence domain adjustment method as described in any one of claims 1 to 15.

19. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the cache coherence domain adjustment method as described in any one of claims 1 to 15.

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