Data reading processing method, multi-level cache processor architecture, cache controller and equipment

Abstract

The invention provides a data reading processing method, a multi-level cache processor architecture, a cache controller and equipment, the method is applied to the multi-level cache processor architecture, and the multi-level cache processor architecture comprises special caches corresponding to processor cores and shared caches shared by the processor cores. The method comprises the following steps: under the condition that a write request hits shared-state first data in a special cache, the special cache sends an exclusive-state read request to a shared cache; and before the special cache receives the first data in the exclusive state returned by the shared cache, if the special cache receives the second data returned by the shared cache and confirms that the first data needs to be evicted when the second data is filled into the special cache, the special cache cancels the operation of sending the eviction request to the shared cache. According to the method, the problem of inconsistent cache data of the processor can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to a data reading processing method, a multi-level cache processor architecture, a cache controller and a device. BACKGROUND

[0002] In a multi-level cache multi-core processor architecture, a dedicated cache is usually configured for each processor core, and a shared cache is configured for each processor core. When a processor sends a write request to modify a target data to the dedicated cache, the dedicated cache needs to first prepare the target data in an exclusive state. If the write request hits the target data in a shared state in the dedicated cache, the dedicated cache needs to send an exclusive state read request to the shared cache to request the target data in the exclusive state. After receiving the exclusive state read request sent by the dedicated cache, the shared cache notifies the dedicated caches of each processor core to invalidate the target data in the shared state, and then returns the target data in the exclusive state to the dedicated cache sending the exclusive state read request.

[0003] Before the shared cache returns the target data in the exclusive state, if the shared cache returns data corresponding to a request which is older and evicts the target data in the shared state in the dedicated cache, at this time the dedicated cache sends an eviction request to the shared cache, and the shared cache considers that the dedicated cache does not exist the target data when receiving the eviction request.

[0004] However, after the shared cache returns the target data in the exclusive state to the dedicated cache in response to the exclusive state request, the target data exists in the dedicated cache, so that when other processor cores perform write operations on the target data, the shared cache does not notify the dedicated cache of the current processor core to invalidate the target data, which leads to inconsistency of the target data in the dedicated caches of different processor cores. SUMMARY

[0005] Based on the above technical problems, the present application provides a data reading processing method, a multi-level cache processor architecture, a cache controller and a device, which can avoid the problem of inconsistency of processor cache data.

[0006] The first aspect of the present application provides a data reading processing method applied to a multi-level cache processor architecture, the multi-level cache processor architecture comprising a dedicated cache corresponding to each processor core respectively, and a shared cache shared by the processor cores, and the method comprises:

[0007] In the case that the write request hits first data in the dedicated cache, the dedicated cache sends an exclusive state read request to the shared cache; wherein the first data in the dedicated cache is in a shared state, and the exclusive state read request is used to request to read the first data in an exclusive state;

[0008] If the private cache receives second data returned by the shared cache and confirms that the first data needs to be evicted when the second data is filled into the private cache, the private cache cancels the operation of sending an eviction request to the shared cache.

[0009] In some implementations, in a case where the exclusive state read request hits the first data in the private cache, the method further includes:

[0010] The private cache stores data information of the first data into a buffer; the data information of the first data includes an address and parameter information of a cache line where the first data is located;

[0011] After the private cache receives the second data returned by the shared cache, the method further includes:

[0012] The private cache determines whether data needs to be evicted when the second data is filled into the private cache;

[0013] In a case where it is confirmed that data needs to be evicted, information of data to be evicted is compared with data information in the buffer;

[0014] In a case where the information of the data to be evicted is consistent with the data information in the buffer, the private cache confirms that the first data needs to be evicted when the second data is filled into the private cache.

[0015] In some implementations, in a case where the exclusive state read request hits the first data in the second-level cache, the method further includes:

[0016] The private cache adds a state identifier to the first data, and the state identifier is used to represent a shared non-eviction state;

[0017] After the private cache receives the second data returned by the shared cache, the method further includes:

[0018] The private cache determines whether data needs to be evicted when the second data is filled into the private cache;

[0019] In a case where it is confirmed that data needs to be evicted, it is determined whether the data to be evicted carries the state identifier;

[0020] In a case where it is confirmed that the data to be evicted carries the state identifier, the private cache confirms that the first data needs to be evicted when the second data is filled into the private cache.

[0021] In some implementations, the private cache includes a first level cache and a second level cache, and the method further includes:

[0022] The first level cache queries the first data in an exclusive state from the locally cached data in a case where a write instruction for modifying the first data is received;

[0023] The first level cache sends the exclusive state read request to the second level cache in a case where the first data in an exclusive state is not queried from the local cache.

[0024] In some implementations, the method further includes:

[0025] In a case where the private cache receives the first data in an exclusive state returned by the shared cache, the private cache determines the first data in an exclusive state as return data corresponding to the exclusive state read request.

[0026] In some implementations, the method further includes:

[0027] The shared cache sends a snoop request to each private cache corresponding to each processor core in the multi-level cache processor architecture in a case where the exclusive state read request is received, the snoop request being used to indicate invalidating the first data in the private cache.

[0028] In some implementations, the private cache includes a first level cache and a second level cache, the shared cache includes a third level cache, and the multi-level processor architecture includes a plurality of processor cores, each of which is respectively configured with a private first level cache and a private second level cache, and the plurality of processor cores share the third level cache.

[0029] The second aspect of the present application provides a cache controller applied to a private cache of a multi-level cache processor architecture, the multi-level cache processor architecture including a private cache corresponding to each processor core and a shared cache shared by the processor cores, and the cache controller includes:

[0030] A request sending unit is configured to send an exclusive state read request to the shared cache in a case where a write request hits first data in the private cache, wherein the first data in the private cache is in a shared state, and the exclusive state read request is used to request reading the first data in an exclusive state;

[0031] A data filling unit is configured to cancel an operation of sending an eviction request to the shared cache before receiving the first data in an exclusive state returned by the shared cache, if second data returned by the shared cache is received and it is confirmed that the first data needs to be evicted when the second data is filled into the private cache.

[0032] The third aspect of the present application provides a multi-level cache processor architecture, comprising a plurality of processor cores each corresponding to a private cache, and a shared cache shared by the plurality of processor cores, and the multi-level cache processor architecture is configured to implement the data reading processing method.

[0033] The fourth aspect of the present application provides a computer device comprising the cache controller or the multi-level cache processor architecture.

[0034] The data reading processing method provided by the present application can cancel the operation of sending the eviction request to the shared cache, that is, not sending the eviction request to the shared cache, if the second data needs to be written into the private cache and the first data needs to be evicted before the private cache receives the exclusive first data returned by the shared cache. In this way, the data state of the private cache recorded by the shared cache is consistent with the actual data state of the private cache, and the problem of cache data inconsistency caused by the shared cache failing to accurately record the data state of the private cache when other processor cores need to write the first data and invalidate the first data in the private cache of each processor core through the shared cache can be avoided. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the provided drawings.

[0036] Figure 1 A structural schematic diagram of a multi-level cache processor architecture provided by an embodiment of the present application.

[0037] Figure 2 A structural schematic diagram of another multi-level cache processor architecture provided by an embodiment of the present application.

[0038] Figure 3 A flowchart of a data reading processing method provided by an embodiment of the present application.

[0039] Figure 4 A structural schematic diagram of a cache controller provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] The technical scheme of the embodiment of the present application is suitable for an application scenario of reading data from a cache by a processor, and is particularly suitable for an application scenario of reading exclusive state data from a cache by a processor. The technical scheme of the embodiment of the present application can ensure that the data in the cache corresponding to each processor core meets consistency in the process of reading exclusive state data from the cache by the processor.

[0041] In the hierarchy of a computer storage system, a cache is a high-speed small-capacity memory between a central processing unit and a main memory, which is composed of static memory chips (SRAM) and has a relatively small capacity but a speed higher than that of the main memory, close to the speed of the CPU.

[0042] The working principle of the cache is that when the CPU wants to read a data, the CPU first searches in the CPU cache, reads and sends the data to the CPU for processing if the data is found; if the data is not found, the data is read from the relatively slow memory and sent to the CPU for processing, and the data block where the data is located is called into the cache, so that the reading of the entire block of data is performed from the cache in the future, without calling the memory. Such a reading mechanism increases the hit rate of the CPU reading the cache, that is, the data to be read by the CPU next time is more likely to be in the CPU cache, and only a small amount of data needs to be read from the memory. This greatly saves the time of the CPU directly reading the memory, and also makes the CPU read data without waiting basically.

[0043] The data in the cache is only a copy of part of the data in the memory, so when the CPU searches for data in the cache, it may not be found (because some data is not copied from the memory to the cache), and the CPU will still read the data from the memory at this time. Therefore, the more frequently the data is accessed, the longer the data exists in the cache. At the same time, with the change of time, the data that is accessed most frequently also changes, so the data in the cache needs to be replaced according to a certain algorithm frequently, so as to ensure that the data in the cache is always the data that is accessed most frequently.

[0044] The technical scheme of the embodiment of the present application is suitable for a multi-level cache processor architecture, and in the multi-level cache processor architecture, a plurality of levels of caches are included, such as two levels of caches, three levels of caches, four levels of caches, or any number of levels of caches.

[0045] In the multi-level cache described above, according to the distance between the cache and the processor core, the multi-level cache can be defined as a first-level cache, a second-level cache, a third-level cache, and so on. The closer the level of the cache, the closer the distance between the cache and the processor core, and the faster the speed of the processor core reading data from the cache. For example, the speed of the processor core reading data from the first-level cache is higher than that from the second-level cache, and the speed of the processor core reading data from the second-level cache is higher than that from the third-level cache.

[0046] Generally, the closer the level of the cache, the higher the frequency of the stored data being read by the processor core, and the farther the level of the cache, the lower the frequency of the stored data being read by the processor core. Moreover, generally, the closer the level of the cache, the smaller the space of the cache, and the farther the level of the cache, the larger the space of the cache.

[0047] Figure 1 is a schematic diagram of a multi-level cache processor architecture provided by an embodiment of the present application. In the multi-level cache processor architecture, a plurality of processor cores are included, and a dedicated cache is configured for each processor core, and a shared cache of the processor cores is also configured in the multi-level cache processor architecture. The shared cache accesses the system main memory through the network on chip.

[0048] In other embodiments, different regions can be divided for the plurality of processor cores, and a dedicated cache is configured for each processor core in each region, and a shared cache is shared by the processor cores in the region. The shared caches of the plurality of regions share the system main memory through the network on chip.

[0049] For each processor core, when it needs to read data, it first reads from its own dedicated cache. If the target data is not hit in the dedicated cache, the dedicated cache requests the target data from the shared cache. When the shared cache returns the target data to the dedicated cache, the dedicated cache returns the target data to the processor core and caches the target data locally. In the above process, if the shared cache also does not have the target data, the shared cache requests the target data from the main memory.

[0050] In Figure 1 The multi-level cache processor architecture shown in FIG. 8 can be further divided into a plurality of levels, i.e., the dedicated cache and the shared cache can each include a plurality of levels of cache.

[0051] Figure 2 is another multi-level cache processor architecture provided by an embodiment of the present application. In this architecture, the dedicated cache configured for the processor core includes two levels of cache.

[0052] Referring to Figure 2 As shown, the multi-level cache processor architecture includes a first level cache L1, a second level cache L2 and a third level cache L3.

[0053] The first level cache L1 is further divided into an instruction cache L1I and a data cache L1D, the instruction cache L1I is used to cache instructions, and the data cache L1D is used to cache data.

[0054] The instruction cache L1I and the data cache L1D included in the first level cache L1 share the second level cache L2.

[0055] In the multi-level cache processor architecture, a plurality of processor cores are included, and for each processor core, a dedicated first level cache (including an instruction cache L1I and a data cache L1D) and a second level cache L2 are respectively configured. A plurality of processor cores share a third level cache L3.

[0056] Continuing to refer to Figure 2 For a plurality of processor cores, different regions can also be divided, and for each processor core in each region, a dedicated first level cache (including an instruction cache L1I and a data cache L1D) and a second level cache L2 are respectively configured. The processor cores in the region share a third level cache L3. The processor cores in a plurality of regions share a system main memory through an on-chip network.

[0057] In the above processor architecture, when a LOAD instruction misses the data to be read in L1D, L1D will send a read request to L2 to read the data from L2. If the data is still not in L2, a read request is sent to L3 to read the data from L3. If the data is still not in L3, the data needs to be read from the main memory. In the above process, if the data to be read is read in a certain level cache, the data is returned to the upper cache in turn until it is returned to the processor. For example, if the data is read from L2, the cache line where the data is located is returned to L1, and the cache line is stored in L1, and L1 returns the cache line to the processor.

[0058] In the cache system, the state of the data includes exclusive state (Exclusive) and shared state (Shared). Among them, exclusive state means that data only exists in the cache of one CPU core. In this state, the CPU core can freely modify the data without notifying other CPU cores.

[0059] Shared state means that the same data may have copies in the caches of multiple CPU cores, and these copies are consistent with the data in main memory. In this state, if any CPU core wants to modify data, it needs to notify the other CPU cores to mark the corresponding data in their caches as invalid before it can make the modification.

[0060] When a CPU core reads data from memory into its cache, if the data is not in the caches of other CPU cores, then that data is in an exclusive state in the cache of that CPU core. If other CPU cores also read the same data into their respective caches, then the state of that data in the caches of all these CPU cores changes from exclusive to shared.

[0061] When a CPU core wants to modify data in shared state, it needs to send a request to the bus to notify other CPU cores to mark the corresponding data in their cache as invalid. Then, when the CPU core performs a write operation on the data, the data in the cache will become modified.

[0062] For example in Figure 2 In the multi-level cache processor architecture shown, when a STORE write instruction sent by a processor core does not find the target data to be written in the first-level cache L1, a LOAD read request will be sent to the second-level cache L2 to request a target data in exclusive state.

[0063] If a read request from L1 cache hits shared data in L2 cache, L2 cache sends a read request to L3 cache to request exclusive access to the target data. Since L3 cache is shared by all processor cores, it can send a listener request to each processor core's L2 cache, informing it to invalidate the target data in its local cache. If L2 cache confirms that the target data also exists in L1 cache, it sends a listener request to L1 cache, informing it to invalidate its local cache. Once L3 cache returns the target data to L2 cache, it becomes exclusive access to that data and can be written to by the processor core.

[0064] In the above process, after the second level cache L2 sends a read request for requesting the target data in exclusive state to the third level cache L3, if another data with the same index but different way as the target data is returned by the third level cache L3 to the second level cache L2 before the target data is returned by the third level cache L3 to the second level cache L2, the target data in the second level cache L2 is evicted when the other data is filled into the second level cache L2, and the second level cache L2 needs to send an eviction request for evicting the target data to the third level cache L3.

[0065] For the third level cache L3, a certain time is needed for pipeline processing, in the above process, the third level cache L3 considers that the second level cache L2 first sends a read request for requesting the target data to the third level cache L3, and then sends an eviction request for evicting the target data, at this time, the third level cache L3 considers that the target data does not exist in the second level cache L2.

[0066] However, there is still a read request for requesting the target data in exclusive state in the third level cache L3, which needs to return the target data to the second level cache L2, when the target data in exclusive state is returned by the third level cache L3 to the second level cache L2, the target data exists in the second level cache L2 again. This leads to the inconsistency between the data state of the second level cache L2 recorded by the third level cache L3 and the actual data state of the second level cache L2. The direct consequence of this situation is that when other processor cores need to perform write operation on the target data and request the target data in exclusive state from the third level cache L3, the third level cache L3 considers that the target data does not exist in the second level cache L2 and the first level cache L1 of the current processor core, and therefore does not send a snoop request to invalidate the target data to the second level cache L2 and the first level cache L1 of the current processor core. Thus, after the other processor cores perform write operation on the target data in their private caches, the target data in the private caches of different processor cores is inconsistent, which will inevitably affect the correct operation of the processor.

[0067] In view of the above technical problems, the embodiment of the present application provides a data reading processing method, which can avoid the inconsistency of data in different caches in a multi-level cache processor architecture.

[0068] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0069] This application provides a data reading and processing method, which is applied to a multi-level cache processor architecture. The multi-level cache processor architecture can be found in [reference needed]. Figure 1 As shown, this multi-level cache processor architecture includes multiple processor cores, dedicated caches for each processor core, and shared caches shared by all processor cores.

[0070] In other embodiments, the structure of the multi-level cache processor architecture applying the above data read processing method can be found in [reference needed]. Figure 2 As shown, each processor core in the corresponding architecture is configured with a dedicated Level 1 cache (L1) and Level 2 cache (L2), and is also configured with a shared Level 3 cache (L3).

[0071] This method can be executed by the dedicated cache of the processor core in the multi-level cache processor architecture described above. When the dedicated cache of the processor core includes multi-level caches, the method is executed by the last level cache in the dedicated cache.

[0072] See Figure 3 As shown in the embodiments of this application, the data reading and processing method includes:

[0073] S101. If a write request hits the first data in the dedicated cache, the dedicated cache sends an exclusive read request to the shared cache.

[0074] The write request mentioned above refers to the request sent by the processor core to the dedicated cache to request a write operation on the first data. As described in the above embodiment, the processor core can only perform a write operation on the first data when it is in an exclusive state in the dedicated cache.

[0075] When the dedicated cache receives the write request from the processor core, it first queries the local cache for the first data in exclusive mode. If the first data in exclusive mode is found, the processor core is allowed to perform a write operation on that first data.

[0076] If the first data in the shared state is found, the dedicated cache needs to request the first data in the exclusive state from the shared cache.

[0077] In some embodiments, when the dedicated cache includes a first-level cache, a write request hitting the first data in the dedicated cache may be achieved by the dedicated cache retrieving the first data from its included first-level cache when it receives the write request.

[0078] In other embodiments, when the dedicated cache includes multi-level caching, for example... Figure 2As shown, when the private cache includes the first-level cache L1 and the second-level cache L2, the first-level cache L1 of the private cache can query the first data from the local cache of the first-level cache L1 after receiving the write request. Alternatively, if the first-level cache L1 does not query the first data from the local cache data after receiving the write request, the first-level cache L1 sends an exclusive-state read request to the second-level cache, to request the first data in the exclusive state. The second-level cache L2 queries the first data from the local cache data of the second-level cache L2 after receiving the exclusive-state read request, and the first data is also considered as a hit of the write request in the private cache.

[0079] In the embodiment of the present application, the first data in the private cache is in the shared state, and therefore, in the above scenario, the write request hits the first data in the private cache, which is actually the first data in the shared state in the private cache.

[0080] When the write request hits the first data in the shared state in the private cache, it indicates that the first data in the exclusive state does not exist in the private cache, that is, the first data also exists in the private cache of another processor core. At this time, the private cache sends an exclusive-state read request to the shared cache to request reading the first data in the exclusive state from the shared cache.

[0081] S102, before the private cache receives the first data in the exclusive state returned by the shared cache, if the private cache receives second data returned by the shared cache, and it is confirmed that the first data needs to be evicted when the second data is filled into the private cache, the private cache cancels the operation of sending an eviction request to the shared cache.

[0082] Specifically, when the shared cache receives the exclusive-state read request sent by the private cache, on the one hand, the shared cache sends a monitoring request to the private cache of each processor core in the multi-level cache processor architecture, to instruct the private cache of each processor core to invalidate the first data in the local cache. On the other hand, the shared cache reads the first data requested by the exclusive-state read request from the local cache or from the system main memory, and returns the first data to the private cache sending the exclusive-state read request after reading the first data.

[0083] Since the processor core frequently reads data from the cache, before the private cache sends the exclusive-state read request to the shared cache, the private cache can also send a read request to the shared cache for reading other data.

[0084] The pipeline of the shared cache needs certain processing time, so each request needs certain time to return data after reaching the shared cache. After the private cache sends the exclusive-state read request to the shared cache, the shared cache may return the second data requested by the read request received before the exclusive-state read request, before the shared cache returns the exclusive-state first data to the private cache.

[0085] For the private cache, the second data returned by the shared cache is received before the first data returned by the shared cache. At this time, the second data needs to be filled into the private cache.

[0086] If the second data received by the private cache needs to evict the first data in the shared state in the private cache when filling the private cache, for example, the second data and the first data are data of the same index but different ways, the first data needs to be evicted before the second data is written into the private cache.

[0087] In the embodiment of the present application, for the above scenario, when the private cache confirms that the first data needs to be evicted when the second data is written into the private cache, the operation of sending the eviction request to the shared cache is cancelled, that is, the eviction request is not sent to the shared cache. The private cache can directly evict the first data from the private cache and then write the second data into the private cache in this case.

[0088] When the shared cache returns the exclusive-state first data to the private cache, the private cache writes the exclusive-state first data into the private cache. When the first data is written into the private cache, if a data needs to be evicted, according to the cache data update rule, the data that has existed in the private cache for a longer time is selected to be evicted, and the second data is not selected to be evicted.

[0089] For the shared cache, the second data and the first data are returned to the private cache in sequence, so the shared cache records the second data and the first data in the private cache. For the private cache, the first data is evicted when the second data from the shared cache is received, but the first data from the shared cache is received later. At this time, the second data and the first data actually exist in the private cache. Therefore, the data state of the private cache recorded by the shared cache is consistent with the actual data state of the private cache.

[0090] As can be seen from the above, the data reading processing method provided by the embodiments of the present application can cancel the operation of sending the eviction request to the shared cache, that is, not send the eviction request to the shared cache, if the second data needs to be written into the private cache and the first data needs to be evicted before the private cache receives the exclusive-state first data returned by the shared cache. In this way, the data state of the private cache recorded by the shared cache is consistent with the actual data state of the private cache, and the problem of cache data inconsistency caused by the fact that the shared cache fails to accurately record the data state of the private cache when the other processor core needs to write the first data and invalidates the first data in the private cache of each processor core through the shared cache can be avoided.

[0091] In another embodiment, after the private cache receives the exclusive-state first data returned by the shared cache, the first data is written into the private cache. When the first data is written into the private cache, if one data needs to be evicted, the data that has been in the private cache for a longer time is selected to be evicted according to the cache data update rule, and the second data is not selected to be evicted.

[0092] Then, the private cache determines the exclusive-state first data as the return data corresponding to the exclusive-state read request. In some embodiments, after the private cache determines the exclusive-state first data as the return data corresponding to the exclusive-state read request, the private cache can notify the processor core to perform a write operation on the first data. Alternatively, when the private cache is the second-level cache L2 in the multi-level cache processor architecture as shown in FIG. 1, the private cache returns the exclusive-state first data returned by the third-level cache L3 to the first-level cache L1 that sends the exclusive-state read request, so that the processor core can perform a write operation on the exclusive-state first data in the first-level cache L1. Figure 2

[0093] In another embodiment, a judgment manner of the private cache for judging whether the first data needs to be evicted when the second data returned by the shared cache is filled into the private cache is disclosed.

[0094] When the exclusive-state read request hits the first data in the shared state in the private cache, the private cache stores the data information of the first data in the shared state into a buffer, for example, stores the address and parameter information of the cache line where the first data is located into the buffer. Then, the private cache sends an exclusive-state read request to the shared cache for requesting the exclusive-state first data.

[0095] Before the private cache receives the exclusive-state first data returned by the shared cache, if the private cache receives the second data returned by the shared cache, the private cache judges whether the data needs to be evicted when the second data is filled into the private cache.

[0096] ​If no data needs to be evicted, the private cache fills the second data into the private cache.

[0097] If data needs to be evicted, the private cache compares information of the data to be evicted with the data information stored in the buffer.

[0098] If the information of the data to be evicted is different from the data information stored in the buffer, the private cache sends an eviction request to the shared cache for indicating eviction of the data to be evicted, and evicts the data to be evicted.

[0099] If the information of the data to be evicted is consistent with the data information stored in the buffer, the private cache can confirm that the data to be evicted is the first data, that is, can confirm that the shared-state first data in the private cache needs to be evicted when the second data returned by the shared cache is filled into the private cache.

[0100] In another embodiment, another way for a private cache to determine whether the first data needs to be evicted when the second data returned by the shared cache is filled into the private cache is disclosed.

[0101] When an exclusive-state read request hits the first data in the private cache in the shared state, the private cache adds a state identifier to the first data in the shared state, and the state identifier indicates a shared clean no eviction (SC-NE) state.

[0102] Before the private cache receives the exclusive-state first data returned by the shared cache, if the private cache receives the second data returned by the shared cache, the private cache determines whether data needs to be evicted when the second data is filled into the private cache.

[0103] If no data needs to be evicted, the private cache fills the second data into the private cache.

[0104] If data needs to be evicted, the private cache determines whether the data to be evicted carries the state identifier.

[0105] If the information of the data to be evicted does not carry the state identifier, the private cache evicts the data to be evicted, and then sends an eviction request to the shared cache for indicating eviction of the data to be evicted.

[0106] If the information of the data to be evicted carries the state identifier, the private cache can confirm that the data to be evicted is the first data, that is, can confirm that the first data in the shared state needs to be evicted when the second data returned by the shared cache is filled into the private cache.

[0107] Correspondingly, the embodiment of the application further provides a cache controller, which can be applied to a private cache of a multi-level cache processor architecture. The multi-level cache processor architecture includes private caches corresponding to respective processor cores and a shared cache shared by the respective processor cores. As shown in Figure 4 The cache controller includes:

[0108] The request sending unit 100 is configured to send an exclusive state read request to the shared cache in a case where a write request hits first data in the private cache. The first data in the private cache is in a shared state, and the exclusive state read request is used to request reading of the first data in an exclusive state.

[0109] The data filling unit 110 is configured to, before receiving the first data in the exclusive state returned by the shared cache, cancel the operation of sending an eviction request to the shared cache in a case where the second data returned by the shared cache is received and it is confirmed that the first data needs to be evicted when the second data is filled into the private cache.

[0110] In some implementations, the request sending unit 100 is further configured to store data information of the first data into a buffer. The data information of the first data includes an address and parameter information of a cache line where the first data is located.

[0111] The data filling unit 110 is further configured to determine whether data needs to be evicted when the second data is filled into the private cache. In a case where it is confirmed that data needs to be evicted, the information of data to be evicted is compared with the data information in the buffer. In a case where the information of the data to be evicted is consistent with the data information in the buffer, it is confirmed that the first data needs to be evicted when the second data is filled into the private cache.

[0112] In some implementations, the request sending unit 100 is further configured to add a state identifier to the first data. The state identifier is used to represent a shared non-eviction state.

[0113] The data filling unit 110 is further configured to determine whether data needs to be evicted when the second data is filled into the special cache; in a case where it is determined that data needs to be evicted, determine whether the data to be evicted carries the state identifier; and in a case where it is determined that the data to be evicted carries the state identifier, determine that the first data needs to be evicted when the second data is filled into the special cache.

[0114] In some implementations, the special cache includes a first-level cache and a second-level cache, and the request sending unit 100 is further configured to control the first-level cache to perform the following operations:

[0115] In a case where a write instruction for modifying the first data is received, query the first data in an exclusive state from the local cache data;

[0116] In a case where the first data in an exclusive state is not queried from the local cache, send the exclusive state read request to the second-level cache.

[0117] In some implementations, the data filling unit 110 is further configured to:

[0118] In a case where the first data in an exclusive state returned by the shared cache is received, determine the first data in an exclusive state as return data corresponding to the exclusive state read request.

[0119] In some implementations, the special cache includes a first-level cache and a second-level cache, the shared cache includes a third-level cache, and the multi-level processor architecture includes a plurality of processor cores, and the first-level cache and the second-level cache are respectively configured for each of the processor cores, and the plurality of processor cores share the third-level cache.

[0120] The cache controller provided by the embodiment belongs to the same application concept as the data reading processing method provided by the above-mentioned embodiments of the application, can execute the data reading processing method provided by any of the above-mentioned embodiments of the application, and has the corresponding function modules and beneficial effects of the execution method. Technical details not described in detail in the embodiment can be referred to the specific processing content of the data reading processing method provided by the above-mentioned embodiments of the application, which will not be described here.

[0121] The functions implemented by the above-mentioned units can be respectively implemented by the same or different processors, and the embodiments of the application are not limited.

[0122] It should be understood that the units in the above apparatus can be implemented in the form of processor calling software. For example, the apparatus includes a processor connected with a memory, the memory stores instructions, and the processor calls the instructions stored in the memory to implement any of the above methods or realize the functions of the units of the apparatus, wherein the processor can be a general processor such as CPU or microprocessor, and the memory can be an internal memory or an external memory of the apparatus. Alternatively, the units in the apparatus can be implemented in the form of hardware circuit, and the functions of part or all of the units can be realized by the design of the hardware circuit, which can be understood as one or more processors. For example, in one implementation, the hardware circuit is ASIC, and the functions of part or all of the units are realized by the design of the logical relationship of the elements in the circuit. For another example, in another implementation, the hardware circuit can be realized by PLD, and taking FPGA as an example, it can include a large number of logic gate circuits, and the connection relationship between the logic gate circuits is configured by a configuration file, so as to realize the functions of part or all of the units. All the units of the above apparatus can be realized in the form of processor calling software, or realized in the form of hardware circuit, or part of them is realized in the form of processor calling software, and the remaining part is realized in the form of hardware circuit.

[0123] In the embodiments of the present application, the processor is a circuit with signal processing capability. In one implementation, the processor can be a circuit with instruction reading and running capability, such as CPU, microprocessor, GPU, or DSP, etc. In another implementation, the processor can realize certain functions through the logical relationship of hardware circuit, which is fixed or can be reconfigured, such as ASIC or PLD implemented hardware circuit, such as FPGA, etc. In the reconfigurable hardware circuit, the process of the processor loading configuration document to realize hardware circuit configuration can be understood as the process of the processor loading instructions to realize the functions of part or all of the units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as a kind of ASIC, such as NPU, TPU, DPU, etc.

[0124] It can be seen that each unit in the above apparatus can be one or more processors (or processing circuits) configured to implement the above method, such as CPU, GPU, NPU, TPU, DPU, microprocessor, DSP, ASIC, FPGA, or a combination of at least two of these processor forms.

[0125] In addition, all or part of each unit in the above apparatus can be integrated together or can be independently implemented. In one implementation, the units are integrated together to be implemented in the form of a SOC. The SOC can include at least one processor for implementing the functions of any of the above methods or implementing the functions of each unit of the apparatus. The at least one processor can be of different types, such as including a CPU and an FPGA, a CPU and an artificial intelligence processor, a CPU and a GPU, and the like.

[0126] Another embodiment of the present application also provides a multi-level cache processor architecture, which includes a plurality of processor cores, and includes a dedicated cache corresponding to each processor core respectively, and a shared cache shared by the plurality of processor cores. The structure of the multi-level cache processor architecture can be referred to as shown in the following figure. Figure 1 Or Figure 2 The multi-level cache processor architecture is configured to implement the data reading processing method described in any of the above embodiments.

[0127] Another embodiment of the present application also provides a computer device, which includes the cache controller described in the above embodiments, or the computer device includes the multi-level cache processor architecture described in the above embodiments.

[0128] For each of the above method embodiments, in order to simply describe, it is expressed as a combination of a series of actions, but those skilled in the art should know that the present application is not limited to the order of the actions described, because according to the present application, certain steps can be performed in other order or simultaneously. Secondly, those skilled in the art should know that the embodiments described in the specification all belong to preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0129] It should be noted that each of the embodiments in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments, and the same and similar parts between each embodiment can be referred to. For the device embodiment, since it is basically similar to the method embodiment, it is described relatively simply, and the relevant parts can be referred to the part of the method embodiment.

[0130] The steps in the method of each embodiment of the present application can be adjusted, combined and deleted in sequence according to actual needs, and the technical features recorded in each embodiment can be replaced or combined.

[0131] The modules and sub-modules in the device and terminal of each embodiment of the present application can be combined, divided and deleted according to actual needs.

[0132] It should be understood that the disclosed terminal, device and method can be implemented in other ways. For example, the terminal embodiments described above are merely illustrative. For example, the division of modules or sub-modules is merely a logical function division. In actual implementation, another division manner can be used. For example, a plurality of sub-modules or modules can be combined or integrated into another module, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed modules can be indirect coupling or communication connection through some interfaces, devices or modules, and can be electrical, mechanical or other forms.

[0133] The modules or sub-modules described as separate components can or can not be physically separate, and the components of the modules or sub-modules can or can not be physical modules or sub-modules, i.e. can be located in one place or distributed on a plurality of network modules or sub-modules. Some or all of the modules or sub-modules can be selected according to actual needs to achieve the purpose of the embodiment.

[0134] In addition, the functional modules or sub-modules in each embodiment of the present application can be integrated into a processing module, or each module or sub-module can exist physically, or two or more modules or sub-modules can be integrated into one module. The integrated module or sub-module can be realized in the form of hardware or software functional module or sub-module.

[0135] The skilled person can further realize that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in general terms in the above description. Whether the functions are realized in hardware or software depends on the specific application and design constraints of the technical solution. The skilled person can use different methods to realize the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0136] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein can be directly implemented by hardware, software units executed by a processor, or a combination of both. The software units can be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0137] Finally, it should be noted that, in this document, the term "only" is used simply to set off from one entity or action to another in order to avoid the use of the term "and / or" or the like for the sake of clarity. In no way should the term "only" be interpreted as implying that there is an implied exclusion of any referenced entity or action. Moreover, the terms "comprising", "including", or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the recited element.

[0138] The above description of disclosed embodiments provides enabling teaching for making or using the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data reading and processing method, characterized in that, Applied to a multi-level cache processor architecture, the multi-level cache processor architecture including dedicated caches corresponding to each processor core and shared caches shared by all processor cores, the method includes: If a write request hits the first data in the dedicated cache, the dedicated cache sends an exclusive read request to the shared cache; wherein the first data in the dedicated cache is in a shared state, and the exclusive read request is used to request to read the first data in an exclusive state; Before the dedicated cache receives the first data in exclusive state returned by the shared cache, if the dedicated cache receives the second data returned by the shared cache and confirms that the first data needs to be evicted when filling the dedicated cache with the second data, the dedicated cache cancels the operation of sending an eviction request to the shared cache.

2. The method according to claim 1, characterized in that, In the event that an exclusive read request hits the first data in the dedicated cache, the method further includes: The dedicated cache stores the data information of the first data in the buffer; the data information of the first data includes the address and parameter information of the cache line where the first data is located; After the dedicated cache receives the second data returned by the shared cache, the method further includes: The dedicated cache determines whether data needs to be evicted when the second data is filled into the dedicated cache. If it is confirmed that data needs to be evicted, the information of the data to be evicted is compared with the data information in the buffer. If the information of the data to be evicted matches the information of the data in the buffer, the dedicated cache determines that the first data needs to be evicted when the second data is filled into the dedicated cache.

3. The method according to claim 1, characterized in that, In the case where an exclusive read request hits the first data in the second-level cache, the method further includes: The dedicated cache adds a status identifier to the first data, and the status identifier is used to indicate a shared, non-eviction state. After the dedicated cache receives the second data returned by the shared cache, the method further includes: The dedicated cache determines whether data needs to be evicted when the second data is filled into the dedicated cache. If it is confirmed that data needs to be evicted, determine whether the data to be evicted carries the aforementioned status identifier; If the data to be evicted is confirmed to carry the status identifier, the dedicated cache confirms that the first data needs to be evicted when the second data is filled into the dedicated cache.

4. The method according to any one of claims 1 to 3, characterized in that, The dedicated cache includes a first-level cache and a second-level cache, and the method further includes: When the first-level cache receives a write instruction to modify the first data, it queries the first data in exclusive state from the local cache data. If the exclusive state of the first data is not found in the local cache, the first-level cache sends the exclusive state read request to the second-level cache.

5. The method according to any one of claims 1 to 3, characterized in that, The method further includes: When the dedicated cache receives the first data in exclusive state returned by the shared cache, the dedicated cache determines the first data in exclusive state as the return data corresponding to the exclusive state read request.

6. The method according to any one of claims 1 to 3, characterized in that, The method further includes: Upon receiving the exclusive read request, the shared cache sends a listening request to the dedicated cache corresponding to each processor core in the multi-level cache processor architecture. The listening request is used to indicate that the first data in the dedicated cache is invalid.

7. The method according to any one of claims 1 to 3, characterized in that, The dedicated cache includes a first-level cache and a second-level cache, the shared cache includes a third-level cache, the multi-level processor architecture includes multiple processor cores, and each processor core is configured with a dedicated first-level cache and a second-level cache, while the multiple processor cores share the third-level cache.

8. A cache controller, characterized in that, A dedicated cache for a multi-level cache processor architecture, wherein the multi-level cache processor architecture includes a dedicated cache corresponding to each processor core and a shared cache shared by all processor cores, and the cache controller includes: A request sending unit is configured to send an exclusive read request to the shared cache when a write request hits the first data in the dedicated cache; wherein the first data in the dedicated cache is in a shared state, and the exclusive read request is used to request to read the first data in an exclusive state; The data filling unit is used to cancel the operation of sending an eviction request to the shared cache if it receives the second data returned by the shared cache before receiving the first data in the exclusive state returned by the shared cache, and confirms that the first data needs to be evicted when filling the second data into the dedicated cache.

9. A multi-level cache processor architecture, characterized in that, The multi-level cache processor architecture includes dedicated caches for each processor core and a shared cache shared by the processor cores. The multi-level cache processor architecture is configured to implement the data read processing method as described in any one of claims 1 to 7.

10. A computer device, characterized in that, It includes the cache controller as described in claim 8, or the multi-level cache processor architecture as described in claim 9.

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