Method for expanding bus of signal processor

Abstract

The invention belongs to the technical field of expansion of a high-speed data bus of a high-performance OpenVPX signal processor, and discloses a method for expanding a bus of a signal processor. The system comprises a backboard, a function module, a power supply module, an OpenVPX bus, a case, a fan unit and a 100Gbps optical fiber bus, by adding the 100Gbps optical fiber bus for transmission from the front board, the problems of technology, cost and reliability caused by a 25Gbps high-speed electric signal transmission link are avoided, the performance of processors such as a CPU, a DSP and a GPU can be fully played, a high-performance signal processor is quickly put into engineering application, and the system has a wide application prospect. The problem that the weapon equipment technology falls behind due to the fact that the weapon equipment development period lags behind the industrial electronic system period too much is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-performance OpenVPX signal processor high-speed data bus expansion, in particular to a method for expanding the signal processor bus. BACKGROUND

[0002] Radar detects target signals from reflected echoes by transmitting detection signals. The target in the echo is actually mixed in the background of strong clutter, such as cloud and rain, sea wave, weather clutter, tree, hill, building geographical clutter, aluminum foil jamming, etc. The so-called detection is signal processing, which filters out the clutter to find the target and obtain its motion characteristics and motion trajectory through real-time processing algorithm of radar signals. The data volume and calculation volume are very large, and a single processing module cannot meet the requirements of real-time processing of radar signals, and parallel computing of multiple processing modules must be used, which involves data transmission between modules, i.e. the problem of bus bandwidth. At the same time, firstly, hypersonic, strong stealth, low, slow and small targets hidden in clutter, unmanned aerial vehicle swarm and complex electronic jamming technology put forward higher requirements on the detection performance of radar; secondly, the application of new system radars such as digital array radar, multi-pulse aperture radar, MIMO radar and distributed radar makes the data volume of modern radar processing greatly increase; thirdly, the information processing technology is continuously improved, the clutter suppression method is refined, and the use of artificial intelligence technology such as deep learning in the field of radar information processing intensifies the contradiction between calculation speed and bus bandwidth. At present, the signal processor widely used is OpenVPX bus architecture, OpenVPX has three levels of interconnection bus: management plane (Management Plane), the physical layer of which is usually 400K / 100K rate I2C bus, mainly used for hardware monitoring and management in the chassis, such as collection and over-threshold protection of temperature, voltage and current information; control plane (Control Plane), the physical layer of which is a gigabit network SerDes electrical signal bus, mainly used for task allocation, task scheduling and sending control instruction information of system software; data plane (Data Plane), the physical layer of which is usually a high-speed data bus port (Port) bound by four channels (the basic unit of data transmission, Lane), mainly used for transmission of original echo data, data in signal processing process, point track information, video information, etc. The Lane here can be high-speed serial bus ETH, SRIO, PCIe, etc. At present, the OpenVPX signal processor designed and manufactured according to VITA 65-2010 is widely used in engineering, and the channel rate of VPX MultiGig RT2 connector used according to its standard is 10Gbps, i.e. the maximum rate of each port (x4 channel) is 40Gbps.

[0003] Demands such as broadband anti-stealth, drone swarms, and intelligent systems are driving continuous updates to radar technology and architecture. The massive increase in echo data and complex processing methods, coupled with enormous computational demands, place higher demands on the performance of radar signal processors. To meet real-time requirements, radar signal processors must not only possess high computational performance, but also have increased bus transmission bandwidth; the existing 40Gbps rate is no longer sufficient. Although the VITA organization has recently upgraded the OpenVPX specification to VITA 65.1-2021 and upgraded the VPX connector to the 25Gbps MultiGig RT3, the signal transmission of the signal processor involves... Figure One The entire high-speed serial link, as shown, exhibits increasingly prominent impedance discontinuities in 25G links due to connector insertion loss, return loss, crosstalk between signals, chip package fan-out vias, signal line layer-changing vias, connector vias, and signal pads. Sometimes, repeater circuits are necessary, but these not only occupy board space and increase wiring complexity, but also face challenges due to limited market demand and high technical barriers, with no domestically produced 25G chips currently available. Furthermore, the dielectric constant and uniformity of PCB materials, processing technology, and other supporting industrial factors limit its application in military embedded systems to the laboratory or trial stage. Even if it matures and can be used on a large scale in the future, production costs will increase significantly, and incompatibility with existing equipment will hinder upgrades to in-service and production equipment. Therefore, adding a fiber optic bus without altering the original signal processor architecture, increasing the bus bandwidth by over 100Gbps, is a pressing issue that needs to be addressed. Summary of the Invention

[0004] This invention provides a method for expanding the bus of a signal processor, aiming to construct a method that significantly expands the bandwidth of the data transmission bus between signal processor modules in an easily implementable manner. This reduces the requirements for components, materials, and manufacturing processes in a 25G signal transmission link, enabling the production of a new generation of high-performance signal processors at a lower cost without altering the original three-level bus. Furthermore, when upgrading older equipment, performance can be improved simply by replacing modules, requiring little or no modification to the structure, layout, or wiring of the existing equipment.

[0005] To achieve the above objectives, the present invention provides a method for expanding a signal processor bus, comprising the following steps: Step 1: Use a signal processor based on the OpenVPX bus. The signal processor includes a backplane, functional modules, a power supply module, an OpenVPX bus, a chassis, and a fan unit. The functional modules include two data exchange modules and a load module. Step 2: Insert 2 data exchange modules in one chassis, the 2 data exchange modules are the same kind of data exchange module, and 1+1 redundancy design is performed on the 2 data exchange modules to realize 1:1 online backup; No more than 8 load modules and no more than 3 power modules are inserted in one chassis; Step 3: Provide a dual-channel IPMB management interface based on I2C protocol for the power module, and the power module is used to power the load module, the data exchange module and the fan unit; Step 4: The OpenVPX bus transmits electrical signals from the backplane; Step 5: The 100Gbps optical fiber expansion bus transmits electrical signals from the front panel and does not transmit electrical signals from the backplane.

[0006] Further, the backplane is a physical carrier for realizing module interconnection, including 3 power slots and 10 function slots; The 10 function slots of the backplane include 8 processing slots and 2 exchange slots; Each slot of the 8 processing slots leads out 2 channels of 10Gx4 high-speed bus to be interconnected with the 2 exchange slots respectively, and the single-channel rate is 10Gbps; Each slot of the 8 processing slots leads out 2 channels of SGMII gigabit network to be interconnected with the 2 exchange slots respectively; Two-by-two adjacent slots of the 8 processing slots provide 2 channels of PCIe 3.0x4 bus interconnection, and the single-channel rate is 8Gbps; The dual-channel IPMB management interface based on I2C protocol is associated with the 3 power slots and the 10 function slots; external power supply 220V DC input, the power slot leads out DC +12V, 3.3V, 48V power supply, wherein +12V, 3.3V are used to power the function module, and +48V is used to power the cooling DC fan in the fan unit.

[0007] Further, if the power consumption of the modules in the signal processing machine is > the power provided by 2 power modules, then the number of power modules is 3, and 2+1 redundancy design is not performed on the power modules, and the 3 power modules are connected in parallel for power supply; If the power provided by 1 power module is < the power consumption of the modules in the signal processing machine ≤ the power provided by 2 power modules, then the number of power modules is 2 or 3; If the number of power modules is 2, then the 2 power modules are connected in parallel for power supply; If the number of power modules is 3, then 2+1 redundancy design is performed on the power modules to realize 2:1 online backup; If the power consumption of the modules in the signal processing machine is ≤ the power provided by 1 power module, then the number of power modules is 1 or 2; If the number of power modules is 1, then 1 power module is used for power supply; If the number of power modules is 2, the power modules are designed with 1+1 redundancy, realizing 1:1 online backup.

[0008] Further, the load module can be a general computing module, including a main processor, a bus bridge, a 25G optical-electric module, an acceleration processor, a gigabit network controller, a board-level manager; The PCIe bus of the main processor is converted into two 40Gbps SerDes signals of one branch by the bus bridge and sent to the VPX P1 plug, and transmitted to two data exchange modules through the backplane respectively, forming a data plane. The 8x25Gbps SerDes signals of another branch are sent to the 25G optical-electric module and converted into multimode optical signals. The signals of the eight channels can be aggregated into two 100GbE network interfaces or SRIO 4.0 ports and transmitted to two data exchange modules through the MT optical interfaces of the front board respectively, forming an expanded data plane. The data of the data plane and the expanded data plane can be directly transmitted to the main processor for processing, or first sent to the acceleration processor for processing, and then transmitted to the main processor for processing after filtering useless data, including clutter and interference. The PCIe bus of the main processor is converted into two 40Gbps SerDes signals of one branch by the bus bridge and sent to the VPX P1 plug, and transmitted to two data exchange modules through the backplane respectively, forming a data plane. The board-level manager manages the working state of the load module, including chip temperature, working voltage, working current, resource usage, fault condition, and transmits it to the VPX P0 plug through its two I2C buses, and then transmits it to two data exchange modules through the backplane respectively, forming a monitoring plane. The main working power supply of the load module is provided by a 12V DC / DC converter, and the front board uses eight LED indicator lights to indicate the working state. The debugging and maintenance of the load module can be performed through the serial port and network interface of the front board.

[0009] Further, the data exchange module includes a bus switch, a switch manager, a 25G optical-electric module, a gigabit network switch, a manager shared by a chassis manager and a board-level manager. The switch manager sets two bus switches through the PCIe bus or the I2C bus, including initialization, working mode selection, and rate setting. One switching path is 12 40Gpbs ports of the two bus switches. The SerDes electrical signals of the 12 40Gpbs ports are transmitted to the VPX P2-P5 plugs, and data exchange is performed with the load modules on the left and right sides through the backplane, forming a data plane. The SerDes signals of the 8*100Gbps ports of the other exchange channel are transmitted to the 25G optoelectronic module, converted into multimode optical signals, transmitted to the 8 load modules on the left and right sides through the MT optical ports of the front plate respectively to exchange data, forming an extended data plane. The data of the data plane and the extended data plane can be directly exchanged in the bus switch, or the data between two bus switches is exchanged outside the chip. The exchange manager sets the 16-port gigabit network switch through the gigabit network and the SPI bus, including initialization, working mode selection, rate setting, and the SerDes signals of the 12 gigabit networks of the gigabit network switch are transmitted to the VPX P1 plug, respectively through the backplane to the load modules on the left and right sides, forming a control plane. The manager used by the chassis manager and the board-level manager manages the working state of the data exchange module, including chip temperature, working voltage, working current, resource usage, and fault condition. The 2 I2C buses of the manager used by the chassis manager and the board-level manager are transmitted to the VPX P0 plug, respectively through the backplane to the load modules on the left and right sides, and the I2C buses on the load modules are connected in the form of bus nodes, forming a monitoring plane. The main working power supply of the data exchange module is provided by the 12V DC / DC converter, and the front plate uses 8 LED indicator lights to indicate the working state. The debugging and maintenance of the data exchange module can be performed through the serial port and the network port of the front plate.

[0010] Further, the load module in step 1 is a module that meets the OpenVPX specification. The load module can be one or more of a general CPU computing module, a DSP computing module, a GPU computing module, an FPGA computing module, and a record storage module.

[0011] Further, the OpenVPX bus in step 4 is a standard VITA 65-2010 OpenVPX bus, including an intelligent platform management bus IPMB, a task control bus 1GbE gigabit network, and a data bus 40Gbps serial bus.

[0012] Beneficial effects: the application provides a method for expanding the bus of a signal processor, which avoids technical, cost and reliability problems of a 25Gbps high-speed electrical signal transmission link, and can fully exert the performance of a CPU, a DSP, a GPU and other processors, quickly put a high-performance signal processor into engineering application, and solve the problem of backwardness of weapon equipment technology caused by excessive lag of a weapon equipment development cycle relative to an industrial electronic system cycle. The specific beneficial effects include the following four aspects: (1) in a 1+1 redundant working mode, the bandwidth of a data channel is increased from 40Gbps to 140Gbps or more. Without using the redundancy function, the bandwidth is doubled, and in both working modes, the bandwidth is increased to 350% of the original bandwidth, greatly improving the data exchange efficiency and providing hardware support for the application of an algorithm with a large amount of processed data such as artificial intelligence in the system. (2) the application has a higher rate, enables the system to process, track and attack more targets in one cycle, and is faster in response, leaving enough processing time for the system to take measures to ensure victory. (3) the anti-interference and low attenuation characteristics of the optical fiber transmission bus greatly reduce the problem that the error rate of high-speed electrical signal data transmission increases with the rate. (4) for the upgrading and performance improvement of old equipment, the application provides an easy-to-implement and low-cost solution, which has good economic and social benefits. BRIEF DESCRIPTION OF DRAWINGS

[0013] Figure 1 is a high-speed serial link composition diagram related to the prior art; Figure 2 is a signal processor composition diagram related to the embodiment of the application; Figure 3 is a signal processor double-star exchange diagram related to the embodiment of the application; Figure 4 is a signal processor backplane logic interconnection relationship diagram related to the embodiment of the application; Figure 5 is a signal processor system architecture diagram related to the embodiment of the application; Figure 6 is a signal processor box logic interconnection diagram related to the embodiment of the application; Figure 7 is a load module block diagram related to the embodiment of the application; Figure 8 is a data exchange module block diagram related to the embodiment of the application. DETAILED DESCRIPTION Embodiment 1

[0014] Figure 1 is a high-speed serial link composition diagram related to the prior art.

[0015] A method for expanding a signal processor bus, comprising the steps of: Step 1: using a signal processor based on an OpenVPX bus, the signal processor comprising a backplane, a functional module, a power module, an OpenVPX bus, a case, and a fan unit, the functional module comprising two data exchange modules and a load module; Step 2: inserting two data exchange modules into one case, the two data exchange modules being the same kind of data exchange module, and the two data exchange modules being designed in a 1+1 redundancy manner to realize 1:1 online backup; inserting no more than eight load modules and no more than three power modules into one case; Step 3: providing a dual-path IPMB management interface based on an I2C protocol for the power module, the power module being used to supply power to the load module, the data exchange module, and the fan unit; Step 4: transmitting electrical signals from the backplane by the OpenVPX bus; Step 5: transmitting electrical signals from the front panel by a 100Gbps fiber expansion bus, and not transmitting electrical signals from the backplane.

[0016] The signal processor of the embodiment is composed of a load module, a data exchange module, a power module, a backplane, a case, and a fan unit, as shown in Figure 2 The load module can be a general-purpose CPU computing module, a DSP computing module, a GPU computing module, an FPGA computing module, a record storage module, and the like, which are modules conforming to the OpenVPX specification. Up to eight load modules can be inserted, and these modules can be the same kind or different kinds, and the variety and quantity can be configured according to actual needs.

[0017] 2 data exchange modules, which can be common high-speed serial buses, such as ETH exchange modules, SRIO exchange modules, FC exchange modules, PCIe exchange modules, etc. The two data exchange modules can be the same kind of data exchange module or different kinds of data exchange module. In the embodiment, the same kind of data exchange module is adopted. Because in weapon equipment, task reliability is placed in the first place, the purpose of setting two data exchange modules is to perform 1+1 redundancy design, that is, 1:1 online backup. When one exchange channel fails, it is automatically switched to another exchange channel. The main indicators for measuring a data exchange module are the channel (Lane) rate and the port (Port) quantity. Usually, four channels are aggregated into one port, that is, ×4 channels are one port. In the original signal processor running in the improved design of the embodiment, the signal processor runs in the original signal processor running in the improved design of the embodiment, the channel rate is 10Gbps, and the port rate is 4×10Gbps=40Gbps. That is, the commonly used bus rate or bandwidth is 40Gbps. Note that this is the indicator after the redundancy design. When the redundancy function is not required, the two data exchange modules work in parallel, and the total bandwidth is 80Gbps. The redundancy design is not necessary. In the case where the requirement is not high, only one data exchange module can be used. The embodiment is based on 1+1 redundancy design.

[0018] The power module is mainly used for power supply of the computing module, the exchange module and the fan unit in the signal processor. The +12V therein is the main power supply for the function module, the +3.3V is the auxiliary power supply for management, and the +48V is the power supply for the cooling DC fan in the fan unit. The power module provides a double IPMB (I2C) management interface. Up to three power modules can be inserted into one case. In order to improve the task reliability, 2+1 redundancy design is performed. When the power consumption of the module inserted into the signal processor is greater than the power provided by two power supplies, the 2+1 redundancy design can be cancelled, and the three power modules are connected in parallel for power supply. The power supply system has current sharing function. When the power consumption of the module inserted into the signal processor is relatively small or the number of modules is small, one power module is sufficient to provide the required power, and two power modules can be inserted for 1+1 redundancy design.

[0019] In the signal processor, a star interconnection mode is adopted between the modules. The positions of the modules are equal, the communication mode is consistent, and the communication delay is basically consistent, so that the expansion in the case is easy to realize. For the demand of higher performance application system, system expansion can be realized based on the interconnection of the exchange modules between the cases. Figure 3 is a double-star exchange diagram of the signal processor related to the embodiment of the application, Figure 3The middle data bus 1 and the data bus 2 are point-to-point serial buses, the two buses are completely consistent and equal in status, and they include a 1GbE SerDes, a 40GbE or a 40Gbps SRIO 3.0 or other 40Gbps SreDes serial bus electrical signal, and also include a 100Gbps optical fiber signal expanded by the application.

[0020] By Figure 3 It can be known that the interconnection of the modules adopts a star interconnection architecture based on the OpenVPX specification, according to power supply, management and application requirements, the system logical architecture is divided into a utility plane, a management plane, a control plane, a data plane and an expansion plane (the plane refers to a physical and logical channel for interconnection between devices) according to the design idea of OpenVPX, and the logical interconnection relationship of the backboard is as shown in Figure 4 The backboard contains three power slots (XSP1-XSP3) and ten function slots (including eight processing slots and two switching slots, XS1-XS10); each slot of the processing slots 1-8 leads out two 10Gx4 high-speed buses to be interconnected with the switching slots 1 and 2 respectively, and the single-channel rate is 10Gbps; each slot of the processing slots 1-8 leads out two SGMII gigabit networks to be interconnected with the switching slots 1 and 2 respectively; two PCIe 3.0x4 buses are provided between every two adjacent slots of the processing slots 1-8 to be interconnected, and the single-channel rate is 8Gbps; two IPMB management interfaces based on the I2C protocol are connected to three power slots and ten function slots; an external 220V DC power supply is input, and the power slots lead out DC +12V, 3.3V and 48V power supplies, in which the +12V and 3.3V are used to supply power to the function modules, and the +48V is used to supply power to the cooling DC fan in the fan unit; as shown in the monitoring plane in Figure 4 .

[0021] Figure 5 The signal processing machine system architecture diagram of the embodiment is shown in Figure Five The three buses below are an intelligent platform management bus IPMB, a task control bus 1GbE gigabit network and a data bus 40Gbps serial bus, which are standard VITA 65-2010 OpenVPX buses and are electrical signals from the backboard. The embodiment increases a 100Gbps optical fiber bus transmitted from the front board, i.e.

[0022] Figure 6The signal processing machine box logical interconnection diagram involved in the embodiment of the present application is described as follows: (1) Basic plane: the basic plane provides the most basic services for the system, including system power supply, system reference clock, system reset, system test signal and the like.

[0023] (2) Management plane: the management plane is used for organizing and managing hardware resources based on the IPMI standard, and is mainly composed of a ChMC (chassis management controller) and an IPMC.

[0024] (3) Control plane: according to the requirements of the OpenVPX standard, the control plane needs to use a low-delay, medium-bandwidth, packet-based communication mode. OpenVPX distinguishes control traffic and data traffic, ensures the bandwidth of each channel, and the conflict of one channel does not affect the other channel.

[0025] The control plane gigabit Ethernet of the signal processing machine is used to carry service application management and control data, and adopts a double-star gigabit Ethernet topology architecture.

[0026] (4) Data plane: according to the requirements of the OpenVPX standard, the data plane is responsible for constructing a set of high-bandwidth, low-delay data channels between boards and backplanes, and is used to carry service data such as echo data and intermediate processing process data. The communication protocols of the physical layer, the logical layer and the network layer are all applied to the data plane.

[0027] In the embodiment, a ×4 high-speed serial bus data plane is reserved to transmit inter-module service data. The ×4 high-speed serial bus data plane can be a 40GbE network, a 40Gbps SRIO 3.0, a single-channel 8.5Gbps FC or the like different interface protocol.

[0028] (5) Extension plane: the extension plane realizes the interconnection between a module and two adjacent modules. Like the data plane, the extension plane needs to use a low-delay, high-bandwidth channel to support its communication. The single functional module of the signal processing machine supports three modes of outputting one group of PCIe (4.0 and above, compatible with 3.0 / 2.0 / 1.0, the same below) ×16 or two groups of PCIe ×8 or four groups of PCIe ×4. The functional modules are interconnected by point-to-point between the PCIe bus and the adjacent modules.

[0029] (6) Extended data plane: in the embodiment, on the basis of the above several planes, the data between the modules is interconnected by the MT optical fiber of the VPX front plug-in module. Like the SerDes electrical signal on the backplane, it is still point-to-point transmission from the load module to the switching module, and still satisfies Figure 3The dual-star switching architecture of the application, but the physical medium of transmission becomes optical fiber, single-channel rate 25Gbps, and the signal processor adds a high-speed serial bus of ×4 100Gbps to transmit the service data of the data plane.

[0030] Figure 7 The load module block diagram involved in the embodiment of the application. The main processor FT-D2000 is the working core of the whole board, and its PCIe bus is converted into 2 SerDes signals of 40Gbps (4×10 Gbps) of a branch through the bus bridge SDI4820 and sent to the VPX P1 plug, respectively through the backplane to 2 data exchange modules, which are the aforementioned data plane; 8 SerDes signals of 25Gbps of another branch are sent to the 25G optical module HTG8532B and converted into multimode optical signals, and the signals of the 8 channels can be aggregated into 2 network interfaces of 100GbE or ports of SRIO 4.0 and sent to 2 data exchange modules through the MT optical port of the front board, which are the aforementioned extended data plane. The data of the data plane and the extended data plane can be directly sent to the main processor or first sent to the acceleration processor XCVU9P for processing, and after filtering some useless data such as noise and interference, the data is sent to the main processor for further processing. The PCIe bus of the main processor is converted into 2 SerDes signals of 1000M network through the 1000M network controller WX1860 and sent to the VPX P4 plug, respectively through the backplane to 2 data exchange modules, which are the aforementioned control plane. The working state of the whole board such as the main chip temperature, various working voltages, currents, resource usage, fault conditions is managed by the board-level manager (BMC) HM32F407, and its 2 I2C buses are sent to the VPX P0 plug, respectively through the backplane to 2 data exchange modules, which are the aforementioned monitoring plane. The main working power supply of the whole board is provided by the 12V DC / DC converter, and the front board uses 8 LED indicator lights to indicate the working state, and the debugging and maintenance of the load module can be carried out through the serial port and network port of the front board.

[0031] Figure 8Figure 1 is a block diagram of a data exchange module according to an embodiment of the present application. Bus switches SDI4820 #1, #2 are the working cores of the entire board, and the switch manager FMQL45T900 initializes, selects the working mode, sets the rate, etc. of the bus switches through a PCIe bus or an I2C bus. One switching path is 12 40Gpbs ports of the bus switches #1, #2, and the SerDes electrical signals of the ports are sent to the VPX P2-P5 plugs to exchange data with the load modules on the left and right sides through the backplane. The number of ports actually used and the number of load modules that can exchange data can be increased or decreased as needed, which is the aforementioned data plane. The SerDes signals of the other switching path of the 8x100Gbps ports are sent to the 25G optical-electric module HTG8532B to convert into multimode optical signals, which are sent to the MT optical ports of the front board to exchange data with the 8 load modules on the left and right sides, respectively. The number of load modules actually used for data exchange can be increased or decreased as needed, which is the aforementioned extended data plane. The data of the data plane and the extended data plane can be directly exchanged in the bus switches, and the data between the two bus switches can also be exchanged outside the chip. The switch manager controls the 16-port gigabit network switch BCM5396 through a gigabit network and an SPI bus to initialize, select the working mode, set the rate, etc. The SerDes signals of the 12 gigabit networks of the gigabit network switch are sent to the VPX P1 plug to be sent to the load modules on the left and right sides through the backplane, 8 of which are used for load modules in the present application, 2 of which are used for interconnection of the switch modules, and 2 of which are used for system expansion, which is the aforementioned control plane. The data exchange module has a manager FMQL10S400 that is used for chassis management (ChMC) and board-level management (BMC). The working status of the entire board such as the main chip temperature, various working voltages, currents, resource usage, and fault conditions is managed by the board-level manager. The 2 I2C buses of the manager are sent to the VPX P0 plug to be sent to the load modules on the left and right sides through the backplane. The I2C buses on the load modules are connected in the form of bus nodes, which is the aforementioned monitoring plane. The main working power supply of the entire board is provided by a 12V DC / DC converter, and the front board uses 8 LED indicator lights to indicate the working status. The debugging and maintenance of the data exchange module can be performed through the serial port and the network port of the front board.

[0032] The present application provides a method for expanding the signal processor bus, which avoids the technical, cost, and reliability problems of the 25Gbps high-speed electrical signal transmission link. By using the method, the performance of the CPU, DSP, GPU, and other processors can be fully utilized, and the high-performance signal processor can be quickly put into engineering application to solve the problem of the backwardness of weapon equipment technology caused by the excessive lag of the weapon equipment development cycle compared with the industrial electronic system cycle.

[0033] Finally, it should be noted that the above is only the preferred embodiment of the present application, and is not intended to limit the present application, although the embodiments are described in detail with reference to the present application, for those skilled in the art, the technical solutions recorded in the foregoing embodiments can be modified, or some technical features can be replaced, but any modification, equivalent replacement, improvement, etc. within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method of augmenting a signal processor bus, characterized by, The method comprises the following steps: Step 1: using a signal processing machine based on an OpenVPX bus, the signal processing machine comprising a backplane, functional modules, power supply modules, an OpenVPX bus, a case, and a fan unit, the functional modules comprising two data exchange modules and load modules; Step 2: inserting two data exchange modules into one case, the two data exchange modules being the same type of data exchange module, and performing 1+1 redundancy design on the two data exchange modules to realize 1:1 online backup; inserting no more than eight load modules and no more than three power supply modules into one case; Step 3: providing a dual-channel IPMB management interface based on an I2C protocol for the power supply modules, and using the power supply modules to supply power to the load modules, the data exchange modules, and the fan unit; Step 4: transmitting electrical signals from the backplane through the OpenVPX bus; Step 5: transmitting electrical signals from the front panel through a 100Gbps fiber expansion bus, and not transmitting electrical signals from the backplane.

2. The method of augmenting a signal processor bus of claim 1, wherein, The backplane is a physical carrier for realizing interconnection of the modules, and comprises three power supply slots and ten functional slots; The ten functional slots of the backplane comprise eight processing slots and two exchange slots; Each slot of the eight processing slots draws out two channels of 10Gx4 high-speed buses to be connected with the two exchange slots respectively, and the single-channel rate is 10Gbps; Each slot of the eight processing slots draws out two channels of SGMII gigabit networks to be connected with the two exchange slots respectively; Two-way PCIe 3.0x4 buses are provided between every two adjacent slots of the eight processing slots to realize interconnection, and the single-channel rate is 8Gbps; The dual-channel IPMB management interface based on the I2C protocol is associated with the three power supply slots and the ten functional slots; external 220V DC power supply is input, and the power supply slots draw out DC +12V, 3.3V, and 48V power supplies, wherein the +12V and 3.3V power supplies are used to supply power to the functional modules, and the +48V power supply is used to supply power to the cooling DC fans in the fan unit.

3. The method of claim 1, wherein if the power consumption of the modules in the signal processing machine is greater than the power that can be provided by two power supply modules, the number of power supply modules is three, no 2+1 redundancy design is performed, and the three power supply modules are connected in parallel to supply power; if the power that can be provided by one power supply module is less than the power consumption of the modules in the signal processing machine and is less than or equal to the power that can be provided by two power supply modules, the number of power supply modules is two or three; if the number of power supply modules is two, the two power supply modules are connected in parallel to supply power; if the number of power supply modules is three, 2+1 redundancy design is performed on the power supply modules to realize 2:1 online backup; if the power consumption of the modules in the signal processing machine is less than or equal to the power that can be provided by one power supply module, the number of power supply modules is one or two; if the number of power supply modules is one, one power supply module supplies power; if the number of power supply modules is two, 1+1 redundancy design is performed on the power supply modules to realize 1:1 online backup.

4. The method of augmenting a signal processor bus of claim 1, wherein, The load modules can be general-purpose computing modules, and comprise a main processor, a bus bridge, a 25G optical-electric module, an acceleration processor, a gigabit network controller, and a board-level manager. PCIe bus of main processor is converted into 2 40Gbps SerDes signals by bus bridge, and is sent to VPX P1 plug, and is transmitted to 2 data exchange modules through backplane respectively, and forms data plane; 8 25Gbps SerDes signals of another branch are sent to 25G optoelectronic module, are converted into multimode optical signals, the signals of the 8 channels can be aggregated into 2 100GbE network interfaces or SRIO 4.0 ports, and are transmitted to 2 data exchange modules through MT optical interfaces of front board respectively, and form extended data plane; Data of data plane and extended data plane can be directly transmitted to main processor for processing, or is transmitted to main processor for processing after being processed by acceleration processor and filtering useless data, and the useless data includes clutter and interference; PCIe bus of main processor is converted into 2 1000M network SerDes signals by 1000M network controller, and is sent to VPX P4 plug, and is transmitted to 2 data exchange modules through backplane respectively, and forms control plane; Board-level manager manages working states of load module, including chip temperature, working voltage, working current, resource usage, fault condition, and the working states are transmitted to VPX P0 plug through 2 I2C buses, and are transmitted to 2 data exchange modules through backplane respectively, and form monitoring plane; Main working power supply of load module is provided by 12V DC / DC converter, and 8 LED indicator lamps of front board indicate working states, and debugging and maintenance of load module can be carried out through serial port and network interface of front board.

5. The method of augmenting a signal processor bus of claim 1, wherein, Data exchange module includes bus switch, exchange manager, 25G optoelectronic module, 1000M network switch, one manager shared by chassis manager and board-level manager; Exchange manager sets 2 bus switches through PCIe bus or I2C bus, including initialization, working mode selection and rate setting, one exchange channel is 12 40Gpbs ports of 2 bus switches, and SerDes electrical signals of 12 40Gpbs ports are transmitted to VPX P2-P5 plugs, data exchange is carried out through backplane and load modules on left and right sides, and data plane is formed; SerDes signals of 8 100Gbps ports of another exchange channel are transmitted to 25G optoelectronic module, are converted into multimode optical signals, and are transmitted to 8 load modules on left and right sides through MT optical interfaces of front board respectively, and data exchange is carried out, and extended data plane is formed; Data of data plane and extended data plane can be directly exchanged in bus switch, or data between two bus switches is exchanged outside the chip; Exchange manager sets 16 1000M network switches through 1000M network and SPI bus, including initialization, working mode selection and rate setting, SerDes signals of 12 1000M network switches of 1000M network switch are transmitted to VPX P1 plug, and are transmitted to load modules on left and right sides through backplane respectively, and control plane is formed; The chassis manager and the board-level manager combined manager manages the working state of the data exchange module, including chip temperature, working voltage, working current, resource usage, and fault condition. The two I2C buses of the chassis manager and the board-level manager combined manager are transmitted to the VPX P0 plug, and are respectively transmitted to the left and right load modules through the backplane. The I2C buses on the load modules are connected in the form of I2C bus nodes, and a monitoring plane is formed. The main working power supply of the data exchange module is provided by a 12V DC / DC converter, and the front plate is provided with eight LED indicator lamps to indicate the working state. The debugging and maintenance of the data exchange module can be performed through the serial port and the network port of the front plate.

6. The method of augmenting a signal processor bus of claim 1, wherein, The load module in step 1 is a module conforming to the OpenVPX specification. The load module can be one or more of a general CPU computing module, a DSP computing module, a GPU computing module, an FPGA computing module, and a record storage module.

7. The method of augmenting a signal processor bus of claim 1, wherein, The OpenVPX bus in step 4 is a standard VITA 65-2010 OpenVPX bus, including an intelligent platform management bus IPMB, a task control bus 1GbE gigabit network, and a data bus 40Gbps serial bus.

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