Chip digital twin construction, electrical parameter value prediction method and device, medium and electronic equipment

Abstract

The application provides a chip digital twin construction method and device, an electrical parameter value prediction method and device, a medium and an electronic equipment. The method comprises the following steps: performing physical simulation based on an ideal process flow of a standard design parameter provided with a target chip to obtain a physical prediction model; constructing a residual correction model based on actual measurement data; and obtaining the digital twin of the target chip based on the physical prediction model and the residual correction model. The physical prediction model constructed through physical simulation provides an interpretable physical mechanism basis, and the residual correction model constructed based on a real data training set accurately compensates for nonlinear errors. The machine learning model only needs to focus on learning the low-order simple mapping of process deviation, which significantly reduces the model construction complexity and improves the prediction accuracy of the chip digital twin.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of digital twinning, and relates to a chip digital twinning construction method and an electrical parameter value prediction method and device, medium and electronic equipment. BACKGROUND

[0002] In the field of semiconductor manufacturing, there are divergent technical paths for constructing high-precision individualized digital twins for each chip. Existing technologies mainly rely on two schemes: one is based on physical simulation, and a fine device model is established through a technical computer-aided design (TCAD) tool. This scheme requires input of hundreds of process parameters (such as ion implantation dose, gate oxide layer thickness), solving of semiconductor physical equations such as Poisson equation and carrier continuity equation, and simulation of transistor three-dimensional structure and electrical characteristics. However, this path has significant defects: single transistor simulation requires high-performance servers to run for several hours, and the calculation cost and timeliness cannot meet the industrialization requirements of the production line which needs to process millions of chips per day; at the same time, the simulation model cannot completely cover complex physical phenomena such as microscopic stress changes and interface quantum effects, resulting in systematic deviation between predicted values and measured values, forming a "simulation-reality gap".

[0003] The second scheme is a pure machine learning scheme, which collects massive data of the manufacturing process and the final test yield to train an end-to-end neural network model. This path improves the calculation efficiency, but has fundamental limitations: the model presents "black box" characteristics, and the failure mechanism (such as lithography registration error or implantation energy deviation) cannot be explained, making it difficult for technical personnel to trust the results and guide process optimization; and the deep learning model requires massive high-quality labeled data support, and the cost of obtaining wafer-level comprehensive electrical test data is high; more importantly, the model has weak generalization ability, and once the process changes or new defect patterns appear, the prediction performance will decline sharply.

[0004] Therefore, those skilled in the art are in a dilemma - physical simulation is difficult to be applied to mass production due to low calculation efficiency and inherent deviation, and pure machine learning cannot meet the reliability requirements due to lack of explainability and data dependency. SUMMARY

[0005] The application provides a chip digital twinning construction method and an electrical parameter value prediction method and device, medium and electronic equipment, which compensate for the limitations of theoretical models through real data, realize the unification of high-precision prediction and mass production feasibility.

[0006] In a first aspect, a method for constructing a chip digital twin is provided. The method comprises: performing physical simulation based on an ideal process flow of a standard design parameter of a target chip to obtain a physical prediction model; collecting actual values of process parameters and electrical measurement values of a plurality of sample chips of the target chip in a manufacturing process to form a training set; calculating deviations of the actual values of the process parameters of each sample chip in the training set from preset ideal values of the process parameters to generate a process deviation vector; inputting the process deviation vector into the physical prediction model to obtain an electrical parameter prediction value; calculating a prediction residual based on the electrical parameter prediction value and the actual electrical measurement value; taking the process deviation vector of each sample chip in the training set as an input feature and the prediction residual as an output label to generate a residual correction model; and obtaining the digital twin of the target chip based on the physical prediction model and the residual correction model.

[0007] In an implementation form of the first aspect, the physical prediction model is constructed by physical simulation based on the standard design parameter of the target chip and the ideal process flow, comprising: generating reference electrical parameter values of the target chip under different process parameters by physical simulation based on the standard design parameter of the target chip and the ideal process flow; integrating all the reference electrical parameter values to construct a baseline physical sub-model of the target chip; in the baseline physical sub-model, applying an independent process parameter disturbance to each of the process parameters; calculating an electrical parameter variation caused by the process parameter disturbance; calculating an influence gradient value of each of the process parameters based on a ratio of an amplitude of the process parameter disturbance to a corresponding electrical parameter variation; constructing a process disturbance gradient library of the target chip based on the influence gradient values of all the process parameters; and constructing the physical prediction model of the target chip based on the baseline physical sub-model and the process disturbance gradient library.

[0008] In an implementation form of the first aspect, the residual correction model is generated by taking the process deviation vector of each sample chip in the training set as an input feature and the prediction residual as an output label, comprising: selecting a gradient boosting decision tree or a feedforward neural network as a training algorithm and defining a residual correction model architecture; using the selected algorithm to iteratively train the residual correction model architecture with the process deviation vector as an input feature and the prediction residual as an output label until convergence, thereby generating the residual correction model.

[0009] In a second aspect, the application provides a method for predicting an electrical parameter value of a chip, comprising: obtaining a process parameter measured value of a target chip in a manufacturing process; calculating a deviation between the process parameter measured value and a preset ideal value to generate a process deviation vector; inputting the process deviation vector into a preset physical prediction model and a preset residual correction model in parallel to respectively output an electrical parameter physical prediction value and a prediction residual correction value; performing linear summation on the electrical parameter physical prediction value and the prediction residual correction value to generate a final electrical parameter value of the target chip.

[0010] In an implementation form of the second aspect, the method further comprises: presetting a normal threshold value of the final electrical parameter value under each process parameter respectively; and issuing an abnormal early warning when the final electrical parameter value exceeds the corresponding normal threshold value.

[0011] In an implementation form of the second aspect, the method further comprises: dividing the target chip into predefined performance levels based on a numerical interval of the final electrical parameter value.

[0012] In a third aspect, the application provides a device for constructing a chip digital twin, comprising: a physical prediction model construction module, configured to perform physical simulation based on an ideal process flow of a standard design parameter of a target chip to obtain a physical prediction model; a residual correction model construction module, configured to collect process parameter actual values and electrical measurement values of a plurality of sample chips of the target chip in a manufacturing process to form a training set; further configured to calculate a deviation between the process parameter actual values and preset process parameter ideal values of each sample chip in the training set to generate a process deviation vector; further configured to input the process deviation vector into the physical prediction model to obtain an electrical parameter prediction value; further configured to calculate a prediction residual based on the electrical parameter prediction value and the real electrical measurement value; further configured to generate a residual correction model with the process deviation vector of each sample chip in the training set as an input feature and the prediction residual as an output label; and a combination module, configured to obtain a digital twin of the target chip based on the physical prediction model and the residual correction model.

[0013] In a fourth aspect, the application provides a device for predicting an electrical parameter value of a chip, comprising: an obtaining module, configured to obtain a process parameter measured value of a target chip in a manufacturing process; a calculating module, configured to calculate a deviation between the process parameter measured value and a preset ideal value to generate a process deviation vector; a generating module, configured to input the process deviation vector into a preset physical prediction model and a preset residual correction model in parallel to respectively output an electrical parameter physical prediction value and a prediction residual correction value; and a summation module, configured to perform linear summation on the electrical parameter physical prediction value and the prediction residual correction value to generate a final electrical parameter value of the target chip.

[0014] In a fifth aspect, the present application provides an electronic device, comprising: one or more processors; and one or more memories, wherein the memories have computer readable codes stored therein, which, when executed by the one or more processors, implement the method for constructing a chip digital twin or the method for predicting a chip electrical parameter value as described above.

[0015] In a sixth aspect, the present application provides a computer readable storage medium, having a computer program stored thereon, which, when executed by a processor, implements the method for constructing a chip digital twin or the method for predicting a chip electrical parameter value as described above.

[0016] As described above, the method for constructing a chip digital twin, the method for predicting an electrical parameter value, the device, the medium and the electronic device of the present disclosure have the following technical effects:

[0017] (1) The physical prediction model constructed through physical simulation provides an interpretable physical mechanism basis, and the residual correction model constructed based on a real data training set accurately compensates for nonlinear errors; this architecture enables the machine learning model to only focus on learning a low-level simple mapping of process deviations, significantly reduces the model construction complexity, and improves the prediction accuracy of the chip digital twin.

[0018] (2) The baseline physical sub-model is anchored to the reference performance, and the parameter sensitivity is quantified in combination with the process disturbance gradient library; independent disturbance ensures the accuracy of the gradient, and linear superposition calculation achieves millisecond-level response. High-cost simulation is converted into a reusable lookup table, breaking through the efficiency bottleneck and providing a physically interpretable and efficient prediction core for production-level digital twins.

[0019] (3) Through a lightweight algorithm (gradient boosting decision tree / forward neural network) and an iterative training architecture, focus on low-level residual mapping learning. Significantly reduce model complexity and data requirements, efficiently compensate for nonlinear errors not covered by the physical model, improve the prediction accuracy of the digital twin, and ensure the feasibility of real-time deployment in industrial scenarios.

[0020] (4) Through the parallel collaborative architecture of the physical prediction model and the residual correction model, high-fidelity electrical parameter value prediction is achieved. The physical model provides an interpretable linear mechanism basis, and the residual model accurately compensates for nonlinear errors; parallel input and linear summation improve response efficiency. The predicted value has both physical traceability and measured data accuracy, providing core support for individual chip performance characterization.

[0021] (5) Trigger abnormal early warning through pre-set specification range, realize real-time quality interception in manufacturing process; at the same time, divide the performance level according to the numerical interval, so that different levels of chips can accurately adapt to the corresponding terminal application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0022] Figure 1 An exemplary application scenario of the method for constructing the chip digital twin is shown.

[0023] Figure 2 A flowchart of the method for constructing the chip digital twin is shown.

[0024] Figure 3 An exemplary flowchart of the method for constructing the physical prediction model is shown.

[0025] Figure 4 A flowchart of the method for predicting the chip electrical parameter value is shown.

[0026] Figure 5 A structural diagram of the device for constructing the chip digital twin is shown.

[0027] Figure 6 A structural diagram of the device for predicting the chip electrical parameter value is shown.

[0028] Figure 7 An exemplary structural diagram of the electronic device is shown. DETAILED DESCRIPTION

[0029] The present application is described in detail below with specific reference being made to certain embodiments. It is to be understood that the following examples are merely illustrative of the present application and that other advantages and benefits will be apparent in view of the following detailed description. The present application can be implemented or applied in other different embodiments and the details in the present description can be modified or changed based on different views and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0030] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present application, and the diagrams only show the components related to the present application, not the number, shape and size of the components when actually implemented. The actual implementation of each component may be randomly changed in terms of type, number and proportion, and the component layout type may also be more complex.

[0031] Personalized digital twins refer to establishing a dedicated virtual model for each traceable physical chip on the production line. This model accurately reflects the individual performance differences of the chip due to its unique manufacturing process. This model is not a general-purpose chip model, but follows the principle of "one chip, one model," achieving independent digital mapping for a single chip. Current technological advancements face a significant dilemma: while physical simulation methods have a certain mechanistic basis, they often suffer from high computational resource consumption, high time costs, and deviations from actual measurement results; while pure machine learning methods, although possessing data processing capabilities, are limited in their application for accurate prediction due to their black-box nature and over-reliance on data quality and scale. Therefore, this disclosure provides a technical solution that can both deduce based on clear physical mechanisms and achieve high computational efficiency by combining machine learning methods. Furthermore, it can introduce real measurement data to correct inherent biases in theoretical models, thereby achieving a synergy of high precision and high efficiency within a unified framework.

[0032] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0033] like Figure 1 As shown, it illustrates an application scenario of this application. The construction scenario of the chip digital twin includes: a physical simulation module 110, a real data acquisition module 120, and a construction module 130.

[0034] The physical simulation module 110 is based on the physical principles of semiconductor devices and constructs a physical prediction model of the target chip using technical computer-aided design (TCAD) tools. Specifically, it inputs standard design parameters and an ideal process flow, solves the Poisson equation and the carrier continuity equation to simulate the electrical characteristics of the device, and generates baseline electrical parameter values. It then applies independent micro-perturbations to key process parameters and calculates the changes in electrical parameters, generating influence gradient values ​​and forming a process perturbation gradient library. This transforms high-cost physical simulation into a reusable pre-computation model, providing a physically interpretable predictive framework for the digital twin.

[0035] The real data acquisition module 120 acquires the actual values ​​of key process parameters in chip manufacturing through online measurement equipment on the production line, calculates the deviation between the parameters and the ideal values ​​to generate a structured process deviation vector, and simultaneously performs electrical tests on the sample chip through a wafer probe station to obtain real electrical measurement values. This constructs a data bridge connecting physical simulation and real manufacturing, forming the process-performance mapping pair required for training the residual correction model.

[0036] The construction module 130 works in conjunction with the above model to generate an individualized digital twin.

[0037] Firstly, such as Figure 2As shown, the embodiment of the present application provides a chip digital twin construction method, including the following steps S210-S270.

[0038] S210, physical simulation is performed based on an ideal process flow of a standard design parameter of a target chip to obtain a physical prediction model.

[0039] Specifically, by inputting the standard design parameter of the target chip and the ideal process flow parameter into a semiconductor device physical simulation tool (including but not limited to Synopsys, Cadence and Siemens), the Poisson equation, the carrier continuity equation and the quantum mechanics correction equation are solved, the three-dimensional electrical characteristics of the device under ideal conditions are simulated, the reference electrical parameter value is output by running the simulation, and the physical prediction model is constructed based thereon. The physical prediction model is used to predict the reference electrical performance of the target chip under ideal process conditions, and provides an interpretable physical basis for subsequent process deviation impact analysis.

[0040] In an embodiment of the present application, as shown, Figure 3 the physical prediction model is constructed in a "gradient library" manner, including the following steps S211-S217.

[0041] S211, based on the standard design parameter of the target chip and the ideal process flow, the reference electrical parameter value of the target chip under different process parameters is generated by physical simulation.

[0042] Specifically, at least 5 discrete points in the ideal value ± 20% range of the key process parameters are selected for independent scanning; the Poisson equation and the carrier continuity equation are solved by running TCAD simulation at each parameter point, the threshold voltage, the saturation drain current, the sub-threshold swing and the off-state drain current are output, and the mapping relationship between the parameter combination and the corresponding reference value is structured and stored.

[0043] Exemplarily, the process parameters include one or more combinations of gate oxide layer thickness, ion implantation dose, gate length, gate width and shallow trench isolation depth.

[0044] S212, all reference electrical parameter values are integrated to construct a baseline physical sub-model of the target chip.

[0045] Specifically, a mapping function from continuous parameter space to electrical parameters (such as Vth_base = f_interp(Tox, Lg, Dose)) is generated by three-dimensional spline interpolation, and the function is encapsulated as a callable module to realize the function of inputting standard process parameter values and outputting reference electrical parameter vectors.

[0046] S213, in the baseline physical sub-model, an independent process parameter perturbation is applied to each of the process parameters.

[0047] Specifically, after selecting the target parameter, other parameters are fixed as ideal values, and a symmetric perturbation ±δ (δ value is 1% of the ideal value) is applied to ensure that the perturbation between parameters is not coupled.

[0048] S214, calculate the amount of change of the electrical parameter caused by the process parameter perturbation.

[0049] S215, based on the ratio of the amplitude of the process parameter perturbation to the corresponding electrical parameter change, calculate the influence gradient value of each process parameter.

[0050] Specifically, by the way of gradient = Δperformance / Δparameter, the gradient of each process parameter to the electrical parameter is calculated, and the influence intensity of the unit process deviation is quantified.

[0051] S216, based on the influence gradient value of all process parameters, construct the process perturbation gradient library of the target chip.

[0052] Specifically, the mapping relationship between (process parameter, electrical parameter) combination and gradient value is stored by using hash table data structure, that is, the gradient library is formed.

[0053] S217, based on the baseline physical sub-model and the process perturbation gradient library, construct the physical prediction model of the target chip.

[0054] Specifically, when constructing the physical prediction model of the target chip, based on the reference electrical parameter value output by the baseline physical sub-model and the influence gradient value stored in the process perturbation gradient library, the core calculation rule of the physical prediction model is defined as the electrical parameter prediction value is equal to the sum of the reference value and all process deviations multiplied by the corresponding influence gradient value, that is, it satisfies the mathematical relationship: M_predict = M_base + Σ(Gradient_jk × ΔP_j), wherein Σ represents the summation operation of all key process parameters j.

[0055] The process deviation vector is taken as the input, wherein ΔP_j represents the deviation amount of the actual value of the jth process parameter from the ideal value; the baseline physical sub-model is called to input the standard process parameter value and output the reference electrical parameter value M_base; according to the parameter index in the process deviation vector and the target electrical parameter type, the corresponding influence gradient value is queried from the process perturbation gradient library; the product accumulation operation is performed according to the above mathematical relationship to generate the electrical parameter prediction value; the calculation process is packaged as a callable function module to realize the core function of inputting the process deviation vector and outputting the electrical parameter prediction value.

[0056] It should be particularly pointed out that the construction of the process disturbance gradient library involves multiple TCAD simulation calculations, but it is a one-time pre-completion operation, and the resulting cost can be shared by the subsequent mass chips.

[0057] In the present implementation, millisecond-level efficient prediction is achieved through pre-computed gradient library and linear algorithm, while the physical interpretability of the influence of process parameter variation on electrical performance is preserved.

[0058] In some embodiments, to improve the capture ability of the physical prediction model for nonlinear effects, the construction method of the physical prediction model can be extended by quadratic polynomial fitting.

[0059] Specifically, after generating the process disturbance gradient library, an enhanced prediction model containing a second-order term is further constructed based on the TCAD simulation dataset: first, a synergistic disturbance is applied to the key process parameter combination (such as gate oxide layer thickness Tox and gate length Lg), that is, multiple parameters (such as Tox±σ and Lg±σ) are disturbed simultaneously in the baseline physical sub-model; the parameter interaction data (such as ΔVth(Tox±σ, Lg±σ)) are obtained by simulating the change in electrical parameters. Subsequently, a least squares method is used to fit a quadratic polynomial response surface model, and the mathematical expression is:

[0060] M_predict = M_base +∑(Gradient_j×ΔP_j) + ∑∑(Hessian_jk ×ΔP_j×ΔP_k)

[0061] Where Hessian_jk is the second-order partial derivative ( ), representing the nonlinear coupling effect between parameters. Implementation includes:

[0062] At least 9 discrete points (including center points and axial points) are selected in the process parameter space, and TCAD simulation is performed to obtain electrical parameter values; the dataset is substituted into the quadratic polynomial equation, and the gradient vector (first-order coefficient) and Hessian matrix (second-order coefficient) are solved by matrix operation; the gradient vector and Hessian matrix are stored in the extended gradient library, and the key is (parameter combination, electrical parameter) pair (such as (Tox-Lg, Vth)); after inputting the process deviation vector, the calculation is performed according to the polynomial equation, and the prediction value containing nonlinear effects is output.

[0063] In the present implementation, by introducing a second-order interaction term, the synergistic effect between process parameters can be accurately represented, improving the accuracy of linear model prediction, especially for performance prediction of strong quantum confinement devices such as FinFET.

[0064] S220, collect the actual values of the process parameters and electrical measurement values of the plurality of sample chips of the target chip in the manufacturing process to form a training set.

[0065] Specifically, in the process of collecting training data of multiple sample chips of the target chip, the actual values of the process parameters are obtained by coordinating the line manufacturing execution system (MES) and the online measurement equipment: first, the key process layers of the sample chips are measured non-destructively by using an optical critical dimension measuring instrument (OCD) or a scanning electron microscope (SEM) in the manufacturing process to obtain the actual values of the gate oxide layer thickness, ion implantation dose, gate length, gate width, and shallow trench isolation depth; then, the deviation amount of each process parameter actual value from the preset ideal value is calculated to generate a structured process deviation vector. At the same time, the same sample chip is subjected to electrical testing by a wafer probing station: real electrical parameter values such as threshold voltage, saturation drain current, sub-threshold swing, and off-state leakage current are measured under a preset bias condition (such as Vds=0.05V / Vgs scanning 0-1V) to form an electrical measurement value vector. Finally, the process deviation vector and the electrical measurement value vector of each sample chip are paired to construct a structured training data set.

[0066] The training set covers at least 200 sample chips, ensuring that the process deviation distribution range (such as ΔTox∈[-0.2nm,+0.2nm]) fully reflects the production fluctuation characteristics, thereby providing a data basis for residual correction model training.

[0067] S230, calculating the deviation of the actual value of the process parameter of each sample chip in the training set from the preset ideal value of the process parameter, and generating a process deviation vector.

[0068] Specifically, in the process of generating the process deviation vector, deviation calculation is performed for each sample chip in the training set: the actual measurement value of the key process parameter is obtained by the line manufacturing execution system (MES), and an algebraic subtraction operation is performed on it and the preset ideal value of the process parameter to generate a structured process deviation vector.

[0069] S240, inputting the process deviation vector into the physical prediction model to obtain an electrical parameter prediction value.

[0070] Specifically, after inputting the process deviation vector into the pre-constructed physical prediction model, the model performs the following calculation process: first, the baseline physical sub-model is called to obtain a reference electrical parameter value, then the influence gradient value of each process parameter on the target electrical parameter is queried from the process disturbance gradient library, and finally the electrical parameter prediction value is calculated according to the linear superposition formula. The calculation is completed within milliseconds, and the prediction value vector of the electrical parameters including the threshold voltage, saturation drain current, etc. is output.

[0071] S250, calculating a prediction residual based on the electrical parameter prediction value and the real electrical measurement value.

[0072] Specifically, when calculating the prediction residual based on the electrical parameter prediction value and the real electrical measurement value, an algebraic subtraction operation is independently performed for each electrical parameter to generate a residual vector. It should be particularly pointed out that, since the physical prediction model has captured the main linear effect, the residual magnitude is significantly reduced, and the distribution is approximately zero-mean Gaussian distribution, and this feature greatly reduces the learning complexity of the subsequent residual correction model.

[0073] S260, taking the process deviation vector of each sample chip in the training set as the input feature and the prediction residual as the output label, generating a residual correction model.

[0074] In an embodiment of the present application, constructing the residual correction model includes steps S261-S262.

[0075] S261, selecting a gradient boosting decision tree or a feedforward neural network as a training algorithm, and defining a residual correction model architecture.

[0076] Specifically, first, a gradient boosting decision tree (Gradient Boosting Decision Tree) or a feedforward neural network (Feedforward Neural Network) is selected as a training algorithm; wherein the gradient boosting decision tree uses the XGBoost framework, the tree depth is ≤5, and the tree number is ≤100, and the feedforward neural network is configured as a lightweight architecture containing 1-3 hidden layers and ≤50 neurons per layer. This design ensures that the model complexity matches the residual magnitude.

[0077] S262, taking the process deviation vector as the input feature and the prediction residual as the output label, using the selected algorithm to iteratively train the residual correction model architecture until convergence, generating the residual correction model.

[0078] Specifically, the process deviation vector is defined as the input feature space, and the prediction residual vector (including threshold voltage residual, saturation current residual, etc.) is defined as the output label space. The selected algorithm is used to iteratively train the initial model architecture: the mean square error (MSE) is used as the loss function, and the parameters are adjusted by the stochastic gradient descent (SGD) or Adam optimizer. For example, when the loss function of the validation set changes by <1e -5 when the model converges. Finally, the residual correction model is generated, and its output is the prediction residual correction value vector.

[0079] In the present implementation, since the learning goal of the residual correction model is limited to small-scale residuals that fluctuate around zero, the mapping relationship complexity is much lower than learning the complete physical system end-to-end. This feature allows the model architecture to be greatly simplified, and the training data requirement is significantly reduced, which can meet the industrial-level precision requirements. It should be particularly noted that the core innovation of the present implementation is to apply machine learning algorithms to the specific technical task of "predicting residuals", rather than limiting the specific algorithm type; any machine learning algorithm suitable for regression prediction (including but not limited to gradient boosting decision trees, feedforward neural networks, support vector regression, etc.) falls within the scope of the present application.

[0080] S270, based on the physical prediction model and the residual correction model, obtaining a digital twin of the target chip.

[0081] In the present implementation, the physical model provides a traceable process-performance mapping basis, the residual model compensates for local nonlinear effects, reduces prediction errors, and forms a chip individualized digital twin with explainability and industrial usability.

[0082] In a second aspect, as shown in Figure 4 Based on the chip digital twin constructed in the first aspect, the present embodiment provides a method for predicting the electrical parameter value of a chip, including the following steps S410-S440.

[0083] S410, obtaining the measured value of the process parameter of the target chip in the manufacturing process.

[0084] Specifically, the measured value of the key process parameter of the target chip is collected in real time by the online measurement equipment integrated into the semiconductor production line, including the optical critical dimension measurement instrument (OCD), scanning electron microscope (SEM) or focused ion beam microscope (FIB). For example, the key process parameters include gate oxide layer thickness (Tox), ion implantation dose (Dose), gate length (Lg), gate width (Wg) and shallow trench isolation depth (STI_depth), and the measurement accuracy needs to meet ±0.1nm (dimension parameter) or ±1% (dose parameter). The collection process is synchronized with the manufacturing execution system (MES), ensuring that the data acquisition and timestamping are completed within 10 seconds after each process step is completed, forming an original process data set bound to the wafer map coordinates (such as Die#X_Y).

[0085] S420, calculating the deviation of the measured value of the process parameter from the preset ideal value to generate a process deviation vector.

[0086] Specifically, the measured value of the process parameter collected in real time is subjected to algebraic subtraction operation with the preset ideal value, and the calculation formula is: ΔP_j = P_actual - P_ideal

[0087] wherein ΔP_j represents the deviation amount of the jth process parameter; the deviation amounts of all key process parameters are combined in a fixed order (gate oxide thickness→ implantation dose→ gate length→ gate width→ STI depth) into a process deviation vector [ΔTox, ΔDose, ΔLg, ΔWg, ΔSTI_depth]; the data structure of the vector is a 5-dimensional floating-point array, the storage format conforms to the IEEE 754 standard, the numerical range covers the typical process fluctuation interval (such as ΔTox ∈ [-0.2nm, +0.2nm]), and a data check code (CRC-32) is added to guarantee the transmission integrity.

[0088] S430, the process deviation vector is input into a preset physical prediction model and a preset residual correction model in parallel, and electrical parameter physical prediction values and predicted residual correction values are output respectively.

[0089] Specifically, the process deviation vector is synchronously distributed to the physical prediction model and the residual correction model through a high-speed data bus (such as PCIe 4.0), wherein,

[0090] The physical prediction model calls a pre-constructed baseline physical sub-model to output a reference electrical parameter value (M_base), and queries a corresponding influence gradient value (such as ) from a process disturbance gradient library, and performs linear superposition calculation:

[0091] and outputs an electrical parameter physical prediction value vector [Vth_predict, Id_predict, SS_predict];

[0092] The residual correction model is based on a lightweight machine learning architecture (gradient boosting decision tree GBDT or 3-layer feedforward neural network), and processes the process deviation vector in a forward propagation manner to output a predicted residual correction value vector [Error_predicted_Vth, Error_predicted_Id, Error_predicted_SS]; the parallel processing of the double models is realized through a hardware accelerator (GPU / FPGA).

[0093] S440, the electrical parameter physical prediction value and the predicted residual correction value are linearly summed to generate the final electrical parameter value of the target chip.

[0094] Specifically, the electrical parameter physical prediction value output by the physical prediction model and the predicted residual correction value output by the residual correction model are subjected to algebraic addition operation element by element: M_final_k = M_predict_k + Error_predicted_k, wherein k ∈ {Vth, Id, SS}, to generate the final electrical parameter value.

[0095] In an embodiment of the present application, the method for predicting the chip electrical parameter value further comprises: presetting a normal threshold value of the final electrical parameter value under each process parameter respectively; and issuing an abnormal early warning when the final electrical parameter value exceeds the corresponding normal threshold value.

[0096] Specifically, when presetting the normal threshold value of the final electrical parameter value, the allowable fluctuation range of each electrical parameter is defined according to the product specification sheet (Datasheet) of the target chip: a double-sided threshold value is configured for the threshold voltage (Vth) (such as Vth_min=0.45V, Vth_max=0.52V), and an upper limit threshold value is configured for the off-state leakage current (Ioff) (such as Ioff_max=1nA / μm). The threshold value set is stored in the process control file of the production line manufacturing execution system (MES) in the form of key-value pairs, and the data structure is: {parameter type: [threshold lower limit, threshold upper limit],...}. When the high-fidelity electrical parameter value (M_final) exceeds the corresponding threshold value, a three-level early warning mechanism is triggered, wherein,

[0097] The first level is real-time alarm signal generation, which triggers an audible and visual alarm device through a hardware interrupt signal (such as a GPIO pin level jump), and marks the abnormal chip coordinates in the wafer Map;

[0098] The second level is a work order interception instruction, which automatically sends an instruction to the MES system to intercept the subsequent process flow (such as packaging test) of the chip;

[0099] The third level is a root cause diagnosis report, which associates the process deviation vector (ΔP_vector) with the gradient value of the physical prediction model to generate an abnormal traceability report (example: “Vth exceeds limit due to ΔTox=+0.15nm, exceeds threshold value by 5%”).

[0100] It should be particularly noted that the early warning response delay is ≤10 milliseconds, which guarantees the real-time performance of mass production; and the threshold value supports dynamic calibration - when the predicted residual correction value (Error_predicted) of the residual correction model continuously deviates from the zero mean value, the threshold value is adaptively adjusted according to the formula: threshold new = threshold old × (1 + k·Error_predicted) (k is the sensitivity coefficient, and the default value is 0.05).

[0101] In an embodiment of the present application, the method for predicting the chip electrical parameter value further comprises: dividing the target chip into a pre-defined performance level based on the numerical interval of the final electrical parameter value.

[0102] Specifically, in the implementation of chip performance level division, the target chip is classified into a pre-defined level based on the numerical interval of the final electrical parameter value, and the core lies in establishing a precise matching mechanism between electrical performance and terminal application scenarios.

[0103] When the final electrical parameter value is in the optimal interval (e.g., the threshold voltage approaches the theoretical minimum value, and the leakage current is significantly lower than the standard value), the chip is classified into a high-performance grade (Grade A+), such chips have high calculation accuracy, low signal delay, and strong stability, and are allocated to high-precision application scenarios, including data center artificial intelligence training chips (need to process hundreds of billions of parameter models), automatic driving real-time decision systems (nanosecond-level response requirements), and industrial precision control equipment (nanometer-level motion precision dependence), to ensure the reliability of the core system under extreme working conditions.

[0104] When the final electrical parameter value is in the intermediate interval, the chip is classified into a mainstream performance grade (Grade A), which has balanced performance to meet regular calculation requirements and energy consumption control, and is mainly applied to consumer electronics master control chips (e.g., multi-task processing of smart phone SoC), smart home central control modules (temperature and humidity linkage control), and vehicle entertainment systems (high-definition video and audio decoding). Such scenarios have moderate peak performance requirements, but need to ensure long-term operation stability.

[0105] When the final electrical parameter value is in the basic interval, the chip is classified into an economic grade (Grade B / C), such chips have low cost and basic function implementation as the core advantage, and are suitable for Internet of Things sensor nodes (e.g., intermittent data transmission of agricultural temperature and humidity monitors), home appliance control units (washing machine timing switch), and traditional fuel vehicle basic electronic systems (window motor control). These scenarios have low computing power requirements and large fault tolerance space, which can fully exert the cost-effective advantage of the chip.

[0106] In the present implementation, the grading mechanism realizes the global optimal allocation of semiconductor industry resources through strong coupling of electrical performance and application scenarios.

[0107] In a third aspect, as Figure 5 indicated, a construction device of a chip digital twin of the present disclosure is shown, and it should be noted that the principle and technical implementation of the construction method of the chip digital twin can refer to the construction device of the chip digital twin in the previous embodiment (e.g., Figure 2 ), and therefore the present embodiment will not be repeated.

[0108] The construction device of the chip digital twin 500 includes a physical prediction model construction module 501, a residual correction model construction module 502, and a combination module 503. Among them,

[0109] The physical prediction model construction module 501 is configured to perform physical simulation based on an ideal process flow provided with standard design parameters of a target chip to obtain a physical prediction model.

[0110] The residual correction model construction module 502 is configured to collect process parameter actual values and electrical measurement values of a plurality of sample chips of the target chip in a manufacturing process to form a training set, calculate deviations of the process parameter actual values of each sample chip in the training set from preset process parameter ideal values to generate a process deviation vector, input the process deviation vector into the physical prediction model to obtain an electrical parameter prediction value, calculate a prediction residual based on the electrical parameter prediction value and the real electrical measurement value, and generate a residual correction model by taking the process deviation vector of each sample chip in the training set as an input feature and the prediction residual as an output label.

[0111] The combination module 503 is configured to obtain the digital twin of the target chip based on the physical prediction model and the residual correction model.

[0112] In a fourth aspect, as shown in Figure 6 It should be noted that the principle and technical implementation of the chip electrical parameter value prediction device can refer to the chip electrical parameter value prediction method in the previous embodiments (for example, the chip electrical parameter value prediction method in the first aspect). Figure 4 Therefore, the chip electrical parameter value prediction device will not be repeated here.

[0113] The chip electrical parameter value prediction device 600 includes an acquisition module 601, a calculation module 602, and a generation module 603. Among them,

[0114] The acquisition module 601 is configured to acquire process parameter measured values of a target chip in a manufacturing process.

[0115] The calculation module 602 is configured to calculate deviations of the process parameter measured values from preset ideal values to generate a process deviation vector.

[0116] The generation module 603 is configured to input the process deviation vector into the digital twin of any one of the first aspect to generate a final electrical parameter value of the target chip.

[0117] The modules / units described as separate components can or can not be physically separate, and the components shown as modules / units can or can not be physical modules, that is, they can be located in one place, or they can be distributed on multiple network units. Part or all of the modules / units can be selected according to actual needs to achieve the purpose of the embodiments of the present application. For example, the functional modules / units in each embodiment of the present application can be integrated in one processing module, or each module / unit can be physically separate, or two or more modules / units can be integrated in one module / unit.

[0118] In a fifth aspect, an electronic device is provided, including one or more processors and one or more memories; the memories store computer readable codes which, when executed by the one or more processors, implement the method for constructing a chip digital twin according to the first aspect, or the method for predicting a chip electrical parameter value according to the second aspect. In addition, the electronic device can further include an I / O interface, a communication module, and other conventional electronic devices, which will not be described herein. Figure 7 As shown in the figure, the electronic device includes one or more processors and one or more memories; the memories store computer readable codes which, when executed by the one or more processors, implement the method for constructing a chip digital twin according to the first aspect, or the method for predicting a chip electrical parameter value according to the second aspect. In addition, the electronic device can further include an I / O interface, a communication module, and other conventional electronic devices, which will not be described herein.

[0119] The descriptions of the corresponding flows or structures of the above respective figures are each focused on, and the parts not described in detail in a certain flow or structure can be referred to the related descriptions of other flows or structures.

[0120] In an implementation manner of the present disclosure, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the method for constructing a chip digital twin according to the first aspect, or the method for predicting a chip electrical parameter value according to the second aspect.

[0121] Those of ordinary skill in the art can understand that all or part of the steps of the above-mentioned method embodiments can be instructed by a program to complete the processor, and the program can be stored in a computer readable storage medium, and the storage medium is a non-transitory medium, for example, a random access memory, a read-only memory, a flash memory, a hard disk, a solid state disk, a magnetic tape, a floppy disk, an optical disc, and any combination thereof. The above-mentioned storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available medium can be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a digital video disc (DVD)), or a semiconductor medium (for example, a solid state disk (SSD)), etc.

[0122] In an implementation form of the application, the embodiments of the application can further provide a computer program product comprising one or more computer instructions. When the computer instructions are loaded and executed on a computing device, the processes or functions described in the embodiments of the application are wholly or partially generated. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website site, computer or data center to another website site, computer or data center through wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) mode. The computer program product is executed by the computer, and the computer executes the method described in the foregoing method embodiments. The computer program product can be a software installation package, and when the foregoing method needs to be used, the computer program product can be downloaded and executed on the computer.

[0123] In several embodiments provided in the application, it should be understood that the disclosed system, device or method can be implemented in other ways. For example, the device embodiments described above are only illustrative, for example, the division of modules / units is only a logical function division, and actual implementation can have another division mode, for example, a plurality of modules or units can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the displayed or discussed each other can be through some interface, device or module or unit indirect coupling or communication connection, which can be electrical, mechanical or other forms.

[0124] Those of ordinary skill in the art should further appreciate that the units and algorithm steps of the examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of the examples have been described in the above description in general terms. Whether the functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the application.

[0125] The above embodiments only exemplarily illustrate the principles and effects of the application, and are not used to limit the application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical idea disclosed in the application should be covered by the claims of the application.

Claims

1. A method for constructing a chip digital twin, characterized in that, include: Physical simulation is performed based on an ideal process flow with standard design parameters set for the target chip to obtain a physical prediction model; The actual values ​​of process parameters and electrical measurement values ​​of multiple sample chips of the target chip during the manufacturing process are collected to form a training set; Calculate the deviation between the actual value of the process parameter and the preset ideal value of the process parameter for each sample chip in the training set, and generate a process deviation vector; The process deviation vector is input into the physical prediction model to obtain the predicted values ​​of electrical parameters; Based on the predicted electrical parameters and the measured electrical values, the prediction residual is calculated; Using the process deviation vector of each sample chip in the training set as input features and the predicted residual as output label, a residual correction model is generated. Based on the physical prediction model and the residual correction model, a digital twin of the target chip is obtained.

2. The method for constructing a chip digital twin according to claim 1, characterized in that, The physical simulation based on the ideal process flow with standard design parameters of the target chip to obtain a physical prediction model includes: Based on the standard design parameters and ideal process flow of the target chip, the baseline electrical parameter values ​​of the target chip under different process parameters are generated through physical simulation. Integrate all the aforementioned baseline electrical parameter values ​​to construct a baseline physical sub-model of the target chip; In the baseline physical sub-model, an independent process parameter perturbation is applied to each of the process parameters; Calculate the change in electrical parameters caused by the disturbance of the process parameters; Based on the ratio of the amplitude of the disturbance of the process parameters to the corresponding change in the electrical parameters, the influence gradient value of each process parameter is calculated. Based on the influence gradient values ​​of all the process parameters, a process perturbation gradient library for the target chip is constructed. Based on the baseline physical sub-model and the process perturbation gradient library, a physical prediction model for the target chip is constructed.

3. The method for constructing a chip digital twin according to claim 1, characterized in that, The step of generating a residual correction model by using the process deviation vector of each sample chip in the training set as input features and the predicted residual as output label includes: Choose either gradient boosting decision tree or feedforward neural network as the training algorithm, and define the residual correction model architecture; Using the process deviation vector as input features and the predicted residual as output label, the selected algorithm is used to iteratively train the residual correction model architecture until convergence, thereby generating the residual correction model.

4. The method for constructing a chip digital twin according to claim 1, characterized in that, The process parameters include one or more combinations of gate oxide thickness, ion implantation dose, gate length, gate width, and shallow trench isolation depth.

5. A method for predicting the electrical parameter values ​​of a chip, characterized in that, include: Obtain the measured values ​​of the process parameters of the target chip during the manufacturing process; Calculate the deviation between the measured values ​​of the process parameters and the preset ideal values, and generate a process deviation vector; The process deviation vector is input into the digital twin constructed by any one of the methods described in claims 1-4 to generate the final electrical parameter values ​​of the target chip.

6. The method for predicting chip electrical parameter values ​​according to claim 5, characterized in that, The step of inputting the process deviation vector into the digital twin as described in any one of claims 1-4 to generate the final electrical parameter values ​​of the target chip includes: The process deviation vector is input in parallel to the preset physical prediction model and the preset residual correction model, and the physical prediction value and the prediction residual correction value of the electrical parameters are output respectively. The final electrical parameter values ​​of the target chip are generated by linearly summing the physical prediction values ​​of the electrical parameters and the prediction residual correction values.

7. The method for predicting chip electrical parameter values ​​according to claim 5, characterized in that, Also includes: Preset the normal threshold values ​​for the final electrical parameters under each process parameter; An abnormal warning is issued when the final electrical parameter value exceeds the corresponding normal threshold.

8. The method for predicting chip electrical parameter values ​​according to claim 5, characterized in that, Also includes: Based on the numerical range of the final electrical parameter values, the target chip is classified into a predefined performance level.

9. A device for constructing a chip digital twin, characterized in that, include: The physical prediction model building module is used to perform physical simulations based on an ideal process flow with standard design parameters of the target chip to obtain a physical prediction model. The residual correction model construction module is used to collect the actual values ​​of process parameters and electrical measurement values ​​of multiple sample chips of the target chip during the manufacturing process to form a training set; It is also used to calculate the deviation between the actual value of the process parameter and the preset ideal value of the process parameter for each sample chip in the training set, and to generate a process deviation vector; It is also used to input the process deviation vector into the physical prediction model to obtain the predicted values ​​of electrical parameters; It is also used to calculate the prediction residual based on the predicted values ​​of the electrical parameters and the actual measured values ​​of the electrical parameters; It is also used to generate a residual correction model by taking the process deviation vector of each sample chip in the training set as the input feature and the prediction residual as the output label; The combination module is used to obtain a digital twin of the target chip based on the physical prediction model and the residual correction model.

10. A device for predicting the electrical parameters of a chip, characterized in that, include: The acquisition module is used to acquire the measured values ​​of the process parameters of the target chip during the manufacturing process; The calculation module is used to calculate the deviation between the measured values ​​of the process parameters and the preset ideal values, and generate a process deviation vector; A generation module is used to input the process deviation vector into a digital twin constructed by any one of the methods of claims 1-4 to generate the final electrical parameter values ​​of the target chip.

11. An electronic device, characterized in that, include: One or more processors; and One or more memories, wherein the memories store computer-readable code that, when executed by the one or more processors, implements the method for constructing a chip digital twin as described in any one of claims 1 to 4; or the method for predicting chip electrical parameter values ​​as described in any one of claims 5 to 8.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, implements the method for constructing a chip digital twin as described in any one of claims 1 to 4; or the method for predicting chip electrical parameter values ​​as described in any one of claims 5 to 8.

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