Core random memory read reference circuit design method and system

Abstract

The application provides a magnetic core random memory reading reference circuit design method and system, relates to the technical field of circuit design, and comprises the following steps: acquiring a magnetic core memory parameter specification and simulating generation of a bit line current distribution curve, extracting maximum and minimum current values and dividing a current regulation interval, and selecting a median value of a highest reading success rate interval as an optimal reference current; further detecting actual output currents at different temperature points, establishing a temperature compensation model and designing a compensation circuit, and finally converting into a layout design file. The application can accurately determine the optimal reference current and realize temperature compensation, and effectively improves reading reliability and stability of the magnetic core memory.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of circuit design, in particular to a magnetic-core memory read reference circuit design method and system. BACKGROUND

[0002] As a new type of non-volatile storage technology, magnetic-core memory has attracted widespread attention due to its high speed, low power consumption, unlimited write life and good integration capability. In the magnetic-core memory, the reliability of the read operation directly affects the overall performance of the memory, and the read reference circuit design is a key link to ensure the accuracy of the read operation.

[0003] The read process of the traditional magnetic-core memory relies on the difference between the resistance state of the storage unit and the reference resistance, and determines whether the storage unit stores logic "0" or logic "1" by the size of the current flowing through the bit line. However, with the shrinking of the process and the increase of the memory capacity, the read operation of the magnetic-core memory faces more and more challenges.

[0004] The traditional design method lacks a comprehensive analysis of the bit line current distribution characteristics, resulting in inaccurate reference current setting, which cannot adapt to the resistance distribution changes of the storage unit in large-scale arrays, thereby reducing the reliability of the read operation. The existing reference current design often uses empirical formula or fixed offset to determine, without fully considering the influence of process fluctuation and device aging on current distribution, making it difficult to achieve optimal read window. The traditional read reference circuit is sensitive to temperature changes, lacks effective temperature compensation mechanism, and the reference current value deviates greatly at different working temperatures, which significantly increases the read error rate in high temperature or low temperature environment, affecting the stability and reliability of the system.

[0005] There is an urgent need for a magnetic-core memory read reference circuit design method that can accurately analyze the bit line current distribution, determine the optimal reference current value and realize temperature compensation, in order to improve the accuracy and reliability of the read operation. SUMMARY

[0006] The magnetic-core memory read reference circuit design method and system provided by the embodiments of the present application can solve the problems in the prior art.

[0007] In a first aspect, the present application provides a magnetic-core memory read reference circuit design method, comprising:

[0008] Obtaining the parameter specification of the target magnetic-core memory, and generating a bit line current distribution curve according to the parameter specification through a random access memory performance simulator;

[0009] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0010] detecting an actual output current of the reference circuit at different temperature points, calculating a deviation between the actual output current and the optimal reference current value, establishing a temperature compensation model according to the deviation, designing a compensation circuit based on the temperature compensation model, converting the compensation circuit into a layout design file, and completing the design of the target magnetic core random access memory read reference circuit.

[0011] generating a bit line current distribution curve by a random access memory performance simulator according to the parameter specification includes:

[0012] The parameter specification includes a working voltage range and a process parameter, a current sampling window is established according to the working voltage range, and a sampling interval of the current sampling window is adaptively adjusted by an iterative optimization algorithm until the sampling interval covers the maximum and minimum working currents of the target magnetic core random access memory;

[0013] A random access memory performance simulator is used to perform Monte Carlo current sampling on a storage cell array of the target magnetic core random access memory according to the sampling interval and the number of sampling points, and a bit line current distribution curve is generated.

[0014] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0015] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0016] extracting a maximum current value and a minimum current value of the bit line current distribution curve, dividing a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating a storage cell read success rate in each of the current adjustment intervals, and selecting a median value of a current adjustment interval with a highest storage cell read success rate as an optimal reference current value;

[0017] The median of each current adjustment interval is taken as a test current value, a storage cell array of the target magnetic core random memory is subjected to a read operation by using the test current value, and a ratio of a successful number of the read operation to a total test number is counted to obtain a storage cell read success rate corresponding to each current adjustment interval;

[0018] Each current adjustment interval is sorted according to the storage cell read success rate, a current adjustment interval with the highest storage cell read success rate is selected, and the median of the current adjustment interval is determined as an optimal reference current value.

[0019] The actual output current of the reference circuit at different temperature points is detected, a deviation between the actual output current and the optimal reference current value is calculated, and a temperature compensation model is established according to the deviation.

[0020] The reference circuit is subjected to multi-point temperature scanning in a preset temperature range, the actual output current at each temperature point is collected, the deviation between the actual output current and the optimal reference current value is calculated, and a temperature-current response model is established according to the correspondence between the temperature points and the deviation.

[0021] The compensation circuit is converted into a layout design file, and the design of the target magnetic core random memory read reference circuit is completed.

[0022] The structure parameters and device parameters of the compensation circuit are determined according to the temperature compensation model, and the compensation circuit is divided into a temperature detection module and a compensation control module.

[0023] The device layout scheme is generated according to the structure of the compensation circuit, the layout positions of the temperature detection module and the compensation control module are optimized, and the layout design of the target magnetic core random memory read reference circuit is completed.

[0024] The second aspect of the embodiment of the application provides a magnetic core random memory read reference circuit design system, which comprises:

[0025] The first unit is configured to obtain the parameter specification of the target magnetic core random memory, and generate a bit line current distribution curve by using a random access memory performance simulator according to the parameter specification.

[0026] The second unit is configured to extract a maximum current value and a minimum current value of the bit line current distribution curve, divide a difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculate a storage cell read success rate in each current adjustment interval, and select a median of a current adjustment interval with the highest storage cell read success rate as an optimal reference current value.

[0027] The third unit is configured to detect actual output currents of the reference circuit at different temperature points, calculate deviations between the actual output currents and the optimal reference current value, establish a temperature compensation model according to the deviations, design a compensation circuit based on the temperature compensation model, convert the compensation circuit into a layout design file, and complete the design of the target magnetic core random access memory read reference circuit.

[0028] In a third aspect, an electronic device is provided, comprising:

[0029] a processor;

[0030] a memory for storing processor-executable instructions;

[0031] The processor is configured to invoke the instructions stored in the memory to execute the method described above.

[0032] In a fourth aspect, a computer-readable storage medium is provided, which stores computer program instructions, and the computer program instructions are executed by a processor to implement the method described above.

[0033] The present application has the following advantages:

[0034] By obtaining the target magnetic core random access memory parameter specification and generating a bit line current distribution curve using a performance simulator, the read success rate of the storage unit in different current intervals is evaluated, and the optimal reference current value is selected, thereby improving the accuracy and reliability of the read operation.

[0035] A compensation mechanism based on temperature changes is introduced, and a temperature compensation model is established by detecting the deviations between the actual output currents at different temperature points and the optimal reference current value, thereby effectively solving the read error problem caused by temperature drift in traditional design.

[0036] The theoretical design is combined with the actual circuit, and the layout design file of the compensation circuit is implemented, so that the entire read reference circuit design method is realizable and practical, and the stability and performance of the magnetic core random access memory in actual application are improved. BRIEF DESCRIPTION OF DRAWINGS

[0037] Figure 1 FIG. 1 is a flowchart of a magnetic core random access memory read reference circuit design method according to an embodiment of the present application;

[0038] Figure 2 FIG. 2 is a schematic diagram of a magnetic memory storage unit according to an embodiment of the present application;

[0039] Figure 3 FIG. 3 is a schematic diagram of a storage array according to an embodiment of the present application;

[0040] Figure 4For the embodiment of the present application, refer to the resistance structure schematic diagram. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical scheme and advantages of the embodiment of the present application more clear, the technical scheme in the embodiment of the present application will be described clearly and completely below in combination with the drawings in the embodiment of the present application. Obviously, the described embodiment is only a part of the embodiment of the present application, not all the embodiments. Based on the embodiment in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the protection scope of the present application.

[0042] The technical scheme of the present application will be described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes can not be described in some embodiments.

[0043] Figure 1 For the flowchart of the design method of the read reference circuit of the magnetic core random memory of the embodiment of the present application, as shown in Figure 1 The method comprises the following steps:

[0044] Obtaining the parameter specification of the target magnetic core random memory, generating the bit line current distribution curve through the random access memory performance simulator according to the parameter specification;

[0045] Extracting the maximum current value and the minimum current value of the bit line current distribution curve, dividing the difference value between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating the storage unit reading success rate in each current adjustment interval, and selecting the median value of the current adjustment interval with the highest storage unit reading success rate as the optimal reference current value;

[0046] Detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, establishing a temperature compensation model according to the deviation, designing a compensation circuit based on the temperature compensation model, converting the compensation circuit into a layout design file, and completing the design of the read reference circuit of the target magnetic core random memory.

[0047] In an optional embodiment, generating the bit line current distribution curve through the random access memory performance simulator according to the parameter specification comprises:

[0048] The parameter specification comprises the working voltage range and the process parameter, establishing a current sampling window according to the working voltage range, and adaptively adjusting the sampling interval of the current sampling window through an iterative optimization algorithm until the sampling interval covers the maximum and minimum working current of the target magnetic core random memory;

[0049] A random access memory performance simulator is used to perform Monte Carlo current sampling on the memory cell array of the target magnetic core random access memory according to the sampling interval and the number of sampling points, and to generate bit line current distribution curves.

[0050] A method for generating bit line current distribution curves based on parameter specifications using a random access memory performance simulator. This method analyzes the current characteristics of magnetic core random access memory and accurately simulates and generates bit line current distribution curves through adaptive current sampling window adjustment and Monte Carlo sampling technology.

[0051] The parameter specifications in this embodiment include the operating voltage range and process parameters. The operating voltage range defines the normal operating voltage range of the target magnetic core random access memory, for example, 1.0V to 1.2V. Process parameters include key parameters such as transistor threshold voltage, channel length, and oxide thickness. Taking a 28nm process as an example, the transistor threshold voltage is 0.35V, the channel length is 25nm, and the oxide thickness is 1.2nm. These parameters form the basis for subsequent current sampling and distribution curve generation.

[0052] Based on the operating voltage range, the system establishes an initial current sampling window. For an operating voltage range of 1.0V to 1.2V, the initial sampling window can be set to 50μA to 300μA, covering the current variation range. The determination of the sampling window takes into account the influence of operating voltage, temperature changes, and process fluctuations on the current. In practical applications, the initial window cannot completely cover the maximum and minimum operating current of the target magnetic core random access memory; therefore, iterative optimization algorithms are needed to adaptively adjust the current sampling window.

[0053] The iterative optimization algorithm employs a binary search strategy, gradually adjusting the sampling window boundaries through multiple iterations. In each iteration, the system uses the current sampling window to perform initial current sampling on the target memory, acquiring 100 sampling points. If more than 5% of the sampling points fall outside the window boundaries, the sampling window is adjusted: for the lower boundary, if a current value is less than the current lower boundary, the lower boundary is decreased by 25 μA; for the upper boundary, if a current value is greater than the current upper boundary, the upper boundary is increased by 25 μA. After adjustment, sampling and evaluation are performed again until no more than 1% of the sampling points fall outside the boundaries, or the maximum number of iterations (10) is reached.

[0054] In practice, after the first iteration, the sampling window was adjusted to 40μA to 320μA. After five iterations, the window was finally determined to be 30μA to 350μA. At this point, 99.5% of the sampling points fell within the window range, which met the requirements of the maximum and minimum operating current of the target magnetic core random access memory.

[0055] Once the sampling interval is determined, the system sets the number of sampling points, typically 10,000, to ensure the accuracy of the statistical analysis. The random access memory performance simulator performs Monte Carlo current sampling on the memory cell array of the target core random access memory according to the set sampling interval and number of sampling points. The simulator considers process parameter fluctuations, generating randomized process parameter variations for each memory cell. For example, the transistor threshold voltage may randomly fluctuate by ±10% from a base of 0.35V, and the channel length may randomly fluctuate by ±8% from a base of 25nm.

[0056] During Monte Carlo sampling, the simulator constructs a 256×256 memory cell array model and randomizes the parameters of each cell. In read operation mode, the simulator calculates the current value on the bit line and records the sampling result for each time. The sampled current value includes two parts: read current and leakage current. The read current mainly depends on the operating voltage and transistor characteristics, while the leakage current is significantly affected by process variations.

[0057] For each sampling point, the simulator records the complete current value and the specific conditions under which it occurred, such as operating voltage, temperature, and the degree of deviation of affected process parameters. In a real-world example, with an operating voltage of 1.1V and a temperature of 85°C, the current distribution of 10,000 sampling points ranged from 32μA to 347μA, with an average of 185μA and a standard deviation of 58μA.

[0058] After sampling, the system generates a bitline current distribution curve based on the sampled data. The sampling interval from 30μA to 350μA is divided into 32 equal intervals, and the number of sampling points in each interval is counted to form a frequency distribution histogram. Subsequently, an interpolation algorithm is used to smooth the histogram, generating a continuous probability density curve. In this embodiment, the current distribution exhibits approximately normal distribution characteristics, but with a slight right skew, reflecting the asymmetric influence of process variations on the current characteristics.

[0059] To enhance the readability of the current distribution curves, key statistical indicators are marked, including the mean (185 μA), median (175 μA), maximum (347 μA), and minimum (32 μA). The ±3σ range, from 11 μA to 359 μA, is also marked, covering 99.7% of the current distribution. These statistical indicators help designers understand the current distribution characteristics and the impact of process variations.

[0060] The resulting bit line current distribution curve is presented graphically, with the horizontal axis representing the current value (μA) and the vertical axis representing the probability density. The curve shape reflects the current characteristics of the target magnetic core random access memory under given operating voltage and process conditions, providing an important reference for memory design, performance evaluation, and reliability analysis.

[0061] Through the specific implementation methods described above, designers can accurately understand and predict the current characteristics of magnetic core random access memory, optimize circuit design to adapt to process variations, and improve product yield and reliability.

[0062] In one optional implementation, the maximum and minimum current values ​​of the bit line current distribution curve are extracted, and the difference between the maximum and minimum current values ​​is divided into multiple current adjustment intervals, including:

[0063] The maximum and minimum current values ​​of the bit line current distribution curve are extracted, and an adaptive partitioning algorithm is used to divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals. The adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the difference between the maximum and minimum current values, and the interval width of adjacent current adjustment intervals changes non-linearly.

[0064] Extracting the maximum and minimum current values ​​from the bitline current distribution curve and dividing the difference between the maximum and minimum current values ​​into multiple current adjustment intervals is a key technical step. This implementation details how to implement this process using an adaptive partitioning algorithm.

[0065] Bit line current distribution curves are typically obtained through memory array testing. In practical applications, a current detection circuit can be used to scan the current of all bit lines in the memory array, record the current value of each bit line, and generate a current distribution curve. For example, in a memory array containing 1024 bit lines, the measured current distribution range is 75μA to 125μA.

[0066] After obtaining the bitline current distribution curve, the first step is to perform an extreme value extraction operation. By traversing all current values ​​in the current distribution curve, the maximum current value Imax and the minimum current value Imin are determined. In the example above, Imax = 125 μA and Imin = 75 μA are extracted.

[0067] Based on the extracted extreme values, the bit line current range ΔI is calculated, i.e., ΔI = Imax - Imin. In the example, ΔI = 125μA - 75μA = 50μA. The current range ΔI is a fundamental parameter for determining the number and width of current regulation intervals.

[0068] The adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the magnitude of the current range ΔI. The algorithm adopts the following strategy: when ΔI is small (e.g., ΔI < 30 μA), a smaller number of intervals are set; when ΔI is medium (e.g., 30 μA ≤ ΔI < 70 μA), a medium number of intervals are set; when ΔI is large (e.g., ΔI ≥ 70 μA), a larger number of intervals are set.

[0069] In this example, ΔI = 50 μA falls within the medium range, so the algorithm divides the current range into 5 intervals. Dynamically determining the number of intervals allows the method to adapt to the current distribution characteristics of different storage devices, improving the accuracy and adaptability of the adjustment.

[0070] Unlike traditional uniform partitioning methods, the adaptive partitioning algorithm in this implementation uses a non-linearly varying interval width design. The interval width of adjacent current adjustment intervals changes non-linearly; specifically, it achieves the characteristic of gradually increasing interval width from the low current value end to the high current value end.

[0071] For the 50μA current range in the example, the five intervals are divided as follows: the first interval is [75μA, 82μA], with a width of 7μA; the second interval is [82μA, 91μA], with a width of 9μA; the third interval is [91μA, 102μA], with a width of 11μA; the fourth interval is [102μA, 115μA], with a width of 13μA; and the fifth interval is [115μA, 125μA], with a width of 10μA.

[0072] This nonlinear partitioning takes into account the actual characteristics of bit line current distribution in memory devices. Generally, finer adjustments are needed in regions with smaller current values, while wider intervals can be used in regions with larger current values. In implementation, exponential or polynomial functions can be used to calculate the boundary values ​​of each interval, ensuring a smooth change in interval width.

[0073] To determine the precise boundaries of each interval, the adaptive partitioning algorithm also analyzes the density characteristics of the current distribution curve. Narrower intervals are defined in regions where current values ​​are densely concentrated, while wider intervals are defined in regions where current values ​​are sparsely distributed. This strategy ensures a balance between the accuracy and efficiency of current regulation.

[0074] In its implementation, the algorithm first counts the number of bit lines within each small current segment, generating a current distribution density curve. For example, in this example, the number of bit lines in each cell within the range of 75μA to 125μA can be counted in steps of 0.5μA. Based on the statistical results, regions with high current distribution density are identified, such as the 85μA-95μA region with 40% of the bit lines, and more refined divisions are applied to these regions.

[0075] Considering the differences in memory characteristics, the algorithm also introduces configurable parameters to optimize interval partitioning. These parameters include the number of basic intervals, nonlinear coefficients, and density weighting factors, which can be adjusted according to different types or processes of memory devices. For example, for high-density memory, the nonlinear coefficient can be increased to make the interval width variation more significant.

[0076] After the intervals are divided, the algorithm stores the results in the control register, providing a basis for subsequent bitline current adjustment. Each interval corresponds to a specific adjustment strategy, such as adjustment voltage magnitude, adjustment step size, and adjustment timing parameters. For example, a larger current increase is applied to the bitlines in the first interval [75μA, 82μA], while a smaller current decrease is applied to the bitlines in the fifth interval [115μA, 125μA].

[0077] The aforementioned adaptive partitioning algorithm enables intelligent division of bitline current adjustment intervals, flexibly adjusting the number and width of intervals based on actual current distribution characteristics, thereby improving the performance consistency and reliability of the memory. This method is particularly suitable for bitline current equalization control in large-scale integrated memory devices, effectively solving the problem that traditional fixed interval partitioning methods are ill-suited to diverse current distributions.

[0078] In one optional implementation, calculating the memory cell read success rate within each current adjustment interval, and selecting the median of the current adjustment interval with the highest memory cell read success rate as the optimal reference current value includes:

[0079] The median value of each current adjustment range is used as the test current value. The test current value is used to perform a read operation on the memory cell array of the target magnetic core random access memory. The ratio of the number of successful read operations to the total number of tests is calculated to obtain the memory cell read success rate corresponding to each current adjustment range.

[0080] Each current adjustment interval is sorted according to the success rate of the memory cell read, and the current adjustment interval with the highest success rate of the memory cell read is selected. The median value of this current adjustment interval is determined as the optimal reference current value.

[0081] In practical applications, by calculating the success rate of memory cell reads within each current adjustment range and selecting the median of the current adjustment range with the highest memory cell read success rate as the optimal reference current value, the read accuracy and stability of the magnetic core random access memory can be effectively improved.

[0082] For the target magnetic core random access memory (RAM), multiple current adjustment ranges are defined. For example, the adjustable range of the reference current can be set from 0.5 μA to 10 μA, and then divided into several intervals, such as [0.5 μA, 1.5 μA], [1.5 μA, 2.5 μA], [2.5 μA, 3.5 μA], [3.5 μA, 4.5 μA], [4.5 μA, 5.5 μA], [5.5 μA, 6.5 μA], [6.5 μA, 7.5 μA], [7.5 μA, 8.5 μA], and [8.5 μA, 9.5 μA]. These current adjustment ranges can be determined based on the technical parameters and expected operating conditions of the RAM.

[0083] For each defined current adjustment range, the system calculates the midpoint as the test current value. Taking the above range as an example, the test current values ​​are 1.0μA, 2.0μA, 3.0μA, 4.0μA, 5.0μA, 6.0μA, 7.0μA, 8.0μA, and 9.0μA. The system applies each test current value to the memory cell array of the target magnetic core random access memory for read test operations.

[0084] During testing, a specific test current value is used to perform read operations on multiple memory cells in the memory cell array. To ensure the statistical significance of the test results, the number of tests is usually set to a large value; for example, for an array containing 1024×1024 memory cells, 10,000 memory cells can be randomly selected for testing. The system records the result of each read operation, including the number of successful and failed reads.

[0085] The success criterion for a read operation is that the system can correctly identify the data bit (0 or 1) stored in the memory cell. Read failures include: the inability to identify the stored data bit, or the identified data bit not matching the actual stored data bit. For each test current value, the system calculates the ratio of successful reads to the total number of tests to obtain the memory cell read success rate for the corresponding current adjustment range.

[0086] Assuming that the actual test results for the above nine current adjustment ranges show that the memory cell read success rates are 76.5%, 85.3%, 92.7%, 97.8%, 99.2%, 98.5%, 95.3%, 89.7%, and 82.1%, respectively. The system sorts the current adjustment ranges according to these read success rates, from highest to lowest: [4.5μA, 5.5μA] (99.2%), [5.5μA, 6.5μA] (98.5%), [3.5μA, 4.5μA] (97.8%), [6.5μA, 7.5μA] (95.3%), [2.5μA, 3.5μA] (92.7%), [7.5μA, 8.5μA] (89.7%), [1.5μA, 2.5μA] (85.3%), [8.5μA, 9.5μA] (82.1%), and [0.5μA, 1.5μA] (76.5%).

[0087] The current adjustment range [4.5μA, 5.5μA] with the highest memory cell read success rate (99.2%) was selected, significantly higher than other ranges. The system determined the median value of this range, 5.0μA, as the optimal reference current value.

[0088] To verify the effectiveness of the selected optimal reference current value, the system can perform further finer tests around that current value. For example, tests can be conducted in 0.1 μA increments within the range of 4.5 μA to 5.5 μA to obtain a more accurate optimal reference current value. Suppose that through fine-tuning, the read success rate at 5.2 μA is found to be 99.5%, higher than the 99.2% at 5.0 μA, then 5.2 μA can be determined as the final optimal reference current value.

[0089] In practical applications, this optimal reference current value is configured in the read circuit of the target magnetic core random access memory. During a read operation, the read circuit compares this reference current value with the current generated by the memory cell to determine the data bits stored in the cell. By using the current value with the highest read success rate as a reference, the system can minimize read errors and improve data reliability.

[0090] The optimal reference current value may vary depending on the batch of magnetic core random access memory (RAM) or the operating environment. Therefore, the system can execute the above method during the RAM initialization phase or periodic maintenance to recalculate and update the optimal reference current value. This dynamic adjustment mechanism can adapt to different operating conditions and maintain a high read success rate.

[0091] Through the technical implementation described in detail above, this method can effectively determine the optimal reference current value for magnetic core random access memory, improve the accuracy and stability of memory reading, reduce data reading errors, extend the service life of memory, and enhance the overall reliability and performance of the system.

[0092] In one optional implementation, detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, and establishing a temperature compensation model based on the deviation includes:

[0093] Multi-point temperature scanning is performed on the reference circuit within a preset temperature range. The actual output current at each temperature point is collected, and the deviation between the actual output current and the optimal reference current value is calculated. Based on the correspondence between the temperature point and the deviation, a temperature-current response model is established.

[0094] When performing multi-point temperature scanning on a reference circuit within a preset temperature range, the temperature range can be set to -40℃ to 125℃, which is a commonly used industrial-grade temperature range for electronic devices. Within this temperature range, temperature points are selected for scanning, with temperature intervals set to 5℃, meaning measurements are taken at temperature points from -40℃, -35℃, -30℃... up to 125℃. To ensure measurement accuracy, high-precision temperature control equipment, such as a constant temperature chamber, can be used, with a temperature control accuracy of ±0.1℃.

[0095] For each temperature point test, the reference circuit is placed in a temperature-controlled chamber. After the temperature stabilizes (usually 15-20 minutes), the actual output current is collected using a precision current measuring instrument. The resolution of the precision current measuring instrument should be at the 0.01μA level to ensure measurement accuracy. For example, at 25℃, assume the actual output current of the reference circuit is 10.25μA.

[0096] After obtaining the actual output current at each temperature point, the deviation from the optimal reference current value needs to be calculated. The optimal reference current value can be determined according to the design specifications. For example, at a normal temperature of 25℃, the designed optimal reference current value is 10.00μA. The deviation is calculated by subtracting the optimal reference current value from the actual output current. Taking the above data as an example, at 25℃, the deviation is 10.25μA - 10.00μA = 0.25μA, which is a deviation rate of 2.5%.

[0097] For measurements across the entire temperature range, a series of data pairs between temperature points and corresponding deviation values ​​can be obtained. For example, the actual current measured at -40℃ is 9.50μA with a deviation of -0.50μA; the actual current measured at 0℃ is 9.85μA with a deviation of -0.15μA; the actual current measured at 25℃ is 10.25μA with a deviation of 0.25μA; the actual current measured at 75℃ is 10.75μA with a deviation of 0.75μA; and the actual current measured at 125℃ is 11.20μA with a deviation of 1.20μA.

[0098] Based on the collected temperature points and corresponding deviation data pairs, a temperature-current response model is established. This model can be constructed using a piecewise linear interpolation method, that is, a linear relationship is used between adjacent temperature points to describe the change in temperature and current deviation. Taking the above data as an example, between -40℃ and 0℃, the deviation changes from -0.50μA to -0.15μA; between 0℃ and 25℃, the deviation changes from -0.15μA to 0.25μA; between 25℃ and 75℃, the deviation changes from 0.25μA to 0.75μA; and between 75℃ and 125℃, the deviation changes from 0.75μA to 1.20μA.

[0099] For large datasets, data processing software can be used to construct a temperature-current response model. By using temperature as the independent variable and current deviation as the dependent variable, a functional model describing the relationship between the two can be obtained. This model can be in the form of a polynomial fit; depending on the characteristics of the measurement data, different orders of fitting methods, such as quadratic or cubic polynomials, can be selected. For the above measurement data, a quadratic polynomial model describing the relationship between temperature and current deviation can be obtained through fitting.

[0100] To improve model accuracy, the density of temperature scans can be increased. In temperature ranges where current changes drastically, such as the extremely low temperature range (-40℃ to -20℃) and the high temperature range (100℃ to 125℃), the temperature interval can be reduced to 2℃ to obtain more refined data. For example, in the -40℃ to -20℃ range, measurements can be performed at temperature points such as -40℃, -38℃, -36℃, etc.

[0101] The established temperature-current response model needs to be verified for accuracy. Temperature points not involved in the model establishment, such as -25℃, 15℃, 50℃, and 100℃, can be selected. The actual output current at these temperature points is measured and compared with the model's predicted value. If the error between the predicted and actual measured values ​​is within an acceptable range (typically ±1%), then the model's accuracy meets the requirements.

[0102] Once the temperature-current response model is established, it can be used to guide the design of compensation circuits. Based on the current deviations predicted by the model at different temperatures, corresponding compensation networks can be designed to counteract the effects of temperature changes. For example, in response to the trend of increasing current in high-temperature regions shown by the model, a compensation circuit with a negative temperature coefficient can be designed to provide the opposite adjustment effect when the temperature rises.

[0103] To accommodate the characteristics of the reference circuit, the compensation network can employ a bipolar design, providing compensation in different directions in the low-temperature and high-temperature regions. For example, when the temperature is below 25°C, the compensation network provides positive compensation, increasing the output current; when the temperature is above 25°C, it provides negative compensation, reducing the output current, thereby maintaining the stability of the output current across the entire temperature range.

[0104] Through the detailed temperature scanning, data acquisition, deviation calculation, and model building process described above, the current output characteristics of the reference circuit at different temperatures can be accurately described, providing a reliable basis for subsequent temperature compensation and ensuring that the reference circuit can provide an output close to the optimal reference current value across the entire temperature range, meeting the needs of high-precision applications.

[0105] In one optional implementation, the design of a compensation circuit based on the temperature compensation model, the conversion of the compensation circuit into a layout design file, and the completion of the design of the target magnetic core random access memory read reference circuit include:

[0106] Based on the temperature compensation model, the structural and device parameters of the compensation circuit are determined, and the compensation circuit is divided into a temperature detection module and a compensation control module.

[0107] Based on the structure of the compensation circuit, generate a device layout scheme, optimize the layout positions of the temperature detection module and the compensation control module, and complete the layout design of the target magnetic core random access memory read reference circuit.

[0108] When designing a compensation circuit based on a temperature compensation model, the structural and device parameters of the compensation circuit are determined according to the temperature compensation model. This temperature compensation model describes the resistance variation characteristics of the magnetic core random access memory (RAM) read reference circuit at different temperatures. The temperature compensation model establishes the relationship between temperature and the rate of resistance change by measuring the resistance change of a standard sample within the temperature range of -40℃ to 125℃. For example, in actual tests, when the temperature rises from 25℃ to 85℃, the magnetic tunnel junction resistance decreases by an average of 15.3%, while when the temperature drops to -20℃, the resistance increases by an average of 11.7%.

[0109] The compensation circuit is divided into two functional modules: a temperature detection module and a compensation control module. The temperature detection module uses a PN junction temperature sensor design, utilizing the characteristic that the forward voltage of a silicon diode is negatively correlated with temperature. Specifically, two identical diodes, D1 and D2, are used, each with different current densities (typically in a 1:8 ratio). The voltage difference ΔV across the diodes is measured, and this voltage difference is proportional to the absolute temperature. The temperature detection module uses a bandgap reference circuit to provide a stable reference current. When the current density ratio is selected as 1:8, the temperature coefficient is approximately -2mV / ℃. At room temperature (25℃), the measured ΔV is 198mV; at 85℃, ΔV increases to 318mV; and at -20℃, ΔV decreases to 142mV, achieving a detection accuracy of ±1℃.

[0110] The compensation control module employs an adjustable current source structure, adjusting the operating current of the reference circuit based on the voltage signal output from the temperature detection module. This module includes a voltage-to-current conversion circuit and a current distribution circuit. The voltage-to-current conversion circuit, composed of an operational amplifier and a MOSFET, converts the temperature detection voltage into a control current proportional to the temperature. The current distribution circuit uses a current mirror structure, increasing the read current at high temperatures and decreasing it at low temperatures based on the temperature characteristic curve of the magnetic tunnel junction. In the specific design, at a reference temperature of 25℃, the read current is set to 50μA; when the temperature rises to 85℃, the current automatically increases to 57.6μA to compensate for signal attenuation caused by the reduced resistance; when the temperature drops to -20℃, the current decreases to 44.2μA to accommodate the increased resistance.

[0111] In the device parameter design of the compensation circuit, the diodes for the temperature detection module are selected as PN junctions with an area of ​​10μm×10μm, and the bias currents are set to 10μA and 80μA respectively. The operational amplifier is selected as a low offset voltage model, with an offset voltage less than 0.5mV and a common-mode rejection ratio greater than 80dB. The current mirror of the compensation control module uses well-matched PMOS transistors, and the transistor size ratio is precisely designed according to the temperature-resistance curve, with the W / L ratio adjusted by 3.5% for every 10℃ temperature change. All transistors adopt a long-channel design to reduce channel modulation effects and improve current replication accuracy.

[0112] Based on the determined compensation circuit structure, a device layout scheme is generated. The layout design adopts a symmetrical layout technique, focusing on optimizing the placement of the temperature detection module and the compensation control module. The temperature detection module is positioned around the core unit array, maintaining an appropriate distance from the memory cells to avoid the thermal effects of memory operations affecting temperature detection accuracy. The detection diodes adopt a concentric ring structure to reduce the influence of temperature gradients, and the spacing between the two diodes is kept within 50μm to ensure that they sense the same temperature.

[0113] The compensation control module is positioned near the read reference circuit to reduce signal transmission line length and minimize parasitic effects. The current mirror transistor employs an interdigitated layout to improve matching accuracy. The core transistor area ratio is designed to be 1:1.153:0.847, corresponding to compensation requirements in temperature ranges of -40℃, 25℃, and 125℃. Key matching components utilize a dumbbell structure and guard ring design to reduce stress and edge effects.

[0114] During layout optimization, the analog circuitry is isolated using guard rings to prevent noise coupling from the digital circuitry. Power lines use wide metal traces and are routed separately to reduce the impact of IR voltage drop. An isolation zone is provided around the temperature sensor to avoid the influence of heat sources. Critical signal lines use differential routing to improve anti-interference capabilities. After layout completion, DRC and LVS checks are performed to ensure that the layout is consistent with the circuit design.

[0115] After layout implementation and simulation verification, the compensation circuit can control the temperature drift of the read reference circuit within ±3.5% in the temperature range of -40℃ to 125℃, meeting the requirements for stable operation of magnetic core random access memory over a wide temperature range. Actual testing shows that after introducing the compensation circuit, the read window margin is increased from 15% to 26% across the entire temperature range, effectively improving the reliability of the memory under extreme temperatures, and reducing the error rate from the order of 10^-6 to the order of 10^-9.

[0116] like Figures 2-4 As shown, the method includes:

[0117] The reference circuit is implemented using a combination of MTJ resistors and polysilicon resistors. A reference resistor is formed by selecting an RP-state MTJ and a polysilicon resistor R0, where the RP-state MTJ is implemented with a column of memory cells in the NMOS transistor array. The RP-state MTJ resistor used for reference achieves good process matching with the MTJs in the array, exhibiting nearly identical process corner variation characteristics. Resistor R0 is adjusted using trimming techniques so that its resistance at the process corner is equal to half the sum of RAP and RP.

[0118] For example, a memory array employs a 512 word line and 1056 bit line structure, configured with 32 I / Os, each I / O containing 33 bit lines. A memory cell consists of an NMOS transistor connected to a median switch (MTJ). The gates of the NMOS transistors in each row are connected to the same word line, and each column of memory cells is connected to the same bit line and source line. The RP-state MTJs in the reference resistors are placed within the memory array, with each I / O equipped with a column of RP-state MTJs for reference. The reference MTJ column is located one-quarter of the way from the edge of a single I / O, minimizing the lateral trace distance difference between the bit lines of each column of memory cells and the corresponding reference cell connected to the input of the sensitive amplifier.

[0119] The reference MTJ has the same structure as the memory cell and is selected by a MOSFET. The gate of the MOSFET is connected to the word line of the memory cell in the same row. When reading a memory cell at a certain location, the reference MTJ at the corresponding location is selected simultaneously. When reading the near-end cell 0, WL0 and reference MTJ0 are selected; when reading the far-end cell 511, WL511 and reference MTJ511 are selected. This structure ensures that the reference cell and the memory cell have the same bit line and source line parasitic resistances on the read path. Simultaneously, unselected memory cells and reference MTJs on the same bit line have similar leakage currents.

[0120] In the read topology circuit, the memory cell and the reference circuit are connected to the two input terminals of the sensitive amplifier via clamping transistors M0 and M1. Clamping transistors M0 and M1 clamp the potentials of nodes BL and BLR to the read voltage, while SL and SLR are grounded. The read current is in the same direction as the write RP state, avoiding read interference from the MTJ in the traditional reference circuit composed of RAP and RP states. The read timing is divided into three stages: pre-charge, development, and amplified output. In the pre-charge stage, transistors M3 and M4 are turned on to charge the SAIP and SAIN nodes to the same potential. In the development stage, transistors M3 and M4 are turned off, and the clamping voltage VCLAMP clamps the BL and BLR nodes to the same read voltage. The different resistances of the two branches result in different discharge rates for the SAIP and SAIN nodes, forming a potential difference. In the amplified output stage, the sensitive amplifier amplifies the weak signal difference between the SAIP and SAIN nodes and outputs the data through a latched signal.

[0121] The initialization of the reference circuit is achieved by controlling the write circuit of the memory cell. The initialization circuit connects a low-dropout linear regulator to the N node of the reference circuit via a MOSFET. During initialization, transistor M1 is turned off, the VINIT signal is controlled to turn on transistor M2, and the corresponding word line is opened, causing MTJ in the reference circuit to be written to the RP state. Specifically, the initialization process is as follows: VCLAMP is pulled low to turn off M0 and M1, the word line and transistor M2 are turned on, a write voltage is applied to the N node and maintained for a certain period of time to complete the initialization.

[0122] This design scheme counteracts most of the leakage current's impact on the read window by introducing a leakage current similar to that on the bit line into the reference path. During each read operation, the parasitic resistance at the reference cell and memory cell ends is the same, thus offsetting the parasitic resistance's influence on the read window. The reference circuit only requires the RP-state MTJ, which is arranged in a separate column in the memory array, simplifying the initialization process. Furthermore, the design of the read current direction avoids read interference problems.

[0123] A second aspect of the present invention provides a design system for a magnetic core random access memory read reference circuit, comprising:

[0124] The first unit is used to obtain the parameter specifications of the target magnetic core random access memory, and generate a bit line current distribution curve based on the parameter specifications through a random access memory performance simulator.

[0125] The second unit is used to extract the maximum and minimum current values ​​of the bit line current distribution curve, divide the difference between the maximum and minimum current values ​​into multiple current adjustment intervals, calculate the memory cell read success rate in each current adjustment interval, and select the median of the current adjustment interval with the highest memory cell read success rate as the optimal reference current value.

[0126] The third unit is used to detect the actual output current of the reference circuit at different temperature points, calculate the deviation between the actual output current and the optimal reference current value, establish a temperature compensation model based on the deviation, design a compensation circuit based on the temperature compensation model, convert the compensation circuit into a layout design file, and complete the design of the target magnetic core random access memory read reference circuit.

[0127] A third aspect of the present invention provides an electronic device, comprising:

[0128] processor;

[0129] Memory used to store processor-executable instructions;

[0130] The processor is configured to invoke instructions stored in the memory to execute the aforementioned method.

[0131] A fourth aspect of the present invention provides a computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the aforementioned method.

[0132] This invention can be a method, apparatus, system, and / or computer program product. The computer program product may include a computer-readable storage medium having computer-readable program instructions loaded thereon for performing various aspects of the invention.

[0133] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of designing a core random access memory read reference circuit, characterized by, The method comprises the following steps: Obtaining the parameter specification of the target magnetic core random memory, generating a bit line current distribution curve through a random access memory performance simulator according to the parameter specification, comprising: The parameter specification includes a working voltage range and a process parameter, a current sampling window is established according to the working voltage range, and the sampling interval of the current sampling window is adaptively adjusted through an iterative optimization algorithm until the sampling interval covers the maximum and minimum working current of the target magnetic core random memory; Using a random access memory performance simulator, a Monte Carlo current sampling is performed on the memory cell array of the target magnetic core random memory according to the sampling interval and the number of sampling points to generate a bit line current distribution curve; Extracting the maximum current value and the minimum current value of the bit line current distribution curve, dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating the memory cell read success rate in each current adjustment interval, and selecting the median value of the current adjustment interval with the highest memory cell read success rate as the optimal reference current value; Detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, and establishing a temperature compensation model according to the deviation; based on the temperature compensation model, a compensation circuit is designed, the compensation circuit is converted into a layout design file, and the design of the target magnetic core random memory read reference circuit is completed.

2. The method of claim 1, wherein, Extracting the maximum current value and the minimum current value of the bit line current distribution curve, dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals comprises: Extracting the maximum current value and the minimum current value of the bit line current distribution curve, and dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals by using an adaptive partitioning algorithm, wherein the adaptive partitioning algorithm dynamically determines the number of current adjustment intervals based on the difference between the maximum current value and the minimum current value, and the interval width of adjacent current adjustment intervals changes nonlinearly.

3. The method of claim 1, wherein, In each of the current adjustment intervals, the memory cell read success rate is calculated, and the median value of the current adjustment interval with the highest memory cell read success rate is selected as the optimal reference current value, comprising: Taking the median value of each current adjustment interval as a test current value, performing a read operation on the memory cell array of the target magnetic core random memory using the test current value, and calculating the ratio of the number of successful read operations to the total number of tests to obtain the memory cell read success rate corresponding to each current adjustment interval; According to the memory cell read success rate, each current adjustment interval is sorted, and the current adjustment interval with the highest memory cell read success rate is selected, and the median value of the current adjustment interval is determined as the optimal reference current value.

4. The method of claim 1, wherein, Detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, and establishing a temperature compensation model according to the deviation comprises: The reference circuit is subjected to multi-point temperature scanning in a preset temperature range, actual output currents at each temperature point are collected, deviations between the actual output currents and the optimal reference current value are calculated, and a temperature-current response model is established according to the correspondence between the temperature points and the deviations.

5. The method of claim 1, wherein, The compensation circuit is designed based on the temperature compensation model, the compensation circuit is converted into a layout design file, and the design of the target magnetic core random memory read reference circuit is completed, including: The structure parameters and device parameters of the compensation circuit are determined according to the temperature compensation model, and the compensation circuit is divided into a temperature detection module and a compensation control module; A device layout scheme is generated according to the structure of the compensation circuit, the layout positions of the temperature detection module and the compensation control module are optimized, and the layout design of the target magnetic core random memory read reference circuit is completed.

6. A core random access memory read reference circuit design system for implementing the method of any of the preceding claims 1-5, characterized by, It includes: The first unit is used for acquiring the parameter specification of the target magnetic core random memory, and generating a bit line current distribution curve through a random access memory performance simulator according to the parameter specification; The second unit is used for extracting the maximum current value and the minimum current value of the bit line current distribution curve, dividing the difference between the maximum current value and the minimum current value into a plurality of current adjustment intervals, calculating the storage unit read success rate in each current adjustment interval, and selecting the median value of the current adjustment interval with the highest storage unit read success rate as the optimal reference current value; The third unit is used for detecting the actual output current of the reference circuit at different temperature points, calculating the deviation between the actual output current and the optimal reference current value, establishing a temperature compensation model according to the deviation, designing a compensation circuit based on the temperature compensation model, converting the compensation circuit into a layout design file, and completing the design of the target magnetic core random memory read reference circuit.

7. An electronic device, comprising: It includes: A processor; A memory for storing processor-executable instructions; The processor is configured to call the instructions stored in the memory to execute the method of any one of claims 1 to 5.

8. A computer-readable storage medium having stored thereon computer program instructions, wherein, The computer program instructions are executed by the processor to implement the method of any one of claims 1 to 5. The computer program instructions are executed by the processor to implement the method of any one of claims 1 to 5.

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