Memory and method for constructing memory

Abstract

A memory includes a multi-level data path partition circuit and includes at least: a first data path hierarchy partition including at least one input configured to input data to or output data from the memory via at least one global input-output circuit; a second data path hierarchy partition configured to input data to or output data from the memory between one of a plurality of write assist circuits and one of the at least one global input-output circuit, wherein at least one of the plurality of write assist circuits and at least another of the plurality of write assist circuits are located in central portions of the upper and lower part cell memory arrays, respectively; and a third data path hierarchy partition configured to input data to or output data from the memory between one of the plurality of column multiplexing circuitry and the sense amplifier circuit and one of the plurality of write assist circuits.

Description

TECHNICAL FIELD

[0001] The technical field relates to a memory and a method for constructing a memory with improved internal data path partitioning. The technical field is applicable, but not limited to, data path partitioning arrangements that reduce capacitance while improving memory access time and cycle time. BACKGROUND

[0002] As is known, a bit cell or bitcell is the basic building block of a memory array, which in turn is the basic building block of a memory chip. Each cell includes a small circuit with a memory element and a selector. The memory element stores data (a logic '1' or a logic '0'), and the selector activates the cell at access time.

[0003] As is known, a typical static random access memory (SRAM) / read only memory (ROM) uses such bitcell memory arrays that employ clock signal routing and use techniques to access (read or write) the memory elements. To improve access to the memory, as is known, buffers are inserted in the clock path, typically to optimize and reduce the resistance-capacitance (RC) delay. However, the use of buffers in the memory increases the silicon area and gate delay of the memory. The insertion of such logic buffers in the memory increases the gate delay because each logic buffer introduces some propagation delay to the clock signal. In addition, the impact of these capacitances will directly increase the switching power as the input gate capacitance and metal capacitance increase.

[0004] Also, as is known, a typical SRAM / ROM uses a single or two-level clock partitioning scheme. In a two-level clock partitioning scheme, the first clock level is driven by metal load and the second level is driven by gate load. Here, a memory bank clock is used to select either the top memory bank or the bottom memory bank, where the memory internal clock is the input signal. A memory 'address' signal is used to decode at the memory bank level and at the memory row level and select between the top and bottom memory banks of the memory. In the known memory, the memory bank clock decoding produces another internal clock that is used as an input signal for word line decoding. The word line decoding is used to produce a word line to select a particular row of the memory. For the word line decoding, the first input will be the internal clock produced using the memory bank clock decoding and the second input is the decoded address provided by a pre-decoder. However, this arrangement increases the clock switching power consumed.

[0005] Figure 1Two simplified known representations 100, 150 of memory architectures are shown. The first memory 100 shows an SRAM 6T bitcell array 110 for storing data. The first memory 100 includes a column multiplexer function 115 configured to select a particular bitcell to perform a write / read operation. The first memory 100 and the second memory 150 include a memory region 130 dedicated to single level data partitioning and 1-level memory bank clock decoding. The first memory 100 is shown with a charge pump circuit 125 configured to provide a negative boost voltage to bitlines of the bitcells and global input / output (Gio), and write drivers and write assist circuitry 135 at the memory bottom configured to provide input to and obtain output from the first memory 100. Internal clock signals are also shown at 150 and 155.

[0006] Figure 2 A known simplified representation of a memory architecture 200 is also shown. The memory architecture 200 includes a first bitcell memory bank including a bitcell array and sometimes referred to as a bitcell bank left (BB-L) quadrant 210, and a second bitcell memory bank sometimes referred to as a bitcell bank right (BB-R) quadrant 250.

[0007] In an SRAM, global input and output circuitry supporting write bitlines 150 and global read bitlines 155 includes latches for input and output data, and drivers for latched input data and output data. Local bitlines 220 run vertically in the memory bank and connect to the pass gates of each memory bitcell in a column of the memory bank, then into bitline multiplexing circuitry and local sense amplifier circuitry 115. The column multiplexing and local sense amplifier circuitry 115 connects one of the group bitlines to the global bitline write 150 in a write cycle, and to the global read bitline read 155 in a read operation. The local sense amplifier circuitry is used to amplify the voltage difference between the local bitline and the local bitline bar, and pre-charge or discharge the global bitline read based on the data read, which is ultimately provided to the input port of the output driver.

[0008] In Figure 2In this single level data partitioning design of the prior art, the global write bitlines 150 and the global read bitlines 155 each have a large data path run length to the farthest column multiplexing and sense amplifier circuitry 115, which increases the capacitance load and resistance. Since the capacitance load on the global write bitlines 150 is large, it requires a large capacitor to generate a negative voltage / boost for write assist operations, also increasing the write driver circuitry dynamic power. Since the capacitor required on the global read bitlines 155 is large, the read dynamic power and access time will also have large values. Clock pins 140 are provided to these two memories to provide the system clock to the memories.

[0009] It is known that access time optimization is challenging in lower technology nodes, typically referring to smaller channel lengths of transistors below 28 nm. Due to the increase in resistance and capacitance, the RC delay will typically also be large. The cross section of metal in the memory and the metal run length is small, so the resistance increases. Furthermore, these developments result in a decrease in the thickness of the capacitive gate oxide, so the capacitance increases, which results in a very large access time. Furthermore, with the decrease in gate oxide thickness, the gate load becomes larger compared to higher technology nodes, as exemplified by the known capacitance formula

[0010] C = εA / d [1]

[0011] where the capacitance is denoted (C), ε is the dielectric constant of the dielectric material, A is the area of one plate, and d is the distance between the plates (i.e., the thickness of the oxide).

[0012] Therefore, switching capacitance results in an increase in signal switching power. Signal switching power is the power consumed when changing the state of the input pins of the SRAM. Examples of input pins that affect this parameter are address, data, write enable, etc. Each gate of a transistor will have a gate capacitance load, and that gate will be connected as an input to another device, so switching the input of a gate device also switches the gate capacitance load of that device, commonly referred to as switching capacitance. Switching capacitance is the capacitance of the network that is pre-charged / discharged in the operation of the SRAM.

[0013] Therefore, switching capacitance results in an increase in switching power, since the capacitance load is directly connected to the energy consumption, which is E = (1 / 2)CV2, so if the capacitance will increase, that means it will also result in an increase in switching power.

[0014] Generally, two different schemes are known for data partitioning. In the first scheme, data information is decoded at each memory bank level and charge pumps are deployed at each memory bank, which results in larger silicon area. In the second scheme, data information is decoded at a global input-output (Gio) level and charge pumps are deployed once at the input-output level, which results in higher active power, where total active power is the power consumed in SRAM read / write operations.

[0015] The present inventors have recognized and appreciated the following impacts that affect memory access time. The active power of the SRAM depends on the per-bit power, where the per-bit power refers to the additional active power consumed while performing read / write operations in case of an increase in the number of bits configured for the SRAM. The total active power of the SRAM is the sum of the per-bit active power * total number of bits + static active power. To optimize the per-bit power, it is required to reduce the data path capacitance switching, as any dynamic power = C * V 2 f, where C is the total capacitance being pre-charged, V is the supply voltage, and f is the frequency. The present inventors have also recognized and appreciated that the access time and clock power are determined as the key optimization parameters for the memory. The internal clock distribution is one of the main factors of the access time. The clock switching power during the active operation in the memory is constant for a given word size, which the present inventors have determined as an important percentage of the total power consumption of the SRAM.

[0016] Therefore, there is a need for a memory and a method for reducing memory access time. SUMMARY

[0017] The present invention provides a memory and a method of building a memory architecture, as described in the appended claims. Particular embodiments of the present invention are set forth in the dependent claims. These and other aspects of the present invention will become evident to those skilled in the art from the following description, which is given by way of example in accordance with the embodiments described hereinafter.

[0018] According to a first aspect, there is provided a memory comprising a multi-level data path partitioning circuit, the memory comprising at least: a first data path level partition comprising at least one input configured to input data to or output data from the memory via at least one global input-output circuit; a second data path level partition configured to input data to or output data from the memory between one of a plurality of write assist circuits and one of the at least one global input-output circuit, wherein at least one of the plurality of write assist circuits and at least another of the plurality of write assist circuits are located in respective central portions of an upper bitcell memory array and a lower bitcell memory array; a third data path level partition (330) configured to input data to or output data from the memory between one of a plurality of column multiplexing circuitry and sense amplifier circuits and one of the plurality of write assist circuits.

[0019] In some examples, the memory comprises a center comprising a center portion, the center portion comprising the multi-level data path partitioning, and wherein the at least one upper bitcell memory array and the at least one lower bitcell memory array comprise bitcell memory arrays located on a first side of the memory and on a second side of the memory.

[0020] In some examples, at least one of the plurality of write assist circuits and at least another of the plurality of write assist circuits are located in respective sides of the central portions of the upper bitcell memory array and the lower bitcell memory array.

[0021] In some example embodiments, the memory can: wherein each of the plurality of write assist circuits is positioned equidistantly relative to the at least one global input-output circuit and respective ones of the plurality of column multiplexing circuitry and sense amplifier circuits.

[0022] In some example embodiments, the first data path level partition is positioned such that 40-60% of the at least one upper bitcell memory array is above the first data path partition and 60-40% of the at least one lower bitcell memory array is below the first data path partition.

[0023] In examples, wherein the first data path level partition is centered between the at least one upper bitcell memory array and the at least one lower bitcell memory array. It is additionally preferred that the location of the first data path level partition in the memory reduces global read bit length by 3 / 8.

[0024] In an example embodiment, the second data path hierarchical partition is located between the first data path hierarchical partition and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array. Preferably, the second data path hierarchical partition is located within 40-60% distance from the first data path hierarchical partition and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array. Further preferably, the second data path hierarchical partition is centrally located with respect to the first data path hierarchical partition (310) and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array.

[0025] In an example embodiment, the third data path hierarchical partition is located between the second data path hierarchical partition and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array. Preferably, the third data path hierarchical partition is located within 40-60% distance from the second data path hierarchical partition and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array. Further preferably, the third data path hierarchical partition is centrally located with respect to the second data path hierarchical partition (320) and a lower bitcell of the lower bitcell memory array or an upper bitcell of the upper bitcell memory array.

[0026] In an example embodiment, the memory is one of: static random access memory, SRAM; read only memory, ROM.

[0027] According to a second aspect, there is provided a method of constructing a memory comprising a plurality of data path partition circuits, the memory comprising: at least a first data path hierarchical partition; a second data path hierarchical partition located between one of a plurality of write assist circuits and one of at least one global input-output circuit and a third data path hierarchical partition located between one of a plurality of column multiplexing circuitry and sense amplifier circuits and one of the plurality of write assist circuits, wherein the method comprises: inputting data to or outputting data from the memory from an input of the first data path hierarchical partition via the at least one global input-output circuit; inputting or outputting data to or from the memory using the second data path hierarchical partition; inputting data to or outputting data from the memory using the third data path hierarchical partition. BRIEF DESCRIPTION OF DRAWINGS

[0028] Further details, aspects and embodiments of the application will be described, by way of example only, with reference to the drawings. In the drawings, like reference numbers are used to identify like or functionally similar elements. Elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale.

[0029] Figure 1 Two simplified known representations of memory architecture are shown.

[0030] Figure 2 A simplified known representation of memory architecture is shown, showing data paths and global read bit line paths and global write bit line paths.

[0031] Figure 3 A simplified representation of a three-level memory data path partitioning scheme with improved write assist circuitry deployment according to example embodiments is shown.

[0032] Figure 4 A representation of a three-level memory data path partitioning scheme according to example embodiments is shown, showing global read bit line paths and global write bit line paths and latched data paths and local bit line data paths.

[0033] Figure 5 A simplified flow diagram of a clock generation method in a multi-level memory partitioning scheme according to example embodiments is shown. DETAILED DESCRIPTION

[0034] The present inventors have recognized and appreciated that data paths in memory are a major contributor to switching power during active operations in memory. Switching power contributes to optimizing power consumption and can be used to extend battery life and reduce overall power consumption. In addition, the present inventors have recognized and appreciated that charge pumps used to provide negative boost voltage for write operations, if deployed locally or globally, result in an increase in silicon area and an increase in active power usage.

[0035] In response to these observations, the present inventors have recognized and appreciated that employing a partitioning scheme for data paths in memory ensures a reduction in the total length of the metal lines, which in turn reduces the total capacitance associated with the data paths. With the reduction in capacitance of the data paths, the rise / fall time of the data path clock signal will also be reduced, which will reduce the overall delay of the timing path. Thus, the data partitioning scheme also contributes to improving memory access time and cycle time. Partitioning of the data paths also contributes to reducing resistance, which provides an opportunity to reduce the amount of metal used in the data paths, e.g., reducing the width of the metal, while improving RC delay performance and setup time of data. In this context, the setup time of data to be stored in, for example, SRAM refers to the minimum time before the arrival of a clock active edge at which the data should maintain its state. Reduction in the width of the metal also contributes to reducing the total capacitance while keeping the length of the data paths unchanged. In this way, the resistance-capacitance (RC) delay will remain unchanged, but the capacitance will be reduced. The examples described herein partition the data paths into three levels.

[0036] In response to these observations, the inventors herein have further realized and appreciated that careful and strategic deployment of write assist circuitry at the second stage of the data path reduces the capacitance requirement to generate negative voltages for the write assist circuitry and also optimizes the RC delay of the data path signals. This helps to reduce the switching capacitance, thereby reducing the active power of the memory. Further, careful and strategic deployment of charge pump circuitry can be employed to provide the best gain in reducing the overall memory silicon area and dynamic power required to perform write operations.

[0037] Further, partitioning the internal data path into, for example, three tiers also includes the optimal deployment / location of write assist circuitry, which the skilled person appreciates is a complex implementation challenge.

[0038] The following detailed description is merely illustrative in nature and is not intended to limit the embodiments of the subject matter or the application and uses of such embodiments. As used herein, the word “example” means “serving as an example, instance, or illustration.” Any implementation described herein as an example is not necessarily to be construed as preferred or advantageous over other implementations.

[0039] Reference is now made to Figure 3 , according to example embodiments, a simplified representation of a three-tier memory data path partitioning scheme 300 with improved write assist circuitry deployment is shown. In particular, Figure 3 A three-tier memory is shown and described in more detail, in particular where a first partition data path tier 310 is employed to resolve a bitcell bank (BB) memory region into quadrants, i.e., a left upper quadrant 350, a right upper quadrant 352, a left lower quadrant 354, and a right lower quadrant 356. Two second partition data path tiers 320, 322 are employed to divide each quadrant into two further bitcell bank (BB) memory arrays. Similarly, four further ‘third’ partition data path tiers 330, 331, 332, 333 are employed to divide each half-quadrant into eight further bitcell bank (BB) memory arrays, resulting in 16 equal-sized bitcell bank (BB) memory arrays.

[0040] Reference is now made to Figure 4 , according to example embodiments, a more detailed representation of a three-tier memory data path partitioning scheme 400 is shown, showing global read bitline paths and global write bitline paths and latched data paths and local bitline data paths. As shown, the three-tier memory data path partitioning scheme 300 with improved write assist circuitry deployment includes decoders and control circuitry in a central portion 410 of the memory. Preferably, the memory is one or more of a static random access memory SRAM or a read-only memory ROM.

[0041] The decoder and control circuitry 410 has input latches for address input pins and other input pins, such as: write enable, chip select, margin control pins, decoding circuitry for the address, and an internal clock generation buffer. Typically, the write enable pin is used to select read and write operations in the memory. The chip select input is used to enable or disable operation of the memory, and the margin pin is used to control the margin. The decoding circuitry is preferably used to select a row in the memory by means of the address pins. The internal clock buffer is used to generate an internal clock signal that will march vertically.

[0042] As shown, the memory (300, 400) comprises a multi-level data path partitioning circuit, the memory (300, 400) comprising at least: a first data path level partition (310) comprising at least one input configured to input data to or output data from the memory (300, 400) via at least one global input-output circuit (360, 362); a second data path level partition (320) configured to input data to or output data from the memory (300, 400) between one of a plurality of write assist circuits (430, 431, 432, 433) and one of the at least one global input-output circuit (360, 362), wherein at least one of the plurality of write assist circuits (430, 431, 432, 433) and at least another of the plurality of write assist circuits (430, 431, 432, 433) are located in a central portion of an upper bitcell memory array (411, 412, 413, 414, 421, 422, 423, 424) and a lower bitcell memory array (415, 416, 417, 418, 425, 426, 427, 428), respectively; a third data path level partition (330) configured to input data to or output data from the memory (300, 400) between one of a plurality of column multiplexing circuitry and sense amplifier circuits (441, 442, 443, 444, 445, 446, 447, 448) and one of the plurality of write assist circuits (430, 431, 432, 433).

[0043] In an example embodiment, the memory (300, 400) includes a center portion (410) that includes a multi-tiered data path partition, and wherein the at least one upper bitcell memory array (411, 412, 413, 414, 421, 422, 423, 424) and the at least one lower bitcell memory array (415, 416, 417, 418, 425, 426, 427, 428) include bitcell memory arrays located on a first side (411, 412, 413, 414, 415, 416, 417, 418) of the memory (300, 400) and on a second side (421, 422, 423, 424, 425, 426, 427, 428) of the memory (300, 400). Preferably, at least one of the plurality of write assist circuits (430, 431, 432, 433) and at least another of the plurality of write assist circuits (430, 431, 432, 433) are located in respective sides of the center portion of the upper bitcell memory array (350, 352) and the lower bitcell memory array (354, 356), respectively. Further preferably, each of the plurality of write assist circuits (430, 431, 432, 433) are positioned equidistant with respect to the at least one global input-output circuit (360, 362) and a respective one of the plurality of column multiplexing circuitry and sense amplifier circuits (441, 442, 443, 444, 445, 446, 447, 448).

[0044] In the illustrated more detailed representation of the three-tier memory data path partition scheme 400, a first global input-output memory access circuit 360 is provided and includes a first (illustrated right-hand side) portion of the memory to provide a second global input-output memory access 362. The global input-output circuits 360, 362 are placed in the middle of the memory and are used to generate data signals for either the upper or lower half of the memory 300, 400. This placement of the global input-output circuits 360, 362 provides a first tier partition 310 of the data. This first tier partition directly reduces the global read bit line length 456 by 3 / 8, which reduces the RC delay by 3 / 16 and the metal load capacitance by 3 / 8, thereby reducing the read dynamic power and access time of the memory 300, 400. In an ideal implementation, a precise center placement of the first tier partition provides the greatest advantage. However, it has also been determined that a center placement with a 20% tolerance, i.e., placement at 40-60%, provides an acceptable advantage. In an example, the first data path tier partition (310) is positioned such that 40-60% of the memory array (415, 416, 417, 418, 425, 426, 427, 428, 411, 412, 413, 414, 421, 422, 423, 424) is above the first data path partition (310) and 60-40% of the memory array (411, 412, 413, 414, 421, 422, 423, 424, 415, 416, 417, 418, 425, 426, 427, 428) is below the first data path partition (310). Preferably, the first data path tier partition is centrally positioned in the memory 300, 400 between the at least one upper bit cell memory array (411, 412, 413, 414, 421, 422, 423, 424) and the at least one lower bit cell memory array (415, 416, 417, 418, 425, 426, 427, 428).

[0045] In the illustrated more detailed representation of the three-level memory data path partitioning scheme 400, the write drivers and charge pump circuitry 430, 431, 432, 433 are disposed in each quadrant substantially in the middle of the first and second halves of the memory (e.g., SRAM). That is, the write assist and charge pump circuit 430 is located in the LU quadrant 350, preferably in the center of the quadrant 350. The write assist and charge pump circuit 432 is located in the RU quadrant 352, preferably in the center of the quadrant 352. The write assist and charge pump circuit 431 is located in the LL quadrant 354, preferably in the center of the quadrant 354. The write assist and charge pump circuit 433 is located in the RL quadrant 356, preferably in the center of the quadrant 356. This disposition of the write assist and charge pump circuitry results in a reduced data line run length. It also can decode upper or lower half data selection, further reducing data switching capacitance. Thus, in this manner, on each side of the memory, the write and write assist circuitry is disposed in the middle of the upper and lower halves of the memory. That is, there is write and write assist circuitry in each of the LU, RU, LL, and RL quadrants of the memory 300, 400. At these locations, a second level of partitioning of the data 320 is performed, in which two global write bit lines are generated for each lower and upper half of the memory, which run up the side of the memory to the middle of each quadrant of the memory 300, 400. Again, in an ideal implementation, an exact center disposition of the second level of data partitioning provides the greatest advantage. However, it has also been determined that a center disposition within a 20% tolerance, i.e., disposed between 40-60%, provides an acceptable advantage. In an example embodiment, the second data path level of partitioning (320) is between the first data path level of partitioning (310) and the lower bitcell of the lower bitcell memory array (415, 416, 417, 418, 425, 426, 427, 428) or the upper bitcell of the upper bitcell memory array (411, 412, 413, 414, 421, 422, 423, 424). Preferably, the second data path level of partitioning (320) is within 40-60% distance from the first data path level of partitioning (310) and the lower bitcell of the lower bitcell memory array (415, 416, 417, 418, 425, 426, 427, 428) or the upper bitcell of the upper bitcell memory array (411, 412, 413, 414, 421, 422, 423, 424).In an example, the second data path hierarchical partition (320) is centrally located relative to the first data path hierarchical partition (310) and the lower bitcell memory arrays (415, 416, 417, 418, 425, 426, 427, 428) lower bitcells or the upper bitcell memory arrays (411, 412, 413, 414, 421, 422, 423, 424) upper bitcells.

[0046] In the illustrated more detailed representation of the three-level memory data path partitioning scheme 400, a third level data partition 330 is also performed in the middle of each eighth of the memory, where a global write bit line 452 connects local bit lines 454 of either the upper or lower half of the memory to column multiplexing circuitry and sense amplifier circuitry 441, 442, 443, 444, 445, 446, 447, 448. Here, the local bit lines 454 are connected to the drains of the pass gates of the bit cells. Again, in an ideal implementation, a precise center placement provides the greatest advantage. However, it has also been determined that a center placement with a 20% tolerance, i.e., placement within 40-60%, provides an acceptable advantage. In an example, the third data path hierarchical partition (330) is located between the second data path hierarchical partition (320) and the lower bitcell memory arrays (415, 416, 417, 418, 425, 426, 427, 428) lower bitcells or the upper bitcell memory arrays (411, 412, 413, 414, 421, 422, 423, 424) upper bitcells. Preferably, the third data path hierarchical partition (330) is located within 40-60% distance from the second data path hierarchical partition (320) and the lower bitcell memory arrays (415, 416, 417, 418, 425, 426, 427, 428) lower bitcells or the upper bitcell memory arrays (411, 412, 413, 414, 421, 422, 423, 424) upper bitcells. In another example, where the third data path hierarchical partition (330) is centrally located relative to the second data path hierarchical partition (320) and the lower bitcell memory arrays (415, 416, 417, 418, 425, 426, 427, 428) lower bitcells or the upper bitcell memory arrays (411, 412, 413, 414, 421, 422, 423, 424) upper bitcells.

[0047] In the examples described herein, the write and write assist circuitry 430, 431, 432, 433 are disposed at the second tier partition. In this way, the present inventors have determined that the amount of capacitance required to generate a negative voltage is reduced when the write and write assist circuitry 430, 431, 432, 433 must discharge the load of only one of the global write bit lines 452 and the local bit lines 454.

[0048] The present inventors have recognized and appreciated that the size of the charge pump capacitance required to generate a particular negative boost voltage depends on the total capacitance associated with the metal that will carry the negative boost voltage to the pass gate of the bit cell that is being written to data. In this case, it is the capacitance associated with one global write bit line 452 and one local bit line 454, and due to the three-tier memory data path partitioning scheme 300, 400, the capacitance has been reduced as compared to the known prior art of Figure 1 and Figure 2 In this way, the global write bit line 452 will only have a metal load of 1 / 8 the length of the memory height, while the local bit line 454 will have a metal load of 1 / 8 the length of the memory height and the drain capacitance load of the pass gate of the bit cell. Thus, the capacitance requirement for write assist is lower, which in turn reduces the silicon area and dynamic write power. Thus, in this way, following the methods described herein, the total capacitance load of the global write line 452 and the global read bit line 456 is reduced. These in turn reduce the time required to pre-charge the global write line 452 and the global read bit line 456, and help to reduce the cycle time of the memory.

[0049] In the illustrated more detailed representation of the three-tier memory data path partitioning scheme 400, the first global input-output memory access 360 and the first (illustrated right-hand side) portion of the memory to provide the second global input-output memory access 362 are disposed in the middle of the memory, and are used to Using latched data and address information generate data signals for either the upper or lower half of the memory. This is the first tier data partition 310.

[0050] There are two global read bit lines, one for the upper half of the memory and one for the lower half. For the upper half of the memory, the global read bit line will travel from the top column multiplex and LSA circuitry, through each column multiplex and LSA circuitry in between, and to the global input-output, and for the lower half of the memory, the global read bit line will travel from the bottom column multiplex and LSA circuitry, through each column multiplex and LSA circuitry in between, and to the global input-output.

[0051] While the examples described herein have been described with reference to three levels of data path partitioning resulting in 16 substantially equal area bitcell memory region storage areas, it is contemplated that other designs can be employed to benefit from the concepts described herein, such as partitioning the data path into, for example, 8 (roughly equal) areas, separated by various functional / circuitry access logic, etc. Similarly, it is contemplated that other designs can be employed to benefit from the concepts described herein, as will be appreciated by those skilled in the art, such as by way of example, 6 region or 32 region implementations, so long as the individual bitcell memory region and individual data path lengths are substantially equal in a number of, for example, three data path level partitioning schemes.

[0052] Reference is now made to Figure 5 , according to example embodiments, a simplified flowchart 500 is shown of constructing a memory including a multi-level data path partitioning circuit, such as the multi-level data path partitioning circuit 300, 400 in Figure 3 and 4 . The memory includes memory regions which are divided into quadrants, namely a top left quadrant 350, a top right quadrant 352, a bottom left quadrant 354 and a bottom right quadrant 356. Each quadrant is divided into two further bitcell bank (BB) memory arrays using two second partition data path levels 320, 322. Similarly, each half-quadrant is divided into eight further bitcell bank (BB) memory arrays using four further 'third' partition data path levels 330, 331, 332, 333, resulting in 16 equal size bitcell bank (BB) memory arrays.

[0053] The simplified flowchart 500 includes at 510 inputting data to or outputting data from the memory from an input of a first data path level partition via at least one global input output circuit, followed at 520 inputting data to or outputting data from the memory using a second data path level partition, and finally at 530 inputting or outputting data from the memory using a third data path level partition.

[0054] It is contemplated that the concepts described herein are suitable for all memories, particularly those which benefit from improved access. Of course, the methods are also applicable to other memory applications.

[0055] In the foregoing specification, the application has been described with reference to specific examples of embodiments of the application. It is evident, however, that various modifications and changes can be made thereto without departing from the scope of the application as set forth in the claims which follow. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

[0056] The connections herein are for example, any type of connection suitable to transfer signals from or to the respective nodes, units, or devices. Accordingly, unless implied or stated otherwise, a connection between nodes or units can be an electrical and / or physical connection. Connections can be shown or described as being direct connections, and / or indirect connections. Indirect connections can comprise intervening connections. In contrast, direct connections can be connections without intervening connections. Connections can be shown or described as being a single connection, and / or a plurality of connections. A plurality of connections can be shown or described as being a single bus, for example. However, it is to be understood that the various embodiments can be implemented in which the connections are implemented in a manner different than shown or described. For example, indirect connections can be used, for example, instead of direct connections, and vice versa. Further, multiple connections can be replaced with a single connection that transfers multiple signals, and vice versa. Likewise, a single connection that carries multiple signals can be separated into various different connections that carry the signals. Therefore, many options exist for transferring signals. Those skilled in the art will understand that the architectures shown or described herein are merely examples and that in fact many other architectures can be implemented which achieve the same functionality.

[0057] Any arrangement of components to achieve the same functionality is effectively 'associated' such that the desired functionality is achieved. Hence, any two components herein combined to achieve a particular functionality can be seen as 'associated with' each other such that the desired functionality is achieved, irrespective of architectures or intermediate components. Likewise, any two components so associated can also be viewed as being 'operably connected', or 'operably coupled', to each other to achieve the desired functionality.

[0058] Furthermore, those skilled in the art will recognize that boundaries between the functionality of the above described operations merely illustrative. The multiple operations can be combined into a single operation, a single operation can be separated into a plurality of operations and the ordering of operations can be rearranged. Also, alternative embodiments can include multiple instances of a particular operation, and the order of operations can be rearranged in various other embodiments. Additionally, the illustrated examples can be implemented as circuitry located within the same physical hardware, or separate physical hardware. In some examples, various components can be implemented within discrete or integrated circuitry, therefore the logical and physical package boundaries can vary from implementation to implementation. Also, a combination of hardware and software could be used to implement the same functionality as long as the desired functionality is achieved. Thus, other embodiments are within the scope of the present disclosure. Furthermore, many embodiments are described in terms of sequences of actions to be performed by, for example, elements of a computing device. It will be recognized that various actions described herein can be performed by specific circuits, for example, and / or by program instructions being executed by one or more processors. Additionally, these sequences of actions can be carried out on a real-time basis or in a non-real-time basis. The use of the terms "first", "second" and / or "third" does not limit the scope of these terms but merely identifies individual elements of an embodiment. Further, the use of the term "or" is inclusive, meaning and / or, unless the context clearly indicates otherwise. The use of the term "and" is both inclusive and exclusive, meaning and / or as well as mutually exclusive, unless the context clearly indicates otherwise.

[0059] Furthermore, examples, or portions thereof, can implemented as software or code that is executed by physical circuit systems, or as software or code that is converted into a logic representation of physical circuit systems, such as in the form of any suitable type of hardware description language, for example. Also, the present application is not limited to physical devices or units implemented in non-programmable hardware but can also be applied to programmable devices or units able to perform the desired sampling error and compensation by operating according to suitable program code, such as microcomputers, personal computers, notebooks, personal digital assistants, electronic games, automotive and other embedded systems, cellular telephones and various other wireless devices, which are collectively referred to herein as 'computer systems'. However, other modifications, changes and alternatives are possible. The description and drawings are, therefore, to be regarded as illustrative in nature rather than restrictive.

[0060] In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word 'comprising' does not exclude the presence of elements or steps other than those listed in a claim. Further, the word 'a' or 'an' preceding an element does not exclude the presence of a plurality of such elements. Furthermore, the usage of the words first, second and third, if any, does not limit the scope and does not require these words to indicate different stages or order of importance. The usage of the words 'first','second', 'third', etc., if any, are used merely to identify individual elements, and do not limit the scope of the application. The terms 'comprise', 'comprising', 'comprises' and 'comprised of' do not exclude the presence of other elements or steps than those listed in a claim. The terms 'a' and 'an' shall not be construed to mean 'one', unless expressly stated otherwise. The use of the term 'or' in the claims is used to mean 'and / or' unless specifically stated otherwise.

Claims

1. A memory comprising multi-level data path partitioning circuitry, characterized in that, The memory includes at least: A first data path hierarchical partition includes at least one input configured to input data to or output data from the memory via at least one global input-output circuit. A second data path hierarchical partition is configured to input data to or output data from the memory between one of a plurality of write auxiliary circuits and one of the at least one global input-output circuit, wherein at least one of the plurality of write auxiliary circuits and at least another of the plurality of write auxiliary circuits are respectively located in the central portions of the upper part-cell memory array and the lower part-cell memory array; and The third data path level partition is configured to input or output data to the memory between one of the plurality of column multiplexing circuit systems and sense amplifier circuits and one of the plurality of write auxiliary circuits.

2. The memory according to claim 1, characterized in that, The memory includes a central portion, the central portion including the multi-level data path partitions, and wherein the at least one upper part cell memory array and the at least one lower part cell memory array include bit cell memory arrays located on a first side and a second side of the memory.

3. The memory according to claim 2, characterized in that, The first data path hierarchical partition is positioned such that the bit cell memory array is within the range of 40-60% above the first data path partition and is positioned such that the bit cell memory array is within the range of 60-40% below the first data path partition.

4. The memory according to claim 3, characterized in that, The second data path hierarchical partition is located between the first data path hierarchical partition and the lower unit of the lower unit memory array or the upper unit of the upper unit memory array.

5. The memory according to claim 3, characterized in that, The third data path hierarchical partition is located between the second data path hierarchical partition and the lower unit of the lower unit memory array or the upper unit of the upper unit memory array.

6. A method for constructing a memory including multi-level data path partitioning circuits, characterized in that, The memory includes: Segment at least the first data path level; The second data path hierarchy is divided between one of a plurality of write auxiliary circuits and at least one of a global input-output circuit, and A third data path hierarchy is segmented between one of the multiple column multiplexing circuit systems and the sense amplifier circuit, and one of the multiple write auxiliary circuits. Data is input to or output from the memory from the input of the first data path hierarchical partition via at least one global input-output circuit; Data is input to or output to the memory using the second data path hierarchy partition, and The third data path level partition is used to input data to or output data from the memory.

7. The method for constructing a memory according to claim 6, characterized in that, The memory includes a central portion, the central portion including the multi-level data path partitions, and wherein the at least one upper part cell memory array and the at least one lower part cell memory array include bit cell memory arrays located on a first side and a second side of the memory.

8. The method for constructing a memory according to claim 7, characterized in that, At least one of the plurality of write auxiliary circuits and at least another of the plurality of write auxiliary circuits are respectively located on each side of the central portion of the upper part cell memory array and the lower part cell memory array.

9. The method for constructing a memory according to claim 6, characterized in that, Each of the plurality of write-assist circuits is equidistant from its counterpart in the at least one global input-output circuit and the plurality of column multiplexing circuit systems and sense amplifier circuits.

10. The method for constructing a memory according to claim 6, characterized in that, The second data path hierarchical partition is centered relative to the first data path hierarchical partition and the lower unit of the lower unit memory array or the upper unit of the upper unit memory array.

Images