Method and system for intelligently sealing and testing wafer in semiconductor chip

Abstract

The invention discloses an intelligent sealing test method and system for a wafer in a semiconductor chip, and relates to the technical field of semiconductor manufacturing, and the method comprises the steps: initializing a magneto-electric field cooperation parameter, optimizing the magneto-electric field cooperation parameter through a multi-target genetic algorithm, and driving core-shell nanoparticles to carry out the metallization filling of a high-precision through hole wafer, generating a wafer with a metalized through hole structure; based on the metalized through hole structure wafer, bonding parameters are generated through a laser Doppler frequency vibration spectrum analysis method, flip interconnection is achieved through a thermal ultrasonic virtual process, and a low-defect bonding wafer is generated; a finite element inversion algorithm is adopted, a stress distribution map of a bonding interface is established, an anti-thermal-stress packaging layer is constructed through an intelligent stress matching algorithm, and the low-defect bonding wafer is packaged; and through a multi-target genetic algorithm, magnetoelectric field cooperation parameters are optimized, core-shell nano-particles are driven to directionally deposit, and accurate control over the metallization filling process is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a wafer intelligent packaging and testing method and system in a semiconductor chip. BACKGROUND

[0002] In the field of semiconductor chip packaging and testing, a traditional method usually adopts a step-by-step process control strategy. A conventional technical solution mainly includes: obtaining wafer surface topography parameters through optical measurement equipment, performing stress simulation in combination with finite element analysis, and performing process optimization based on an empirical formula. In a specific implementation, a white light interferometer is used to measure surface characteristics, material parameters are obtained through thermal mechanical analysis, and a bonding process is implemented according to an industry standard. This method has formed a complete technical system, and its reliability has been verified by long-term practice.

[0003] However, the prior art has two main deficiencies in dealing with advanced packaging requirements: first, the traditional topography-stress analysis adopts a static processing method of step-by-step Z-score standardization and Pearson correlation, which is difficult to realize dynamic thickness compensation of a three-dimensional through-hole grid model; second, conventional thermal ultrasonic bonding process parameters are generated based on an empirical formula, and there is a lack of collaborative optimization of surface acoustic wave resonance spectrum data and thermal mechanical coupling fields. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a wafer intelligent packaging and testing method in a semiconductor chip to solve the problems of insufficient dynamic thickness compensation of a three-dimensional through-hole and inaccurate collaborative optimization of thermal ultrasonic bonding parameters.

[0006] To solve the above technical problems, the present application provides the following technical solutions: In a first aspect, the present invention provides a smart wafer packaging and testing method for semiconductor chips, comprising: acquiring three-dimensional morphology data, temperature distribution, and bonding stress data of the wafer surface; constructing a three-dimensional via mesh model using a data fusion algorithm and optimizing it using a PPO algorithm to generate a high-precision via wafer; initializing magnetoelectric field coordination parameters and optimizing the magnetoelectric field coordination parameters using a multi-objective genetic algorithm, and driving core-shell nanoparticles to metallize and fill the high-precision via wafer to generate a wafer with a metallized via structure; generating bonding parameters based on the metallized via wafer using laser Doppler frequency spectrum analysis and realizing flip-chip interconnection using thermo-ultrasonic virtual process to generate a low-defect bonded wafer; establishing a stress distribution map of the bonding interface using a finite element inversion algorithm, constructing a thermal stress resistant encapsulation layer using an intelligent stress matching algorithm, and encapsulating the low-defect bonded wafer; and predicting the thermal stress resistant encapsulation effect score based on the structural parameters of the encapsulated low-defect bonded wafer and the initial material parameters of the bonding interface using multi-physics coupling simulation and generating a test report.

[0007] As a preferred embodiment of the wafer intelligent packaging and testing method for semiconductor chips described in this invention, the steps for constructing a three-dimensional via network model using a data fusion algorithm are as follows: Z-score normalization was used to perform dimensionless processing on the three-dimensional morphology data of the wafer surface to generate a normalized morphology feature matrix; Based on the normalized morphology feature matrix and bond stress data, a morphology-stress correlation coefficient table is generated using the Pearson correlation coefficient. The Marching Cubes algorithm is used to transform the normalized topographic feature matrix into a triangular mesh, and thickness compensation is incorporated according to the topographic-stress correlation coefficient table to generate a stress-compensated three-dimensional through-hole mesh model.

[0008] As a preferred embodiment of the intelligent wafer packaging and testing method for semiconductor chips described in this invention, the step of optimizing by the PPO algorithm to generate high-precision through-hole wafers refers to using the PPO algorithm to optimize the geometric parameters of the three-dimensional through-hole mesh model, generating a through-hole parameter instruction set, and converting the through-hole parameter instruction set into device control signals through a G-code parser to drive the device to generate high-precision through-hole wafers.

[0009] As a preferred embodiment of the wafer intelligent packaging and testing method for semiconductor chips described in this invention, the magnetoelectric field coordination parameters include magnetic field strength, electric field strength, and core-shell nanoparticle concentration. The magnetoelectric field parameters were optimized using a multi-objective genetic algorithm, and core-shell nanoparticles were used to metallize and fill high-precision through-hole wafers, generating wafers with metallized through-hole structures. The steps are as follows. Initialize the magnetoelectric field co-parameters based on the geometric parameters of the three-dimensional through-hole mesh model; The non-dominated sorting and elitist preservation strategy are performed on the magnetoelectric field coordination parameter to generate a Pareto optimal solution set; The three-dimensional through-hole grid model of the core-shell nanoparticles is driven by the Pareto optimal solution set to generate a wafer of a metalized through-hole structure.

[0010] As a preferred scheme of the wafer intelligent packaging method in the semiconductor chip, the bonding parameters are generated by the laser Doppler frequency spectrum analysis method, and the flip-chip interconnection is realized by the thermal ultrasonic virtual process to generate a low-defect bonded wafer, and the steps are as follows, Based on the wafer of the metalized through-hole structure, the laser Doppler frequency spectrum analysis method is combined with the fast Fourier transform spectrum analysis to extract the surface acoustic wave resonance spectrum data; Based on the surface acoustic wave resonance spectrum data, the thermal-mechanical coupling finite element analysis method is used to identify the temperature field and stress field distribution to generate a set of thermal ultrasonic bonding process parameters; Based on the set of thermal ultrasonic bonding process parameters and the three-dimensional structure data of the wafer of the metalized through-hole structure, the surface wave activation algorithm is used to generate bonding parameters, and the bonding alignment parameter set is generated by the flip-chip interconnection alignment compensation algorithm; Based on the bonding alignment parameter set and the wafer surface temperature distribution, the multi-temperature zone progressive annealing method is used for gradient temperature regulation to generate a low-defect bonded wafer.

[0011] As a preferred scheme of the wafer intelligent packaging method in the semiconductor chip, the stress distribution map of the bonding interface is established by the finite element inversion algorithm, the thermal stress resistant packaging layer is constructed by the intelligent stress matching algorithm, and the low-defect bonded wafer is packaged, and the steps are as follows, The stress wave signal on the surface of the low-defect bonded wafer is obtained by SAW, the lattice distortion variable is measured by X-ray diffraction method, and the stress distribution map of the bonding interface is established by the finite element inversion algorithm; Based on the stress distribution map of the bonding interface, a three-dimensional stress field model containing the flip-chip bump, the metalized through-hole and the bonding interface is constructed by the discrete element analysis method; The initial material parameters of the bonding interface are obtained by the principal stress trajectory analysis method, nanoindentation test and thermal mechanical analyzer measurement of the three-dimensional stress field model of the bonding interface, and are optimized by the deep DDPG algorithm based on the Actor-Critic framework; Based on the optimized initial material parameters of the bonding interface, the packaging layer resistant to thermal stress is constructed by the variable density topology optimization algorithm, and the low-defect bonded wafer is packaged.

[0012] As a preferred scheme of the wafer intelligent encapsulation test method in the semiconductor chip, wherein: the anti-thermal stress packaging effect is evaluated by the multi-physical field coupling simulation, and the steps are as follows, The anti-thermal stress packaging effect score is predicted by the triple nonlinear coupling calculation of the Gaussian attenuation function, the error function and the hyperbolic tangent function through the multi-physical field nonlinear coupling scoring method. Based on the historical packaging test data, the packaging effect evaluation threshold is defined, and the anti-thermal stress packaging effect score is compared, the anti-thermal stress packaging effect is analyzed, and the test report is generated. The test report includes the anti-thermal stress packaging effect score, the structure parameters of the low-defect bonded wafer after packaging, the stress distribution map of the bonding interface and the packaging improvement suggestions.

[0013] In the second aspect, the application provides a wafer intelligent encapsulation test system in a semiconductor chip, which comprises a three-dimensional modeling module, a metal filling module, a flip-chip interconnection module, a packaging module and an evaluation module; the three-dimensional modeling module is used for collecting three-dimensional topographic data, temperature distribution and bonding stress data of a wafer surface, constructing a three-dimensional through-hole grid model by using a data fusion algorithm, and generating a high-precision through-hole wafer by optimizing through a PPO algorithm; the metal filling module is used for initializing magnetic-electric field synergy parameters, optimizing the magnetic-electric field synergy parameters through a multi-objective genetic algorithm, and driving core-shell nanoparticles to metalize and fill the high-precision through-hole wafer to generate a metalized through-hole structure wafer; the flip-chip interconnection module is used for generating bonding parameters by using a laser Doppler frequency vibration spectrum analysis method based on the metalized through-hole structure wafer, and realizing flip-chip interconnection by using a thermal ultrasonic virtual process to generate a low-defect bonded wafer; the packaging module is used for establishing a stress distribution map of a bonding interface by using a finite element inversion algorithm, constructing an anti-thermal stress packaging layer by using an intelligent stress matching algorithm, and packaging the low-defect bonded wafer; and the evaluation module is used for predicting an anti-thermal stress packaging effect score by using a multi-physical field coupling simulation based on the structure parameters of the low-defect bonded wafer after packaging and the initial material parameters of the bonding interface, and generating a test report.

[0014] In the third aspect, the application provides a computer device comprising a memory and a processor, and the memory stores a computer program, wherein: the computer program is executed by the processor to realize any step of the wafer intelligent encapsulation test method in the semiconductor chip according to the first aspect of the application.

[0015] In the fourth aspect, the application provides a computer readable storage medium, which stores a computer program, wherein: the computer program is executed by the processor to realize any step of the wafer intelligent encapsulation test method in the semiconductor chip according to the first aspect of the application.

[0016] The present application has the beneficial effects that: by Z-score standardization processing wafer surface three-dimensional topography data and generating normalized topography feature matrix, the non-dimensional integration of multi-source heterogeneous data is realized, and a reliable foundation is provided for stress compensation. By optimizing the magnetic and electric field coordination parameters through the multi-objective genetic algorithm and driving the core-shell nanoparticles to deposit directionally, the precise control of the metallization filling process is realized, the filling uniformity and structure stability are ensured by combining the Pareto optimal solution set, and the overall quality and reliability of the optimized wafer are improved. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Fig. 1 A flow chart of the wafer intelligent packaging and testing method in the semiconductor chip.

[0019] Fig. 2 A schematic diagram of the wafer intelligent packaging and testing system in the semiconductor chip.

[0020] Fig. 3 A flow chart of the three-dimensional via grid model construction.

[0021] Fig. 4 A flow chart of the metallization filling optimization. DETAILED DESCRIPTION

[0022] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.

[0023] In the following description, many specific details are set forth in order to provide a thorough understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the connotation of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0024] Secondly, the "one embodiment" or "embodiment" referred to herein means that the specific features, structures or characteristics can be included in at least one implementation of the present application. "In one embodiment" appearing in different places in the specification does not mean the same embodiment, nor is it an independent or selective embodiment that excludes other embodiments.

[0025] REFERENCE Figs. 1-4 For one embodiment of the present application, the embodiment provides a wafer intelligent packaging and testing method in a semiconductor chip, comprising the following steps: S1, collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional via grid model using a data fusion algorithm, and optimize it through a PPO algorithm to generate a high-precision via wafer; The wafer surface three-dimensional topography data includes surface roughness, step height, aperture size and position deviation.

[0026] The bonding stress data includes shear stress, normal contact stress and thermal mismatch stress.

[0027] It should be noted that the wafer surface three-dimensional topography data is obtained by scanning with a white light interferometer, the surface roughness is measured with a non-contact optical profiler, the step height is obtained with a high-precision laser displacement sensor, and the aperture size and position deviation are captured with an automatic optical inspection device based on machine vision. The shear stress is measured with a cross-beam stress sensor, the normal contact stress is captured with a thin film pressure sensor array, and the thermal mismatch stress is calculated with an X-ray diffraction stress analyzer combined with the thermal expansion coefficient difference.

[0028] The wafer surface three-dimensional topography data is dimensionless processed by Z-score standardization to generate a normalized topography feature matrix; Further, the wafer surface three-dimensional topography data is processed by Z-score standardization. The topography data of each dimension is subtracted from the mean value of the current dimension and divided by the standard deviation to eliminate the dimensional difference and retain the distribution characteristics of the three-dimensional topography data. The mean value of each dimension after processing is zero and the standard deviation is 1, forming a normalized topography feature matrix with uniform dimensions.

[0029] Based on the normalized topography feature matrix and the bonding stress data, the topography-stress correlation coefficient table is generated by Pearson correlation coefficient; Further, the normalized topography feature matrix and the bonding stress data are matched according to the sampling point position, and the Pearson correlation coefficient of the topography feature matrix and the bonding stress data is identified by the covariance method to quantify the linear correlation between the wafer surface three-dimensional topography data and the bonding stress data, and finally generate the topography-stress correlation coefficient table; The normalized topography feature matrix is converted to a triangular mesh using the Marching Cubes algorithm, and the stress compensation is implanted according to the topography-stress correlation coefficient table to generate a three-dimensional via grid model with stress compensation.

[0030] Further, the normalized topography feature matrix is converted into a triangular mesh by the Marching Cubes algorithm, which establishes a regular cubic mesh in three-dimensional space and interpolates the isosurface based on the topography feature value. The topography-stress correlation coefficient table is used to determine the compensation coefficient of each mesh vertex. After weight distribution and accumulation of the Pearson correlation coefficient, it is converted into a thickness compensation amount. The thickness compensation amount is implanted into the triangular mesh through vertex displacement, so that the triangular mesh automatically adjusts the geometric morphology in the stress-sensitive area, and finally generates a three-dimensional via mesh model with stress compensation.

[0031] The PPO algorithm is used to optimize the geometric parameters of the three-dimensional via mesh model, and a via parameter instruction set is generated.

[0032] Further, the three-dimensional via mesh model with stress compensation is used as the input of the PPO algorithm, and the via inclination angle, aperture compensation amount, side wall thickness and filling density are used as the optimized geometric parameters. The PPO algorithm establishes a strategy network and a value network based on the three-dimensional via mesh model with stress compensation. The strategy network outputs the geometric parameter adjustment action, and the value network evaluates the state value. In the iterative optimization process, the strategy network generates a geometric parameter adjustment scheme, calculates the immediate reward based on the stress distribution and structural strength, and the value network evaluates the state value. Finally, a via parameter instruction set is obtained, which minimizes the thermal mismatch stress and maximizes the structural strength.

[0033] The via parameter instruction set is converted into a device control signal through a G code parser, and a high-precision via wafer is generated by driving the device.

[0034] Further, after the via parameter instruction set is input into the G code parser, the parser decomposes the via parameter instruction set into coordinate movement instructions and machining parameters executable by the machine tool according to the ISO 6983 standard. The via inclination angle is converted into a rotary axis angle instruction, the aperture compensation amount is mapped into a tool radial compensation value, the side wall thickness generates an axial feed rate parameter, and the filling density is converted into a laser power or deposition rate control signal. The parsed device control signal is transmitted to the servo driver of the machining equipment through the field bus, driving the spindle motor, linear motor and auxiliary actuator to act in coordination, accurately executing the via machining process on the wafer surface, and finally generating a high-precision via wafer.

[0035] S2, initialize the magneto-electric field synergy parameter, optimize the magneto-electric field synergy parameter through a multi-objective genetic algorithm, and drive the core-shell nanoparticles to metalize and fill the high-precision via wafer to generate a wafer with a metalized via structure; Based on the geometric parameters of the three-dimensional via mesh model, the magneto-electric field synergy parameter is initialized; the magneto-electric field synergy parameter includes the magnetic field strength, the electric field strength and the core-shell nanoparticle concentration; The non-dominated sorting and elitist strategy are performed on the magneto-electric field synergy parameters to generate a Pareto optimal solution set; Further, the non-dominated sorting is the core operation of the multi-objective genetic algorithm. By comparing the objective function values of individuals in the population, individuals that are not simultaneously dominated by other individuals in all objectives are divided into the first front level, and then subsequent front levels are determined recursively. The elitist strategy selects individuals with higher front levels into the next generation during each generation evolution process, while preserving some excellent parent individuals to prevent the loss of high-quality genes. In the optimization process of magneto-electric field synergy parameters, the multi-objective genetic algorithm first initializes a population containing combinations of magnetic field strength, electric field strength, and core-shell nanoparticle concentration. In each iteration, the multi-objective genetic algorithm performs non-dominated sorting on the current population, divides the population individuals into several non-dominated front levels according to the two optimization objectives of minimizing thermal mismatch stress and maximizing structural strength. Then, the elitist strategy is used to select candidate solutions from the individuals with the highest front levels into the next generation in proportion, while preserving some parent individuals with special advantages. After generating new individuals through crossover and mutation operations, the multi-objective genetic algorithm re-evaluates and updates the non-dominated front level division. After multiple iterations, the population gradually converges to the Pareto front, and finally outputs the Pareto optimal solution set of the magneto-electric field synergy parameters that achieve the optimal balance between thermal mismatch stress and structural strength.

[0036] The Pareto optimal solution set is used to drive the core-shell nanoparticles to deposit in a three-dimensional via grid model to generate a wafer of metalized via structures.

[0037] Further, the magnetic field strength, electric field strength, and core-shell nanoparticle concentration parameters included in the Pareto optimal solution set are directly applied to the deposition process control. The magnetic field strength parameter adjusts the current output of the electromagnetic field generating device to establish a specific magnetic field distribution in the deposition cavity; the electric field strength parameter controls the voltage difference between the electrodes to form a directional electric field; and the core-shell nanoparticle concentration parameter adjusts the supply rate of the nanoparticle suspension. Under the synergistic action of the magnetic field and the electric field, the core-shell nanoparticles move along the trajectory set by the stress compensation geometry of the three-dimensional via grid model, and accurately deposit according to the spatial structure of the three-dimensional via grid model. Finally, a required metalized structure is formed in the via, and the preparation of the wafer of metalized via structures is completed.

[0038] S3, based on the wafer of metalized via structures, generate bonding parameters through laser Doppler frequency spectrum analysis, and realize flip-chip interconnection using thermal ultrasound virtual process to generate a low-defect bonded wafer; Based on the wafer of metalized via structures, laser Doppler frequency spectrum analysis combined with fast Fourier transform spectrum analysis is used to extract surface acoustic wave resonance spectrum data; Further, based on the metallized via structure wafer, first, the laser Doppler vibro-spectrum analysis method is used to apply a standard sweep excitation of 10-50 MHz to the surface of the metallized via structure wafer and collect the vibration displacement signal, then the fast Fourier transform spectrum analysis is used to convert the vibration displacement signal in the frequency domain to generate the frequency spectrum characteristics. According to the frequency spectrum characteristics, the scanning frequency of the laser Doppler vibro-spectrum analysis method is adjusted in real time, and finally the three-point calibration method is used to calibrate the output surface acoustic wave resonance spectrum data. The laser Doppler vibro-spectrum analysis method provides the vibration displacement signal in the extraction process, and the fast Fourier transform spectrum analysis is responsible for the frequency spectrum analysis, and the two are realized through real-time interaction to achieve cooperative optimization.

[0039] Based on the surface acoustic wave resonance spectrum data, the thermal-mechanical coupling finite element analysis method is used to identify the temperature field and stress field distribution, and the thermal ultrasonic bonding process parameter set is generated; Further, the surface acoustic wave resonance spectrum data is used as input, and by solving the boundary value of the coupled heat conduction equation and elastic mechanics equation, the temperature field and stress field distribution of the metallized via structure wafer at the bonding interface is identified, and finally the thermal ultrasonic bonding process parameter set is generated.

[0040] It should be noted that the coupled solving process of the heat conduction equation and the elastic mechanics equation is as follows: the surface acoustic wave resonance spectrum data is used as the boundary condition, the heat conduction equation is used to establish the temperature field control equation based on the Fourier law, and the thermal conductivity parameter of the metallized via structure wafer is considered; the elastic mechanics equation describes the stress-strain relationship caused by thermal expansion through the generalized Hooke's law, and the stress distribution is solved by combining the temperature field calculation result. Two equations are iteratively solved through temperature-stress coupling terms, and the temperature field is updated first and then the stress field is calculated in each iteration until convergence. Finally, the numerical solution that completely describes the temperature field and stress field distribution at the bonding interface is output.

[0041] Based on the thermal ultrasonic bonding process parameter set and the three-dimensional structure data of the metallized via structure wafer, the surface wave activation algorithm is used to generate the bonding parameters, and the flip-chip interconnection alignment compensation algorithm is used to generate the bonding alignment parameter set.

[0042] Further, the surface wave activation algorithm is used to calculate the propagation characteristics and energy distribution of the surface acoustic wave at the bonding interface, so as to determine the optimal bonding pressure distribution area and ultrasonic vibration mode parameters. The flip-chip alignment compensation algorithm reads the via position coordinates in the three-dimensional structure data of the metallized via structure wafer, calculates the position offset compensation amount in combination with the bonding pressure distribution area, and outputs a bonding alignment parameter set containing a lateral displacement correction value and an angle adjustment amount. The flip-chip alignment compensation algorithm is a numerical calculation method for precise alignment. By analyzing the via position coordinates in the three-dimensional structure data of the metallized via structure wafer, in combination with the thermal ultrasonic bonding process parameter set, the lateral displacement amount and the rotation angle that need to be compensated are identified. At the same time, the geometric transformation principle is used to establish the mapping relationship between the actual position and the theoretical position of the via, and the bonding alignment parameter set is output.

[0043] It should be noted that the three-dimensional structure data of the metallized via structure wafer includes via three-dimensional geometric dimensions, metal plating layer thickness, material properties and position coordinates. The acquisition method is to measure the via morphology by an optical interferometer, and to perform tomographic scanning by EDX composition analysis and X-ray diffraction method.

[0044] Based on the bonding alignment parameter set and the wafer surface temperature distribution, a multi-temperature zone progressive annealing method is used for gradient temperature regulation to generate a low-defect bonded wafer.

[0045] Further, the displacement correction value and the angle adjustment amount provided by the bonding alignment parameter set are converted into coordinate mapping of the heating area, and in combination with the wafer surface temperature distribution data, a spatial temperature gradient is established in the multi-temperature zone heating device. The temperature gradient regulates the thermal field distribution of each stage of annealing, and the annealing process is divided into three stages of heating, holding and cooling: in the heating stage, the heating rate of each temperature zone is adjusted according to the bonding alignment parameter set, so that the high stress area is preferentially heated; in the holding stage, the temperature gradient distribution is maintained, so that a uniform intermetallic compound is formed at the bonding interface; in the cooling stage, the cooling curve of each temperature zone is controlled to match the difference in thermal expansion coefficient of different regions. The entire process dynamically adjusts the temperature zone power through real-time feedback of the wafer surface temperature distribution data, and finally realizes a low-defect bonded wafer with stress release and interface optimization.

[0046] S4, a finite element inversion algorithm is used to establish a stress distribution map of the bonding interface, and an intelligent stress matching algorithm is used to construct a thermal stress resistant packaging layer to package the low-defect bonded wafer; The SAW is used to obtain the stress wave signal of the low-defect bonded wafer surface, the X-ray diffraction method is used to measure the lattice distortion amount, and the finite element inversion algorithm is used to establish a stress distribution map of the bonding interface; The specific process of establishing the stress distribution map of the bonding interface by the finite element inversion algorithm is as follows: firstly, a three-dimensional grid discrete system is constructed according to the actual geometric size of the low-defect bonded wafer, and the stress wave signal and the lattice distortion variable are obtained. The Navier-Cauchy wave equation and the stress-strain relationship of the generalized Hooke's law are solved by the finite element inversion algorithm, and the conjugate gradient method is used for iterative optimization of the stress tensor distribution of the grid node. After each iteration, the root mean square error of the calculated stress wave field and the measured stress wave field is compared, and the calculation is terminated when the error is lower than the stress convergence threshold (defined according to the SAW sensor measurement accuracy and X-ray diffraction error analysis, the value range is 0.05-0.15MPa). The final output of the bonding interface stress distribution map contains complete three-dimensional stress tensor information, and the first principal stress, shear stress concentration area and stress gradient change characteristics are displayed in the form of color cloud picture. The spatial resolution of the map matches the detection accuracy of the SAW sensor, and can accurately identify the micron-scale stress abnormal area.

[0047] Based on the stress distribution map of the bonding interface, a three-dimensional stress field model including flip-chip bumps, metallized vias and bonding interfaces is constructed by using the discrete element analysis method.

[0048] Further, firstly, the flip-chip bumps are decomposed into a cluster of spherical units, the metallized vias are converted into a chain of cylindrical units, and the bonding interface generates a layer of contact surface units by using the discrete element analysis method. The normal force between units is calculated by Hertz contact theory, the critical slip friction force between contact surfaces is calculated by Coulomb friction model, and the initial stress field is applied in combination with the stress distribution map. Under the condition of thermal-mechanical coupling, the displacement and deformation of the discrete element are iteratively calculated according to Newton's law of motion, and the contact network and stress transmission path are dynamically updated. The final output of the three-dimensional stress field model presents the contact stress of the flip-chip bump, the stress concentration area inside the via structure and the shear stress distribution of the bonding interface.

[0049] It should be noted that the bonding interface refers to the intermetallic compound connection layer formed by the thermal ultrasonic bonding process of the wafer and the substrate; Based on the three-dimensional stress field model, the high stress aggregation area coordinates of the bonding interface are identified by the principal stress trajectory analysis method; Further, the stress trajectory analysis method first calculates the magnitude and direction of the principal stress at each grid node, then generates a cluster of principal stress trajectory lines by using the numerical streamline tracking technology, identifies the high stress aggregation area on the bonding interface, extracts the center point coordinates of the high stress aggregation area as the key position marker, and outputs them in the form of a three-dimensional coordinate list, accurately marking the spatial position of the dangerous area on the bonding interface where the stress value exceeds 85% of the material yield strength.

[0050] Based on the high stress aggregation area coordinates of the bonding interface, the initial material parameters of the bonding interface are measured by nanoindentation test and thermal mechanical analyzer; Further, the high stress concentration area coordinates guide the probe positioning of the nanoindentation tester, and the local elastic modulus and hardness are obtained by nanoindentation testing at the marked position; the thermal mechanical analyzer performs point thermal expansion coefficient testing according to the high stress concentration area coordinates. The two measurement results are combined to generate the initial material parameters of the complete bonding interface of the key area of the bonding interface.

[0051] The initial material parameters of the bonding interface include the elastic modulus, the thermal expansion coefficient, the Poisson's ratio, and the fracture toughness.

[0052] With the objectives of minimizing the thermal mismatch stress and maximizing the structural strength, a deep DDPG algorithm based on the Actor-Critic framework is used to optimize the initial material parameters of the bonding interface. Further, the deep DDPG algorithm based on the Actor-Critic framework takes the initial material parameters of the bonding interface as the state input, the Actor network outputs the material parameter adjustment action, and the Critic network evaluates the comprehensive benefits of the thermal mismatch stress and the structural strength. The deep DDPG algorithm stores the state-action-reward samples in the experience replay buffer, and uses a double network structure to suppress the overestimation bias. In each iteration, the Actor network generates optimization suggestions for the elastic modulus, Poisson's ratio, and other parameters, and the Critic network calculates the Q value to guide the policy update. The optimization process continues until the thermal mismatch stress reduction rate and the structural strength improvement rate reach a balance, and the final optimized initial material parameters of the bonding interface are obtained. For example, the optimized initial material parameters of the bonding interface can reduce the stress concentration coefficient of the bonding interface by more than 35% under 300℃ thermal cycling.

[0053] Based on the optimized initial material parameters of the bonding interface, a thermal stress-resistant packaging layer is constructed through a variable density topology optimization algorithm, and the low-defect bonded wafer is packaged.

[0054] Further, the optimized initial material parameters of the bonding interface are taken as input, and the variable density topology optimization algorithm establishes a density field within the packaging layer design domain, with thermal conductivity and elastic modulus as constraint conditions, and updates the unit density through SIMP iteration, so as to minimize the maximum von Mises stress of the packaging layer under thermal load. Sensitivity analysis is used to guide the evolution of the density field during the optimization process, and finally a thermal stress-resistant packaging layer with gradient porosity structure is generated, and the low-defect bonded wafer is packaged. The packaging layer is integrated with the low-defect bonded wafer through a physical vapor deposition process, for example, the optimized packaging structure can reduce the thermal mismatch stress peak by 40% while maintaining more than 98% structural integrity.

[0055] It should be noted that the physical vapor deposition process is a technology that deposits materials in the form of atoms or molecules on the surface of a substrate to form a thin film through vacuum evaporation, sputtering, or arc discharge.

[0056] S5, based on the structure parameters of the packaged low-defect bonded wafer and the initial material parameters of the bonding interface, and through multi-physical field coupling simulation, the anti-thermal stress packaging effect is evaluated, and a test report is generated.

[0057] The structure parameters of the packaged low-defect bonded wafer include unit size, wall thickness, and geometric profile tolerance.

[0058] Based on the structure parameters of the packaged low-defect bonded wafer and the material performance parameters of the packaging layer, a multi-physical field nonlinear coupling scoring method is adopted, and through the triple nonlinear coupling calculation of the Gaussian attenuation function, the error function, and the hyperbolic tangent function, the anti-thermal stress packaging effect score is predicted, and the expression is: ; Wherein, is the anti-thermal stress packaging effect score, is the unit size of the packaged low-defect bonded wafer, is the wall thickness of the packaged low-defect bonded wafer, is the geometric profile tolerance of the packaged low-defect bonded wafer, is the stress concentration coefficient of the packaged low-defect bonded wafer, is the stress sensitivity coefficient of the packaged low-defect bonded wafer, is the thermal mismatch tolerance threshold, is the thermal expansion coefficient of the optimized bonding interface, is the thermal expansion coefficient of the packaged low-defect bonded wafer, is the critical fracture stress of the optimized bonding interface, is the measured stress of the bonding interface at the high stress aggregation coordinate point, is the transverse coordinate of the high stress aggregation area of the bonding interface, is the longitudinal coordinate of the high stress aggregation area of the bonding interface, is the depth coordinate of the high stress aggregation area of the bonding interface.

[0059] Further, based on the structure parameters of the packaged low-defect bonded wafer and the material performance parameters (thermal expansion coefficient ) of the packaging layer, firstly, the stress concentration coefficient of the packaged low-defect bonded wafer is calculated. The stress concentration effect is evaluated by the formula , wherein is the stress sensitivity coefficient of the packaged low-defect bonded wafer, which is used to quantify the sensitivity of stress concentration to reliability. The influence of the difference in the thermal expansion coefficient is calculated by , wherein is the thermal expansion coefficient of the optimized bonding interface, The coefficient of thermal expansion of the low-defect bonded wafer after packaging, The thermal mismatch tolerance threshold reflects the upper limit of the allowable thermal expansion difference. The hyperbolic tangent function part is used to evaluate the stress safety margin of the high-stress accumulation area (lateral coordinate , longitudinal coordinate , and depth coordinate ) of the bonding interface, the critical fracture stress of the optimized bonding interface, and the measured stress of the corresponding coordinate point. Finally, the output values of the Gaussian attenuation function, the error function, and the hyperbolic tangent function are multiplied in turn to complete the triple nonlinear coupling calculation, generating a thermal stress resistance packaging effect score in the range of 0 to 1. The higher the score , the better the comprehensive performance of the packaging structure in terms of stress concentration suppression, thermal matching optimization, and fracture risk avoidance under thermal-mechanical coupling conditions.

[0060] It should be noted that the stress concentration coefficient of the low-defect bonded wafer after packaging ranges from 1.0 to 3.0, with a larger value indicating a higher degree of stress concentration.

[0061] The stress sensitivity coefficient of the low-defect bonded wafer after packaging ranges from 0.5 to 2.0 MPa, with a smaller value indicating that the material is more sensitive to stress concentration.

[0062] The coefficient of thermal expansion of the optimized bonding interface ranges from 4.0 × 10 -6 / K to 8.0 × 10 -6 / K, depending on the composition of the bonding material.

[0063] The coefficient of thermal expansion of the low-defect bonded wafer after packaging ranges from 2.0 × 10 -6 / K to 6.0 × 10 -6 / K.

[0064] The thermal mismatch tolerance threshold is defined based on the statistical distribution of the thermal cycle failure critical value in historical packaging reliability test data, and its value ranges from 0.5 × 10 -6 / K to 2.0 × 10 -6 / K.

[0065] Based on historical packaging test data, the packaging effect evaluation threshold S1 is defined; It should be noted that historical packaging test data includes thermal cycle life, bonding interface peel strength, crack propagation rate, and other performance parameters. The packaging effect evaluation threshold S1 ranges from 0.65 to 0.82.

[0066] When ≥S1, it is considered that the anti-thermal stress packaging effect has thermal mechanical stability and structural reliability; For example, the anti-thermal stress packaging effect score reaches 0.78, and the complete bonding interface remains intact after 1000 times of -55℃~150℃ thermal cycling.

[0067] When <S1, it is considered that the anti-thermal stress packaging effect has thermal stress concentration or bonding interface failure risk, and the wall thickness distribution or geometric tolerance needs to be optimized for process iteration.

[0068] For example, the anti-thermal stress packaging effect score of the packaging sample is 0.62, and the bonding interface cracks after 500 times of thermal cycling, and the wall thickness needs to be adjusted from 50μm to 65μm and the geometric tolerance needs to be re-optimized.

[0069] According to the packaging effect evaluation results, a test report is generated.

[0070] The test report includes the anti-thermal stress packaging effect score, the structural parameters of the low-defect bonded wafer after packaging, the stress distribution map of the bonding interface, and the packaging improvement suggestions.

[0071] The embodiment also provides a wafer intelligent packaging and testing system for semiconductor chips, which comprises a three-dimensional modeling module, a metal filling module, a flip-chip interconnection module, a packaging module, and an evaluation module. The three-dimensional modeling module is used to collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional through-hole grid model by using a data fusion algorithm, and generate a high-precision through-hole wafer by optimizing through a PPO algorithm. The metal filling module is used to initialize magnetic-electric field synergy parameters, optimize the magnetic-electric field synergy parameters by using a multi-objective genetic algorithm, and drive core-shell nanoparticles to metalize the high-precision through-hole wafer to generate a metalized through-hole structure wafer. The flip-chip interconnection module is used to generate bonding parameters by using a laser Doppler frequency spectrum analysis method based on the metalized through-hole structure wafer, and realize flip-chip interconnection by using a thermal ultrasonic virtual process to generate a low-defect bonded wafer. The packaging module is used to establish a stress distribution map of the bonding interface by using a finite element inversion algorithm, construct an anti-thermal stress packaging layer by using an intelligent stress matching algorithm, and package the low-defect bonded wafer. The evaluation module is used to predict the anti-thermal stress packaging effect score by using a multi-physical field coupling simulation based on the structural parameters of the low-defect bonded wafer after packaging and the initial material parameters of the bonding interface, and generate a test report.

[0072] The embodiment also provides a computer device suitable for the wafer intelligent sealing method in the semiconductor chip, including a memory and a processor; the memory is used to store computer executable instructions, and the processor is used to execute the computer executable instructions to realize the wafer intelligent sealing method in the semiconductor chip proposed in the above embodiment.

[0073] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected through a system bus. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is used to communicate with external terminals in a wired or wireless manner. The wireless manner can be achieved through WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, a trackball or a touchpad arranged on the shell of the computer device, or an external keyboard, a touchpad or a mouse, etc.

[0074] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to realize the wafer intelligent sealing method in the semiconductor chip proposed in the above embodiment. The storage medium can be realized by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0075] To sum up, the application realizes the non-dimensional integration of multi-source heterogeneous data by Z-score standardization processing of wafer surface three-dimensional topography data and generating a normalized topography feature matrix, and provides a reliable foundation for stress compensation. Through multi-objective genetic algorithm optimization of magnetoelectric field synergy parameters and driving of core-shell nanoparticle directional deposition, precise control of the metalization filling process is realized, the filling uniformity and structure stability are ensured in combination with the Pareto optimal solution set, and the overall quality and reliability of the optimized wafer are improved.

[0076] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application and are not limiting. Although the present application has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the technical solutions of the present application, and they should be covered in the scope of the claims of the present application.

Claims

1. A wafer intelligent packaging and testing method for semiconductor chips, characterized in that: include, Three-dimensional morphology data, temperature distribution and bonding stress data of wafer surface are collected, a three-dimensional through-hole mesh model is constructed using a data fusion algorithm, and optimized using the PPO algorithm to generate a high-precision through-hole wafer; Initialize the magnetoelectric field coordination parameters, optimize the magnetoelectric field coordination parameters through a multi-objective genetic algorithm, and drive core-shell nanoparticles to metallize and fill high-precision through-hole wafers to generate wafers with metallized through-hole structures. Based on the metallized through-hole structure wafer, bonding parameters are generated by laser Doppler frequency vibration spectrum analysis, and flip-chip interconnection is realized by thermo-ultrasonic virtual process to generate low-defect bonded wafers. The finite element inversion algorithm is used to establish the stress distribution map of the bonding interface, and a thermal stress resistant encapsulation layer is constructed through an intelligent stress matching algorithm to encapsulate the low-defect bonding wafer. Based on the structural parameters of the low-defect bonded wafer after packaging and the initial material parameters of the bonding interface, the thermal stress resistance packaging effect score is predicted by multiphysics coupling simulation and a test report is generated.

2. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 1, characterized in that: The steps for constructing a three-dimensional via network model using a data fusion algorithm are as follows: Z-score normalization was used to perform dimensionless processing on the three-dimensional morphology data of the wafer surface to generate a normalized morphology feature matrix; Based on the normalized morphology feature matrix and bond stress data, a morphology-stress correlation coefficient table is generated using the Pearson correlation coefficient. The Marching Cubes algorithm is used to transform the normalized topographic feature matrix into a triangular mesh, and thickness compensation is incorporated according to the topographic-stress correlation coefficient table to generate a stress-compensated three-dimensional through-hole mesh model.

3. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 2, characterized in that: The process of optimizing the PPO algorithm to generate high-precision through-hole wafers refers to using the PPO algorithm to optimize the geometric parameters of the three-dimensional through-hole mesh model, generating a through-hole parameter instruction set, and then using a G-code parser to convert the through-hole parameter instruction set into equipment control signals to drive the equipment to generate high-precision through-hole wafers.

4. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 1, characterized in that: The magnetoelectric field synergistic parameters include magnetic field strength, electric field strength, and core-shell nanoparticle concentration; The magnetoelectric field parameters were optimized using a multi-objective genetic algorithm, and core-shell nanoparticles were used to metallize and fill high-precision through-hole wafers, generating wafers with metallized through-hole structures. The steps are as follows. Initialize the magnetoelectric field co-parameters based on the geometric parameters of the three-dimensional through-hole mesh model; A Pareto optimal solution set is generated by applying a non-dominated sorting and elite retention strategy to the magnetoelectric field cooperative parameters. Pareto optimal solution set is used to drive the directional deposition of core-shell nanoparticles on a three-dimensional through-hole mesh model to generate wafers with metallized through-hole structures.

5. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 4, characterized in that: The steps for generating bonding parameters through laser Doppler frequency spectroscopy analysis and achieving flip-chip interconnection using thermo-ultrasonic virtual technology to generate low-defect bonded wafers are as follows. Based on a metallized through-hole structure wafer, laser Doppler frequency vibration spectrum analysis combined with fast Fourier transform spectrum analysis is used to extract surface acoustic wave resonance spectrum data. Based on surface acoustic wave resonance spectrum data, the temperature and stress field distributions are identified by thermomechanical coupling finite element analysis, and a set of thermo-ultrasonic bonding process parameters is generated. Based on the thermo-ultrasonic bonding process parameter set and the three-dimensional structural data of the metallized through-hole structure wafer, the bonding parameters are generated by the surface wave activation algorithm, and the bonding alignment parameter set is generated by the flip-chip interconnect alignment compensation algorithm. Based on the bonding alignment parameter set and wafer surface temperature distribution, a multi-temperature zone progressive annealing method is used for gradient temperature control to generate low-defect bonded wafers.

6. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 1, characterized in that: The process involves employing a finite element inversion algorithm to establish a stress distribution map of the bonding interface, constructing a thermal stress-resistant encapsulation layer using an intelligent stress matching algorithm, and then encapsulating the low-defect bonded wafer. The steps are as follows. Stress wave signals on the surface of low-defect bonded wafers were acquired using SAW (Self-Diffraction), lattice distortion was measured using X-ray diffraction, and stress distribution maps of the bonding interfaces were established using a finite element inversion algorithm. Based on the stress distribution spectrum of the bonding interface, a three-dimensional stress field model including flip-chip bumps, metallized through holes and bonding interfaces is constructed using the discrete element analysis method. The initial material parameters of the bonding interface were obtained by principal stress trajectory line analysis, nanoindentation test and thermomechanical analysis, and then optimized by the deep DDPG algorithm based on the Actor-Critic framework. Based on the initial material parameters of the optimized bonding interface, a thermal stress-resistant encapsulation layer is constructed using a variable density topology optimization algorithm, and the low-defect bonded wafer is then encapsulated.

7. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 1, characterized in that: The evaluation of the anti-thermal stress encapsulation effect through multiphysics coupling simulation follows these steps. The multiphysics nonlinear coupling scoring method is adopted to predict the thermal stress resistance packaging effect score through triple nonlinear coupling calculation of Gaussian decay function, error function and hyperbolic tangent function; Based on historical packaging test data, a packaging effect evaluation threshold is defined and compared with the thermal stress resistance packaging effect score to analyze the thermal stress resistance packaging effect and generate a test report. The test report includes a thermal stress resistance packaging performance score, structural parameters of the low-defect bonded wafer after packaging, stress distribution map of the bonding interface, and packaging improvement suggestions.

8. A wafer intelligent packaging and testing system for semiconductor chips, based on the wafer intelligent packaging and testing method for semiconductor chips according to any one of claims 1 to 7, characterized in that: It includes a 3D modeling module, a metal infill module, a flip-chip interconnect module, a packaging module, and an evaluation module; The 3D modeling module is used to collect 3D morphology data, temperature distribution and bonding stress data of the wafer surface, construct a 3D through-hole mesh model using a data fusion algorithm, and optimize it using the PPO algorithm to generate a high-precision through-hole wafer. The metal filling module is used to initialize the magnetoelectric field coordination parameters, optimize the magnetoelectric field coordination parameters through a multi-objective genetic algorithm, and drive core-shell nanoparticles to metallize and fill high-precision through-hole wafers to generate wafers with metallized through-hole structures. The flip-chip interconnect module is used to generate bonding parameters based on metallized through-hole structure wafers by using laser Doppler frequency vibration spectrum analysis and to realize flip-chip interconnect using thermo-ultrasonic virtual process to generate low-defect bonded wafers. The packaging module is used to establish the stress distribution map of the bonding interface using the finite element inversion algorithm, and to construct a thermal stress resistant packaging layer through the intelligent stress matching algorithm, and to package the low-defect bonding wafer. The evaluation module is used to predict the thermal stress resistance packaging effect score based on the structural parameters of the packaged low-defect bonded wafer and the initial material parameters of the bonding interface, and generate a test report through multiphysics coupling simulation.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the wafer intelligent packaging and testing method for semiconductor chips according to any one of claims 1 to 7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the wafer intelligent packaging and testing method for semiconductor chips according to any one of claims 1 to 7.

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