Electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits

Abstract

The application discloses an electrostatic discharge protection structure for electrostatic discharge protection of an integrated circuit, which comprises a first chip; the first chip comprises a peripheral circuit and a kernel circuit; the peripheral circuit comprises a first peripheral connection pad of a first port of the peripheral circuit, and a first electrostatic discharge protection circuit connected with the first peripheral connection pad; the kernel circuit comprises a kernel external interface circuit, a kernel internal interface circuit, a first kernel function circuit and a kernel connection pad; the kernel external interface circuit is connected with the first peripheral connection pad; the kernel connection pad is connected with the kernel internal interface circuit, and the first kernel function circuit is connected with the kernel internal interface circuit; a second chip; the second chip comprises a first connection pad, an interface circuit and a second kernel function circuit; the first connection pad is connected with the kernel connection pad of the first chip and connected with the interface circuit; and the interface circuit is connected with the second kernel function circuit. The application can provide effective electrostatic discharge protection for a multi-chip with high-density connection pads.

Description

Technical Field

[0001] This application relates to the field of integrated circuits, and more specifically to an electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits. Background Technology

[0002] Integrated circuits (ICs), as core components of modern electronic products, are developing at a significantly accelerated pace. However, as the critical dimensions of ICs approach the physical limits of quantum tunneling, traditional methods of scaling down to increase the number of transistors on a chip face enormous challenges. To overcome this limitation, the industry is gradually turning to three-dimensional stacking integration technology, increasing the number of stacked layers to achieve performance improvements. Thus, manufacturing thinner chips has become key to meeting the demand for more stacked layers.

[0003] Currently, electrostatic discharge (ESD) protection for two-dimensional (2D) integrated circuits mainly relies on peripheral circuits. Specifically, integrated circuits consist of two main parts: core circuits and peripheral circuits. The core circuits are responsible for logic processing, analog signal processing, and storage functions, and are not directly connected to the outside. The peripheral circuits are mainly responsible for signal transmission and power supply, and are directly affected by the external environment, especially electrostatic discharge (ESD) pulses.

[0004] However, with the continuous reduction in the critical dimensions of integrated circuits, the decrease in operating voltage, and the application of new ultra-thin materials, these traditional technologies face new challenges in terms of cost and implementation difficulty. Especially with the rise of 3D integrated circuit (3D IC) technology, the layout and stacking of interconnect pads in 3D ICs differ from traditional 2D chips, resulting in an order-of-magnitude increase in the number of interconnect pads between chips. Existing ESD protection structures are difficult to directly transplant, leading to the failure of electrostatic discharge (ESD) protection. Furthermore, the industry typically uses an additional chip layer with ESD protection circuitry to protect the integrated circuit from ESD, which wastes the effective area of ​​the transistors. Summary of the Invention

[0005] This application provides an electrostatic discharge (ESD) protection structure for integrated circuits, which can provide effective ESD protection for multi-chip circuits with high-density interconnect pads while ensuring efficient utilization of transistor area. The specific solution is as follows:

[0006] This application provides an electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits, comprising:

[0007] At least one first chip; the first chip includes peripheral circuitry and core circuitry; the peripheral circuitry includes at least a first peripheral connection pad for a first port and a first electrostatic discharge (ESD) protection circuit connected to the first peripheral connection pad; the first ESD protection circuitry provides ESD protection for the first port; the core circuitry includes at least one external core interface circuit, at least one internal core interface circuit, a first core functional circuit, and at least one core connection pad; the external core interface circuitry is directly or indirectly connected to the first peripheral connection pad, and is used to transmit external signals to the first core functional circuit and / or transmit signals from the first core functional circuit to the outside; the core connection pad is connected to the internal core interface circuit, and the first core functional circuit is connected to the internal core interface circuit, and the internal core interface circuit is used for signal transmission between the first core functional circuit and a second core functional circuit; at least one second chip; the second chip includes at least one first connection pad, at least one interface circuit, and a second core functional circuit; the first connection pad is connected to the core connection pad of the first chip and to the interface circuit; the interface circuit is connected to the second core functional circuit, and is used for signal transmission between the second core functional circuit and the first core functional circuit.

[0008] Compared with the prior art, this application has the following advantages:

[0009] This application provides an electrostatic discharge (ESD) protection structure for integrated circuits, comprising the following steps: at least one first chip; the first chip includes peripheral circuitry and a core circuit; the peripheral circuitry includes at least a first peripheral connection pad for a first port and a first ESD protection circuit connected to the first peripheral connection pad; the first ESD protection circuitry provides ESD protection for the first port; the core circuit includes at least one external core interface circuit, at least one internal core interface circuit, a first core functional circuit, and at least one core connection pad; the external core interface circuitry is directly or indirectly connected to the first peripheral connection pad, and the external core interface circuitry transmits external signals to the first internal core interface circuit. The system includes a core functional circuit and / or a core functional circuit that transmits signals from the first core functional circuit to the outside; the core connection pad is connected to the core internal interface circuit, the first core functional circuit is connected to the core internal interface circuit, and the core internal interface circuit is used for signal transmission between the first core functional circuit and the second core functional circuit; at least one second chip; the second chip includes at least one first connection pad, at least one interface circuit, and a second core functional circuit; the first connection pad is connected to the core connection pad of the first chip and to the interface circuit; the interface circuit is connected to the second core functional circuit and is used for signal transmission between the second core functional circuit and the first core functional circuit.

[0010] As can be seen, the electrostatic discharge (ESD) protection structure for integrated circuits provided in this application embodiment, since the first ESD protection circuit of the first chip is connected to the outside, and the interface circuit of the second chip is connected to the core connection pad of the first chip through the first connection pad, and is also connected to the second core functional circuit of the second chip, can isolate the second chip from the influence of external electrostatic pulses by means of the first ESD protection circuit of the first chip, without directly connecting the second chip to external circuits. Furthermore, compared with the prior art using an additional chip layer specifically for ESD protection circuits, this application does not specifically set up a chip layer with ESD protection circuits, but achieves ESD protection for both the first and second chips through the first ESD protection circuit set on the peripheral circuit of the first chip, which can effectively reduce the waste of effective transistor area in three-dimensional integrated circuits. Therefore, the ESD protection structure for integrated circuits provided in this application embodiment can provide effective ESD protection for multiple chips with high-density connection pads while ensuring the effective transistor area utilization rate of integrated circuits. Attached Figure Description

[0011] Figure 1This is a schematic diagram of an electrostatic discharge protection structure for integrated circuits provided by the present invention.

[0012] Figure 2 This is a schematic diagram of an example of a two-layer stacked structure in which the first chip and the second chip are vertically stacked to form an electrostatic discharge protection structure for integrated circuits provided in this application embodiment.

[0013] Figure 3 This is another schematic diagram of a three-layer stacked structure in which the first chip and the second chip are vertically stacked to form an electrostatic discharge protection structure for integrated circuits provided in this application embodiment.

[0014] Figure 4 This is a schematic diagram of the first chip and the second chip placed horizontally side by side in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application.

[0015] Figure 5 This is another schematic diagram of the structure of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0016] Figure 6 This is a schematic diagram of an example of the power supply circuit structure of the peripheral connecting pad to the power supply band of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0017] Figure 7 This is another schematic diagram of the power supply circuit structure of the peripheral connecting pad to the power supply band of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0018] Figure 8 This is a schematic diagram of an example of the power supply circuit structure of the peripheral circuit to the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0019] Figure 9 This is another schematic diagram of the power supply circuit structure of the peripheral circuit to the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0020] Figure 10 This is a schematic diagram of an example of the power supply circuit structure of the second chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0021] Figure 11 This is another schematic diagram of the second chip with a power supply circuit structure in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0022] Figure 12 This is a schematic diagram illustrating an example of how the first chip core circuit supplies power to the second chip via a power supply circuit in an electrostatic discharge protection structure for integrated circuits provided in this application embodiment.

[0023] Figure 13 This is another schematic diagram illustrating how the first chip core circuit supplies power to the second chip via a power supply circuit in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment.

[0024] Figure 14 This is another schematic diagram of the second chip structure in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0025] Figure 15 This is a schematic diagram of an example of an electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0026] Figure 16 This is another schematic diagram of the electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0027] Figure 17 This is another schematic diagram of the electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0028] Figure 18 This is another schematic diagram of the electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment.

[0029] Figure 19 This is a schematic diagram of the first chip core circuit and interface structure in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0030] Figure 20 This is a schematic diagram of the second chip circuit and interface structure in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0031] Figure 21 This is a schematic diagram of an example of an electrostatic discharge protection structure for integrated circuits provided in this application embodiment, where the second chip has peripheral circuitry. Detailed Implementation

[0032] Many specific details are set forth in the following description to provide a full understanding of this application. However, this application can be implemented in many other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of this application; therefore, this application is not limited to the specific embodiments disclosed below.

[0033] It should be noted that the terms "first," "second," "third," etc., in the claims, specification, and drawings of this application are used to distinguish similar objects and are not used to describe a specific order or sequence. Such data are interchangeable where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown or described herein. Furthermore, the terms "comprising," "having," and their variations are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that includes a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to these processes, methods, products, or apparatuses.

[0034] It should be understood that in the embodiments of this application, "at least one" means one or more, and "more than one" means two or more. "And / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. The character " / " generally indicates that the related objects before and after it are in an "or" relationship. "Contains A, B and / or C" means containing any one, two, or three of A, B, and C.

[0035] It should be understood that in the embodiments of this application, "B corresponding to A", "B corresponding to A", "A corresponds to B" or "B corresponds to A" means that B is associated with A, and B can be determined based on A. Determining B based on A does not mean that B is determined solely based on A; B can also be determined based on A and / or other information.

[0036] Based on the reasons mentioned in the background art, in order to provide effective electrostatic discharge protection for multi-chip high-density interconnect pads while ensuring the effective utilization rate of transistor area in integrated circuits, this application provides an electrostatic discharge protection structure for integrated circuits.

[0037] like Figure 1 The diagram shown is a schematic of an electrostatic discharge (ESD) protection structure for integrated circuits provided by the present invention, including... Figure 1 part a and Figure 1 Part b, in which, Figure 1Part a is a schematic diagram of an example structure of at least one first chip C1 included in an electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits. Figure 1 Part b is a schematic diagram of an example structure of at least one second chip C2 included in an electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits.

[0038] like Figure 1 As shown in part a, the first chip C1 includes peripheral circuitry 101 and core circuitry 102. The peripheral circuitry 101 includes at least a first peripheral connection pad 31 for a first port and a first electrostatic discharge (ESD) protection circuit 51 connected to the first peripheral connection pad 31. The first ESD protection circuit 51 provides ESD protection for the first port. The core circuitry 102 includes at least one external core interface circuit 61, at least one internal core interface circuit 62, a first core functional circuit 10, and at least one core connection pad 71. The external core interface circuit 61 is directly or indirectly connected to the first peripheral connection pad 31, and is used to transmit external signals to the first core functional circuit 10 and / or transmit signals from the first core functional circuit 10 to the outside. The core connection pad 71 is connected to the internal core interface circuit 62, and the first core functional circuit 10 is connected to the internal core interface circuit 62. The internal core interface circuit 62 is used for signal transmission between the first core functional circuit 10 and the second core functional circuit 20.

[0039] The first port is the interface through which the first chip interacts with external circuits (such as circuit boards, other chips, sensors, buttons, displays, etc.) via electrical signals. The first port can be an input port that only receives signals from external circuits and does not send signals to external circuits; the first port can also be an output port that only sends signals to external circuits and does not receive signals from external circuits; the first port can also be an input / output port (I / O port) that both sends signals to and receives signals from external circuits.

[0040] The kernel external interface circuit 61 (such as...) Figure 17 (613 and 614 in the figure) can be directly connected to the first peripheral connecting pad 31, or they can be connected through the isolation structure of the first electrostatic discharge protection circuit 51 (such as... Figure 16The kernel external interface circuit 61 is connected to the first kernel functional circuit 10, and the kernel external interface circuit 61 is connected to the first kernel functional circuit 10. Thus, when the first port is an input port, the signal from the external line received from the first port can be transmitted to the kernel external interface circuit 61 through the first peripheral connection pad 31, and the signal from the external line can be transmitted to the first kernel functional circuit 10 through the kernel external interface circuit 61; when the first port is an output port, the signal sent by the first kernel functional circuit 10 can be transmitted to the first peripheral connection pad 31 through the kernel external interface circuit 61, and the signal sent by the first kernel functional circuit 10 can be transmitted from the first port to the external line through the first peripheral connection pad 31; when the first port is an input / output port, the signal from the external line received from the first port can be transmitted to the kernel external interface circuit 61 through the first peripheral connection pad 31, and the signal from the external line can be transmitted to the first kernel functional circuit 10 through the kernel external interface circuit 61, and the signal sent by the first kernel functional circuit 10 can also be transmitted to the first peripheral connection pad 31 through the kernel external interface circuit 61, and the signal sent by the first kernel functional circuit 10 can be transmitted from the first port to the external line through the first peripheral connection pad 31.

[0041] The kernel interface circuit 62 is connected to the kernel connection pad 71 and to the first kernel function circuit 10. The kernel connection pad 71 is directly or indirectly connected to the second kernel function circuit 20 of the second chip. In this way, the signal of the first kernel function circuit 10 can be transmitted to the second kernel function circuit 20 of the second chip through the kernel interface circuit 62, or the signal of the second kernel function circuit 20 can be transmitted to the first kernel function circuit 10.

[0042] The first chip C1 eliminates the influence of external electrostatic pulses through a first electrostatic discharge protection circuit 51 connected to the first peripheral connection pad 31.

[0043] like Figure 1 As shown in part b, the second chip C2 includes at least one first connection pad 81, at least one interface circuit 65, and a second core function circuit 20; the first connection pad 81 is connected to the core connection pad 71 of the first chip C1 and to the interface circuit 65; the interface circuit 65 is connected to the second core function circuit 20 and is used for signal transmission between the second core function circuit 20 and the first core function circuit 10.

[0044] When the first connection pad 81 is an input connection pad and the interface circuit 65 is an input interface circuit, the signal sent by the first core function circuit 10 can be transmitted to the first connection pad 81 through the core connection pad 71, and the signal sent by the first core function circuit 10 can be transmitted to the interface circuit 65 through the first connection pad 81, and the signal sent by the first core function circuit 10 can be transmitted to the second core function circuit 20 through the interface circuit 65. When the first connection pad 81 is an output connection pad and the interface circuit 65 is an output interface circuit, the signal sent by the second core function circuit 20 can be transmitted to the first connection pad 81 through the interface circuit 65, and the signal sent by the second core function circuit 20 can be transmitted to the core connection pad 71 through the first connection pad 81, and the signal sent by the second core function circuit 20 can be transmitted through the core connection pad 71. The signal can be transmitted from the first kernel functional circuit 10 to the first kernel functional circuit 10. When the connection pad 81 is an input / output connection pad and the interface circuit 65 is an input / output interface circuit, the signal sent by the first kernel functional circuit 10 can be transmitted to the first connection pad 81 through the kernel connection pad 71, and the signal sent by the first kernel functional circuit 10 can be transmitted to the interface circuit 65 through the first connection pad 81, and the signal sent by the first kernel functional circuit 10 can be transmitted to the second kernel functional circuit 20 through the interface circuit 65. Alternatively, the signal sent by the second kernel functional circuit 20 can be transmitted to the first connection pad 81 through the interface circuit 65, and the signal sent by the second kernel functional circuit 20 can be transmitted to the kernel connection pad 71 through the first connection pad 81, and the signal sent by the second kernel functional circuit 20 can be transmitted to the first kernel functional circuit 10 through the kernel connection pad 71.

[0045] This application provides an electrostatic discharge (ESD) protection structure for integrated circuits, comprising the following steps: at least one first chip; the first chip includes peripheral circuitry and a core circuit; the peripheral circuitry includes at least a first peripheral connection pad for a first port and a first ESD protection circuit connected to the first peripheral connection pad; the first ESD protection circuitry provides ESD protection for the first port; the core circuit includes at least one external core interface circuit, at least one internal core interface circuit, a first core functional circuit, and at least one core connection pad; the external core interface circuitry is directly or indirectly connected to the first peripheral connection pad, and the external core interface circuitry transmits external signals to the first internal core interface circuit. The system includes a core functional circuit and / or a core functional circuit that transmits signals from the first core functional circuit to the outside; the core connection pad is connected to the core internal interface circuit, the first core functional circuit is connected to the core internal interface circuit, and the core internal interface circuit is used for signal transmission between the first core functional circuit and the second core functional circuit; at least one second chip; the second chip includes at least one first connection pad, at least one interface circuit, and a second core functional circuit; the first connection pad is connected to the core connection pad of the first chip and to the interface circuit; the interface circuit is connected to the second core functional circuit and is used for signal transmission between the second core functional circuit and the first core functional circuit.

[0046] As can be seen, the electrostatic discharge (ESD) protection structure for integrated circuits provided in this application embodiment, since the first ESD protection circuit of the first chip is connected to the outside, and the interface circuit of the second chip is connected to the core connection pad of the first chip through the first connection pad, and is also connected to the second core functional circuit of the second chip, can isolate the second chip from the influence of external electrostatic pulses by means of the first ESD protection circuit of the first chip, without directly connecting the second chip to external circuits. Furthermore, compared with the prior art using an additional chip layer specifically for ESD protection circuits, this application does not specifically set up a chip layer with ESD protection circuits, but achieves ESD protection for both the first and second chips through the first ESD protection circuit set on the peripheral circuit of the first chip, which can effectively reduce the waste of effective transistor area in three-dimensional integrated circuits. Therefore, the ESD protection structure for integrated circuits provided in this application embodiment can provide effective ESD protection for multiple chips with high-density connection pads while ensuring the effective transistor area utilization rate of integrated circuits.

[0047] Optionally, the connection between the first connection pad 81 and the core connection pad 71 of the first chip can be any of the following: bonding connection, micro solder joint connection, or connection through a via and connection structure.

[0048] In one optional implementation, the first chip and the second chip are stacked vertically. The following is combined with... Figure 2 and Figure 3 Detailed introduction:

[0049] like Figure 2 The diagram shown is an example of a two-layer stacked structure formed by vertically stacking a first chip and a second chip in an electrostatic discharge protection structure for integrated circuits provided in this application embodiment. The first peripheral connection pad 31 in the first chip C1 is converted into an external connection structure 921 through a through-hole structure 901 and connected to an external circuit. The core connection pad 71 in the first chip C1 and the first connection pad 81 in the second chip C2 are bonded together.

[0050] like Figure 3 The diagram shown is another example of a three-layer stacked structure formed by vertically stacking the first chip and the second chip in an electrostatic discharge protection structure for integrated circuits provided in this application embodiment. It includes a first chip C1, a second chip C2 without peripheral circuits, and a second chip C3 with peripheral circuits. The first peripheral connection pad of the first chip C1 includes connection pad 311 and connection pad 312. Connection pad 311 is converted into an external connection structure 923 and connected to an external circuit through a through-hole structure 908, and connection pad 312 is converted into an external connection structure 921 and connected to an external circuit through a through-hole structure 904. The core connection pad in the first chip C1 includes connection pad 711. The first connection pad in the second chip C2 includes connection pad 812, and the first connection pad in the second chip C3 includes connection pad 813. Connection pad 711 is connected to connection structure 911 through a through-hole structure 907, connection pad 812 is connected to connection structure 911 through a through-hole structure 903, and connection pad 813 is connected to connection structure 911 through a through-hole structure 905, thereby realizing the connection between the core connection pad in the first chip C1 and the first connection pad in the second chip C2. The peripheral circuit connection pad 313 of the second chip C3 is converted into an external connection structure 922 and connected to an external circuit through a through-hole structure 906. It should be noted that although... Figure 3In the example, the through-hole structure connecting the external connection structure is a single structure. In actual use, because the core connection pad of the first chip and the first connection pad of the second chip are relatively small compared to the first peripheral connection pad of the first chip, multiple through-hole structures may be used to connect a single first peripheral connection pad to the external connection structure in order to ensure sufficient external connection driving capability. For example, multiple through-hole structures 908 may be used to connect the first peripheral connection pad 311 to the external connection structure 923. The specific number used depends on the actual needs and process conditions. If the through-hole structure size is small (e.g., 1µm), more can be used (e.g., 100), and if the through-hole structure size is large (e.g., 5µm), fewer can be used (e.g., 4), and so on. Both the peripheral connection pad of the first chip and the peripheral connection pad of the second chip with peripheral circuitry have similar requirements for external connection structures, which will not be elaborated further.

[0051] In one optional implementation, the first chip and the second chip are placed horizontally side by side. For example... Figure 4 The diagram shows a first chip and a second chip placed horizontally side-by-side in an electrostatic discharge (ESD) protection structure for integrated circuits provided in this application. The core connection pad in the first chip C1 includes a connection pad 711, and the first connection pad in the second chip C2 includes a connection pad 811. When the first chip C1 and the second chip C2 are placed horizontally side-by-side, connection pads 811 and 711 are respectively connected to an intermediate carrier board Z1, so that the connection between connection pads 811 and 711 is achieved through an ESD shielded connection line or optical signal line 911 on the intermediate carrier board Z1. The connection structures 903 and 909 in the intermediate carrier board Z1 are generally hole connection structures, relatively short, and generally protected by an ESD shielding structure. They typically do not require further ESD shielding. However, it should be understood that in practical applications, further ESD shielding can be applied to connection structures 903 and 909 according to actual needs. The connecting pad 811 and the intermediate carrier plate Z1, and the connecting pad 711 and the intermediate carrier plate Z1 are respectively connected in any of the following ways: bonding connection, micro solder joint connection, or connection through perforation and connection structure.

[0052] Optional, such as Figure 4As shown, the electrostatic discharge shielded connection line includes a connection line shielded by an electrostatic discharge shielded connection structure such as a target ground connection line and / or a target power connection line (e.g., connection line 911 shielded by connection lines 961, 962, and 963); a target power connection line connected to the power supply connection line of the peripheral circuit of the first chip, a core circuit power connection line of the core circuit of the first chip (as shown in the figure, connection line 962 is connected to the power supply connection pad 3261 and connected to the core circuit power connection line), a power supply connection line of the peripheral circuit of the second chip, and a power connection line of the second chip (as shown in the figure, connection line 962 is connected to the second chip power connection pad 826 and connected to the core circuit power connection line). Connect the target ground connection line to any one or more of the following connection lines: the ground connection line of the peripheral circuit of the first chip, the ground connection line of the core circuit of the first chip (as shown in the figure, connection line 961 is connected to the power supply ground connection pad 3371 and connected to the core circuit ground connection line), the ground connection line of the peripheral circuit of the second chip, the ground connection line of the second chip (connection line 961 is connected to the second chip ground connection pad 837 and connected to the second chip ground connection line), and the shielding dedicated ground connection line (as shown in the figure, connection line 963 is connected to the shielding dedicated ground connection pad 922 and connected to the shielding dedicated ground connection line). In one specific implementation, for example, a dedicated shielded ground connection line (connector 963 connected to the dedicated shielded ground connection pad 922) can be used for initial shielding against electrostatic discharge (ESD) pulses, preventing ESD pulses from entering the carrier board Z1 and damaging the chip. Then, an ESD shielded connection structure using connectors 961 and 962 is used for connection. It should be noted that the ESD shielded connection structure can be a complete plane or a continuous wire mesh, avoiding long-distance breaks or interruptions to ensure good electrical connection and signal integrity. Since voltage regulation and filtering are performed between the power connection line and the ground connection line, connectors 961 and 962 can be connected to either the power connection line or the ground connection line. It should be noted that the target ground connection line and / or target power connection line generally retain the power supply function of the connection line; and when the target ground connection line is connected to multiple ground connection lines, the power supply function of the multiple ground connection lines shall not be damaged, that is, the target ground connection line shall not be directly connected to multiple indirectly connected ground connection lines; when the target power connection line is connected to multiple power connection lines, the power supply function of the multiple power connection lines shall not be damaged, that is, the target power connection line shall not be directly connected to multiple indirectly connected power connection lines.

[0053] Optional, such as Figure 1As shown in part a, the peripheral circuit 101 further includes a second peripheral connection pad 32 for a power port, a third peripheral connection pad 33 for a ground port, and a second electrostatic discharge (ESD) protection circuit 52 connecting the power port and the ground port; the second ESD protection circuit 52 provides ESD protection for the power port and ground port of the first chip; the second peripheral connection pad 32 is connected to an external power source and to the power connection line 321 of the peripheral circuit 101; the third peripheral connection pad 33 is connected to an external ground and to the ground connection line 331 of the peripheral circuit 101; the power connection line 321 and the ground connection line 331 of the peripheral circuit 101 are used to supply power to the peripheral circuit 101. Figure 5 The diagram shown is another example of the structure of the first chip in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment. The core circuit 102 of the first chip C1 further includes a core circuit power connection line 3211 and a core circuit ground connection line 3311 for supplying power to the core circuit 102. Figure 1 As shown in part b, the second chip C2 also includes a second chip power connection line 821 and a second chip ground connection line 831 for supplying power to the second chip C2.

[0054] The power port is the input interface for the first chip to receive the power supply voltage (such as 3.3V, 1.8V, 5V, etc.) provided by an external power source. It is connected to at least one second peripheral connection pad 32 to transmit the power supply voltage provided by the external power source to the peripheral circuit 101 through the second peripheral connection pad 32. The ground port is the reference potential point of the first chip (usually defined as 0V). It is connected to at least one third peripheral connection pad 33. The third peripheral connection pad 33 is connected to the external ground and the first connection line 331 of the peripheral circuit 101, respectively, which can form a current loop and establish a unified reference potential.

[0055] Optionally, the power connection line 3211 of the core circuit 102 is directly or indirectly connected to the power connection line 321 of the peripheral circuit 101, and the ground connection line 3311 of the core circuit 102 is directly or indirectly connected to the ground connection line 331 of the peripheral circuit 101.

[0056] The following is passed Figures 5-13 The power supply methods of the first chip and the second chip in the electrostatic discharge protection structure for integrated circuits provided in the embodiments of this application are described below:

[0057] The power connection line 3211 of the core circuit 102 is connected to the peripheral circuit 101 in any of the following ways: the power connection line 3211 of the core circuit 102 is connected to the fourth peripheral connection pad 34 that supplies power to the core circuit (see reference). Figure 5 The power connection line 3211 of the core circuit 102 is connected to the fourth peripheral connection pad 34 through the first power supply circuit P1 (please refer to...). Figure 6 , Figure 6 This is a schematic diagram of an example of the power supply circuit structure of the peripheral connection pad to the power supply band of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment. Figure 6 Circuits 622, 621, 623, and 624 in the diagram are the internal interface circuits of the core circuit. The power connection line 3211 of the core circuit 102 is connected to the power connection line 321 of the peripheral circuit 101 through the second power supply circuit P2 (please refer to...). Figure 8 , Figure 8 This is a schematic diagram of an example of the power supply circuit structure of the peripheral circuit to the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment. In this way, the core circuit 102 can be powered through the peripheral circuit.

[0058] The core circuit 102 ground connection 3311 is connected to the peripheral circuit 101 in any of the following ways: the core circuit 102 ground connection 3311 is connected to the fifth peripheral connection pad 35 that supplies power to the core circuit 102 (see reference). Figure 5 The core circuit 102 ground connection line 3311 is connected to the fifth peripheral connection pad 35 through the first power supply circuit P1 (please refer to...). Figure 6 The core circuit 102 ground connection line 3311 is connected to the peripheral circuit 101 ground connection line 331 through the second power supply circuit P2 (please refer to...). Figure 8 It should be noted that, in order to reduce the cumulative voltage difference caused by voltage rise at various nodes of the electrostatic network, when the disturbance requirement to the ground connection is not particularly high, even when using a power supply circuit, the ground electrode is usually directly connected (please refer to...). Figure 7 and Figure 9 , Figure 7 This is another schematic diagram of the power supply circuit structure of the peripheral connecting pad to the power supply band of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application. Figure 9 This is another schematic diagram of the power supply circuit structure of the peripheral circuit to the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in the embodiments of this application.

[0059] Please refer to Figure 5The fourth peripheral connection pad 34 is connected to at least one of the power connection line 321 and the ground connection line 331 of the peripheral circuit 101 through the fourth electrostatic discharge protection circuit 54; the fifth peripheral connection pad 35 is connected to the ground connection line 331 of the peripheral circuit 101, or the fifth peripheral connection pad 35 is connected to at least one of the power connection line 321 and the ground connection line 331 of the peripheral circuit 101 through the fifth electrostatic discharge protection circuit 55. The fourth electrostatic discharge (ESD) protection circuit 54 can quickly release the ESD pulse current to the power connection line 321 (VDD) and / or ground connection line 331 (GND) of the peripheral circuit 101 when an ESD event occurs in the fourth peripheral connection pad 34, and safely discharge the high-energy electrostatic current through the peripheral circuit ESD protection network; the fifth ESD protection circuit 55 can quickly release the ESD pulse current to the power connection line 321 (VDD) and / or ground connection line 331 (GND) of the peripheral circuit 101 when an ESD event occurs in the fifth peripheral connection pad 35, and safely discharge the high-energy electrostatic current through the peripheral circuit ESD protection network; thus achieving the effect of protecting the internal circuitry of the chip from damage by ESD pulses.

[0060] Optional, such as Figure 5As shown, a third electrostatic discharge (ESD) protection circuit 53 is provided between the power connection line 3211 and the ground connection line 3311 of the core circuit 102. This third ESD protection circuit 53 further protects the core circuit 102 from ESD damage, preventing ESD pulse current from entering the core circuit and causing excessive voltage difference between the power connection line 3211 and the ground connection line 3311. When the power connection line 3211 of the core circuit 102 is indirectly connected to the power connection line 321 of the peripheral circuit 101, and the ground connection line 3311 of the core circuit 102 is indirectly connected to the ground connection line 331 of the peripheral circuit 101, the power connection line 3211 of the core circuit 102 and the power connection line 321 of the peripheral circuit 101 are indirectly connected through a first ESD protection unit D1, and the ground connection line 3311 of the core circuit 102 is directly connected to the ground connection line 331 of the peripheral circuit 101 or indirectly connected through a second ESD protection unit D2. The first electrostatic discharge (ESD) protection unit D1 is used to prevent excessive voltage difference between the power connection line 3211 of the core circuit 102 and the power connection line 321 of the peripheral circuit 101 under the action of an ESD pulse. The second ESD protection unit D2 is used to prevent excessive voltage difference between the ground connection line 3311 of the core circuit 102 and the ground connection line 331 of the peripheral circuit 101 under the action of an ESD pulse, thereby preventing ESD damage to the core external interface circuit 61 that connects the peripheral circuit 101 and the core circuit 102. It should be noted that when the power connection line and the ground connection line are indirectly connected through the ESD protection unit, the stability of the power supply can be guaranteed. However, when there are many ESD protection units causing the ESD path to be connected in series, there will be a problem of excessive voltage rise on the ESD path. Therefore, when the disturbance requirement of the ground connection line is not particularly high, the second ESD protection unit D2 can be short-circuited.

[0061] Optional, please refer to Figure 1 part a and Figure 1 In part b, the first chip C1 further includes a first chip power supply connection pad 326 and a first chip ground connection pad 337; the second chip C2 further includes a second chip power supply connection pad 82 and a second chip ground connection pad 83; the first chip C1 power supply connection pad 326 is connected to the second chip C2 power supply connection pad 82, and the first chip C1 ground connection pad 337 is connected to the second chip C2 ground connection pad 83, so as to supply power to the second chip C2 through the first chip C1.

[0062] Optionally, the power connector pad 82 of the second chip C2 can be directly connected to the power connector cable 821 of the second chip (please refer to...). Figure 1(part b), or the second chip power connection pad 82 is indirectly connected to the second chip C2 power connection line 821 via the third power supply circuit P3 (please refer to...). Figure 10 , Figure 10 This is a schematic diagram of an example of a second chip with a power supply circuit structure in an electrostatic discharge protection structure for integrated circuits provided in this application embodiment. The interface circuit includes... Figure 10 (Circuits 651, 652, 653, and 654 in the circuit diagram); when the second chip C2 is directly powered by the first chip, the power connection pad 82 is directly connected to the power connection line 821; when further power is required through the third power supply circuit P3 of the second chip, the power connection pad 82 of the second chip is indirectly connected to the power connection line 821 of the second chip C2 through the third power supply circuit P3. The ground connection pad 83 of the second chip C2 is directly connected to the ground connection line 831 of the second chip (please refer to...). Figure 1 (part b); or the second chip C2 ground connection pad 83 is directly connected to the second chip ground connection line 831 through the third power supply circuit P3 (please refer to...) Figure 10 ) or indirect connection (please refer to) Figure 11 , Figure 11 This is another schematic diagram of the power supply circuit structure of the second chip in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment); in specific implementation, the connection method between the second ground connection pad and the second chip ground connection line can be determined based on the anti-interference capability between the first chip core circuit and the second chip ground connection line. Specifically, if the impact of interference on the circuit exceeds an acceptable range, an indirect connection method can be selected; if the impact of interference on the circuit is within an acceptable range, a direct connection method can be selected.

[0063] The power supply connection pad 326 of the first chip C1 is directly connected to the power connection line 3211 of the core circuit 102 (please refer to...). Figure 5 Alternatively, the first chip power supply connection pad 326 can be indirectly connected to the core circuit power connection line 3211 via the fourth power supply circuit P4 (please refer to...). Figure 12 , Figure 12 This is a schematic diagram illustrating an example of how the first chip core circuit supplies power to the second chip via a power supply circuit in an electrostatic discharge protection structure for integrated circuits provided in this application embodiment.

[0064] When the first chip C1 directly supplies power to the second chip via the power connection line 3211 of the core circuit 102, the power supply connection pad 326 is directly connected to the power connection line 3211 of the core circuit 102. When the second chip needs to be supplied with power through the fourth power supply circuit P4 of the first chip, the power supply connection pad 326 of the first chip is indirectly connected to the power connection line 3211 of the core circuit via the fourth power supply circuit P4. The ground connection pad 337 of the first chip C1 is directly connected to the ground connection line 3311 of the core circuit 102 (please refer to...). Figure 5 Alternatively, the first chip C1 power supply ground connection pad 337 can be directly connected to the core circuit ground connection line 3311 through the fourth power supply circuit P4 (please refer to...). Figure 12 ) or indirect connection (please refer to) Figure 13 , Figure 13 This is another schematic diagram of the electrostatic discharge protection structure for integrated circuits provided in this application, in which the first chip core circuit supplies power to the second chip via a power supply circuit. In specific implementations, the connection method between the first chip power supply ground connection pad and the core circuit ground connection line can be determined based on the anti-interference capability between the first chip core circuit and the ground connection line of the second chip. Specifically, if the interference's impact on the circuit exceeds an acceptable range, an indirect connection method can be selected; if the interference's impact on the circuit is within an acceptable range, a direct connection method can be selected.

[0065] Generally, the core circuit of the first chip C1 and the second chip C2 operate at the same voltage. If mutual interference between the core circuits of the first chip C1 and the second chip C2 is acceptable, the third power supply circuit P3 and the fourth power supply circuit P4 can be omitted. When voltage inconsistencies or interference isolation are required, the third power supply circuit P3 and / or the fourth power supply circuit P4 can be used for power supply. The third power supply circuit P3 and the fourth power supply circuit P4 can be flexibly selected according to actual needs. For example, in scenarios requiring large-scale power supply, the fourth power supply circuit P4 can undertake the main power supply function, thereby avoiding large-scale power supply circuit design on the second chip; or, if the second chip also has analog circuits requiring high-precision power, the third power supply circuit P3 can be further used locally on the basis of the fourth power supply circuit. Furthermore, in a GPU and SRAM stacked structure, due to the high cost per unit area of ​​the GPU, the GPU, as the first chip, mainly provides the power supply path connection, while the SRAM, as the second chip, can use its own power supply circuit (the third power supply circuit P3) to regulate and manage the input voltage, achieving autonomous power supply. This improves the flexibility of power distribution in integrated circuits.

[0066] It should be noted that both the first chip and the second chip may have multiple power supply requirements. For example, different analog circuit modules may require independent power supplies. Therefore, the power supply requirements of the first power supply circuit P1, the second power supply circuit P2, the third power supply circuit P3, and the fourth power supply circuit P4 may not be unique, and they can all be flexibly selected in the manner described above.

[0067] Optional, such as Figure 14 The diagram shown is another example of the second chip structure in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment. A sixth electrostatic discharge protection circuit 56 is located between the power connection line 821 and the ground connection line 831 of the second chip C2. This provides a low-impedance discharge path when an electrostatic discharge pulse is sent to the power connection line of the second chip, safely guiding the transient electrostatic discharge current from the power connection line to the ground connection line, preventing high voltage from breaking down the internal circuitry of the second chip, and protecting the second chip from damage.

[0068] Optionally, the first electrostatic discharge protection circuit 51 includes at least one of a diode, a clamping circuit, and a secondary protection circuit. For example... Figure 15 The diagram shown is an example of an electrostatic discharge (ESD) protection circuit in the peripheral circuit of the first chip in an ESD protection structure for integrated circuits provided in this application embodiment. The first ESD protection circuit 51 includes the diode (511 (e.g., ...)). Figure 18 5111, 5112), 512 (such as Figure 18 In the case where diodes (5121, 5122) and secondary protection circuits (515, 516) are included, an isolation structure 517 is connected between diodes (511, 512) and secondary protection circuits (515, 516); in the case where the first electrostatic discharge protection circuit 51 includes clamping circuits (513, 514) and secondary protection circuits (515, 516), an isolation structure 517 is connected between clamping circuits (513, 514) and secondary protection circuits (515, 516); in the case where the first electrostatic discharge protection circuit 51 includes diodes (511, 512) and the core external interface circuit 61 includes output transistors (611, 612) (see details...), Figure 16 , Figure 16 This is another schematic diagram of the electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment. An isolation structure 517 is connected between the diodes (511, 512) and the output transistors (611, 612) of the core external interface circuit. The isolation structure 517 is used for voltage division to protect the core interface circuit 61 from breakdown damage.

[0069] Optional, such as Figure 15 As shown, circuit 513 in the clamping circuit is connected to the first peripheral pad 31 and to the power connection line 321 of the peripheral circuit 101. Circuit 514 in the clamping circuit is connected to the first peripheral pad 31 and to the ground connection line 331 of the peripheral circuit 101. The clamping circuits (513, 514) are used to release the electrostatic pulse input from the first peripheral pad 31 to the power connection line 321 and / or ground connection line 331 of the peripheral circuit 101, thereby effectively achieving electrostatic discharge protection.

[0070] The secondary protection circuits (515, 516) are connected to the first peripheral pad connection 31 and to at least one of the power connection line 321 and the ground connection line 331 of the peripheral circuit 101. The secondary protection circuits (515, 516) are used to release part of the electrostatic pulse current to the power and / or ground connection lines, thereby effectively achieving electrostatic discharge protection. In practical implementation, 515 is usually connected to the power connection line 321 and 516 is connected to the ground connection line 331. When the power connection line and the ground connection line can clamp the electrostatic discharge voltage to an extremely low voltage, if a 10uF or even 100uF electrostatic discharge protection capacitor or capacitor array is used between the power connection line and the ground connection line, the electrostatic pulse (such as HBM4000V) can be clamped to below 0.1V. The power connection line 321 and the ground connection line 331 of the peripheral circuit 101 can be considered to be at the same potential. The secondary protection circuit (515, 516) can be placed in any set to eliminate the electrostatic discharge damage to the core external interface circuit 61 caused by the electrostatic pulse introduced by the first peripheral pad connection 31.

[0071] Optional, such as Figure 15 As shown, the clamping circuit (513 (including 5131, 5132 and 5133), 514 (including 5141, 5142 and 5143)) and the secondary protection circuit (515, 516) respectively include at least one of the following: a dynamically coupled MOSFET, a dynamically coupled SCR (silicon controlled rectifier) ​​or parasitic SCR, a dynamically coupled BJT (bipolar junction transistor) or parasitic BJT, a diode with low breakdown voltage, a MOSFET with low breakdown voltage, an SCR with low breakdown voltage, and a BJT with low breakdown voltage.

[0072] Optional, such as Figure 17The diagram shown is another example of the electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment. Taking a dynamically coupled NMOS transistor as a 514 clamping circuit as an example, this structure consists of a capacitor 5143, a resistor 5142, and an NMOS transistor 5141. The capacitor 5143 and the resistor 5142 form a dynamically coupled trigger circuit. When the power supply is stable, the resistor 5142 pulls the gate of the NMOS transistor 5141 low to ground level, and the NMOS transistor 5141 is in the off state. When an electrostatic pulse is input from the first peripheral connection pad 31, if a positive electrostatic pulse is applied to the third peripheral connection pad 33 (ground connection pad), the pulse signal will pass through the diode 511. (Diode 511 can be independent or parasitic within the PMOS transistor 5131 of clamping circuit 513.) The voltage across capacitor 5143 cannot change abruptly. Therefore, capacitor 5143 will divide the voltage with the gate parasitic capacitance of NMOS transistor 5141, coupling a voltage to the gate of NMOS transistor 5141, triggering NMOS transistor 5141 to turn on. It may even further trigger the NMOS parasitic BJT to turn on, releasing the electrostatic pulse to ground connection 331 and then to the third peripheral connection pad 33. The gate voltage of NMOS transistor 5141 will become ground level after the electrostatic pulse is released, or it will be restored to ground level through resistor 5142, turning off NMOS transistor 5141. Low breakdown voltage triggering structures are also commonly used in electrostatic discharge (ESD) protection. Specific examples include the off-state PMOS shown in Figure 515 and the off-state NMOS shown in Figure 516. This structure reduces the reverse bias breakdown voltage of the PN junction by adjusting the doping concentration. When ESD occurs, the voltage across the device is higher than its operating voltage, thus lowering the reverse bias breakdown level of the PN junction and triggering parasitic structures (such as MOS parasitic BJTs) to discharge. Because of the low breakdown voltage, low breakdown voltage triggering structures generally have a larger static leakage current, but they do not have the coupling time problem of dynamic coupling triggering structures. The choice can be based on specific requirements. Figure 17As shown, even with electrostatic discharge (ESD) protection structures such as diode 511, dynamic coupling NMOS transistor 521 clamping circuit, and dynamic coupling NMOS transistor 514 clamping circuit, the gate-to-ground connection line 331 of the NMOS transistor 613 in the core external interface circuit still has a high voltage, and there is even a risk of gate breakdown of the NMOS transistor 613. The secondary protection circuit 516, due to its low breakdown voltage characteristics, will break down first, triggering the opening of the ground connection line 331 to release current. This creates a voltage divider on the isolation structure 517, reducing the voltage difference between the gate and ground connection line 331 of the NMOS transistor 613 in the core external interface circuit, thus providing further ESD protection. It should be noted that since the ESD current shared by the secondary protection circuits (515, 516) is relatively small, conventional MOS transistors can also be used as secondary protection circuits (515, 516) when the drain breakdown voltage of a conventional MOS transistor is less than its gate breakdown voltage.

[0073] Optionally, the isolation structure 517 includes at least one of a resistor, capacitor, inductor, MOSFET, and transistor. For example... Figure 17 As shown, the isolation structure 517 can be a resistor structure; for high-frequency circuits, the isolation structure 517 can also be a composite circuit composed of resistors, capacitors and inductors, which makes it easy to input specific frequency signals and can effectively isolate electrostatic pulses; for structures with low impedance requirements, the isolation structure 517 can also be a normally open MOSFET or a transistor structure, so that the saturation characteristics of the device can be used to limit the electrostatic pulse current while ensuring low impedance.

[0074] Optionally, the second electrostatic discharge protection circuit 52 in the first chip includes at least one of the following: a capacitor, a diode, a dynamically coupled MOSFET, a dynamically coupled SCR (Silicon Controlled Rectifier) ​​or parasitic SCR, a dynamically coupled BJT, a diode with low breakdown voltage, a MOSFET with low breakdown voltage, an SCR with low breakdown voltage, and a BJT with low breakdown voltage. Figure 18 The diagram shown is another example of an electrostatic discharge protection circuit in the peripheral circuit of the first chip in the electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits provided in this application embodiment. The second electrostatic discharge protection circuit 52 is a capacitor with a capacitance value of 0.05uF to 50uF. It can absorb the electrostatic discharge pulse instantly, clamp the voltage below the safe voltage, and then slowly release it through its own leakage current or the additional resistor 524. Figure 17The second electrostatic discharge protection circuit 52 is a dynamically coupled NMOS transistor structure. This structure is dynamically coupled by capacitor 523 and resistor 522 when an electrostatic discharge pulse arrives at power line 321 (as mentioned above, when an electrostatic discharge pulse is input from the first peripheral connection pad 31 and a positive electrostatic pulse is applied to the third peripheral connection pad 33 (ground connection pad)). This triggers NMOS transistor 521 to turn on, forming an electrostatic discharge path between power connection line 321 and ground connection line 331.

[0075] Optional, such as Figure 5 As shown, the first chip C1 includes at least one core interfacing interface circuit, namely a target core interfacing interface circuit 64 (e.g., ...). Figure 19 (643, 644 in part b), the target kernel internal interface circuit 64 is connected to a seventh electrostatic discharge protection circuit 57 (e.g. Figure 19 The seventh electrostatic discharge protection circuit 57 is connected to the core power supply connection line 3211 of the core circuit 102 and / or the core ground connection line 3311 of the core circuit, and the electrostatic discharge protection capability of the seventh electrostatic discharge protection circuit 57 is less than or equal to 100V. The seventh electrostatic discharge protection circuit 57 includes any one of the following: diode, dynamically coupled triggered MOSFET, dynamically coupled triggered SCR (silicon controlled rectifier) ​​or parasitic SCR, dynamically coupled triggered BJT, low breakdown voltage triggered diode, low breakdown voltage triggered MOSFET, low breakdown voltage triggered SCR, and low breakdown voltage triggered BJT.

[0076] like Figure 19 The diagram shown is a schematic of the first chip core circuit and interface structure in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment, including... Figure 19 part a and Figure 19 Part b, Figure 19 In part a, the first chip does not have a seventh electrostatic discharge protection circuit. Figure 19 In part b, the first chip is equipped with a seventh electrostatic discharge (ESD) protection circuit, namely circuit 575 and circuit 576 (575 and 576 are low-breakdown voltage triggered MOS transistors in the figure). It should be noted that since the ESD voltage shared by the seventh ESD protection circuit is relatively small, a conventional MOS transistor can also be used as the seventh ESD protection circuit when the drain breakdown voltage of a conventional MOS transistor is less than the gate breakdown voltage.

[0077] Similarly, such as Figure 14As shown, the first connection pad of the second chip C2 includes a target first connection pad 85, the target first connection pad 85 is connected to an eighth electrostatic discharge protection circuit 58, and the eighth electrostatic discharge protection circuit 58 is connected to the power connection line 821 and / or the ground connection line 831 of the second chip C2; wherein, the electrostatic discharge protection capability of the eighth electrostatic discharge protection circuit 58 is less than or equal to 100V.

[0078] like Figure 20 The diagram shown is a schematic of the second chip circuit and interface structure in the electrostatic discharge protection structure for integrated circuits provided in this application embodiment, including... Figure 20 part a and Figure 20 Part b, Figure 20 In part a, the second chip does not have an eighth electrostatic discharge protection circuit. Figure 20 In part b, the second chip is equipped with an eighth electrostatic discharge (ESD) protection circuit, namely circuit 585 and circuit 586 (585 and 586 are low-breakdown voltage triggered MOS transistors in the figure). Similar to the seventh ESD protection circuit, since the ESD voltage shared by the eighth ESD protection circuit is relatively small, a conventional MOS transistor can also be used as the seventh ESD protection circuit when the drain breakdown voltage of a conventional MOS transistor is less than the gate breakdown voltage.

[0079] Optional, such as Figure 5 As shown, the first peripheral connection pad 31, the second peripheral connection pad 32, the third peripheral connection pad 33, the fourth peripheral connection pad 34, and the fifth peripheral connection pad 35 are respectively connected to the external circuit using at least one of C4 solder balls, micro solder points, bonding, and wire bonding.

[0080] Optional, such as Figure 21 The diagram shown is an example of an electrostatic discharge protection structure for integrated circuits provided in this application embodiment, where the second chip has peripheral circuitry. The second chip C2 further includes peripheral circuitry (such as a chip select signal for a memory). The peripheral circuitry of the second chip C2 is connected to the first chip C1 or external circuitry via at least one of the following methods: C4 solder balls, micro solder joints, bonding, wire bonding, through-holes, and connecting wires.

[0081] Optional, such as Figure 21As shown, a ninth electrostatic discharge (ESD) protection circuit 59 is provided between the power connection line 8211 of the peripheral circuit of the second chip C2 and the ground connection line 8311 of the peripheral circuit of the second chip C2; the power connection line 8211 of the peripheral circuit of the second chip C2 is directly connected to the power connection line 321 of the peripheral circuit of the first chip C1 or connected through the third ESD protection unit D3, and / or directly connected to the power connection line 3211 of the core circuit 102 or connected through the fifth ESD protection unit D5; the ground connection line 8311 of the peripheral circuit of the second chip C2 is directly connected to the ground connection line 331 of the peripheral circuit of the first chip C1 or connected through the fourth ESD protection unit D4, and / or directly connected to the ground connection line of the core circuit or connected through the sixth ESD protection unit D6.

[0082] Complex power networks result in complex ESD protection unit connections between power and ground connections. This increases the area occupied by the ESD protection structure on the chip and can lead to voltage accumulation during ESD discharge. Therefore, in this embodiment, the number of power supply types (such as...) is minimized. Figure 1 part a and Figure 1 As shown in part b), especially the second chip C2 should have as few external circuits as possible (such as...). Figure 1 (As shown in part b). Even when the second chip C2 has peripheral circuitry, try to directly connect it to the power supply and ground connections corresponding to the peripheral circuitry and / or core circuitry of the first chip. Even if a direct power supply connection is not possible, try to directly connect ground connections to ground connections. When mutual interference isolation is required, such as when the second chip needs to connect to external high-precision analog signals, it can be done as follows: Figure 21 The electrostatic discharge (ESD) protection unit is shown. It should be noted that, in cases requiring mutual interference isolation, an ESD protection unit can also be placed between the second chip core circuit and the second chip peripheral circuit (as shown in D7 and D8). Similarly, ESD protection units can be placed between the second chip core circuit and the first chip peripheral circuit, and between the second chip core circuit and the first chip, as in the case of the second chip peripheral circuit to the first chip. These will not be elaborated upon further here.

[0083] Each electrostatic discharge protection unit shall include at least one of the following: a diode, a dynamically coupled MOSFET, a dynamically coupled SCR (Silicon Controlled Rectifier) ​​or parasitic SCR, a dynamically coupled BJT, a diode with low breakdown voltage, a MOSFET with low breakdown voltage, an SCR with low breakdown voltage, or a BJT with low breakdown voltage. The specific unit to be used depends on the actual requirements.

[0084] In particular, if the ground connection lines of each circuit are short-circuited to each other, and the power connection lines and ground connection lines of each group (such as the peripheral circuit of the first chip) are connected by a capacitor structure (such as 10uF) to form an electrostatic discharge protection circuit, since the power supply level is approximately equal to the ground level under the action of electrostatic pulse, and the ground connection lines are short-circuited, no large voltage difference will be generated between them. Therefore, there is no need to place an electrostatic discharge protection unit in the case of multiple power supply.

[0085] Although this application discloses preferred embodiments as described above, it is not intended to limit this application. Any person skilled in the art can make possible changes and modifications without departing from the spirit and scope of this application. Therefore, the scope of protection of this application should be determined by the scope defined in the claims of this application.

Claims

1. An electrostatic discharge protection structure for electrostatic discharge protection of integrated circuits, characterized in that, include: At least one first chip; the first chip includes peripheral circuitry and core circuitry; the peripheral circuitry includes at least a first peripheral connection pad for a first port and a first electrostatic discharge (ESD) protection circuit connected to the first peripheral connection pad; the first ESD protection circuitry provides ESD protection for the first port; the core circuitry includes at least one external core interface circuit, at least one internal core interface circuit, a first core functional circuit, and at least one core connection pad; the external core interface circuitry is directly connected to the first peripheral connection pad or connected to an isolation structure of the first peripheral connection pad, and is used to transmit external signals to the first core functional circuit and / or transmit signals from the first core functional circuit to the outside; the core connection pad is connected to the internal core interface circuit, the first core functional circuit is connected to the internal core interface circuit, and the internal core interface circuit is used for signal transmission between the first core functional circuit and a second core functional circuit of a second chip; At least one second chip; the second chip includes at least one first connection pad, at least one interface circuit, and a second core function circuit; the first connection pad is connected to the core connection pad of the first chip and to the interface circuit; the interface circuit is connected to the second core function circuit, and the interface circuit is used for signal transmission between the second core function circuit and the first core function circuit, and electrostatic discharge protection of the first chip and the second chip is achieved through the first electrostatic discharge protection circuit; the first chip and the second chip are stacked vertically.

2. The electrostatic discharge protection structure according to claim 1, characterized in that, The first connection pad is connected to the core connection pad of the first chip in any of the following ways: bonding connection, micro solder joint connection, or connection through a via and connection structure.

3. The electrostatic discharge protection structure according to claim 1, characterized in that, The peripheral circuit also includes a second peripheral connection pad for the power port, a third peripheral connection pad for the ground port, and a second electrostatic discharge protection circuit connecting the power port and the ground port; the second electrostatic discharge protection circuit is used to provide electrostatic discharge protection for the power port and the ground port of the first chip. The second peripheral connection pad is connected to an external power source and to the power connection line of the peripheral circuit; the third peripheral connection pad is connected to an external ground and to the ground connection line of the peripheral circuit; the power connection line and the ground connection line of the peripheral circuit are used to supply power to the peripheral circuit. The core circuit of the first chip also includes a core circuit power connection line and a core circuit ground connection line for supplying power to the core circuit; The second chip also includes a second chip power connection line and a second chip ground connection line for supplying power to the second chip.

4. The electrostatic discharge protection structure according to claim 3, characterized in that, The power supply connection line of the core circuit is directly or indirectly connected to the power supply connection line of the peripheral circuit, and the ground connection line of the core circuit is directly or indirectly connected to the ground connection line of the peripheral circuit.

5. The electrostatic discharge protection structure according to claim 4, characterized in that, The power connection line of the core circuit and the power connection line of the peripheral circuit are connected in any of the following ways: the power connection line of the core circuit is connected to the fourth peripheral connection pad that supplies power to the core circuit; the power connection line of the core circuit is connected to the fourth peripheral connection pad through a first power supply circuit; or the power connection line of the core circuit is connected to the power connection line of the peripheral circuit through a second power supply circuit. The core circuit ground connection line is connected to the peripheral circuit ground connection line in any of the following ways: the core circuit ground connection line is connected to the fifth peripheral connection pad that powers the core circuit; the core circuit ground connection line is connected to the fifth peripheral connection pad through the first power supply circuit; or the core circuit ground connection line is connected to the peripheral circuit ground connection line through the second power supply circuit. The fourth peripheral connection pad is connected to at least one of the power connection line and ground connection line of the peripheral circuit through the fourth electrostatic discharge protection circuit; the fifth peripheral connection pad is connected to the ground connection line of the peripheral circuit, or the fifth peripheral connection pad is connected to at least one of the power connection line and ground connection line of the peripheral circuit through the fifth electrostatic discharge protection circuit.

6. The electrostatic discharge protection structure according to claim 3, characterized in that, A third electrostatic discharge (ESD) protection circuit is provided between the core circuit power supply connection line and the core circuit ground connection line; when the core circuit power supply connection line is indirectly connected to the power supply connection line of the peripheral circuit, and the core circuit ground connection line is indirectly connected to the ground connection line of the peripheral circuit, the core circuit power supply connection line and the peripheral circuit power supply connection line are connected through a first ESD protection unit, and the core circuit ground connection line and the peripheral circuit ground connection line are directly connected or connected through a second ESD protection unit.

7. The electrostatic discharge protection structure according to claim 3, characterized in that, The first chip further includes a first chip power supply connection pad and a first chip ground connection pad; the second chip further includes a second chip power supply connection pad and a second chip ground connection pad; the first chip power supply connection pad is connected to the second chip power supply connection pad, and the first chip ground connection pad is connected to the second chip ground connection pad, so as to supply power to the second chip through the first chip.

8. The electrostatic discharge protection structure according to claim 7, characterized in that, The second chip power connection pad is connected to the second chip power connection line, or the second chip power connection pad is connected to the second chip power connection line through a third power supply circuit; The second chip ground connection pad is connected to the second chip ground connection line, or the second chip ground connection pad is connected to the second chip ground connection line through the third power supply circuit; The first chip power supply connection pad is connected to the core circuit power connection line, or the first chip power supply connection pad is connected to the core circuit power connection line through the fourth power supply circuit. The first chip power supply ground connection pad is connected to the core circuit ground connection line, or the first chip power supply ground connection pad is connected to the core circuit ground connection line through the fourth power supply circuit.

9. In the electrostatic discharge protection structure according to claim 2, a sixth electrostatic discharge protection circuit is provided between the second chip power connection line and the second chip ground connection line.

10. The electrostatic discharge protection structure according to claim 1, characterized in that, The first electrostatic discharge protection circuit includes at least one of the following: a diode, a clamping circuit, and a secondary protection circuit.

11. The electrostatic discharge protection structure according to claim 10, characterized in that, When the first electrostatic discharge protection circuit includes the diode and the secondary protection circuit, an isolation structure is connected between the diode and the secondary protection circuit; when the first electrostatic discharge protection circuit includes the clamping circuit and the secondary protection circuit, an isolation structure is connected between the clamping circuit and the secondary protection circuit; when the first electrostatic discharge protection circuit includes the diode and the core external interface circuit includes an output transistor, an isolation structure is connected between the diode and the output transistor of the core external interface circuit; the isolation structure is used to protect the core external interface circuit from breakdown damage.

12. The electrostatic discharge protection structure according to claim 10, characterized in that, The clamping circuit is connected to the first peripheral pad and to the power and / or ground connection lines of the peripheral circuit; the clamping circuit is used to release the electrostatic pulse current input from the first peripheral pad to the power and / or ground connection lines of the peripheral circuit.

13. The electrostatic discharge protection structure according to claim 10, characterized in that, The secondary protection circuit is connected to the first peripheral pad and to at least one of the following connections: the power connection line of the peripheral circuit, the ground connection line of the peripheral circuit, the power connection line of the core circuit, and the ground connection line of the core circuit. The secondary protection circuit is used to release a portion of the electrostatic pulse current input from the first peripheral pad to the power and / or ground connection lines.

14. The electrostatic discharge protection structure according to claim 10, characterized in that, The clamping circuit and the secondary protection circuit each include at least one of the following: a dynamically coupled MOSFET, a dynamically coupled SCR, a dynamically coupled BJT, a diode with low breakdown voltage, a MOSFET with low breakdown voltage, an SCR with low breakdown voltage, and a BJT with low breakdown voltage.

15. The electrostatic discharge protection structure according to claim 11, characterized in that, The isolation structure includes at least one of a resistor, capacitor, inductor, MOSFET, and transistor.

16. The electrostatic discharge protection structure according to claim 1, characterized in that, The first chip includes a target core internal interface circuit in at least one core internal interface circuit. The target core internal interface circuit is connected to a seventh electrostatic discharge (ESD) protection circuit, and the seventh ESD protection circuit is connected to the core power supply connection line and / or the core ground connection line of the core circuit. The ESD protection capability of the seventh ESD protection circuit is less than or equal to 100V.

17. The electrostatic discharge protection structure according to claim 1, characterized in that, The second chip includes a target first connection pad in at least one first connection pad, the target first connection pad being connected to an eighth electrostatic discharge protection circuit, and the eighth electrostatic discharge protection circuit being connected to the power connection line and / or the ground connection line of the second chip; wherein the electrostatic discharge protection capability of the eighth electrostatic discharge protection circuit is less than or equal to 100V.

18. The electrostatic discharge protection structure according to claim 5, characterized in that, The first peripheral connection pad, the second peripheral connection pad, the third peripheral connection pad, the fourth peripheral connection pad, and the fifth peripheral connection pad are connected to the external circuit using at least one of the following methods: C4 solder ball, micro solder joint, bonding, and wire bonding.

19. The electrostatic discharge protection structure according to any one of claims 1 to 18, characterized in that, The second chip also includes peripheral circuitry; the peripheral circuitry of the second chip is connected to the first chip or external circuitry via at least one of the following methods: C4 solder balls, micro solder joints, bonding, wire bonding, through-hole connection, and connecting wires.

20. The electrostatic discharge protection structure according to claim 19, characterized in that, A ninth electrostatic discharge (ESD) protection circuit is provided between the power connection line of the peripheral circuit of the second chip and the ground connection line of the peripheral circuit of the second chip; the power connection line of the peripheral circuit of the second chip is directly connected to the power connection line of the peripheral circuit of the first chip or connected through a third ESD protection unit, and / or directly connected to the power connection line of the core circuit or connected through a fifth ESD protection unit; the ground connection line of the peripheral circuit of the second chip is directly connected to the ground connection line of the peripheral circuit of the first chip or connected through a fourth ESD protection unit, and / or directly connected to the ground connection line of the core circuit or connected through a sixth ESD protection unit.

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