Message data processing method and device

Abstract

The invention provides a message data processing method and device, and relates to the technical field of message processing. The method comprises the following steps: extracting the length of a message descriptor; searching at least one storage address corresponding to the length in a preset storage area; and sequentially storing the message descriptors into the storage address according to the arrangement sequence of the Bank. The preset storage area is configured as a Bank linked list storage mode with a plurality of Banks, and each Bank comprises a plurality of storage addresses; the same storage address corresponding to different Bank identifiers is used for storing message descriptors with the same length; the width of each Bank is a preset minimum descriptor storage unit. According to the invention, the message descriptors are stored in a plurality of Banks in a fragmented manner according to the address sequence, variable-length data processing can be supported at the minimum cache cost, and on the premise of ensuring the message transmission order-preserving requirement, the memory access delay is reduced, the resources are effectively utilized, and the optimal balance between the performance and the resources is met.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of message processing, in particular to a message data processing method and device. BACKGROUND

[0002] In the transmission process of network messages, message descriptors need to be acquired first. In order to improve the message transmission performance, the message descriptors are pre-fetched and cached in the hardware. Since the message transmission of the same queue needs to be in order, a linked list is used to store the descriptors of different messages of the same queue when the message descriptors are stored in the hardware. For multiple queues, multiple linked lists need to be used. Since different types of messages are transmitted on the network, in order to improve the transmission efficiency, the lengths of the descriptors of different message types may be different. Therefore, the hardware needs to store message descriptors of different lengths.

[0003] The traditional method of storing descriptors in a linked list is to store the descriptors in a piece of ram. When descriptors of different lengths need to be stored, the bit width of the ram is set to the minimum or maximum of the descriptor bit width. For example, when there are 32 Byte and 256 Byte descriptors, the bit width of the linked list ram can only be set to 32 Byte or 256 Byte. If the ram is set to 32 Byte, 8 taps are needed to complete the writing or reading of the 256 Byte descriptor, which makes the message transmission performance only 1 / 8. If the ram is set to 256 Byte, the cache utilization rate of the 32 Byte descriptor is only 1 / 8, which cannot guarantee both performance and cache utilization. SUMMARY

[0004] Therefore, the purpose of the present application is to provide a message data processing method and device which can support not reducing the message performance and not needing larger cache, and can store message descriptors of different lengths.

[0005] In a first aspect, the present application provides a message data processing method, which comprises: acquiring a message descriptor to be stored; extracting the length of the message descriptor; and searching for at least one storage address corresponding to the length in a preset storage area. The preset storage area is configured in a Bank linked list storage mode with multiple Banks. Each Bank has a unique Bank identifier, and each Bank includes multiple storage addresses. The same storage addresses corresponding to different Bank identifiers are used to store message descriptors of the same length. The width of each Bank is a preset minimum descriptor storage unit. The message descriptors are sequentially stored in the storage addresses according to the arrangement order of the Banks.

[0006] With reference to the first aspect, in a first implementation form of the first aspect, the step of searching for the at least one storage address corresponding to the length of the packet descriptor in the preset storage area comprises: searching for a storage address for storing the length in the preset storage area; determining whether the number of the unoccupied storage addresses in the searched storage address is greater than or equal to the number of the storage addresses required by the length of the packet descriptor; and if yes, determining that the searched storage address matches the length of the packet descriptor.

[0007] With reference to the first aspect, in a second implementation form of the first aspect, the step of searching for the storage address for storing the length in the preset storage area further comprises: obtaining a storage table configured in advance, wherein the storage table is used to record the correspondence between each storage address in the preset storage area and the length of the packet descriptor, and the correspondence is used to represent that the packet descriptor with the preset length is stored in the corresponding storage address; and determining the storage address corresponding to the length based on the storage table.

[0008] With reference to the first aspect, in a third implementation form of the first aspect, the step of sequentially storing the packet descriptor into the storage addresses according to the arrangement order of the Banks comprises: sequentially storing the packet descriptor into the unoccupied storage addresses according to the arrangement order of the Banks.

[0009] With reference to the first aspect, in a fourth implementation form of the first aspect, the method further comprises: if it is determined that the number of the unoccupied storage addresses in the searched storage address is less than the number of the storage addresses required by the length of the packet descriptor; obtaining a first Bank and the unoccupied storage addresses in the first Bank; and taking the unoccupied storage addresses in the first Bank as the starting addresses, sequentially storing the packet descriptor into the same storage addresses in each bank according to the arrangement order of the Banks; wherein the first Bank is a Bank set as the starting bit in the Bank chain table.

[0010] With reference to the first aspect, in a fifth implementation form of the first aspect, the method further comprises: obtaining the maximum length of the packet descriptor in the transmission queue where the packet descriptor is located; searching for a target Bank chain table corresponding to the maximum length and the number of Banks from the preset database according to the maximum length, and determining the storage area where the target Bank chain table is located as the preset storage area.

[0011] With reference to the first aspect, in a sixth implementation form of the first aspect, the method further comprises: sorting the plurality of Banks according to the Bank identifiers, and generating a Bank array.

[0012] In a second aspect, an embodiment of the present application provides a packet data processing apparatus, comprising: a data acquisition module configured to acquire a packet descriptor to be stored; a data processing module configured to extract a length of the packet descriptor; a searching module configured to search at least one storage address corresponding to the length in a preset storage area; wherein the preset storage area is configured to have a Bank linked list storage mode of a plurality of Banks, each of the Banks has a unique Bank identifier, and each of the Banks comprises a plurality of storage addresses; the same storage addresses corresponding to different Bank identifiers are used to store the packet descriptors with the same length; and the width of each of the Banks is a preset minimum descriptor storage unit; and an execution module configured to store the packet descriptor into the storage addresses in sequence according to the arrangement order of the Banks.

[0013] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory stores computer executable instructions capable of being executed by the processor, and the processor executes the computer executable instructions to implement the steps of the packet data processing method of any of the above-mentioned embodiments.

[0014] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the steps of the packet data processing method of any of the above-mentioned embodiments.

[0015] The embodiments of the present application have the following beneficial effects: the present application provides a packet data processing method and apparatus, by providing a Bank linked list storage mode of a plurality of Banks, the packet descriptor can be fragmented and stored into the plurality of Banks in address order, the variable length data processing can be supported with minimum cache cost, and the packet descriptor can be efficiently managed. On the premise of ensuring the packet transmission order requirement, the memory access delay can be reduced, the resources can be effectively utilized, and the optimal balance between performance and resources is met.

[0016] Other features and advantages of the present application will be further described in the following description, and will become apparent from the description, or will be learned through practice of the present application. The objects and other advantages of the present application will be realized and achieved by the structure particularly pointed out in the description, claims, and drawings.

[0017] In order to make the above objects, features and advantages of the present application more apparent, the following will specifically describe preferred embodiments in combination with the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to illustrate the technical solutions in the specific embodiments of the present application or the prior art more clearly, the accompanying drawings needed to be used in the description of the specific embodiments or the prior art will be briefly introduced. Obviously, the accompanying drawings in the following description are some embodiments of the present application, and all other drawings obtained by those of ordinary skill in the art without any creative work based on these drawings are within the protection scope of the present application.

[0019] Figure 1 A flow chart of a packet data processing method provided by an embodiment of the present application is shown in FIG. 1. Figure 2 A flow chart of another packet data processing method provided by an embodiment of the present application is shown in FIG. 2. Figure 3 A structure diagram of a multi-bank linked list provided by an embodiment of the present application is shown in FIG. 3. Figure 4 A structure diagram of a packet data processing device provided by an embodiment of the present application is shown in FIG. 4. Figure 5 A structure diagram of an electronic device provided by an embodiment of the present application is shown in FIG. 5. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the present application will be described clearly and completely in combination with the embodiments. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without any creative work are within the protection scope of the present application.

[0021] In modern communication system and network processing architecture, packet as the basic unit of information transmission, its processing efficiency directly affects the overall performance of the system. Packet descriptor is a metadata structure used to describe the packet attribute, usually contains the packet length, type, priority, source / destination address pointer, check information and other key fields. In the process of packet receiving, forwarding, scheduling or storage, hardware uses linked list structure to store packet descriptor in RAM to support multi-queue and order requirement. But due to the different descriptor length of different packet type (such as 32 bytes and 256 bytes), the design of traditional fixed bit width RAM will cause the contradiction between performance and cache utilization. Specifically, when the RAM bit width is set to the minimum descriptor length (such as 32 bytes), each RAM access cycle ( "beat" ) can only handle a fixed size data unit (such as 32 bytes). Therefore, for larger descriptors (such as 256 bytes), hardware needs to access RAM multiple times to complete a descriptor read-write operation. Since the packet transmission must be in order (the descriptors of the same queue need to be processed in order), multiple accesses of a descriptor will block the processing of subsequent descriptors, further amplifying the performance loss. Especially in multi-queue system, if multiple queues share RAM resources, the contention problem will be more serious. When the RAM bit width is set to the maximum descriptor length (such as 256 bytes), for smaller descriptors (such as 32 bytes), only 32 bytes of space is used. Since the linked list structure requires each descriptor to occupy an independent unit to maintain order, the remaining bytes cannot be utilized by other descriptors, and the cache resources are not effectively utilized, increasing the hardware cost and energy consumption.

[0022] To solve the above problems, the embodiment of the application provides a packet data processing method and device, which organizes storage resources by using Bank structure, and effectively combines the length characteristics of packet descriptors for structured organization, fully utilizes the advantages of parallel access and fast addressing, to improve storage efficiency, reduce access delay, and support high concurrency processing.

[0023] For ease of understanding, first, a packet data processing method provided by the embodiment of the application is described, referring to Figure 1 The method comprises the following steps: Step S102, obtaining a packet descriptor to be stored.

[0024] The packet descriptor is an information structure used to describe a packet metadata, usually includes but is not limited to: packet length, type identifier, priority, timestamp, source / destination port information, checksum, storage pointer, etc., used to provide control information for subsequent packet parsing, forwarding, scheduling or storage operation.

[0025] Step S104, extracting the length of the packet descriptor.

[0026] Step S106, searching for at least one storage address corresponding to the length in a preset storage area.

[0027] Step S108, storing the message descriptor into the storage address in sequence according to the arrangement order of the Bank.

[0028] The preset storage area of the embodiment of the present application is configured as a Bank chain table storage mode with multiple Banks, each Bank including multiple storage addresses. Each Bank has a preset minimum descriptor storage unit as the width. Each Bank has a unique Bank identification, and the same storage address corresponding to different Bank identifications is used to store message descriptors with the same length.

[0029] On the basis of the above-mentioned organization structure of the Bank chain table, the embodiment of the present application proposes a fragmented storage scheme taking the minimum descriptor length as the basic storage unit, taking the number of Banks corresponding to the length of the message descriptor, and all Banks sharing the same storage address mapping. For short message descriptors, only one or a small number of basic storage units are occupied; for long descriptors, they can be occupied as needed. Each message descriptor can sequentially occupy the unoccupied storage address of the Bank, and the Bank with free space can be efficiently utilized by subsequent message descriptors.

[0030] In summary, the embodiment of the present application provides a message data processing method, which can store message descriptors in multiple Banks in address order by providing a Bank chain table storage mode with multiple Banks, can support variable-length data processing with minimum cache cost, and can efficiently manage message descriptors. Under the premise of ensuring the order requirement of message transmission, the memory access delay can be reduced, the resources can be effectively utilized, and the optimal balance between performance and resources can be achieved.

[0031] Further, on the basis of the above-mentioned embodiment, the embodiment of the present application further provides another message data processing method, which refers to Figure 2 The method includes the following steps: Step S202, obtaining a message descriptor to be stored.

[0032] Step S204, extracting the length of the message descriptor.

[0033] Step S206, searching for a storage address for storing the length in a preset storage area.

[0034] In combination with the above steps, each storage address of the preset storage area in the embodiment of the present application can be used to store a message descriptor of a corresponding length, wherein the storage address of each message descriptor can be determined in sequence from the bank according to the transmission order, and the current storage address is determined as the storage address used to store the corresponding length. For example, there are message descriptors of 32B, 64B, 128B and 256B lengths, and the corresponding multi-bank linked list storage design of the embodiment of the present application is described with reference to Figure 3 The width of each bank is 32B, and 8 banks are shown. When data0, data1, data2, data3 and data4 of the lengths of 32 Byte, 64 Byte, 128 Byte, 256 Byte and 32 Byte respectively need to be written into the linked list in sequence. When data0 of the length of 32 Byte is written into the linked list, the linked list allocates the address 0 of bank0 to store; when data1 of the length of 64 Byte is written into the linked list, the linked list allocates the addresses 1 of bank0 and bank1 to store; when data2 of the length of 128 Byte is written into the linked list, the linked list allocates the addresses 2 of bank0, bank1, bank2 and bank3 to store; and when data3 of the length of 256 Byte is written into the linked list, the linked list allocates the addresses 3 of bank0, bank1, bank2, bank3, bank4, bank5, bank6 and bank7 to store. In summary, the message descriptors of different lengths correspond to a storage address respectively.

[0035] In an implementation, a corresponding relationship between the length of the message descriptor and the storage address can be set, and the corresponding relationship is stored in a storage table. When the corresponding storage address of the message descriptor is determined, the pre-configured storage table can be acquired, and the storage address corresponding to the length is determined based on the storage table.

[0036] In an implementation, the storage address of each length of the message descriptor stored can be recorded in the process of real-time transmission of data, and the corresponding relationship between the storage address and the length is dynamically recorded in the above storage table, so that when a message descriptor of the same length is received, the storage address that can be stored can be automatically determined, and intelligent identification and dynamic allocation of the same length are realized.

[0037] Step S208, it is judged whether the number of the storage addresses not occupied in the found storage addresses is greater than or equal to the number of the storage addresses required by the length of the message descriptor.

[0038] Step S210, if yes, it is determined that the found storage address matches the length of the message descriptor.

[0039] Step S212, according to the arrangement order of the Banks, the packet descriptor is stored in the unoccupied storage address in turn.

[0040] Step S214, if the number of unoccupied storage addresses in the found storage address is less than the number of storage addresses required by the length of the packet descriptor; the first Bank is obtained, and the unoccupied storage addresses in the first Bank are obtained. The packet descriptor is stored in the same storage address in each bank in turn, taking the unoccupied storage addresses in the first Bank as the starting address, according to the arrangement order of the Banks.

[0041] In combination with the above steps, the number of Banks of the preset storage area is set in advance, and the packet descriptor of the same length cannot be completely stored in the storage address of the same length. The embodiment of the application determines the remaining number of Banks of the found storage address that can be used for storage, determines whether the current packet descriptor can be completely stored, and if so, stores the current packet descriptor in the storage address. For example, in combination with the above steps, when data4 of 32 Byte length needs to be written into the chain table again, the embodiment of the application first determines whether address 0 can store data, and if so, stores data4 in address 0 of bank1.

[0042] Further, only when bank1~bank7 of address 0 are occupied and the data4 cannot be stored, a new unoccupied storage address is determined from the chain table. The starting storage position of the unoccupied storage address is the Bank set as the starting bit in the Bank chain table, that is, the first Bank. Corresponding to Figure 3 , the starting bit is bank0, and the new storage address is address 4. In summary, the same is true in turn.

[0043] For the packet descriptor of 128 Byte length, it is determined whether there are enough banks such as bank4, bank5, bank6 and bank7 corresponding to address 2 (corresponding to the above data2, 128 Byte length). If the same storage addresses of these banks are not occupied, the packet descriptor is stored in the address, otherwise, step S212 is performed, that is, a new address is determined in the chain table. In summary, for the packet descriptor of the same length, the embodiment of the application first occupies different banks of the same address, and only when all banks of the same address are occupied, the bank of the next address is occupied, which can improve the utilization rate of the cache while not affecting the performance.

[0044] The Bank chain table storage mode of the plurality of Banks in the embodiment of the application can set the Bank width according to a preset minimum descriptor storage unit, for example, the current setting is 32 Byte. In addition, the number of Banks can be determined by the maximum length of the message descriptor, and further, the plurality of Banks can be sorted according to the Bank identifier to generate a Bank array. In an implementation, the Bank identifier can be represented by a number or by an arbitrary character, Figure 3 The Bank identifier is identified in the form of 0-8 numbers.

[0045] In an implementation, the maximum length of the message descriptor can be the theoretical maximum value supported by hardware or can represent the maximum length of the message descriptor in the current transmission queue, for example, 128 Byte. Correspondingly, the target Bank chain table corresponding to the number of Banks and the maximum length can be found from the preset database, and the storage area where the target Bank chain table is located is determined as the preset storage area, so that the message descriptor of each transmission queue can be stored in the matching Bank chain table, the address is saturatedly allocated, and the chain table space is effectively utilized.

[0046] Further, the embodiment of the application further provides a message data processing device, Figure 4 The structural schematic diagram of the embodiment of the application is shown, and the following description is made with reference to Figure 4 The device comprises a data acquisition module 100 configured to acquire a message descriptor to be stored, a data processing module 200 configured to extract the length of the message descriptor, a search module 300 configured to search at least one storage address corresponding to the length in a preset storage area, wherein the preset storage area is configured in a Bank chain table storage mode of a plurality of Banks, each Bank has a unique Bank identifier, and each Bank comprises a plurality of storage addresses; the same storage address corresponding to different Bank identifiers is used to store message descriptors with the same length; and the width of each Bank is a preset minimum descriptor storage unit; and an execution module 400 configured to sequentially store the message descriptor into the storage address according to the arrangement order of the Banks.

[0047] The device embodiment of the embodiment of the application provides a message data processing device, and the implementation principle and the generated technical effects are the same as those of the foregoing method embodiment. For brevity of description, the part not mentioned in the device embodiment can be referred to the corresponding content in the foregoing method embodiment.

[0048] The embodiment of the application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the foregoing Figures 1 to 2The steps of any of the methods shown. Embodiments of the present invention also provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the above-described steps. Figures 1 to 2 The steps of any of the methods shown.

[0049] This invention also provides a schematic diagram of the structure of an electronic device, such as... Figure 5 The diagram shown is a structural schematic of the electronic device, which includes a processor 51 and a memory 50. The memory 50 stores computer-executable instructions that can be executed by the processor 51. The processor 51 executes the computer-executable instructions to implement the above-mentioned... Figures 1 to 5 Any of the methods shown.

[0050] exist Figure 5 In the illustrated embodiment, the electronic device further includes a bus 52 and a communication interface 53, wherein the processor 51, the communication interface 53, and the memory 50 are connected via the bus 52. The memory 50 may include high-speed random access memory (RAM) or non-volatile memory, such as at least one disk drive. Communication between this system network element and at least one other network element is achieved through at least one communication interface 53 (which can be wired or wireless), using the Internet, wide area network, local area network, metropolitan area network, etc. Bus 52 can be an ISA (Industry Standard Architecture) bus, a PCI (Peripheral Component Interconnect) bus, or an EISA (Extended Industry Standard Architecture) bus, or an AMBA (Advanced Microcontroller Bus Architecture) bus. AMBA defines three types of buses: APB (Advanced Peripheral Bus), AHB (Advanced High-performance Bus), and AXI (Advanced deXtensible Interface). Bus 52 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The symbol is represented by a single double-headed arrow, but this does not mean that there is only one bus or one type of bus.

[0051] The processor 51 can be an integrated circuit chip having signal processing capability. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 51 or the instruction in the form of software. The processor 51 described above can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiments of the present application can be directly embodied as a hardware decoding processor for execution, or a combination of hardware and software modules in the decoding processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium in the memory is read by the processor 51, and the hardware thereof is combined to complete the foregoing Figures 1 to 2 any of the methods described.

[0052] The computer program product of the method and device for processing packet data provided by the embodiments of the present application includes a computer readable storage medium storing program codes, the instructions included in the program codes can be used to execute the method described in the foregoing method embodiments, and the specific implementation can be referred to the method embodiments, which will not be described herein. Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process of the system described above can refer to the corresponding process in the foregoing method embodiments, which will not be described herein.

[0053] In addition, in the description of the embodiments of the present application, unless otherwise explicitly specified and limited, the terms "mounting", "connection", "connecting" should be understood in a broad sense, for example, can be fixedly connected, can be detachably connected, or integrally connected; can be mechanically connected, can be electrically connected; can be directly connected, can be indirectly connected through an intermediate medium, can be internal communication of two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. If the functions are realized in the form of software function units and sold or used as independent products, they can be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the present application can be embodied in the form of software products, and the computer software products are stored in a storage medium, including a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in various embodiments of the present application. The foregoing storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, and various media that can store program codes.

[0054] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second", "third" are only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0055] Finally, it should be noted that: the above embodiments are only specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, and are not limited thereto, the protection scope of the present application is not limited thereto, although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art within the technical scope disclosed by the present application can modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to part of the technical features; and these modifications, changes or replacements do not make the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for processing message data, characterized in that, The method includes: Retrieve the message descriptor to be stored; Extract the length of the message descriptor; In a preset storage area, at least one storage address corresponding to the length is searched; wherein, the preset storage area is configured as a linked list storage method with multiple banks, each bank has a unique bank identifier, and each bank includes multiple storage addresses; the same storage address corresponding to different bank identifiers is used to store message descriptors of the same length; and the width of each bank is a preset minimum descriptor storage unit; The message descriptors are stored sequentially into the storage address according to the arrangement order of the Bank.

2. The method according to claim 1, characterized in that, The step of searching for at least one storage address in a preset storage area that corresponds to the length of the message descriptor includes: Locate the storage address in the preset storage area to store the specified length; Determine whether the number of unoccupied storage addresses among the found storage addresses is greater than or equal to the number of storage addresses required for the length of the message descriptor; If so, determine that the found storage address matches the length of the message descriptor.

3. The method according to claim 2, characterized in that, The step of searching for the storage address for storing the length in the preset storage area further includes: Obtain a pre-configured storage table, wherein the storage table is used to record the correspondence between each storage address in the preset storage area and the length of the message descriptor, and the correspondence is used to indicate that a message descriptor of preset length is stored in the corresponding storage address; The storage address corresponding to the length is determined based on the storage table.

4. The method according to claim 2, characterized in that, The step of storing the message descriptors sequentially into the storage address according to the arrangement order of the Bank includes: According to the arrangement order of the Bank, the message descriptors are stored sequentially into the unoccupied storage addresses.

5. The method according to claim 2, characterized in that, The method further includes: If it is determined that the number of unoccupied storage addresses among the found storage addresses is less than the number of storage addresses required for the length of the message descriptor; Then, obtain the first bank and the unoccupied storage addresses in the first bank. Starting from the unoccupied storage addresses in the first bank, store the message descriptors sequentially into the same storage addresses in each bank according to the order of the banks. Wherein, the first Bank is the Bank set as the starting position in the Bank linked list.

6. The method according to claim 1, characterized in that, The method further includes: Obtain the maximum length of the message descriptors in the transmission queue where the message descriptor is located; Based on the maximum length, search the preset database for the target Bank linked list whose number of Banks corresponds to the maximum length, and determine the storage area where the target Bank linked list is located as the preset storage area.

7. The method according to claim 1, characterized in that, The method further includes: The multiple banks are sorted according to the bank identifier to generate a bank array.

8. A message data processing apparatus, characterized in that, The device includes: The data acquisition module is used to acquire the message descriptor to be stored. The data processing module is used to extract the length of the message descriptor; A lookup module is used to find at least one storage address corresponding to the length in a preset storage area; wherein the preset storage area is configured as a Bank linked list storage method with multiple Banks, each Bank has a unique Bank identifier, and each Bank includes multiple storage addresses; the same storage address corresponding to different Bank identifiers is used to store message descriptors of the same length; and the width of each Bank is a preset minimum descriptor storage unit; The execution module is used to store the message descriptors sequentially into the storage address according to the arrangement order of the Bank.

9. An electronic device, characterized in that, The electronic device includes a processor and a memory, the memory storing computer-executable instructions that can be executed by the processor, the processor executing the computer-executable instructions to implement the steps of the message data processing method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, which, when executed by a processor, performs the steps of the message data processing method according to any one of claims 1 to 7.

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