Semiconductor memory device including vertical channel transistor and method of manufacturing the same

Abstract

A semiconductor memory device including a vertical channel transistor and a method of manufacturing the same. The semiconductor memory device includes: a bit line extending in a first direction on a substrate; a filling insulating layer including a channel trench disposed on the bit line and extending in a second direction intersecting the first direction; a first gate insulating layer extending along a side surface and a lower surface of the filling insulating layer; a channel layer extending along a lower surface of the first gate insulating layer and a portion of a side surface of the first gate insulating layer; a word line disposed between a side surface of the filling insulating layer and a side surface of the first gate insulating layer; a gate isolation insulating layer disposed in the channel trench and defined by the bit line and the channel layer; and a data storage pattern electrically connected to the channel layer, in which at least one offset insulating layer is disposed on one side of the word line.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0059429, filed with the Korean Intellectual Property Office on May 3, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Embodiments of the present invention relate to a semiconductor memory device and a method of manufacturing the semiconductor memory device, and more specifically, to a semiconductor memory device including a vertical channel transistor (VCT) and a method of manufacturing the semiconductor memory device. Background Technology

[0004] As the integration density of semiconductor memory devices gradually increases, the integration density of the semiconductor devices contained within them also increases. Since the integration density of two-dimensional (2D) or planar semiconductor memory devices is primarily determined by the area occupied by a single memory cell, it can be affected by the level of technology used to form fine patterns. However, the expensive equipment required to increase pattern fineness may limit the improvement in the integration density of 2D or planar semiconductor memory devices. Therefore, to improve the integration density of semiconductor devices, vertical channel transistors have been developed to replace planar channel transistors that can be formed planarly on semiconductor substrates. Summary of the Invention

[0005] According to an embodiment of the present invention, a semiconductor memory device includes: a bit line extending on a substrate along a first direction; a filling insulating layer including a channel trench disposed on the bit line and extending along a second direction intersecting the first direction; a first gate insulating layer extending along a side surface and a lower surface of the filling insulating layer; a channel layer extending along a portion of the lower surface and a side surface of the first gate insulating layer; a word line disposed between the side surface of the filling insulating layer and the side surface of the first gate insulating layer; a gate isolation insulating layer disposed in the channel trench and defined by the bit line and the channel layer; and a data storage pattern electrically connected to the channel layer, wherein at least one offset insulating layer is disposed on one side of the word line.

[0006] According to an embodiment of the present invention, a method of manufacturing a semiconductor memory device includes: forming a bit line extending along a first direction on a substrate; forming a gate isolation insulating layer in a channel trench disposed on the bit line and extending along a second direction intersecting the first direction; forming a channel layer extending along a side surface of the gate isolation insulating layer and a top surface of the bit line; forming a first gate insulating layer on the channel layer and the gate isolation insulating layer; and forming a first offset insulating layer on the first gate insulating layer. Attached Figure Description

[0007] The above and other aspects of the inventive concept will become more apparent by describing in detail embodiments thereof with reference to the attached drawings, in which:

[0008] Figure 1 is a layout diagram of a semiconductor memory device according to an embodiment of the inventive concept;

[0009] Figure 2 is a cross-sectional view taken along line I-I' of Figure 1 a semiconductor memory device according to an embodiment of the inventive concept;

[0010] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E and Figure 3F are cross-sectional views illustrating an example of a first offset insulating layer of a semiconductor memory device according to an embodiment of the inventive concept;

[0011] Figure 4 is a cross-sectional view taken along line I-I' of Figure 1 a semiconductor memory device according to an embodiment of the inventive concept;

[0012] Figure 5A , Figure 5B , Figure 5C , Figure 5D , Figure 5E and Figure 5F are cross-sectional views illustrating an example of a second offset insulating layer of a semiconductor memory device according to an embodiment of the inventive concept;

[0013] Figure 6 , Figure 7 , Figure 8 and Figure 9 are cross-sectional views taken along line I-I' of Figure 1 a semiconductor memory device according to an embodiment of the inventive concept;

[0014] Figure 10 is a flowchart illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the inventive concept;

[0015] Figure 11A , Figure 11B , Figure 11C , Figure 11D , Figure 11E , Figure 11F , Figure 11G , Figure 11H , Figure 11I , Figure 11J , Figure 11K , Figure 11L and Figure 11Mis a cross-sectional view of a method of manufacturing a semiconductor memory device including a first offset insulating layer according to an embodiment of the inventive concept; and

[0016] Figure 12A , Figure 12B , Figure 12C , Figure 12D , Figure 12E , Figure 12F , Figure 12G , Figure 12H , Figure 12I , Figure 12J and Figure 12K is a cross-sectional view of a method of manufacturing a semiconductor memory device including a second offset insulating layer according to an embodiment of the inventive concept. DETAILED DESCRIPTION

[0017] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings. However, the embodiments can be varied and modified. Here, the embodiments are not to be understood as limited to the disclosure and the accompanying drawings. The embodiments are to be understood to include all changes, equivalents, and substitutes that fall within the idea and scope of the disclosure.

[0018] Technical terms used herein are used only for the purpose of describing embodiments of the inventive concept and not to limit the embodiments of the inventive concept. The singular forms "a," "an," and "the" are intended to include the plural forms, unless the context clearly indicates otherwise.

[0019] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the embodiments belong. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and / or the present disclosure, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0020] When the embodiments are described with reference to the drawings, like numerals can denote like components, and repetitive description related thereto can be omitted or briefly discussed.

[0021] In addition, terms such as first, second, A, B, (a), (b) can be used to describe components of the embodiments. Each of these terms is not used to define the nature, order or sequence of the corresponding components, but is used only to distinguish the corresponding components from other components. It is noted that if one component is described as being "connected," "coupled," or "joined" to another component in the specification, the former can be "connected," "coupled," and "joined" to the latter directly or via a further component.

[0022] Components having the same common function as components included in one embodiment will be described using the same name in other embodiments. Unless otherwise disclosed, the description of any embodiment of the inventive concept can be applied to other embodiments of the inventive concept, and the detailed description of the repeated configuration will be omitted or briefly discussed.

[0023] Figure 1 is a layout diagram of a semiconductor memory device according to an embodiment of the inventive concept. Figure 2 is a cross-sectional view taken along line I-I' of a semiconductor memory device according to an embodiment of the inventive concept. Figure 1 Figures 3A-3F is a cross-sectional view illustrating an example of a first offset insulating layer of a semiconductor memory device according to an embodiment of the inventive concept.

[0024] A semiconductor memory device according to an embodiment of the inventive concept can include memory cells each including a vertical channel transistor (VCT).

[0025] Referring to Figure 1 and Figure 2 , the semiconductor memory device 1A can include a bit line BL, a fill insulating layer 11 including a channel trench CHT, a first gate insulating layer 121, a second gate insulating layer 122, a channel layer 13, a word line WL, a gate isolation insulating layer 14, at least one offset insulating layer 151 and 152, a first cover insulating layer 161, a second cover insulating layer 162, a support insulating layer 17, an insulating film 18, a gate poly layer 19, a landing pad LP, and a data storage pattern DSP.

[0026] A substrate C extending in a first direction D1 and a second direction D2 can be provided. The first direction D1 and the second direction D2 can intersect each other and can be parallel to a top surface of the substrate C. The substrate C can be a semiconductor substrate. For example, the substrate C can be a silicon substrate. Further, the substrate C can include other materials such as silicon germanium, indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide, but the inventive concept is not limited thereto.

[0027] The bit line BL can be disposed on the substrate C. The insulating film 18 can be disposed between the substrate C and the bit line BL. The insulating film 18 can have a peripheral gate structure. The peripheral gate structure can include a peripheral gate insulating film, a peripheral lower conductive pattern, and a peripheral upper conductive pattern.

[0028] The bit line BL can extend longitudinally in the first direction D1. For example, a plurality of bit lines BL can be provided, and the plurality of bit lines BL are spaced apart from each other in the second direction D2.

[0029] ​The bit line BL can include at least one of, for example, doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3(SRO), (Ba, Sr)RuO3(BSRO), CaRuO3(CRO), or LSCo), but the inventive concept is not limited thereto. The bit line BL can include a single layer or multiple layers containing the above-described materials. The bit line BL can include a two-dimensional (2D) semiconductor material. For example, the 2D semiconductor material can include graphene, a carbon nanotube, or a combination thereof.

[0030] The data storage pattern DSP can be electrically connected to a channel layer to be described below. The landing pad LP can be disposed between the channel layer 13 and the data storage pattern DSP.

[0031] The landing pad LP can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape. The landing pad LP can include a conductive material. The landing pad LP can include, for example, at least one of doped polysilicon, a conductive metal nitride, a conductive metal silicide, a metal carbonitride, a conductive metal silicide, a conductive metal oxide, a 2D material, a metal, or a metal alloy.

[0032] The data storage pattern DSP can be disposed on the landing pad LP, respectively. The data storage pattern DSP can be arranged in a matrix form in the second direction D2 and the first direction D1. The data storage pattern DSP can completely or partially overlap the landing pad LP in the third direction D3. For example, each data storage pattern DSP can be in contact with the entire top surface of the corresponding landing pad LP or a portion of the top surface of the corresponding landing pad LP.

[0033] The data storage pattern DSP can be a capacitor. The data storage pattern DSP can include a capacitor dielectric film interposed between a storage electrode and a plate electrode. Here, the storage electrode can be in contact with the landing pad LP. In a plan view, the storage electrode can have various shapes, such as a circular shape, an elliptical shape, a rectangular shape, a square shape, a diamond shape, or a hexagonal shape.

[0034] In addition, the data storage pattern DSP can be a variable resistance pattern that can be switched between two resistance states by an electrical pulse applied to a storage element. For example, the data storage pattern DSP can include a phase change material having a crystalline state that varies according to an amount of current, a perovskite compound, a transition metal oxide, a magnetic material, a ferromagnetic material, or an antiferromagnetic material.

[0035] The fill insulating layer 11 can be a plurality of channel trenches CHT disposed on the bit line BL and extending in a second direction D2 intersecting the first direction D1. Adjacent channel trenches CHT can be spaced apart from each other in the first direction D1. Each of the channel trenches CHT can intersect the bit line BL. A bottom surface of each of the channel trenches CHT can be provided by the bit line BL. A sidewall of each of the channel trenches CHT can be provided by the fill insulating layer 11. The fill insulating layer 11 can be silicon nitride. The fill insulating layer 11 can be formed of a material having a relatively low dielectric constant.

[0036] The first gate insulating layer 121 can extend along the side surface and the bottom surface of the fill insulating layer 11. The first gate insulating layer 121 can be disposed between the word line WL and the channel layer 13. The first gate insulating layer 121 can extend in the second direction D2 parallel to the word line WL. The first gate insulating layer 121 can include, for example, a silicon oxide film, a silicon oxynitride film, a high-k dielectric insulating film having a dielectric constant greater than that of a silicon oxide film, or a combination thereof. Further, the first gate insulating layer 121 can be formed of aluminum oxide (ALO).

[0037] The channel layer 13 can extend along a portion of the side surface and the bottom surface of the first gate insulating layer 121. The channel layer 13 can include, for example, one of indium gallium zinc oxide (IGZO), indium zinc oxide (IZO) doped with impurities, indium oxide (InO), zinc oxide (ZnO), gallium oxide (GaO), tin oxide (SnO), aluminum zinc oxide (AZO), and / or indium tin oxide (ITO). In the indium zinc oxide (IZO) doped with impurities, the impurities can include, for example, at least one of magnesium (Mg), strontium (Sr), barium (Ba), scandium (Sc), yttrium (Y), lanthanum (La), titanium (Ti), zirconium (Zr), hafnium (Hf), aluminum (Al), tin (Sn), or tantalum (Ta). The indium (In), gallium (Ga), and zinc (Zn) can be included in the IGZO in the same or different amounts from each other.

[0038] The word line WL can be disposed between the side surface of the fill insulating layer 11 and the side surface of the first gate insulating layer 121. The word line WL can extend longitudinally in the second direction D2. Adjacent word lines WL can be spaced apart from each other in the first direction D1. A top surface of the word line WL can be disposed at a level lower than that of the top surface of the fill insulating layer 11. The word line WL can be formed along the sidewall of the channel trench CHT.

[0039] The word line WL can include at least one of, for example, doped polysilicon, a metal (e.g., Al, Cu, Ti, Ta, Ru, W, Mo, Pt, Ni, or Co), a conductive metal nitride (e.g., TiN, TaN, WN, NbN, TiAlN, TiSiN, TaSiN, or RuTiN), a conductive metal silicide, or a conductive metal oxide (e.g., PtO, RuO2, IrO2, SrRuO3(SRO), (Ba, Sr)RuO3(BSRO), CaRuO3(CRO), or LSCo), but the inventive concept is not limited thereto. The word line WL can include a single layer or multiple layers including the above-described materials. The word line WL can include a 2D semiconductor material. For example, the 2D semiconductor material can include graphene, a carbon nanotube, or a combination thereof.

[0040] The first cover insulating layer 161 can be disposed between the fill insulating layer 11 and the word line WL. The first cover insulating layer 161 can cover one surface of the word line WL facing the fill insulating layer 11. In addition, the first cover insulating layer 161 can also cover one surface of the offset insulating layers 151 and 152, which will be described below, and a surface of the first gate insulating layer 121 facing the fill insulating layer 11.

[0041] The first cover insulating layer 161 can include an insulating film that can be deposited using a film formation technique having excellent step coverage, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD). For example, the first cover insulating layer 161 can include at least one of silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. For example, the high-k dielectric material can include a metal oxide or a metal oxynitride. For example, the high-k dielectric material can include at least one of SiN, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but the inventive concept is not limited thereto. In other words, the first cover insulating layer 161 can be formed of a material having a dielectric constant greater than that of the fill insulating layer 11 to efficiently prevent oxidation of the word line WL.

[0042] The gate isolation insulating layer 14 can fill a portion of the channel trench CHT defined by the side surfaces of the bit line BL and the channel layer 13. The gate isolation insulating layer 14 can be, for example, silicon nitride. The gate isolation insulating layer 14 can be formed of a material having a relatively low dielectric constant.

[0043] A second cover insulating layer 162 can be disposed on the gate isolation insulating layer 14. For example, the second cover insulating layer 162 can include at least one of silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material can include a metal oxide or a metal oxynitride. For example, the high-k dielectric material can include at least one of SiN, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but the inventive concept is not limited thereto.

[0044] A second gate insulating layer 122 can be disposed on the second cover insulating layer 162. The second gate insulating layer 122 can cover at least a portion of a top surface of the second cover insulating layer 162, but embodiments of the inventive concept are not necessarily limited thereto. The second gate insulating layer 122 can include, for example, a silicon oxide film, a silicon oxynitride film, a high-k dielectric material having a dielectric constant greater than that of a silicon oxide film, or a combination thereof. The second gate insulating layer 122 can be formed of, for example, aluminum oxide (ALO).

[0045] A support insulating layer 17 can be disposed on the fill insulating layer 11 and the second gate insulating layer 122. The support insulating layer 17 can cover at least a portion of a top surface of the fill insulating layer 11 and cover at least a portion of a top surface of the second gate insulating layer 122. However, embodiments of the inventive concept are not necessarily limited thereto. For example, the support insulating layer 17 can include at least one of silicon oxide, silicon oxynitride, or a high-k dielectric material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material can include, for example, a metal oxide or a metal oxynitride. For example, the high-k dielectric material can include, for example, at least one of SiN, HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, or Al2O3, but the inventive concept is not limited thereto.

[0046] At least one offset insulating layer 151 or 152 can be disposed on one side of the word line WL. Due to this structure of the offset insulating layers 151 and 152, a distance between one side of the word line WL and the bit line BL or a distance between one side of the word line WL and the contact can be increased. The offset insulating layers 151 and 152 can extend in the second direction D2, similar to the word line WL. The offset insulating layers 151, 152 can be formed of, for example, silicon dioxide (SiO2) referred to as silica (SiO2).

[0047] The first offset insulating layer 151 can be disposed between the lower side of the word line WL and the first gate insulating layer 121. A first boundary surface 1511 at which the word line WL and an upper end of the first offset insulating layer 151 contact each other can be formed as a horizontal surface. For example, the first boundary surface 1511 can be an interface between the first offset insulating layer 151 and the word line WL. The first offset insulating layer 151 can serve as an offset with respect to the word line WL.

[0048] Accordingly, the distance between the word line WL and the bit line BL can be increased. Based on the above structure, the electric field intensity applied to the portion A between the effective channel EC and the bit line BL can be reduced. Here, the effective channel EC can be a portion in which the channel layer 13, the first gate insulating layer 121, and the word line WL overlap each other in the first direction D1.

[0049] The first offset insulating layer 151 can be provided below the word line WL, and accordingly, the electric field intensity applied to the portion A between the effective channel EC and the bit line BL can be reduced. Thus, the movement of defects from the outside of the effective channel EC to the inside of the effective channel EC can be suppressed. Furthermore, the reliability can be improved by increasing the lifetime of the oxide semiconductor memory device.

[0050] The distance between the word line WL and the bit line BL can be adjusted by changing the length of the first offset insulating layer 151 in the third direction D3. Thus, the electric field intensity applied to the portion A between the effective channel EC and the bit line BL can also be adjusted.

[0051] Reference Figures 3A-3F The first offset insulating layer 151 can have various shapes. Figures 3A-3F is an enlarged view illustrating a portion of the word line WL and a portion of the first offset insulating layer 151 of the semiconductor memory device 1A.

[0052] Reference Figure 3A The first boundary surface 1512 at which the upper end of the word line WL and the upper end of the first offset insulating layer 151 contact each other can be formed to be inclined in a downward direction (e.g., a diagonal downward direction) from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the length (or, for example, the height) of the first offset insulating layer 151 can gradually decrease from the first gate insulating layer 121 to the first cover layer 161.

[0053] Reference Figure 3B The first boundary surface 1513 at which the upper end of the word line WL and the upper end of the first offset insulating layer 151 contact each other can be formed to be inclined in an upward direction (e.g., a diagonal upward direction) from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the length (or, for example, the height) of the first offset insulating layer 151 can gradually increase from the first gate insulating layer 121 to the first cover layer 161.

[0054] Reference Figure 3C The first boundary surface 1514 at which the upper end of the word line WL and the upper end of the first offset insulating layer 151 contact each other can be formed such that a central portion of the first boundary surface 1514 can have a curved shape, for example, a sharp wedge shape that protrudes toward the word line WL.

[0055] Reference Figure 3DA first boundary surface 1515 in which the word line WL and the upper end of the first offset insulating layer 151 can be in contact with each other can be formed in a circular shape protruding toward the word line WL, such that a central portion of the first boundary surface 1515 can have a circular shape.

[0056] Referring to Figure 3E , a first boundary surface 1516 in which the word line WL and the upper end of the first offset insulating layer 151 can be in contact with each other can be formed in a stepped shape descending from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the first boundary surface 1516 can have a first level adjacent to the first gate insulating layer 121 and a second level lower than the first level and between the first level and the first cover layer 161.

[0057] Referring to Figure 3F , a first boundary surface 1517 in which the word line WL and the upper end of the first offset insulating layer 151 can be in contact with each other can be formed in a stepped shape ascending from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the first boundary surface 1517 can have a first level adjacent to the first gate insulating layer 121 and a second level higher than the first level and between the first level and the first cover layer 161.

[0058] Based on the various shapes of the first offset insulating layer 151 described above, the electric field intensity applied to the portion between the effective channel and the bit line can be controlled in various directions.

[0059] Hereinafter, redundant descriptions applicable equally among the above technical concepts are omitted, and differences from other embodiments are mainly described.

[0060] Figure 4 is a cross-sectional view taken along a line I-I' of a semiconductor memory device according to an embodiment of the inventive concept; Figure 1 is a cross-sectional view taken along a line I-I' of a semiconductor memory device according to an embodiment of the inventive concept; Figures 5A-5F is a cross-sectional view taken along a line I-I' of a semiconductor memory device according to an embodiment of the inventive concept;

[0061] Referring to Figure 4 , a second offset insulating layer 152 of the semiconductor memory device 1B can be disposed between the upper side of the word line WL and the first gate insulating layer 121. A second boundary surface 1521 in which the word line WL and the lower end of the second offset insulating layer 152 can be in contact with each other can be formed in a horizontal surface. Accordingly, the second offset insulating layer 152 can serve as an offset with respect to the word line WL.

[0062] Accordingly, the distance between the word line WL and the contact can be increased. Here, the contact can be defined by a component disposed on the channel layer 13. Based on the above structure, the electric field intensity applied to the portion B between the effective channel EC and the contact can be reduced.

[0063] By reducing the electric field intensity applied to the portion B between the effective channel EC and the contact, movement of defects from the outside of the effective channel EC to the inside of the effective channel EC can be suppressed. Furthermore, reliability can be improved by increasing the lifetime of the oxide semiconductor memory device.

[0064] Reference Figures 5A-5F The second offset insulating layer 152 can have various shapes. Figures 5A-5F is an enlarged view illustrating a portion of the word line WL and a portion of the second offset insulating layer 152 of the semiconductor memory device IB.

[0065] Reference Figure 5A The second boundary surface 1522 at which the word line WL and the lower end of the second offset insulating layer 152 contact each other can be formed to be inclined in a downward direction (e.g., a diagonal downward direction) from the first gate insulating layer 121 to the first cover insulating layer 161.

[0066] Reference Figure 5B The second boundary surface 1523 at which the word line WL and the lower end of the second offset insulating layer 152 contact each other can be formed to be inclined in an upward direction (e.g., a diagonal upward direction) from the first gate insulating layer 121 to the first cover insulating layer 161.

[0067] Reference Figure 5C The second boundary surface 1524 at which the word line WL and the lower end of the second offset insulating layer 152 contact each other can be formed such that a central portion of the second boundary surface 1524 can have a curved shape, for example, a sharp wedge shape that protrudes toward the word line WL.

[0068] Reference Figure 5D The second boundary surface 1525 at which the word line WL and the lower end of the second offset insulating layer 152 contact each other can be formed such that a central portion of the second boundary surface 1525 can have a circular shape that protrudes toward the word line WL.

[0069] Reference Figure 5E The second boundary surface 1526 at which the word line WL and the lower end of the second offset insulating layer 152 contact each other can be formed in a stepped shape that rises from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the second boundary surface 1526 can have a first level adjacent to the first gate insulating layer 121 and a second level higher than the first level and between the first level and the first cover layer 161.

[0070] Reference Figure 5FThe second boundary surface 1527, at which the word line WL and the lower end of the second offset insulating layer 152 contact each other, can be formed in a stepped shape descending from the first gate insulating layer 121 to the first cover insulating layer 161. For example, the second boundary surface 1527 can have a first level adjacent to the first gate insulating layer 121 and a second level lower than the first level and between the first level and the first cover layer 161.

[0071] Based on the various shapes of the second offset insulating layer 152 described above, the electric field intensity applied to the portion between the effective channel and the contact can be controlled in various directions.

[0072] Figures 6-9 is a cross-sectional view of a semiconductor memory device according to an embodiment taken along line I-I' of Figure 1 is a cross-sectional view of a semiconductor memory device according to an embodiment taken along line I-I' of

[0073] Referring to Figure 6 The semiconductor memory device 1C can include two offset insulating layers. The first offset insulating layer 151 can be disposed between the lower side of the word line WL and the first gate insulating layer 121, and the second offset insulating layer 152 can be disposed between the upper side of the word line WL and the first gate insulating layer 121.

[0074] The first boundary surface, at which the word line WL and the upper end of the first offset insulating layer 151 contact each other, can be formed as a horizontal surface, an inclined surface, a stepped surface, or a surface in which the center portion protrudes toward the word line WL. Also, the second boundary surface, at which the word line WL and the lower end of the second offset insulating layer 152 contact each other, can be formed as a horizontal surface, an inclined surface, a stepped surface, or a surface in which the center portion protrudes toward the word line WL.

[0075] Referring to Figures 7-9 The semiconductor memory devices 1D, 1E, and 1F can each include a gate poly layer 19 disposed between the first gate insulating layer 121 and the word line WL. The gate poly layer 19 can include at least one of doped polysilicon or doped poly silicon germanium (poly SiGe).

[0076] Referring to Figure 7 The first offset insulating layer 151 of the semiconductor memory device 1D can be disposed between the first gate insulating layer 121 and the lower side of each of the word line WL and the gate poly layer 19. Accordingly, the first offset insulating layer 151 can serve as an offset with respect to the word line WL.

[0077] Referring to Figure 8The second offset insulating layer 152 of the semiconductor storage device 1E can be disposed on the gate poly layer 19. For example, the second offset insulating layer 152 can be formed in a space defined by a side surface of an upper portion of the word line WL, a top surface of the gate poly layer 19, and a side surface of the first gate insulating layer 121. Accordingly, the second offset insulating layer 152 can serve as an offset with respect to the word line WL.

[0078] Referring to Figure 9 The semiconductor storage device 1F can include two offset insulating layers. The first offset insulating layer 151 can be disposed between the first gate insulating layer 121 and a lower side of each of the word line WL and the gate poly layer 19. In addition, the second offset insulating layer 152 can be disposed on the gate poly layer 19 and between the word line WL and the first gate insulating layer 121. In other words, the second offset insulating layer 152 can be formed in a space defined by a side surface of an upper portion of the word line WL, a top surface of the gate poly layer 19, and a side surface of the first gate insulating layer 121.

[0079] Figure 10 FIG. 1 is a flowchart illustrating a method of manufacturing a semiconductor storage device according to an embodiment of the inventive concept.

[0080] Referring to Figure 10 The method can include operations of forming a bit line extending in a first direction on a substrate (operation S11), forming a gate isolation insulating layer configured to fill a portion of a channel trench disposed on the bit line and extending in a second direction intersecting the first direction (operation S12), forming a channel layer extending along a side surface of the gate isolation insulating layer and a top surface of the bit line (operation S13), forming a first gate insulating layer covering the channel layer and the gate isolation insulating layer (operation S14), and forming a first offset insulating layer covering the first gate insulating layer (operation S15).

[0081] The method can further include etching a top surface and a bottom surface of the first offset insulating layer to leave a side surface of the first offset insulating layer (operation S16), and etching the side surface of the first offset insulating layer to leave a portion of the side surface of the first offset insulating layer corresponding to a preset height (operation S17).

[0082] The method can further include forming a word line covering the first gate insulating layer and the portion of the first offset insulating layer left by etching the side surface of the first offset insulating layer (operation S18), and etching a top surface and a bottom surface of the word line to leave a side surface of the word line (operation S19).

[0083] The method can further include etching the side surface of the word line to leave a portion of the side surface of the word line corresponding to a preset height (operation S20).

[0084] The method can further include operations of forming a first cover insulating layer covering the first gate insulating layer, a portion of the first offset insulating layer left by etching a side surface of the first offset insulating layer, and a portion of the word line left by etching a side surface of the word line (operation S21), forming a fill insulating layer on the first cover insulating layer (operation S22), and exposing an upper end of a side surface of the channel layer and forming a data storage pattern electrically connected to the channel layer (operation S23).

[0085] Figures 11A-11M is described according to an embodiment of the inventive concept Figure 1 A cross-sectional view of a method of manufacturing a semiconductor memory device 1A including a first offset insulating layer 151 according to an embodiment of the inventive concept.

[0086] Referring to Figure 11A A bit line BL extending in a first direction can be formed on the substrate C. An insulating film 18 can be formed between the substrate C and the bit line BL. A gate isolation insulating layer 14 can be formed to fill a portion of a channel trench disposed on the bit line BL and extending in a second direction intersecting the first direction. A second cover insulating layer 162 can be disposed on the gate isolation insulating layer 14. A channel layer 13 extending along a side surface of the gate isolation insulating layer 14, a side surface of the second cover insulating layer 162, and a top surface of the bit line BL can be formed. A first gate insulating layer 121 can be formed to cover a top surface of the channel layer 13 and the second cover insulating layer 162.

[0087] Referring to Figure 11B The first offset insulating layer 151 can be formed to cover the first gate insulating layer 121. To form the first offset insulating layer 151, silicon dioxide (SiO2) can be deposited.

[0088] Referring to Figure 11C An upper portion and a lower portion of the first offset insulating layer 151 can be removed through an etching process. Accordingly, only a lateral portion (e.g., a side surface) of the first offset insulating layer 151 covering a side surface of the first gate insulating layer 121 can be left.

[0089] Referring to Figure 11D A sacrificial pattern S can be deposited on the first gate insulating layer 121 at a preset height. For example, the sacrificial pattern S can be deposited on an upper surface and / or a bottom surface of the first gate insulating layer 121. The sacrificial pattern S can be a spin-on hard mask (SOH). Accordingly, a portion of the side surface of the first offset insulating layer 151 corresponding to the preset height can be covered by the sacrificial pattern S, and a remaining portion of the side surface of the first offset insulating layer 151 can remain exposed.

[0090] Referring to Figure 11EThe exposed remaining portions of the side surface of the first offset insulating layer 151 can be removed through a side etching process. Further, the sacrificial pattern S can be removed through an SOH ashing process. Accordingly, only a portion of the first offset insulating layer 151 having a preset height can be left.

[0091] Referring to Figure 11F The word line WL can be formed to cover the first gate insulating layer 121 and the first offset insulating layer 151.

[0092] Referring to Figure 11G The upper and lower portions of the word line WL can be removed through an etching process. For example, a portion of the word line WL extending in the third direction along the sidewall of the first gate insulating layer 121 and disposed on the upper surface of the first offset insulating layer 151 can be left, and a portion of the word line WL extending in the first direction on the channel layer 13 and on the uppermost surface of the first gate insulating layer 121 can be removed through the etching process. Accordingly, only a lateral portion of the word line WL can be left.

[0093] Referring to Figure 11H Another sacrificial pattern S can be deposited on the first gate insulating layer 121 at a preset height. For example, the sacrificial pattern S can be deposited on the lower surface of the first gate insulating layer 121. Accordingly, a portion of the side surface of the word line WL corresponding to the preset height can be covered with the sacrificial pattern S, and the remaining portion of the side surface of the word line WL can remain exposed.

[0094] Referring to Figure 11I The exposed remaining portions of the side surface of the word line WL can be removed through a side etching process. Further, the sacrificial pattern S can be removed through an SOH ashing process. Accordingly, a portion of the word line WL having a preset height can be left. Accordingly, the first offset insulating layer 151 having the preset height can be formed on the side surface of the first gate insulating layer 121, and the word line WL having the preset height can be formed on the first offset insulating layer 151.

[0095] Referring to Figure 11J The first cover insulating layer 161 can be formed to cover the first gate insulating layer 121, the first offset insulating layer 151, and the word line WL.

[0096] Referring to Figure 11K The fill insulating layer 11 can be formed on the first cover insulating layer 161. For example, the fill insulating layer 11 can fill a space defined by the bottom surface and the side surface of the first cover insulating layer 161. Here, the top surface of the fill insulating layer 11 can be formed to have substantially the same height as the top surface of the first cover insulating layer 161.

[0097] Referring to Figure 11LThe support insulating layer 17 can be formed to cover the top surface of the fill insulating layer 11 and the top surface of the first cover insulating layer 161.

[0098] Referring to Figure 11M The upper surface of the channel layer 13 can be exposed through an etching process. Subsequently, the channel layer 13 and the data storage pattern can be electrically connected to each other through the bonding pad.

[0099] Figures 12A-12K A method of manufacturing a semiconductor memory device 1B including a second offset insulating layer 152 according to an embodiment of the inventive concept is described. Figure 4 A cross-sectional view of a method of manufacturing a semiconductor memory device 1B including a second offset insulating layer 152 according to an embodiment of the inventive concept is described.

[0100] Referring to Figure 12A A bit line BL extending in a first direction can be formed on the substrate C. An insulating film 18 can be formed between the substrate C and the bit line BL. A gate isolation insulating layer 14 can be formed to fill a portion of a channel trench disposed on the bit line BL and extending in a second direction intersecting the first direction. A second cover insulating layer 162 can be disposed on the gate isolation insulating layer 14. A channel layer 13 extending along a side surface of the gate isolation insulating layer 14, a side surface of the second cover insulating layer 162, and a top surface of the bit line BL can be formed. A first gate insulating layer 121 can be formed to cover a top surface of the channel layer 13 and the second cover insulating layer 162.

[0101] Referring to Figure 12B A word line WL can be formed to cover the first gate insulating layer 121.

[0102] Referring to Figure 12C An upper portion and a lower portion of the word line WL can be removed through an etching process. Accordingly, only a lateral portion of the word line WL can be left.

[0103] Referring to Figure 12D A sacrificial pattern S can be deposited on the first gate insulating layer 121 at a preset height. For example, the sacrificial pattern S can be deposited on a lower surface of the first gate insulating layer 121. The sacrificial pattern S can be an SOH. Accordingly, a portion of a side surface of the word line WL corresponding to the preset height can be covered with the sacrificial pattern S, and a remaining portion of the side surface of the word line WL can remain exposed.

[0104] Referring to Figure 12E The remaining portion of the side surface of the word line WL that is exposed can be removed through a side etching process. In addition, the sacrificial pattern S can be removed through an SOH ashing process. Accordingly, a portion of the word line WL having the preset height can be left. In other words, the word line WL having the preset height can be formed on the side surface of the first gate insulating layer 121.

[0105] Referring to Figure 12FAn upper portion of a side surface of the word line WL facing the first gate insulating layer 121 can be partially removed by an etching process to form a space between the word line WL and the side surface of the first gate insulating layer 121.

[0106] Referring to Figure 12G The second offset insulating layer 152 can be formed in a portion of the word line WL left after the etching process. For example, the second offset insulating layer 152 can be formed in the space formed between the word line WL and the side surface of the first gate insulating layer 121. Accordingly, the second offset insulating layer 152 can be disposed between the upper side of the word line WL and the first gate insulating layer 121.

[0107] Referring to Figure 12H The first cover insulating layer 161 can be formed to cover the first gate insulating layer 121, the second offset insulating layer 152, and the word line WL.

[0108] Referring to Figure 12I The fill insulating layer 11 can be formed on the first cover insulating layer 161. For example, the fill insulating layer 11 can fill a space defined by a bottom surface and a side surface of the first cover insulating layer 161. Here, a top surface of the fill insulating layer 11 can be formed to have substantially the same height as a top surface of the first cover insulating layer 161.

[0109] Referring to Figure 12J The support insulating layer 17 can be formed to cover a top surface of the fill insulating layer 11 and a top surface of the first cover insulating layer 161.

[0110] Referring to Figure 12K An upper surface of the channel layer 13 can be exposed by an etching process. Subsequently, the channel layer 13 and the data storage pattern can be electrically connected to each other by a bonding pad.

[0111] As described above, in the semiconductor memory device and the method of manufacturing the semiconductor memory device, an offset insulating layer can be disposed on or under a word line to reduce an electric field intensity between an active channel and a bit line or between the active channel and a contact. Further, by using the offset insulating layer, a distance between the word line and the bit line or a distance between the word line and the contact can be increased. Accordingly, it is possible to suppress a defect from moving from an outside of the active channel to an inside of the active channel, and it is possible to improve reliability of the semiconductor memory device.

[0112] While the present inventive concept has been described with reference to embodiments thereof, it is to be understood that the inventive concept is not limited to the embodiments and constructions. Those skilled in the art comprehend variations and changes that can be made thereto without departing from the true spirit and central fairness of the inventive concept.

Claims

1. A semiconductor memory device, comprising: Bit lines extend along a first direction on the substrate; The filling insulation layer includes channels and grooves disposed on the bit line and extending along a second direction intersecting the first direction; A first gate insulating layer extends along the side surface and the lower surface of the filling insulating layer; A channel layer extends along the lower surface of the first gate insulating layer and a portion of the side surface of the first gate insulating layer; The word line is disposed between the side surface of the filling insulating layer and the side surface of the first gate insulating layer; A gate isolation insulating layer is disposed in the channel trench and defined by the bit line and the channel layer; as well as Data storage pattern, electrically connected to the channel layer, At least one offset insulating layer is disposed on one side of the word line.

2. The semiconductor memory device according to claim 1, wherein, A first offset insulating layer is disposed between the lower side of the word line and the first gate insulating layer.

3. The semiconductor memory device according to claim 2, wherein, The first boundary surface where the word line contacts the upper end of the first offset insulating layer is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface whose central portion protrudes toward the word line.

4. The semiconductor memory device according to claim 1, wherein, The second offset insulating layer is disposed between the upper side of the word line and the first gate insulating layer.

5. The semiconductor memory device according to claim 4, wherein, The second boundary surface where the word line contacts the lower end of the second offset insulating layer is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface whose central portion protrudes toward the word line.

6. The semiconductor memory device according to claim 1, wherein, The at least one offset insulating layer includes a first offset insulating layer and a second offset insulating layer. The first offset insulating layer is disposed between the lower side of the word line and the first gate insulating layer, and The second offset insulating layer is disposed between the upper side of the word line and the first gate insulating layer.

7. The semiconductor memory device according to claim 6, wherein, The first boundary surface where the word line contacts the upper end of the first offset insulating layer is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface whose central portion protrudes towards the word line. The second boundary surface where the word line contacts the lower end of the second offset insulating layer is formed as a horizontal surface, an inclined surface, a stepped surface, or a surface whose central portion protrudes toward the word line.

8. The semiconductor memory device according to claim 1, further comprising: A first covering insulating layer is disposed between the filling insulating layer and the word line. The first covering insulating layer covers one surface of the word line facing the filling insulating layer.

9. The semiconductor memory device according to claim 8, wherein, The first covering insulating layer also covers one surface of the offset insulating layer facing the filling insulating layer and one surface of the first gate insulating layer facing the filling insulating layer.

10. The semiconductor memory device according to claim 1, further comprising: A gate polycrystalline layer is disposed between the first gate insulating layer and the word line.

11. The semiconductor memory device according to claim 1, further comprising: A second cover insulating layer is disposed on the gate isolation insulating layer.

12. The semiconductor memory device of claim 11, further comprising: A second gate insulating layer is disposed on the second cover insulating layer.

13. The semiconductor memory device according to claim 12, further comprising: A supporting insulating layer is disposed on the filling insulating layer and the second gate insulating layer.

14. The semiconductor memory device according to claim 1, further comprising: An insulating film is disposed between the bit line and the substrate.

15. The semiconductor memory device according to claim 1, further comprising: The bonding pads are disposed between the channel layer and the data storage pattern.

16. A method for manufacturing a semiconductor memory device, the method comprising: A bit line extending along a first direction is formed on the substrate; A gate isolation insulating layer is formed in a channel trench disposed on the bit line and extending along a second direction intersecting the first direction; A channel layer is formed extending along the side surface of the gate isolation insulating layer and the top surface of the bit line; A first gate insulating layer is formed on the channel layer and the gate isolation insulating layer; as well as A first offset insulating layer is formed on the first gate insulating layer.

17. The method of claim 16, further comprising: The upper and lower portions of the first offset insulating layer are etched to leave a lateral portion of the first offset insulating layer. as well as The lateral portion of the first offset insulating layer is etched to leave a portion of the lateral portion of the first offset insulating layer corresponding to a predetermined height.

18. The method of claim 17, further comprising: A word line is formed, the word line covering the first gate insulating layer and the portion of the first offset insulating layer left by etching the lateral portion of the first offset insulating layer; as well as The upper and lower parts of the letter lines are etched to leave the horizontal portion of the letter lines.

19. The method of claim 18, further comprising: The horizontal portion of the character line is etched to leave a portion of the horizontal portion of the character line corresponding to a predetermined height.

20. The method of claim 19, further comprising: A first overlay insulating layer is formed on the first gate insulating layer, the portion of the first offset insulating layer left by etching the lateral portion of the first offset insulating layer, and the portion of the word line left by etching the lateral portion of the word line; A filler insulating layer is formed on the first covering insulating layer; Expose the upper surface of the channel layer; as well as A data storage pattern electrically connected to the channel layer is formed.

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