Preparation method of semiconductor structure and gallium arsenide bipolar transistor

Abstract

The invention discloses a preparation method of a semiconductor structure and a gallium arsenide bipolar transistor, and belongs to the technical field of semiconductors. The preparation method of the semiconductor structure comprises the following steps: sequentially forming a collector layer, a base layer, an emitter layer and an emitter mesa on a first side of a substrate; etching the first depths of the emitter layer, the base layer and the collector layer from a first region on the surface of the emitter layer by adopting dry etching to form a first platform with a first slope angle; the second depth of the collector layer exposed after dry etching is etched through wet etching, a second platform with a second slope angle is formed, the second slope angle is smaller than the first slope angle, and the sum of the first depth and the second depth is smaller than the thickness of the collector layer, the emitter layer or the base layer is prevented from being laterally etched in the wet etching process to influence electrode contact or device performance, the risk of metal interconnection failure is reduced, and the reliability of the semiconductor structure is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and in particular relates to a method for preparing a semiconductor structure and a gallium arsenide bipolar transistor. Background Technology

[0002] With the rapid development of 5G technology, radio frequency microwave communication technology has made great strides, and gallium arsenide heterojunction bipolar transistors (GaAs HBTs) have become an important part of radio frequency front-end power amplifier circuits.

[0003] In existing GaAs HBT device fabrication processes, the base electrode is often processed simultaneously when creating the collector step, typically using dry etching or wet etching methods. Traditional GaAs HBT device fabrication processes have drawbacks. Specifically, dry etching often results in steep steps that are unfavorable for metal interconnection, while wet etching, due to its isotropic nature, leads to large side etching depths, affecting electrode contact or device performance. Summary of the Invention

[0004] This application aims to address at least one of the technical problems existing in the prior art. To this end, this application proposes a method for fabricating a semiconductor structure and a gallium arsenide bipolar transistor. Through the synergistic effect of dry etching and wet etching, it prevents the emitter layer or base layer from being side-etched during the wet etching process, which could affect the electrode contact or device performance, and reduces the risk of metal interconnect failure, thereby improving the reliability of the semiconductor structure.

[0005] In a first aspect, this application provides a method for fabricating a semiconductor structure, comprising:

[0006] A collector layer, a base layer, an emitter layer, and an emitter mesa are sequentially formed on the first side of the substrate.

[0007] Dry etching is used to etch the emitter layer, base layer and collector layer to a first depth from a first region on the surface of the emitter layer, forming a first platform with a first slope angle;

[0008] Wet etching is used to etch the second depth of the collector layer exposed after dry etching, forming a second platform with a second slope angle. The second slope angle is smaller than the first slope angle, and the sum of the first depth and the second depth is smaller than the thickness of the collector layer.

[0009] According to the semiconductor structure fabrication method of this application, through the synergistic effect of dry etching and wet etching, a first platform is formed at a first depth of the base layer, emitter layer, and collector layer by dry etching. Then, a second platform with a second slope angle is formed at a second portion of the collector by wet etching. This prevents the emitter layer or base layer from being side-etched during the wet etching process, which would affect the electrode contact or device performance. Furthermore, the second slope angle formed by wet etching is smaller than the first slope angle. The inclined sidewalls help the metal to uniformly cover the collector mesa, reducing the risk of metal interconnect failure and improving the reliability of the semiconductor structure.

[0010] According to one embodiment of this application, the thickness of the first platform is 400nm to 600nm.

[0011] According to one embodiment of this application, the ratio of the first depth to the second depth is 1:2 to 1:4.

[0012] According to one embodiment of this application, the second ramp angle is 45° to 60°.

[0013] According to one embodiment of this application, the collector layer includes a lower collector epitaxial layer, a self-stopping layer, and an upper collector epitaxial layer stacked sequentially. A first depth is less than the thickness of the upper collector epitaxial layer, and a second depth is the sum of the depth of the upper collector epitaxial layer exposed after dry etching and the depth of the self-stopping layer. Wet etching is used to etch the second depth of the collector layer exposed after dry etching, including:

[0014] Wet etching was performed on the upper collector epitaxial layer exposed after dry etching using a phosphoric acid-hydrogen peroxide etching solution.

[0015] According to one embodiment of this application, after wet etching of the upper collector epitaxial layer exposed after dry etching using a phosphoric acid-hydrogen peroxide etching solution, the process further includes:

[0016] The self-stopping layer was wet-etched using a hydrochloric acid-based etching solution.

[0017] According to one embodiment of this application, dry etching is performed using fluorine-based plasma.

[0018] According to one embodiment of this application, before dry etching is used to etch the emitter layer, base layer, and collector layer to a first depth from a first region on the surface of the emitter layer to form a first platform with a first ramp angle, the method further includes:

[0019] A passivation layer is deposited on the emitter layer and the side of the emitter mesa away from the base.

[0020] Using the passivation layer as a mask, a dry etching process is performed.

[0021] The thickness of the base layer is 40nm to 60nm, the thickness of the emitter layer is 30nm to 50nm, and the thickness of the collector layer is 2μm to 3μm.

[0022] Secondly, this application provides a gallium arsenide bipolar transistor, which is prepared using the aforementioned fabrication method.

[0023] According to the gallium arsenide bipolar transistor of this application, through the synergistic effect of dry etching and wet etching, a first platform is formed at a first depth of the base layer, emitter layer and collector layer by dry etching, and then a second platform with a second slope angle is formed at a second portion of the collector by wet etching. This prevents the emitter layer or base layer from being side-etched during the wet etching process, which would affect the electrode contact or device performance. Moreover, the second slope angle formed by wet etching is smaller than the first slope angle. The inclined sidewall helps the metal to uniformly cover the collector mesa, reducing the risk of metal interconnect failure and improving the reliability of the semiconductor structure.

[0024] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0025] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the description of the embodiments taken in conjunction with the following drawings, in which:

[0026] Figure 1 This is one of the staged structural diagrams of the semiconductor structure fabrication method provided in the embodiments of this application;

[0027] Figure 2 This is one of the staged structural diagrams of the semiconductor structure fabrication method provided in the embodiments of this application;

[0028] Figure 3 This is the third schematic diagram of the stages of the semiconductor structure fabrication method provided in the embodiments of this application.

[0029] Figure label:

[0030] Substrate 10, collector layer 20, upper collector epitaxial layer 21, self-stopping layer 22, lower collector epitaxial layer 23, base layer 30, base metal 31, emitter layer 40, emitter mesa 41, emitter metal 42, first platform 50, second platform 60. Detailed Implementation

[0031] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0032] In the following description, a "circuit" refers to a conductive loop consisting of at least one element or sub-circuit connected by an electrical or electromagnetic link. When an element or circuit is said to be "coupled to" or "connected to" another element, or when an element / circuit is said to be "coupled at" or "connected at" two nodes, it can be directly coupled to or connected to the other element, or there may be intermediate elements. The connection between elements can be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between them.

[0033] In the description, the terms "first," "second," etc., are used to distinguish similar objects, not to describe a specific order or sequence. It should be understood that such numerical descriptors can be interchanged where appropriate so that embodiments of this application can be implemented in orders other than those illustrated or described herein, and the objects distinguished by "first," "second," etc., are generally of the same class, not limited in number; for example, a first object can be one or more. Furthermore, in the specification and claims, "and / or" indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0034] Furthermore, the use of terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., indicates that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0035] With the rapid development of 5G technology, radio frequency microwave communication technology has made great strides, and gallium arsenide heterojunction bipolar transistors (GaAs HBTs) have become increasingly important in radio frequency front-end power amplifier circuits. GaAs HBT devices have the advantages of high gain, low phase noise, good linearity, single-supply operation, and low cost, and have been widely used in laser or modulator driver circuits in fiber optic communication systems, as well as in high-speed circuits such as electrical multiplexers and demultiplexers, transimpedance amplifiers, and limiting amplifiers.

[0036] However, in existing GaAs HBT device fabrication processes, the fabrication of collector steps is one of the most critical steps. Currently, the commonly used methods for fabricating collector steps mainly include dry etching and wet etching. Although dry etching can effectively control the surface width according to the photolithographic pattern, thereby effectively reducing parasitic capacitance and improving frequency characteristics, the anisotropy of etching can make the steps steep, which is not conducive to subsequent metal interconnection. Wet etching has the advantages of high selectivity and stable control by inserting self-stopping layers, but because wet etching is isotropic, lateral etching occurs simultaneously with vertical etching, affecting electrode contact or device performance.

[0037] This application proposes a method for fabricating a semiconductor structure and a gallium arsenide bipolar transistor. By combining dry etching and wet etching, it prevents lateral erosion defects caused by the isotropic nature of traditional wet etching processes, reduces the risk of metal interconnect failure caused by steep slopes generated by dry etching, and improves the reliability of the semiconductor structure.

[0038] Figures 1 to 3 This illustration shows the staged structures of a semiconductor structure fabricated using the method provided in this application. (Refer to...) Figures 1 to 3 One embodiment of this application proposes a method for preparing a semiconductor structure, including steps 10, 20 and 30.

[0039] Step 10: Sequentially form a collector layer 20, a base layer 30, an emitter layer 40, and an emitter mesa 41 on the first side of the substrate 10;

[0040] Step 20: Using dry etching, the emitter layer 40, the base layer 30 and the collector layer 20 are etched to a first depth from a first region on the surface of the emitter layer 40 to form a first platform 50 with a first slope angle.

[0041] Step 30: Wet etching is used to etch the second depth of the collector layer 20 exposed after dry etching to form a second platform 60 with a second slope angle. The second slope angle is smaller than the first slope angle, and the sum of the first depth and the second depth is smaller than the thickness of the collector layer.

[0042] Reference Figure 1 The substrate 10, as the basic structure of the semiconductor structure, mainly provides rigid support for the entire semiconductor structure, ensuring that the device maintains structural integrity during subsequent processes and long-term use. The material of the substrate 10 can be selected according to the actual application requirements, and is not limited here. For example, the substrate 10 can be gallium arsenide (GaAs).

[0043] On the first side of the substrate 10 after cleaning and surface treatment, the collector layer 20, the base layer 30 and the emitter layer 40 can be epitaxially grown sequentially by metal-organic chemical vapor deposition or molecular beam epitaxy.

[0044] The collector layer 20 is mainly used to collect electrons or holes injected from the emitter, regulated by the base, and arriving at the collector to form the output current. The material of the collector layer 20 can be selected according to the actual application scenario, and is not limited here. For example, the material of the collector layer 20 may include gallium arsenide.

[0045] The base layer 30 is mainly used to form a heterojunction with the emitter, blocking the reverse diffusion of electrons from the base to the emitter, precisely controlling the carrier throughput rate, and improving electron injection efficiency. The material of the base layer 30 can be selected according to the actual application scenario, and is not limited here. For example, the material of the base layer 30 can include gallium arsenide, indium gallium arsenide (InGaAs), or gallium arsenide antimony (GaAsSb), etc.

[0046] The emitter layer 40 provides a high concentration of charge carriers (such as electrons) that can be efficiently injected into the base region through the heterojunction barrier. The material of the emitter layer 40 can be selected according to the actual application scenario and is not limited here. For example, the material of the emitter layer 40 may include indium gallium arsenide phosphide (InGaAsP), indium aluminum gallium phosphide (InAlGaP), or indium gallium phosphide (InGaP), etc.

[0047] The desired emitter mesa 41 pattern is formed on the surface of the emitter layer 40 using photoresist, and the emitter mesa 41 is formed by etching. The emitter mesa 41 can reduce the parasitic capacitance and inductance of the device and improve the frequency response of the device.

[0048] It should be noted that an emitter metal 42 is formed on the side of the emitter mesa 41 away from the base layer 30, and a base metal 31 is formed on the side of the emitter layer 40 and the base layer 30. The base metal 31 forms an ohmic contact with the base layer 30 through the emitter layer 40 via a high-temperature alloy.

[0049] Reference Figure 2After the emitter mesa 41 is formed, photoresist is coated onto the surface of the semiconductor structure. An etching pattern is defined in the area where the first mesa 50 needs to be formed using photolithography. The area without photoresist coating is the first region. The photolithographically etched sample is placed in a dry etching apparatus. Starting from the first region of the emitter layer 40, dry etching is performed along the stacking direction to the first depth of the emitter layer 40, base layer 30, and collector layer 20, initially forming a suitable etching morphology. Because dry etching is anisotropic, meaning the etching rate is much higher in the vertical direction than in the horizontal direction, nearly vertical sidewalls can be formed. Dry etching can effectively control the surface width according to the photolithographic pattern, thereby effectively reducing parasitic capacitance and improving frequency characteristics.

[0050] The specific value of the first ramp angle is affected by factors such as the ratio of etching gas and the ion incident angle in the actual preparation process, and is not limited here. For example, the first ramp angle can be 85° to 90°.

[0051] Reference Figure 3 The isotropic nature of wet etching allows etching to proceed simultaneously in both vertical and horizontal directions, resulting in sloping sidewalls. By controlling the etching time and solution concentration, the slope angle of the second platform can be adjusted. Precise etching of the exposed collector layer 20 using wet etching after dry etching reduces the wet etching time, effectively preventing side-penetration of the base layer 30 and emitter layer 40, and ensuring good electrode contact and excellent electrical performance.

[0052] The specific value of the second slope angle is affected by factors such as the concentration of the etching solution and the etching time in the actual fabrication process, and is not limited here. However, due to the anisotropy of wet etching, the slope angle formed is smaller than that formed by dry etching. For example, the second slope angle can be 30° to 70°.

[0053] According to the semiconductor structure fabrication method of this application, a first platform is formed by dry etching of the base layer 30, emitter layer 40 and collector layer 20 at a first depth through the synergistic effect of dry etching and wet etching. Then, a second platform 60 with a second slope angle is formed by wet etching of the second part of the collector layer 20. This prevents the emitter layer 40 or base layer 30 from being side-etched during the wet etching process, which would affect the electrode contact or device performance. Furthermore, the second slope angle formed by wet etching is smaller than the first slope angle. The inclined sidewalls help the metal to uniformly cover the collector mesa, reduce the risk of metal interconnect failure, and improve the reliability of the semiconductor structure.

[0054] In some embodiments, the ratio of the first depth to the second depth is 1:2 to 1:4.

[0055] The ratio of the first depth to the second depth is 1:2 to 1:4, meaning the ratio of the depth of the collector layer 20 etched during dry etching to the depth of the collector layer 20 etched during wet etching is 1:2 to 1:4. If the ratio of the first depth to the second depth is greater than 1:2, it indicates that the wet etching depth accounts for a smaller proportion. Since dry etching makes the sidewalls of the first platform 50 steep, a larger proportion of dry etching depth may lead to a risk of metal layer fracture due to abrupt changes in step height. If the ratio of the first depth to the second depth is less than 1:2, it indicates that the wet etching depth accounts for a larger proportion. Since wet etching is isotropic, during the etching of the collector layer 20 along the Y direction, etching also occurs along the X direction. If the wet etching depth accounts for a larger proportion, excessive side etching may lead to a comprehensive decrease in the gain, frequency, and reliability of the semiconductor device.

[0056] The ratio of the first depth to the second depth is set to 1:2 to 1:4. This can reduce the risk of metal layer fracture caused by abrupt changes in step height due to an excessive dry etching ratio, and also avoid excessive side etching due to an excessive wet etching ratio.

[0057] It should be noted that the specific ratio of the first depth to the second depth can be determined based on the actual application scenario, and is not limited here. For example, the ratio of the first depth to the second depth can be 1:2.5 or 1:3, etc.

[0058] In some embodiments, the thickness of the first platform 50 is 400 nm to 600 nm.

[0059] The first platform 50 is formed by the first portion of the emitter layer 40, base layer 30, and collector layer 20 after dry etching. The thickness of the first platform 50 is controlled to be greater than or equal to 400 nm, providing sufficient mechanical strength to prevent structural collapse or deformation due to excessive material thinness in subsequent wet etching or high-temperature processes. The uniformity of dry etching usually decreases with increasing etching depth. The thickness of the first platform 50 is less than or equal to 600 nm, which can reduce sidewall tilting or residue caused by differences in etching rate and improve the process window.

[0060] The specific thickness of the first platform 50 can be determined based on the actual application scenario and is not limited here. For example, the thickness of the first platform 50 can be 450nm, 500nm, or 550nm, etc.

[0061] In some embodiments, the second ramp angle is 45° to 60°.

[0062] The second platform 60 is formed by the collector layer 20 after wet etching. It should be noted that in the process of fabricating transistors, after completing the aforementioned dry etching and wet etching steps to define the emitter mesa 41, base mesa, and collector mesa structures and form the geometric outline of the device, it is also necessary to deposit a metal layer on the surface of the collector mesa. After the metal layer is deposited, it is patterned to form the collector electrode.

[0063] The second slope angle is set in the range of 45° to 60°. The moderately inclined sidewall helps the metal to uniformly cover the collector platform, increases the contact area between the metal layer and the collector layer 20, and reduces the contact resistance.

[0064] The specific value of the second ramp angle can be determined according to the actual application scenario, and is not limited here. For example, the second ramp angle of the second platform 60 can be 48°, 50°, or 55°, etc.

[0065] In some embodiments, the collector layer 20 includes a lower collector epitaxial layer 23, a self-stopping layer 22, and an upper collector epitaxial layer 21 stacked sequentially. A first depth is less than the thickness of the upper collector epitaxial layer 21, and a second depth is the sum of the depth of the upper collector epitaxial layer 21 exposed after dry etching and the depth of the self-stopping layer 22. Wet etching is performed on the second depth of the collector layer 20 exposed after dry etching, including:

[0066] The upper collector epitaxial layer 21 exposed after dry etching was wet etched using a phosphoric acid-hydrogen peroxide etching solution.

[0067] The collector layer 20 typically employs a multilayer heteroepitaxial structure to achieve high current gain, low noise, and high-frequency performance. Its typical structure, from bottom to top, includes a lower collector epitaxial layer 23, a self-stopping layer 22, and an upper collector epitaxial layer 21.

[0068] The upper collector epitaxial layer 21 is mainly used to provide a suitable doping concentration and thickness to balance the requirements of current transport and breakdown voltage. The material of the upper collector epitaxial layer 21 can be selected according to the actual application needs, and is not limited here. For example, the material of the upper collector epitaxial layer 21 can be moderately doped gallium arsenide.

[0069] The self-stop layer 22 serves as a selective termination layer in wet etching. It utilizes the difference in etching rate between itself and the upper collector epitaxial layer 21 to achieve self-stopping etching, thus protecting the lower collector epitaxial layer 23 from damage. The material of the self-stop layer 22 can be selected according to the actual application requirements and is not limited here. For example, the material of the self-stop layer 22 can be indium gallium phosphide.

[0070] The lower collector epitaxial layer 23 is mainly used to reduce the collector series resistance and improve the power handling capability of the semiconductor device. The material of the lower collector epitaxial layer 23 can be selected according to the actual application requirements, and is not limited here. For example, the material of the lower collector epitaxial layer 23 can be highly doped gallium arsenide.

[0071] In the dry etching step, the first depth of the upper collector epitaxial layer 21 is etched. During the wet etching step, because... 3+ The solubility in phosphoric acid is extremely low, forming an etching inert layer. Therefore, the phosphoric acid-hydrogen peroxide etching solution is used only for wet etching of the upper collector epitaxial layer 21 exposed after dry etching, forming a platform with a second slope angle, which is beneficial for uniform coverage of the metal layer during subsequent metal deposition.

[0072] It should be noted that the composition ratio of the phosphoric acid-hydrogen peroxide etching solution can be selected according to the actual application requirements, and is not limited here. For example, the composition of the phosphoric acid-hydrogen peroxide etching solution can be H3PO4:H2O2:H2O ~ 1:1:25.

[0073] In some embodiments, after wet etching the upper collector epitaxial layer 21 exposed after dry etching with a phosphoric acid-hydrogen peroxide etching solution, the method further includes wet etching the self-stopping layer 22 with a hydrochloric acid-based etching solution.

[0074] The self-stopping layer 22 is primarily used to provide high selectivity during the etching of the upper collector epitaxial layer 21, ensuring that the etching process stops precisely on the surface of the self-stopping layer 22 and avoiding damage to the lower collector epitaxial layer 23. After the etching of the upper collector epitaxial layer 21 is completed, a portion of the self-stopping layer 22 can be removed using a hydrochloric acid-based etchant. The hydrochloric acid-based etchant selectively etches the self-stopping layer 22 without further etching the upper collector epitaxial layer 21 and the lower collector epitaxial layer 23.

[0075] It should be noted that the composition ratio of the hydrochloric acid-based etching solution can be selected according to the actual application requirements, and is not limited here. For example, the composition of the hydrochloric acid-based etching solution can be H3PO4:HCl:H2O ~ 1:1:1.

[0076] In some embodiments, dry etching is performed using fluorine-based plasma.

[0077] High-energy fluorine-based plasma bombardment can be used to etch the first part of the emitter layer 40, base layer 30, and collector layer 20. The composition of fluorine-based plasma mainly comes from fluorine-containing gases and their mixtures with inert gases and other reactive gases. Fluorine-based gases (such as CF) are less toxic than chlorine-based gases such as Cl and BCl. Dry etching using fluorine-based plasma carries lower operational risks, and byproducts of fluorine-based etching (such as SiF) are more easily removed by the vacuum system, reducing contamination.

[0078] The specific composition of fluorine-based plasma can be selected according to the actual application requirements, and is not limited here. For example, fluorine-based plasma can be CF4 (carbon tetrafluoride).

[0079] In some embodiments, before dry etching is used to etch the emitter layer 40, the base layer 30, and the collector layer 20 to a first depth from a first region on the surface of the emitter layer 40 to form a first platform 50 with a first ramp angle, the method further includes: depositing a passivation layer on the side of the emitter layer 40 and the emitter mesa 41 away from the base; and performing dry etching using the passivation layer as a mask.

[0080] Depositing a passivation layer on the side of the emitter layer 40 and the emitter mesa 41 away from the base can protect the emitter edge from plasma damage during subsequent dry etching and serve as a hard mask for etching, ensuring precise control of the etched area.

[0081] The specific material of the passivation layer can be selected according to the actual application requirements, and is not limited here. For example, the passivation layer can be SiN (silicon nitride).

[0082] In some embodiments, the thickness of the base layer 30 is 40 nm to 60 nm, the thickness of the emitter layer 40 is 30 nm to 50 nm, and the thickness of the collector layer 20 is 2 μm to 3 μm.

[0083] A thinner base layer 30 can significantly shorten the carrier transit time, thereby increasing the device cutoff frequency. However, an excessively thin base layer 30 may increase the base resistance and lead to poor doping uniformity. A thickness of 40nm to 60nm ensures both low base resistance and process controllability. The specific thickness of the base layer 30 can be selected according to the actual application requirements and is not limited here. For example, the thickness of the base layer 30 can be 50nm or 55nm, etc.

[0084] Emitter layer 40 uses a wide bandgap material, and a thickness of 30nm to 50nm ensures a steep heterojunction interface, suppressing reverse hole injection and improving electron injection efficiency. An excessively thick emitter layer 40 increases lateral resistance and capacitance, leading to a decrease in high-frequency performance. A thickness of 30nm to 50nm reduces parasitic resistance while maintaining heterojunction quality. The specific thickness of emitter layer 40 can be selected according to actual application needs and is not limited here. For example, the thickness of emitter layer 40 can be 35nm or 40nm, etc.

[0085] The collector layer 20 typically employs a multilayer heteroepitaxial structure. A thicker collector layer 20 extends the depletion region width, significantly improving the breakdown voltage. The specific thickness of the collector layer 20 can be selected based on actual application requirements and is not limited here. For example, the thickness of the collector layer 20 can be 2.5 μm or 2.8 μm, etc.

[0086] Secondly, this application provides a gallium arsenide bipolar transistor, which is fabricated using the aforementioned semiconductor structure fabrication method.

[0087] The specific steps for fabricating the semiconductor structure can be referred to in the foregoing embodiments, and will not be repeated here.

[0088] In the aforementioned semiconductor structure fabrication method, after wet etching, a metallization layer needs to be deposited on the semiconductor structure surface to achieve electrical connection between the device and external circuits. First, contact holes are formed using photolithography and reactive ion etching processes, followed by the deposition of a diffusion barrier layer and a metal filler material. After filling the trenches with electroplating, global planarization is achieved using chemical mechanical polishing. Subsequently, vertical and horizontal interconnect structures for the source, drain, and gate are constructed through multilayer metal wiring and via interconnects.

[0089] To protect the device from environmental corrosion and mechanical damage, a passivation layer is deposited on the surface of the interconnect structure, and bonding pad openings are formed through photolithography and reactive ion etching. Finally, the device is packaged through wafer dicing, back-side metallization, and plastic or ceramic encapsulation to form a complete gallium arsenide bipolar transistor.

[0090] It should be noted that the aforementioned steps for processing the device after wet etching to form a gallium arsenide bipolar transistor are merely illustrative and not an exhaustive list of the present solution. Any modifications, equivalent substitutions, improvements, or variations made within the spirit and principles of this invention, as well as any other reasonable implementation mode, should be included within the scope of protection of this invention.

[0091] According to the gallium arsenide bipolar transistor of this application, a first platform is formed by dry etching of the base layer 30, emitter layer 40 and collector layer 20 to a first depth through the synergistic effect of dry etching and wet etching. Then, a second platform 60 with a second slope angle is formed by wet etching of the second part of the collector layer 20. This prevents the emitter layer 40 or the base layer 30 from being side-etched during the wet etching process, which would affect the electrode contact or device performance. Moreover, the second slope angle formed by wet etching is smaller than the first slope angle. The inclined sidewall helps the metal to uniformly cover the collector mesa, reducing the risk of metal interconnect failure and improving the reliability of the semiconductor structure.

[0092] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application.

[0093] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A collector layer, a base layer, an emitter layer, and an emitter mesa are sequentially formed on the first side of the substrate. Dry etching is used to etch the emitter layer, the base layer, and the collector layer to a first depth from a first region on the surface of the emitter layer, forming a first platform with a first slope angle; Wet etching is used to etch the second depth of the collector layer exposed after dry etching to form a second platform with a second slope angle, the second slope angle being smaller than the first slope angle, and the sum of the first depth and the second depth being smaller than the thickness of the collector layer.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The ratio of the first depth to the second depth is 1:2 to 1:

4.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The thickness of the first platform is 400nm to 600nm.

4. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The second slope angle is 45° to 60°.

5. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The collector layer includes a lower collector epitaxial layer, a self-stopping layer, and an upper collector epitaxial layer stacked sequentially. The first depth is less than the thickness of the upper collector epitaxial layer. The second depth is the sum of the depth of the upper collector epitaxial layer exposed after dry etching and the depth of the self-stopping layer. The step of etching the second depth of the collector layer exposed after dry etching using wet etching includes: The upper collector epitaxial layer exposed after the dry etching was wet etched using a phosphoric acid-hydrogen peroxide etching solution.

6. The method for preparing a semiconductor structure according to claim 5, characterized in that, After performing wet etching on the upper collector epitaxial layer exposed after dry etching using a phosphoric acid-hydrogen peroxide etching solution, the process further includes: The self-stopping layer was wet-etched using a hydrochloric acid-based etching solution.

7. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The dry etching process uses fluorine-based plasma.

8. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, Before the step of etching the emitter layer, base layer, and collector layer to a first depth from a first region on the surface of the emitter layer using dry etching to form a first platform with a first ramp angle, the method further includes: A passivation layer is deposited on the emitter layer and on the side of the emitter mesa away from the base. Using the passivation layer as a mask, a dry etching step is performed.

9. The method for preparing a semiconductor structure according to any one of claims 1-3, characterized in that, The thickness of the base layer is 40nm to 60nm, the thickness of the emitter layer is 30nm to 50nm, and the thickness of the collector layer is 2μm to 3μm.

10. A gallium arsenide bipolar transistor, characterized in that, The gallium arsenide bipolar transistor is prepared by the method according to any one of claims 1-9.

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