Semiconductor structure and method of manufacturing the same

Abstract

To provide a semiconductor structure and a manufacturing method thereof.SOLUTION: The semiconductor structure includes a substrate, a semiconductor composite layer disposed on the substrate, and a metal electrode structure disposed on the semiconductor composite layer. The semiconductor composite layer includes an N-type gallium arsenide (GaAs) layer disposed on the substrate, a P-type gallium arsenide (GaAs) epitaxial layer disposed on the N-type gallium arsenide (GaAs) layer, and a P-type aluminum gallium arsenide (AlGaAs) epitaxial layer 116 disposed on the P-type gallium arsenide (GaAs) epitaxial layer. The metal electrode structure includes a metal pad layer 122, a metal barrier layer 124 and a metal stack layer 126. The metal barrier layer 124 has a thickness greater than or equal to 500 angstroms (Å) to prevent the metal stack 126 from diffusing through the metal barrier layer 124 to the metal pad layer 122 during the heating process.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a semiconductor structure and a method for manufacturing the same, and more particularly to a semiconductor electrode structure and a method for manufacturing the same. [Background technology]

[0002] III-V compound semiconductors are currently widely used in products such as light-emitting diodes, high-power devices, gas detection devices, and invisible light detection devices. The wafer process for these devices requires a contact process between metal and semiconductor. Based on the physical properties, these contacts are divided into two types: Schottky contact and ohmic contact. To form an ohmic contact at the metal / semiconductor interface, an alloying process is usually performed. Currently, alloy processing and rapid thermal processing (RTP) are the most commonly used processes.

[0003] In metal / semiconductor ohmic contacts, the combination of metal layer design, temperature, and gas flow rate during the fusion process is key to determining whether the specific contact resistance meets the ohmic contact requirements. However, in the pursuit of ohmic contact characteristics between metal and semiconductor, the morphology of the metal electrodes after fusion is often overlooked. This morphology is closely related to the stability of the packaging wire bonding of the subsequent chip. If the morphology of the chip electrodes is abnormal during the process, it can adversely affect the packaging wire bonding, causing pad delamination and resulting in a short circuit of the entire device. To overcome these issues, there is an urgent need to develop innovative semiconductor structures and manufacturing methods that can effectively improve the stability of ohmic contacts of device electrodes and meet the requirements of chip packaging. Summary of the Invention

[0004] The primary objective of the present invention is to provide an innovative semiconductor structure and its manufacturing method. The present invention optimizes the metal electrode structure to form an inverted triangular fusion mark at the interface of the semiconductor composite layer. The inverted triangular fusion mark improves the adhesion between the metal electrode structure and the compound semiconductor layer, thereby enabling the electrode ohmic contact to meet the requirements of chip packaging.

[0005] To achieve the above object, the present invention provides a semiconductor structure including a substrate, a semiconductor composite layer, and a metal electrode structure. The semiconductor composite layer is disposed on the substrate. The metal electrode structure is disposed on the semiconductor composite layer. The metal electrode structure includes a metal pad layer, a metal barrier layer, and a metal stack. The metal barrier layer has a specific thickness and prevents the metal stack from diffusing through the metal barrier layer to the metal pad layer during a heating process.

[0006] In an embodiment of the semiconductor structure of the present invention, the material of the metal barrier layer is selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), zinc (Zn), and iron (Fe).

[0007] In an embodiment of the semiconductor structure of the present invention, the specific thickness of the metal barrier layer is 500 angstroms (Å) or greater.

[0008] In an embodiment of the semiconductor structure of the present invention, when the semiconductor composite layer has a P-type III-V compound layer in contact with a metal stack, the metal stack is a gold (Au) / beryllium gold (BeAu) / gold (Au) stack or a gold (Au) / zinc gold (ZnAu) / gold (Au) stack.

[0009] In an embodiment of the semiconductor structure of the present invention, the P-type III-V compound layer is a P-type aluminum gallium arsenide (P-AlGaAs) layer.

[0010] In an embodiment of the semiconductor structure of the present invention, when the semiconductor composite layer has an N-type III-V compound layer in contact with a metal stack, the metal stack is a gold (Au) / germanium gold (GeAu) / gold (Au) stack.

[0011] In an embodiment of the semiconductor structure of the present invention, the N-type III-V compound layer is an N-type aluminum gallium arsenide (N-AlGaAs) layer.

[0012] In an embodiment of the semiconductor structure of the present invention, the semiconductor structure further comprises a plurality of inverted triangular fusion marks formed at the interface of the metal stack and the semiconductor composite layer after the heating step.

[0013] In an embodiment of the semiconductor structure of the present invention, the metal pad layer is an aluminum layer.

[0014] To achieve the above object, the present invention provides a method for manufacturing a semiconductor structure, the method comprising the steps of: providing a substrate; forming a semiconductor composite layer on the substrate; forming a metal electrode structure on the semiconductor composite layer, the metal electrode structure including sequentially forming a metal stack, a metal barrier layer, and a metal pad layer; and heating the semiconductor structure to form a plurality of inverted triangular fusion marks at the interface between the metal stack and the semiconductor composite layer. The metal barrier layer has a specific thickness and prevents the metal stack from diffusing through the metal barrier layer to the metal pad layer during the heating process.

[0015] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the step of forming a metal barrier layer is to form a metal barrier layer of a material selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), zinc (Zn), and iron (Fe).

[0016] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the step of forming a metal barrier layer is to form a metal barrier layer having a specific thickness of 500 angstroms (Å) or more.

[0017] Those skilled in the art can understand other objects of the present invention, as well as the technical means and embodiments of the present invention, by referring to the drawings and the embodiments described below. [Brief explanation of the drawings]

[0018] [Figure 1] 1 is a cross-sectional view showing the structure of a light-emitting diode according to the present invention; [Figure 2] FIG. 1 is a plan view showing a light-emitting diode according to the present invention; [Figure 3] 1 is a front view of a wafer having a plurality of light emitting diodes of the present invention; [Figure 4] Schematic diagram of a quartz furnace tube for manufacturing light-emitting diodes of the present invention. [Figure 5] 1 is a schematic diagram showing a metal electrode structure and a partial structure of a semiconductor composite layer in a light-emitting diode of the present invention. [Figure 6] SEM image showing the interface between the metal electrode structure and the semiconductor composite layer in the light-emitting diode of the present invention [Figure 7] SEM image showing the interface between the metal electrode structure and the semiconductor composite layer in the light-emitting diode of the present invention [Figure 8] SEM image showing the interface between the metal electrode structure and the semiconductor composite layer in the light-emitting diode of the present invention [Figure 9] SEM image showing the interface between the metal electrode structure and the semiconductor composite layer in the light-emitting diode of the present invention [Figure 10] FIG. 1A is a schematic diagram showing an abnormal morphology of an aluminum electrode in a metal electrode structure in a light-emitting diode of the present invention; FIG. 1B is a schematic diagram showing a normal morphology of an aluminum electrode in a metal electrode structure in a light-emitting diode of the present invention. [Figure 11] Flowchart of manufacturing the light emitting diode of the present invention DETAILED DESCRIPTION OF THE INVENTION

[0019] The present invention will be described below through examples. Note that the examples of the present invention are merely examples of embodiments and are not intended to limit the present invention to the environments, applications, or specific aspects described in the examples. Therefore, the explanation of the examples is intended to explain the present invention, but does not limit the present invention. Note that components not directly related to the present invention are omitted and not shown in the embodiments and drawings. The dimensional relationships between the components in the drawings are intended to facilitate understanding and do not limit the actual dimensions.

[0020] The present invention discloses a semiconductor structure and a manufacturing method thereof, particularly a metal electrode structure for a semiconductor device. The present invention achieves the required ohmic contact at the interface between the metal electrode and the semiconductor layer, improves the morphology of the electrode structure, and eliminates the risk of pad delamination during subsequent packaging processes. Reference is made to FIGS. 1 and 2. FIG. 1 is a cross-sectional view showing the structure of a light-emitting diode 1 of the present invention. FIG. 2 is a plan view showing the light-emitting diode 1 of the present invention. The light-emitting diode 1 of the present invention includes a semiconductor composite layer 110 and a metal electrode structure 120 sequentially disposed on a substrate 100. Another metal electrode structure 121 is disposed on the other side of the substrate 100. Specifically, the substrate 100 may be, for example, but not limited to, an N-type gallium arsenide (GaAs) substrate. The semiconductor composite layer 110 includes, for example, an N-type gallium arsenide (GaAs) layer 112 disposed on the substrate 100, a P-type gallium arsenide (GaAs) epitaxial layer 114 disposed on the N-type gallium arsenide (GaAs) layer 112, and a P-type aluminum gallium arsenide (AlGaAs) epitaxial layer 116 disposed on the P-type gallium arsenide (GaAs) epitaxial layer 114.

[0021] FIG. 3 is a front view of a wafer 201 for manufacturing multiple light-emitting diodes 1 of the present invention. The wafer 201 contains multiple light-emitting diode 1 units formed through processes such as semiconductor epitaxial growth, photolithography, metal vapor deposition, and chemical etching. Next, a fusion process for metal electrodes of the light-emitting diodes 1 is performed using a furnace tube structure as shown in FIG. 4. The furnace tube structure is a quartz furnace tube 202, with a nitrogen gas supply port 203 on the supply side. Coil heaters 204, 205, and 206 surrounding the quartz furnace tube 202 are located on the supply side, center, and front end exterior, respectively. The furnace tube also has an exhaust port 208. Before the fusion process, the entire quartz furnace tube 202 is heated in advance by the coil heaters 204, 205, and 206, and nitrogen gas is supplied at an appropriate flow rate through the gas supply port 203. This allows the entire quartz furnace tube 202 to be uniformly heated, and after about one hour, the wafer 201 is inserted into the quartz furnace tube 202 to carry out the fusion process.

[0022] As shown in Figure 4, multiple wafers 201 are placed on a wafer boat 207 and transported to the center of a quartz furnace tube 202 by an automatically moving quartz pull rod 210. At this time, an automatic sealing port 209 of the furnace tube seals the furnace tube port. After a predetermined time has elapsed at a specific temperature, the automatic sealing port 209 automatically opens. At this time, the quartz pull rod 210 automatically slowly pulls out the wafer boat 207 carrying the wafers 201. As a result, after processing, an ohmic contact is formed at the interface between the metal electrode structure 120 and the P-type aluminum gallium arsenide epitaxial layer 116 in each light-emitting diode unit chip on the wafer 201.

[0023] 5 is a schematic diagram showing a partial structure of the metal electrode structure 120 and the P-type aluminum gallium arsenide epitaxial layer 116 in FIG. 2 . Specifically, the metal electrode structure 120 is disposed on the semiconductor composite layer 110. The metal electrode structure 120 includes a metal pad layer 122, a metal barrier layer 124, and a metal stack 126. In a specific embodiment, when the semiconductor composite layer 110 includes a P-type III-V compound layer, for example, when the P-type III-V compound layer is the P-type aluminum gallium arsenide epitaxial layer 116, a metal stack 126 having a specific thickness is disposed on the P-type aluminum gallium arsenide epitaxial layer 116. The metal stack 126 includes a gold (Au) / beryllium gold (BeAu) layer 1261. In another embodiment, the gold (Au) / beryllium gold (BeAu) layer 1261 can be replaced with gold (Au) / zinc gold (ZnAu). Furthermore, a gold layer 1262 having a specific thickness is formed on the gold (Au) / beryllium gold (BeAu) layer 1261. That is, the metal stack 126 is preferably a gold (Au) / beryllium gold (BeAu) / gold (Au) stack or a gold (Au) / zinc gold (ZnAu) / gold (Au) stack. In another embodiment, when the semiconductor composite layer has an N-type III-V compound layer in contact with the metal stack, for example, when the N-type III-V compound layer is an N-type aluminum gallium arsenide (N-AlGaAs) layer, the metal stack 126 is a gold (Au) / germanium gold (GeAu) / gold (Au) stack.

[0024] Next, a metal barrier layer 124 having a specific thickness is formed on the metal stack 126. For example, the material of the metal barrier layer 124 is selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), zinc (Zn), and iron (Fe). Finally, an aluminum (Al) layer having a thickness of approximately 2 to 4 μm is formed on the metal barrier layer 124 as a metal pad layer 122 for packaging wire bonding. That is, in the light-emitting diode 1 of the present invention, the metal electrode structure 120 is preferably, but not limited to, a composite layer structure of aluminum (Al) / titanium (Ti) / gold (Au) / beryllium gold (BeAu) / gold (Au).

[0025] An example will be described in which the metal barrier layer 124 is titanium (Ti). Hereinafter, for metal barrier layer thicknesses of different thicknesses, e.g., 200 Å, 500 Å, 800 Å, and 1600 Å, the ohmic contact state between the metal electrode structure and the compound semiconductor composite layer in the LED structure and the appearance of the metal electrode after fusion were observed after fusing in a quartz furnace at a specific temperature for a specific time. Furthermore, this appearance is closely related to the stability of subsequent packaging wire bonding of the LED chip.

[0026] 6 to 9 are scanning electron microscope (SEM) images of the metal electrode structure and the semiconductor composite layer in the light-emitting diode of the present invention after fusion at the interface. As shown in FIG. 6, when the titanium layer of the metal barrier layer 124 is only 200 angstroms (Å), it is clearly observed that the metal barrier layer 124 cannot prevent the underlying metal stack structure from breaking through and diffusing into the top metal pad layer 122 after the heating process, forming a diffusion structure 128. As shown in FIG. 7, when the titanium layer of the metal barrier layer 124 is increased to 500 angstroms (Å), the SEM image shows that the diffusion structure 128 is significantly smaller than in FIG. 6. It is also observed that, after the thermal fusion of the metal stack, multiple inverted triangular fusion marks 130 are formed at the interface between the metal electrode structure and the p-type aluminum gallium arsenide epitaxial layer 116 of the semiconductor composite layer 110. The more inverted triangular fusion marks there are, the better the adhesion between the metal electrode structure and the semiconductor composite layer in the LED chip, which makes the pad less susceptible to peeling during the subsequent LED packaging process and allows for the formation of ohmic contact at the metal-semiconductor interface.

[0027] As shown in Figure 8, when the thickness of the titanium layer of the metal barrier layer 124 is increased to 800 angstroms (Å), no diffusion structures 128 are observed in the SEM image. The number of inverted triangular fusion marks 130 on the interface between the metal electrode structure and the P-type aluminum gallium arsenide epitaxial layer 116 also increases substantially. As shown in Figure 9, when the thickness of the titanium layer of the metal barrier layer 124 is increased to 1600 angstroms (Å), a further optimization trend is observed.

[0028] As mentioned above, as shown in FIG. 6, when the thickness of the titanium layer of the metal barrier layer 124 is only 200 angstroms (Å), after the thermal fusion process, SEM images reveal numerous diffusion structures 128 that have penetrated the metal barrier layer 124 and diffused into the metal pad layer 122. If the diffusion level of the diffusion structures 128 is excessive, it can affect the appearance of the metal pad layer 122, e.g., the metal aluminum layer. In severe cases, an aluminum electrode abnormality 702, as shown in FIG. 10(A), can occur. This abnormality 702 can adversely affect the wire bonding process in the subsequent LED packaging process. If such an aluminum electrode abnormality 702 occurs during wafer processing, the production process requires sequential cleaning and removal of the metal electrode structure, e.g., aluminum (Al), titanium (Ti), gold (Au), beryllium gold (BeAu), and gold (Au), using specific chemicals, and then polishing the surface of the p-type aluminum gallium arsenide layer of the semiconductor composite layer. After completing the above process, the wafer must be subjected to metal processing again. Thus, waste occurs, causing a decrease in yield and an increase in production costs several times.

[0029] In contrast, as shown in FIG. 7, when the thickness of the titanium layer of the metal barrier layer 124 is increased to 500 angstroms (Å), the SEM image after the thermal fusion process reveals a significant reduction in the number of diffusion structures 128 that penetrate the metal barrier layer 124 and reach the metal pad layer 122. Furthermore, after the fusion of the metal stack, numerous inverted triangular fusion marks 130 are clearly observed forming from the metal stack toward the p-type aluminum gallium arsenide epitaxial layer 116. The greater the number of fusion marks, the stronger the adhesion between the metal electrode structure and the semiconductor composite layer, reducing the likelihood of pad peeling during the packaging process. In the front view of the chip, a normal morphology 701 of the metal aluminum electrode can be observed, as shown in FIG. 10(B). This normal morphology 701 eliminates concerns about pad peeling during the subsequent packaging process of the LED chip.

[0030] FIG. 11 is a flowchart of the fabrication of a semiconductor structure of the present invention. In step S01, a substrate 100 is prepared. In step S02, a semiconductor composite layer 110 is formed on the substrate 100. In step S03, a metal electrode structure 120 is formed on the semiconductor composite layer 110. The process of forming the metal electrode structure 120 includes sequentially forming a metal stack 126, a metal barrier layer 124, and a metal pad layer 122 on the semiconductor composite layer 110. In step S04, the entire semiconductor structure is heated to form a plurality of inverted triangular fusion marks 130 at the interface between the metal stack 126 and the semiconductor composite layer 110. The metal barrier layer 124 has a specific thickness, for example, 500 Å or more, to prevent the metal stack 126 from diffusing through the metal barrier layer 124 to the metal pad layer 122 during the heating process. For a detailed description, please refer to the above content, and the description will be omitted.

[0031] As described above, the present invention provides an optimized metal electrode structure for a semiconductor structure and a manufacturing method thereof. The present invention uses a metal barrier layer with a specific thickness to prevent metal layers in the metal electrode structure from diffusing to the surface of the metal pad during a heating process, thereby destroying the surface morphology of the metal pad and preventing pad peeling. Meanwhile, in the metal electrode structure, an inverted triangular fusion mark is formed at the interface of the semiconductor composite layer, thereby improving adhesion between the metal electrode structure and the compound semiconductor layer and enabling the electrode's ohmic contact to meet chip packaging requirements.

[0032] The above examples are intended to explain embodiments of the present invention and to explain the characteristic configurations of the present invention. The present invention is not limited to the above examples. Modifications or equivalent arrangements that can be easily made by those skilled in the art are also within the scope of the present invention. The scope of protection of the rights of the present invention is based on the claims. [Explanation of symbols]

[0033] 1. Light-emitting diode 100 boards 110 Semiconductor composite layer 112 N-type gallium arsenide layer 114 P-type gallium arsenide epitaxial layer 116 P-type aluminum gallium arsenide epitaxial layer 120 Metal electrode structure 121 Metal electrode structure 122 Metal Pad Layer 124 Metal Barrier Layer 126 Metal Laminate 1261 Gold / Beryllium Gold Layer 1262 gold layer 128 Diffusion Structure 130 Inverted triangle fusion trace 201 wafer 202 Quartz furnace tube 203 Gas supply port 204 Coil heater 205 Coil heater 206 Coil heater 207 Wafer Boat 208 Exhaust port 209 Automatic sealing mouth 210 Quartz pull rod 701 Normal form 702 Abnormal morphology S01~S04 Process

Claims

1. 1. A semiconductor structure comprising: A substrate; a semiconductor composite layer disposed on the substrate; a metal electrode structure disposed on the semiconductor composite layer, the metal electrode structure including a metal pad layer, a metal barrier layer, and a metal stack; The metal barrier layer has a specific thickness that prevents the metal stack from diffusing through the metal barrier layer to the metal pad layer during a heating process.

2. 2. The semiconductor structure of claim 1, wherein the material of the metal barrier layer is selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), zinc (Zn), and iron (Fe).

3. 2. The semiconductor structure of claim 1, wherein the specified thickness of the metal barrier layer is greater than or equal to 500 angstroms (Å).

4. 2. The semiconductor structure of claim 1, wherein when the semiconductor composite layer has a P-type III-V compound layer in contact with the metal stack, the metal stack is a gold (Au) / beryllium gold (BeAu) / gold (Au) stack or a gold (Au) / zinc gold (ZnAu) / gold (Au) stack.

5. 5. The semiconductor structure of claim 4, wherein said P-type III-V compound layer is a P-type aluminum gallium arsenide (P-AlGaAs) layer.

6. 2. The semiconductor structure of claim 1, wherein when the semiconductor composite layer has an N-type III-V compound layer in contact with the metal stack, the metal stack is a gold (Au) / germanium gold (GeAu) / gold (Au) stack.

7. 7. The semiconductor structure of claim 6, wherein said N-type III-V compound layer is an N-type aluminum gallium arsenide (N-AlGaAs) layer.

8. 2. The semiconductor structure of claim 1, further comprising a plurality of inverted triangular fusion marks formed at the interface between the metal stack and the semiconductor composite layer after the heating step.

9. 2. The semiconductor structure of claim 1, wherein said metal pad layer is an aluminum layer.

10. 1. A method for manufacturing a semiconductor structure, comprising: providing a substrate; forming a semiconductor composite layer on the substrate; forming a metal electrode structure on the semiconductor composite layer, the metal electrode structure including sequentially forming a metal stack, a metal barrier layer, and a metal pad layer; and heating the semiconductor structure to form a plurality of inverted triangular fusion marks at an interface between the metal stack and the semiconductor composite layer; The metal barrier layer has a specific thickness to prevent the metal stack from diffusing through the metal barrier layer to the metal pad layer during a heating process.

11. 11. The manufacturing method according to claim 10, wherein the step of forming the metal barrier layer comprises forming the metal barrier layer of a material selected from the group consisting of titanium (Ti), platinum (Pt), silver (Ag), zinc (Zn), and iron (Fe).

12. 11. The manufacturing method according to claim 10, wherein the step of forming the metal barrier layer comprises forming the metal barrier layer to a specific thickness of 500 angstroms (Å) or more.

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