Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The channel layer structure is suspended above the substrate, and the channel layer structure comprises one or more spaced channel layers in the longitudinal direction; the repairing layer covers the surface of the channel layer; and the gate structure is located on the substrate and stretches across the channel layer structure, and the gate structure surrounds the channel layer in the extension direction of the gate structure and covers the repair layer. The working performance of the semiconductor structure can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the smaller feature size, the channel length of metal-oxide-semiconductor field-effect transistors (MOSFETs) is also continuously shortened. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens. Therefore, the gate structure's control over the channel becomes worse, and it becomes increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor technology has gradually begun to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the area where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has stronger control over the channel and can better suppress short-channel effects. Summary of the Invention

[0004] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to improving the working performance of the semiconductor structure.

[0005] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a channel layer structure suspended above the substrate, wherein the channel layer structure includes one or more spaced channel layers in the longitudinal direction; a repair layer covering the surface of the channel layer; and a gate structure located on the substrate and spanning the channel layer structure, wherein the gate structure surrounds the channel layer along the extending direction of the gate structure and covers the repair layer.

[0006] Optionally, the repair layer covers the upper and lower surfaces of the trench layer.

[0007] Optionally, the semiconductor structure may also include: an isolation layer located between the channel layer structure and the substrate; in the channel layer structure, the bottommost channel layer is in contact with the isolation layer; and a repair layer covering the upper surface of the bottommost channel layer.

[0008] Optionally, the semiconductor structure further includes: a source / drain doped layer located on the substrate on both sides of the gate structure, wherein the source / drain doped layer is in contact with the end of the channel layer structure in the extension direction of the channel layer structure; and an isolation layer is located between the source / drain doped layer and the substrate.

[0009] Optionally, the semiconductor structure further includes: an inner sidewall located between adjacent channel layers and between the gate structure and the source / drain doped layers; and a repair layer located on the surface of the channel layer exposed by the inner sidewall.

[0010] Optionally, the repair layer may be made of silicon germanide.

[0011] Optionally, the thickness of the repair layer is less than or equal to 2 nm.

[0012] Optionally, the channel layer material may include silicon, germanium, silicon germanide, or group III-V semiconductor materials.

[0013] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel layer structure suspended above the substrate, wherein the channel layer structure includes one or more spaced channel layers in the longitudinal direction; forming a repair layer covering the surface of the channel layer; and forming a gate structure on the substrate that spans the channel layer structure, wherein the gate structure surrounds the channel layer along the extension direction of the gate structure and covers the repair layer.

[0014] Optionally, in the step of forming a repair layer covering the surface of the trench layer, the repair layer covers the upper and lower surfaces of the trench layer.

[0015] Optionally, in the step of providing the substrate, an isolation layer is formed on the substrate; in the step of forming a channel layer structure suspended above the substrate, the bottommost channel layer is in contact with the isolation layer; in the step of forming a repair layer covering the surface of the channel layer, the repair layer covers the upper surface of the bottommost channel layer.

[0016] Optionally, in the step of providing the substrate, a stacked structure is formed on the isolation layer, the stacked structure including alternately stacked channel layers and sacrificial layers, wherein the bottom layer of the stacked structure is a channel layer; the step of forming a channel layer structure suspended above the substrate includes: removing the sacrificial layer to form a groove exposing the surface of the channel layer, wherein multiple spaced channel layers constitute the channel layer structure; in the step of forming a repair layer covering the surface of the channel layer, the repair layer is formed on the surface of the channel layer through the groove.

[0017] Optionally, in the step of providing the substrate, a source / drain doped layer is formed on the isolation layer on both sides of the stacked structure along the extension direction of the stacked structure, and the source / drain doped layer is in contact with the end of the stacked structure.

[0018] Optionally, in the step of providing the substrate, an inner sidewall is formed between the sacrificial layer and the source / drain doped layer; in the step of removing the sacrificial layer, the groove exposes the inner sidewall; in the step of forming a repair layer covering the surface of the channel layer, a repair layer is formed on the surface of the channel layer exposed by the inner sidewall.

[0019] Optionally, in the step of forming a gate structure across a channel layer on a substrate, the gate structure fills a groove and covers a repair layer.

[0020] Optionally, an epitaxial growth process can be used to form a repair layer covering the surface of the trench layer.

[0021] Optionally, in the step of forming a repair layer covering the surface of the trench layer, the material of the repair layer includes silicon germanide.

[0022] Optionally, in the step of forming a repair layer covering the surface of the trench layer, the thickness of the repair layer is less than or equal to 2 nm.

[0023] Optionally, in the step of forming a channel layer structure suspended above the substrate, the material of the channel layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material.

[0024] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0025] In the semiconductor structure provided by this invention, a repair layer covers the surface of the channel layer, and a gate structure is located on the substrate and spans the channel layer structure. The gate structure surrounds the channel layer along the extension direction of the gate structure and covers the repair layer. In this invention, the repair layer covering the surface of the channel layer is beneficial to improving the defects on the surface of the channel layer and obtaining a channel surface with higher surface quality. The gate structure surrounds the channel layer and covers the repair layer. Using the repair layer as the channel surface to contact the gate structure results in a better surface quality of the channel surface in contact between the gate structure and the channel layer, which is beneficial to improving the mobility of the channel layer, thereby improving the working performance of the semiconductor structure.

[0026] In the formation method provided by the embodiments of the present invention, a repair layer is formed covering the surface of the channel layer, and a gate structure is formed on the substrate that spans the channel layer structure. The gate structure surrounds the channel layer along the extension direction of the gate structure and covers the repair layer. In the embodiments of the present invention, the repair layer covering the surface of the channel layer is beneficial to improving the defects on the surface of the channel layer and obtaining a channel surface with higher surface quality. The gate structure surrounds the channel layer and covers the repair layer. The repair layer is used as the channel surface to contact the gate structure, so that the surface quality of the channel surface in contact between the gate structure and the channel layer is better, which is beneficial to improving the mobility of the channel layer, thereby improving the working performance of the semiconductor structure. Attached Figure Description

[0027] Figures 1 to 2This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0028] Figures 3 to 4 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention;

[0029] Figures 5 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0030] The performance of current semiconductor structures needs improvement. This paper analyzes the reasons for this need to improve performance using a semiconductor structure formation method as an example.

[0031] Figures 1 to 2 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0032] refer to Figure 1 A substrate 10 is provided, on which a stacked structure is formed, the stacked structure including longitudinally alternating channel layers 22 and sacrificial layers; the sacrificial layers are removed to form trenches 40 located between adjacent channel layers 22, and multiple longitudinally spaced channel layers 22 are retained as channel layer structure 24.

[0033] refer to Figure 2 A gate structure is formed that spans the channel layer structure 24 and fills the trench 40, surrounding the channel layer 22.

[0034] In semiconductor manufacturing, the surface of the channel layer 22 is prone to damage and defects. In particular, the removal of the sacrificial layer can easily damage the exposed surface of the channel layer 22, resulting in poor surface quality and surface defects. After the gate structure 24 is formed, the gate structure 24 surrounds the channel layer 22. Since the surface quality of the channel layer 22 is poor, that is, the surface quality of the channel surface in contact between the gate structure 24 and the channel layer 22 is poor, it affects the mobility of the channel layer 22 and the working performance of the semiconductor structure.

[0035] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate; a channel layer structure suspended above the substrate, wherein the channel layer structure includes one or more spaced channel layers in the longitudinal direction; a repair layer covering the surface of the channel layer; and a gate structure located on the substrate and spanning the channel layer structure, wherein the gate structure surrounds the channel layer along the extending direction of the gate structure and covers the repair layer.

[0036] In the semiconductor structure provided by this invention, a repair layer covers the surface of the channel layer, and a gate structure is located on the substrate and spans the channel layer structure. The gate structure surrounds the channel layer along the extension direction of the gate structure and covers the repair layer. In this invention, the repair layer covering the surface of the channel layer is beneficial to improving the defects on the surface of the channel layer and obtaining a channel surface with higher surface quality. The gate structure surrounds the channel layer and covers the repair layer. Using the repair layer as the channel surface to contact the gate structure results in a better surface quality of the channel surface in contact between the gate structure and the channel layer, which is beneficial to improving the mobility of the channel layer, thereby improving the working performance of the semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 3 to 4 This is a schematic diagram of a corresponding embodiment of the semiconductor structure of the present invention. Figure 3 This is a top view of the gate structure and the source / drain doped layers. Figure 4 yes Figure 3 Sectional view based on the AA direction.

[0039] Reference Figure 3 and Figure 4 The semiconductor structure includes: a substrate 100; and a channel layer structure 200, suspended above the substrate 100, in the vertical direction (e.g., ...). Figure 4 As shown in the Z direction, the channel layer structure 200 includes one or more spaced channel layers 220; a repair layer 250 covering the surface of the channel layer 220; and a gate structure 600 located on the substrate 100 and spanning the channel layer structure 240, the gate structure 600 surrounding the channel layer 220 along the extending direction of the gate structure 600 and covering the repair layer 250.

[0040] Substrate 100 provides the basis for the process operations of forming semiconductor structures. These semiconductor structures include gate-all-around (GAA) transistors and forksheet transistors.

[0041] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0042] In this embodiment, the semiconductor structure further includes an isolation layer 210 located between the channel layer structure 240 and the substrate 100.

[0043] The isolation layer 210 is used to isolate the gate structure 600 from the substrate 100, and the channel layer structure 240 from the substrate 100.

[0044] The bottom of the gate structure 600 and the substrate 100 are isolated by an isolation layer 210. The isolation layer 210 effectively isolates the contact between the gate structure 600 and the substrate 100, thereby reducing the probability of leakage current between the gate structure 600 and the substrate 100. At the same time, the isolation layer 210 effectively isolates the contact between the channel layer 220 and the substrate 100. When the channel layer 220 is turned on, it reduces or avoids the situation where the parasitic capacitance of the substrate 100 increases due to being turned on.

[0045] In this embodiment, the material of the isolation layer 210 includes a dielectric material. The dielectric material can isolate the gate structure 600 and the substrate 100, as well as the channel layer structure 240 and the substrate 100. Moreover, the dielectric material has high process compatibility, thereby reducing the impact of the isolation layer 210 on the process technology.

[0046] In this embodiment, the material of the isolation layer 210 includes SiN, SiON, SiOCN, SiOC, or SiOCH. The smaller k value of SiN, SiON, SiOCN, SiOC, or SiOCH is more conducive to better isolating the gate structure 600 from the substrate 100 and the channel layer structure 240 from the substrate 100, thereby reducing the parasitic capacitance between the gate structure 600 and the substrate 100.

[0047] The channel layer structure 200 includes one or more longitudinally spaced channel layers 220, which serve as channels for transistors.

[0048] In this embodiment, the material of the channel layer 220 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0049] In this embodiment, in the channel layer structure 240, the bottommost channel layer 220 is in contact with the isolation layer 210.

[0050] In the channel layer structure 240, the bottom channel layer 220 is in contact with the isolation layer 210, so that the bottom channel layer 220 is isolated from the substrate 100 through the isolation layer 210.

[0051] Repair layer 250 is used to repair the surface of channel layer 220 to obtain a channel surface with better surface quality.

[0052] In this embodiment, the repair layer 250 covers the surface of the channel layer 220, which helps to improve the defects on the surface of the channel layer 220 and obtain a channel surface with higher surface quality. The gate structure 600 surrounds the channel layer 220 and covers the repair layer 250. The repair layer 250 is used as the channel surface to contact the gate structure 600, so that the surface quality of the channel surface in contact between the gate structure 600 and the channel layer 220 is better, which helps to improve the mobility of the channel layer 220, thereby helping to improve the working performance of the semiconductor structure.

[0053] In this embodiment, the repair layer 250 covers the upper and lower surfaces of the channel layer 220.

[0054] The repair layer 250 covers the upper and lower surfaces of the channel layer 220, and can repair each exposed surface of the channel layer 220, so that each surface of the channel layer 220 has a better surface quality. This results in each channel surface in contact between the gate structure 600 and the channel layer 220 having a better surface quality, which is beneficial to improving the mobility of the channel layer 220 and thus improving the working performance of the semiconductor structure.

[0055] In this embodiment, in the channel layer structure 240, the bottommost channel layer 220 is in contact with the isolation layer 210, and correspondingly, the repair layer 250 covers the upper surface of the bottommost channel layer 220.

[0056] In this embodiment, the material of the repair layer 250 includes silicon germanide.

[0057] The silicon germanide-covered channel layer 220 serves as the channel surface, providing good mobility for the channel. Furthermore, since the channel layer 220 is made of silicon and the repair layer 250 is made of silicon germanide, the repair layer 250 can be formed on the surface of the channel layer 220 using an epitaxial growth process. This process is simple and does not require additional etching, thus reducing damage to the structure.

[0058] Furthermore, the epitaxial growth process allows for better control of process parameters, resulting in high process controllability and making it easier to obtain a more precise thickness of the repair layer 250. The epitaxial growth process also facilitates the formation of a film with fewer impurities, leading to a higher quality repair layer 250. This further helps to improve the defects on the surface of the channel layer 220, resulting in a channel surface with higher surface quality. Consequently, the surface quality of the channel surface at the contact between the gate structure 600 and the channel layer 220 is better, which further helps to improve the mobility of the channel layer 220, and thus further helps to improve the working performance of the semiconductor structure.

[0059] It should be noted that, in this embodiment, the thickness of the repair layer 250 should not be too large. If the thickness of the repair layer 250 is too large, it may occupy too much of the space between adjacent channel layers 220 in the vertical direction, resulting in insufficient space between adjacent channel layers 220 for forming the gate structure 600. This can make it difficult to form the gate structure 600, affect the formation quality of the gate structure 600, and consequently affect the working performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the repair layer 250 is less than or equal to 2 nm.

[0060] The gate structure 600 is used to control the opening and closing of the transistor channel.

[0061] The gate structure 600 surrounds the channel layer 220, so the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area in the channel layer 220 used as channels, thereby increasing the operating current of the semiconductor structure.

[0062] In this embodiment, the gate structure 600 includes a gate dielectric layer surrounding the channel layer 220 along the extending direction of the gate structure 600, and a gate electrode layer located on the gate dielectric layer.

[0063] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220, and the gate electrode layer from the substrate 100.

[0064] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0065] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0066] In this embodiment, the gate structure 600 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0067] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0068] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0069] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0070] In this embodiment, the semiconductor structure further includes a source / drain doped layer 300 located on the substrate 100 on both sides of the gate structure 600, and the source / drain doped layer 300 is in contact with the end of the channel layer structure 240 in the extending direction of the channel layer structure 240.

[0071] The source / drain doped layer 300 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor.

[0072] The doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 300 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 101 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 300 are P-type ions, including B ions, Ga ions, or In ions.

[0073] In this embodiment, the isolation layer 210 is also located between the source / drain doped layer 300 and the substrate 100.

[0074] The isolation layer 210 also extends between the bottom of the source / drain doped layer 300 and the top of the substrate 100, which helps to reduce the leakage current between the source / drain doped layers 300 and also helps to reduce the parasitic capacitance between the source / drain doped layer 300 and the substrate 100.

[0075] In this embodiment, the semiconductor structure further includes an inner sidewall 500 located between adjacent channel layers 220 and between the gate structure 600 and the source / drain doped layers 300.

[0076] The inner wall 500 serves to isolate the gate structure 600 and the source / drain doped layer 300, thereby reducing the parasitic capacitance between the gate structure 600 and the source / drain doped layer 300.

[0077] In this embodiment, the material of the inner sidewall 500 includes a dielectric material, which can provide good isolation between the gate structure 600 and the source / drain doped layer 300.

[0078] Specifically, in this embodiment, the material of the inner sidewall 500 includes SiN, SiON, SiOCN, SiOC, or SiOCH. The smaller k value of SiN, SiON, SiOCN, SiOC, or SiOCH is more conducive to better isolation between the gate structure 600 and the source / drain doped layer 300, thereby reducing the parasitic capacitance between the gate structure 600 and the source / drain doped layer 300.

[0079] It should be noted that in this embodiment, in the semiconductor structure manufacturing process, after the inner wall 500 located between the longitudinally adjacent channel layers 220 is formed, the repair layer 250 covering the surface of the channel layer 220 is then formed. Therefore, in this embodiment, the repair layer 250 is located on the surface of the channel layer 220 exposed by the inner wall 500.

[0080] Figures 5 to 9 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0081] refer to Figure 5 Provides a base of 100.

[0082] The substrate 100 provides the basis for the process operation of forming semiconductor structures. These semiconductor structures include fully enclosed gate transistors and fork-type gate transistors.

[0083] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0084] In this embodiment, during the step of providing the substrate 100, an isolation layer 210 is formed on the substrate 100.

[0085] The isolation layer 210 is used to isolate the subsequently formed gate structure from the substrate 100, and the subsequently formed channel layer structure from the substrate 100.

[0086] The bottom of the gate structure and the substrate 100 are isolated by an isolation layer 210. The isolation layer 210 effectively isolates the contact between the gate structure and the substrate 100, thereby reducing the probability of leakage current between the gate structure and the substrate 100. At the same time, the isolation layer 210 effectively isolates the contact between the channel layer and the substrate 100. When the channel layer is turned on, it reduces or avoids the situation where the parasitic capacitance of the substrate 100 increases due to being turned on.

[0087] In this embodiment, the material of the isolation layer 210 includes a dielectric material. The dielectric material can isolate the gate structure from the substrate 100, as well as the channel layer structure from the substrate 100. Moreover, the dielectric material has high process compatibility, thereby reducing the impact of the isolation layer 210 on the process technology.

[0088] In this embodiment, the material of the isolation layer 210 includes SiN, SiON, SiOCN, SiOC, or SiOCH. The smaller k value of SiN, SiON, SiOCN, SiOC, or SiOCH is more conducive to better isolating the gate structure from the substrate 100 and the channel layer structure from the substrate 100, thereby reducing the parasitic capacitance between the gate structure and the substrate 100.

[0089] In this embodiment, during the step of providing the substrate 100, a stacked structure 200 is formed on the isolation layer 210. The stacked structure 200 includes alternately stacked channel layers 220 and sacrificial layers 230, wherein the bottommost layer of the stacked structure 200 is the channel layer 220.

[0090] In the stacked structure 200, the channel layer 220 serves as the channel of the semiconductor structure, and the sacrificial layer 230 provides a process basis for the subsequent floating arrangement of the channel layer 220 and also occupies space for the gate structure to be formed later. In subsequent processes, the sacrificial layer 230 is removed, leaving the channel layer 220 floating, and a gate structure is formed between the channel layer 220 and the substrate 100, and between adjacent channel layers 220.

[0091] The surface covered by the gate structure in the channel layer 220 is used as a channel. In this embodiment, the top, bottom and sidewalls of the channel layer 220 can all be used as channels, which increases the area used as a channel in the channel layer 220, thereby increasing the operating current of the semiconductor structure.

[0092] In this embodiment, the bottom layer of the stacked structure 200 is the channel layer 220. In the stacked structure 200, the bottom channel layer 220 is in contact with the isolation layer 210, so that the bottom channel layer 220 is isolated from the substrate 100 through the isolation layer 210.

[0093] In this embodiment, during the step of providing the substrate 100, the material of the channel layer 220 includes silicon, germanium, silicon germanide, or a group III-V semiconductor material. As an example, the material of the channel layer 220 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0094] In this embodiment, during the step of providing the substrate 100, the material of the sacrificial layer 230 includes silicon germanide.

[0095] Silicon germanide has a lower etch resistance than silicon, and silicon germanide can form a larger etch selectivity with silicon. Therefore, during the subsequent removal of the sacrificial layer 230, the sacrificial layer 230 is easier to remove, and the damage to the channel layer 220 can be reduced when removing the sacrificial layer 230.

[0096] In other embodiments, the second sacrificial layer can be selected from materials that have an etch selectivity ratio suitable for the channel layer, so as to reduce damage to the channel layer when the second sacrificial layer is removed subsequently.

[0097] In this embodiment, during the step of providing the substrate 100, active and drain doped layers 300 are formed on the isolation layers 210 on both sides of the stacked structure 200 along the extension direction of the stacked structure 200, and the active and drain doped layers 300 are in contact with the ends of the stacked structure 200.

[0098] The source / drain doped layer 300 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor.

[0099] The doping type of the source / drain doped layer 300 is the same as the channel conductivity type of the corresponding transistor. Specifically, when the substrate 100 is used to form an NMOS transistor, the doping ions in the source / drain doped layer 300 are N-type ions, including P ions, As ions, or Sb ions; when the substrate 101 is used to form a PMOS transistor, the doping ions in the source / drain doped layer 300 are P-type ions, including B ions, Ga ions, or In ions.

[0100] In this embodiment, during the step of providing the substrate 100, the isolation layer 210 is also located between the source / drain doped layer 300 and the substrate 100.

[0101] The isolation layer 210 also extends between the bottom of the source / drain doped layer 300 and the top of the substrate 100, which helps to reduce the leakage current between the source / drain doped layers 300 and also helps to reduce the parasitic capacitance between the source / drain doped layer 300 and the substrate 100.

[0102] In this embodiment, during the step of providing the substrate 100, an inner sidewall 500 is also formed between the sacrificial layer 230 and the source / drain doped layer 300.

[0103] The inner wall 500 serves to isolate the subsequently formed gate structure and source / drain doped layer 300, thereby reducing the parasitic capacitance between the gate structure and the source / drain doped layer 300.

[0104] In this embodiment, during the step of providing the substrate 100, the material of the inner sidewall 500 includes a dielectric material, which can provide good isolation for the subsequently formed gate structure and source / drain doped layer 300.

[0105] Specifically, in this embodiment, the material of the inner sidewall 500 includes SiN, SiON, SiOCN, SiOC, or SiOCH. The smaller k value of SiN, SiON, SiOCN, SiOC, or SiOCH is more conducive to better isolation of the subsequently formed gate structure and source / drain doped layer 300, and reduces the parasitic capacitance between the gate structure and the source / drain doped layer 300.

[0106] refer to Figure 6 This forms a channel layer structure 240 suspended above the substrate 100, in the longitudinal direction (e.g., Figure 6 In the Z-direction (as shown), the channel layer structure 240 includes one or more spaced channel layers 220.

[0107] The channel layer 220 is used as a channel in the semiconductor structure.

[0108] In this embodiment, in the step of providing the substrate 100, the bottom layer of the stacked structure 200 is the channel layer 220. Correspondingly, in the step of forming the channel layer structure 240 suspended above the substrate 100, the bottom channel layer 220 is in contact with the isolation layer 210, so that the bottom channel layer 220 is isolated from the substrate 100 through the isolation layer 210.

[0109] In this embodiment, the step of forming a channel layer structure 240 suspended above the substrate 100 includes: removing the sacrificial layer 230 to form a groove 400 exposing the surface of the channel layer 220, and a plurality of spaced-apart channel layers 220 constituting the channel layer structure 240.

[0110] The groove 400 provides space for the subsequent formation of the gate structure. The groove 400 exposes the surface of the channel layer 220, preparing for the subsequent formation of the repair layer.

[0111] In this embodiment, a wet etching process is used to remove the sacrificial layer 230, forming a groove 400 that exposes the surface of the channel layer 220.

[0112] The wet etching process has relatively low process cost and simple operation steps. It can also achieve a large etching selectivity, which is beneficial to reduce damage to the surface of the channel layer 220 during the removal of the sacrificial layer 230.

[0113] In this embodiment, during the step of removing the sacrificial layer 230, the groove 400 also exposes the inner wall 500.

[0114] The recess 400 also exposes the inner sidewall 500, which isolates the gate structure subsequently formed in the recess 400 from the source / drain doped layer 300 through the inner sidewall 500.

[0115] refer to Figure 7 This forms a repair layer 250 covering the surface of the trench layer 220.

[0116] Repair layer 250 is used to repair the surface of channel layer 220 to obtain a channel surface with better surface quality.

[0117] In this embodiment, the repair layer 250 covers the surface of the channel layer 220, which helps to improve the defects on the surface of the channel layer 220 and obtain a channel surface with higher surface quality. The gate structure formed subsequently surrounds the channel layer 220 and covers the repair layer 250. The repair layer 250 is used as the channel surface to contact the gate structure, so that the surface quality of the channel surface in contact between the gate structure and the channel layer 220 is better, which helps to improve the mobility of the channel layer 220, thereby helping to improve the working performance of the semiconductor structure.

[0118] Accordingly, in this embodiment, in the step of forming the repair layer 250 covering the surface of the channel layer 220, the repair layer 250 is formed on the surface of the channel layer 220 through the groove 400.

[0119] In this embodiment, in the step of forming the repair layer 250 covering the surface of the channel layer 220, the repair layer 250 covers the upper and lower surfaces of the channel layer 220.

[0120] The repair layer 250 covers the upper and lower surfaces of the channel layer 220, and can repair each exposed surface of the channel layer 220, so that each surface of the channel layer 220 has a better surface quality. This results in each channel surface in contact with the gate structure having a better surface quality, which is beneficial to improving the mobility of the channel layer 220, and thus to improving the working performance of the semiconductor structure.

[0121] In this embodiment, in the channel layer structure 240, the bottommost channel layer 220 is in contact with the isolation layer 210. Correspondingly, in the step of forming a repair layer 250 covering the surface of the channel layer 220, the repair layer 250 covers the upper surface of the bottommost channel layer 220.

[0122] In this embodiment, in the step of providing the substrate 100, the inner wall 500 occupies a portion of the surface of the channel layer 220. Correspondingly, in the step of forming a repair layer 250 covering the surface of the channel layer 220, the repair layer 250 is formed on the surface of the channel layer 220 exposed by the inner wall 500.

[0123] In this embodiment, in the step of forming the repair layer 250 covering the surface of the trench layer 220, the material of the repair layer 250 includes silicon germanide.

[0124] The silicon germanide-coated channel layer 220 serves as the channel surface, providing better mobility for the channel.

[0125] In this embodiment, in the step of forming the repair layer 250 covering the surface of the trench layer 220, the repair layer 250 covering the surface of the trench layer 220 is formed by an epitaxial growth process.

[0126] The channel layer 220 is made of silicon, and the repair layer 250 is made of silicon germanide. Therefore, the repair layer 250 can be formed on the surface of the channel layer 220 by epitaxial growth process. The formation process is simple and does not require additional etching process, which reduces damage to the structure.

[0127] Furthermore, the epitaxial growth process allows for better control of process parameters, resulting in high process controllability and making it easier to obtain a precise thickness of the repair layer 250. The epitaxial growth process also facilitates the formation of a film with fewer impurities, leading to a higher quality repair layer 250. This further helps to improve the defects on the surface of the channel layer 220, resulting in a channel surface with higher quality. Consequently, the surface quality of the channel surface at the contact between the gate structure and the channel layer 220 is better, which further helps to improve the mobility of the channel layer 220, and thus further improves the working performance of the semiconductor structure.

[0128] It should be noted that, in this embodiment, the thickness of the repair layer 250 in the step of forming the repair layer 250 covering the surface of the channel layer 220 should not be too large. If the thickness of the repair layer 250 is too large, it will easily cause the repair layer 250 to occupy too much of the space between adjacent channel layers 220 in the vertical direction (i.e., the space of the groove 400), resulting in insufficient space between adjacent channel layers 220 in the vertical direction for forming the gate structure. This will easily cause difficulties in the formation of the gate structure, affect the formation quality of the gate structure, and thus affect the working performance of the semiconductor structure. Therefore, in this embodiment, the thickness of the repair layer 250 in the step of forming the repair layer 250 covering the surface of the channel layer 220 is less than or equal to 2 nm.

[0129] Reference Figure 8 and Figure 9 , Figure 9 for Figure 8 A cross-sectional view along the AA direction shows a gate structure 600 formed on the substrate 100 that spans the channel layer structure 240. The gate structure 600 surrounds the channel layer 220 along the extension direction of the gate structure 600 and covers the repair layer 250.

[0130] The gate structure 600 is used to control the opening and closing of the transistor channel.

[0131] The gate structure 600 surrounds the channel layer 220, so the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area in the channel layer 220 used as channels, thereby increasing the operating current of the semiconductor structure.

[0132] In this embodiment, the gate structure 600 includes a gate dielectric layer surrounding the channel layer 220 along the extending direction of the gate structure 600, and a gate electrode layer located on the gate dielectric layer.

[0133] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 220, and the gate electrode layer from the substrate 100.

[0134] The gate dielectric layer material includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. A high-k dielectric material refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0135] It should be noted that the gate dielectric layer may also include a gate oxide layer, which is located between the high-k gate dielectric layer and the channel layer 220. Specifically, the material of the gate oxide layer can be silicon oxide.

[0136] In this embodiment, the gate structure 600 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0137] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to bring out the electrical properties of the metal gate structure.

[0138] In other embodiments, the gate electrode layer may also consist of only the work function layer.

[0139] In other embodiments, the gate structure may also be a polysilicon gate structure, depending on process requirements.

[0140] Specifically, in this embodiment, in the step of forming a gate structure 600 spanning a channel layer structure 240 on a substrate 100, the gate structure 600 fills the groove 400 and covers the repair layer 250.

[0141] The gate structure 600 fills the groove 400 and covers the repair layer 250, so that the top, bottom and sidewalls of the channel layer 220 can all serve as channels, increasing the area in the channel layer 220 used as channels, thereby increasing the operating current of the semiconductor structure. Furthermore, the repair layer 250 serves as the channel surface, which is beneficial to increasing the channel mobility and improving the operating performance of the semiconductor structure.

[0142] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; A channel layer structure, suspended above the substrate, comprising, in the longitudinal direction, one or more spaced channel layers; Repair layer, covering the surface of the trench layer; A gate structure is located on the substrate and spans the channel layer structure, the gate structure surrounds the channel layer along the extension direction of the gate structure and covers the repair layer.

2. The semiconductor structure as described in claim 1, characterized in that, The repair layer covers the upper and lower surfaces of the channel layer.

3. The semiconductor structure as described in claim 2, characterized in that, The semiconductor structure further includes an isolation layer located between the channel layer structure and the substrate; In the channel layer structure, the bottommost channel layer is in contact with the isolation layer; The repair layer covers the upper surface of the bottommost channel layer.

4. The semiconductor structure as described in claim 3, characterized in that, The semiconductor structure further includes: a source / drain doped layer located on the substrate on both sides of the gate structure, and the source / drain doped layer is in contact with the end of the channel layer structure in the extending direction of the channel layer structure; The isolation layer is also located between the source / drain doped layer and the substrate.

5. The semiconductor structure as described in claim 4, characterized in that, The semiconductor structure further includes: an inner sidewall located between adjacent channel layers and between the gate structure and the source / drain doped layers; The repair layer is located on the surface of the exposed trench layer on the inner wall.

6. The semiconductor structure as described in claim 1, characterized in that, The repair layer is made of silicon germanide.

7. The semiconductor structure as described in claim 1, characterized in that, The thickness of the repair layer is less than or equal to 2 nm.

8. The semiconductor structure as described in claim 1, characterized in that, The channel layer material includes silicon, germanium, silicon germanide, or group III-V semiconductor materials.

9. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A channel layer structure is formed suspended above the substrate, wherein, in the longitudinal direction, the channel layer structure comprises one or more spaced channel layers; A repair layer is formed covering the surface of the trench layer; A gate structure is formed on the substrate that spans the channel layer structure, the gate structure surrounding the channel layer along the extension direction of the gate structure and covering the repair layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a repair layer covering the surface of the trench layer, the repair layer covers the upper and lower surfaces of the trench layer.

11. The method for forming a semiconductor structure as described in claim 10, characterized in that, In the step of providing the substrate, an isolation layer is formed on the substrate; In the step of forming the channel layer structure suspended above the substrate, the bottommost channel layer is in contact with the isolation layer; In the step of forming a repair layer covering the surface of the trench layer, the repair layer covers the upper surface of the bottommost trench layer.

12. The method for forming a semiconductor structure as described in claim 11, characterized in that, In the step of providing the substrate, a stacked structure is formed on the isolation layer, the stacked structure including alternately stacked channel layers and sacrificial layers, wherein the bottommost layer of the stacked structure is the channel layer; The step of forming a channel layer structure suspended above the substrate includes: removing the sacrificial layer to form a groove exposing the surface of the channel layer, wherein a plurality of spaced-apart channel layers constitute the channel layer structure; In the step of forming a repair layer covering the surface of the trench layer, the repair layer is formed on the surface of the trench layer through the groove.

13. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of providing the substrate, source and drain doped layers are formed on the isolation layers on both sides of the stacked structure along the extension direction of the stacked structure, and the source and drain doped layers are in contact with the ends of the stacked structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of providing the substrate, an inner sidewall is also formed between the sacrificial layer and the source / drain doped layer; During the step of removing the sacrificial layer, the groove also exposes the inner wall; In the step of forming a repair layer covering the surface of the trench layer, the repair layer is formed on the surface of the trench layer exposed on the inner sidewall.

15. The method for forming a semiconductor structure as described in claim 12, characterized in that, In the step of forming a gate structure across the channel layer structure on the substrate, the gate structure fills the groove and covers the repair layer.

16. The method for forming a semiconductor structure as described in claim 9, characterized in that, An epitaxial growth process is used to form a repair layer covering the surface of the trench layer.

17. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a repair layer covering the surface of the trench layer, the material of the repair layer includes silicon germanide.

18. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a repair layer covering the surface of the channel layer, the thickness of the repair layer is less than or equal to 2 nm.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a channel layer structure suspended above the substrate, the material of the channel layer includes silicon, germanium, silicon germanide, or a group III-V semiconductor material.

Images