Gallium oxide vertical groove MOSFET device and preparation method thereof

Abstract

The invention provides a gallium oxide vertical trench MOSFET device and a preparation method thereof. The gallium oxide vertical trench MOSFET device comprises a gallium oxide substrate, an epitaxial layer located on the first side of the gallium oxide substrate, a plurality of well regions, a plurality of source regions, a gate dielectric layer, a gate, a gate protection layer, a source and an electric field shielding layer. The gallium oxide vertical trench MOSFET device is provided with a first trench and a second trench, the first trench and the second trench are both located in the epitaxial layer, the gate dielectric layer is located on the inner wall of the first trench, the gate completely fills the first trench, and the gate protection layer covers the gate and at least part of the source region; the electric field shielding layer is located on the inner wall of the second groove, the electric field shielding layer is provided with P-type doping, and the source electrode completely fills the second groove and covers the source region, at least part of the well region and the gate protection layer. The reverse leakage current in the device during reverse bias can be avoided, the reliability of the trench gate is improved, and the failure of the device can be avoided.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a gallium oxide vertical trench MOSFET device and a preparation method thereof. BACKGROUND

[0002] The vertical trench metal-oxide-semiconductor field-effect transistor (MOSFET) device is a very important device structure in power switches. When the vertical trench MOSFET device is made in the gallium oxide Ga2O3 material, because the gallium oxide lacks effective P-type semiconductors, it cannot be made into a conventional structure MOSFET like SiC and GaN, and the gate dielectric field breakdown problem will affect the performance of the gallium oxide vertical trench MOSFET device.

[0003] When the gallium oxide vertical trench MOSFET device is in reverse bias, the trench gate cannot be constructed to form an effective high electric field shield, and the high reverse high-voltage critical electric field of up to 8 MV / cm in the gallium oxide epitaxial layer is easy to break down the trench gate dielectric layer, and the device is easy to appear larger reverse leakage current, resulting in device failure.

[0004] Therefore, it becomes a technical problem to be solved urgently to provide a gallium oxide vertical trench MOSFET device capable of avoiding breakdown of the gate dielectric layer. SUMMARY

[0005] Therefore, the purpose of the present application is to provide a gallium oxide vertical trench MOSFET device and a preparation method thereof, which can form an electric field shield in the trench gate region, thereby avoiding the occurrence of reverse leakage current from the drain to the gate in the device, increasing the reliability of the trench gate, and avoiding device failure. The specific scheme is as follows:

[0006] In one aspect, the present application provides a gallium oxide vertical trench MOSFET device, comprising a gallium oxide substrate, an epitaxial layer located on a first side of the gallium oxide substrate, a plurality of well regions, a plurality of source regions, a gate dielectric layer, a gate electrode, a gate protection layer, a source electrode and an electric field shielding layer, and a drain electrode located on a second side of the gallium oxide substrate.

[0007] The gallium oxide substrate and the epitaxial layer have n-type doping, the well regions are located in the epitaxial layer, and the well regions have p-type doping.

[0008] At least part of the source regions are located in the well regions, and the surface of the source regions is flush with the surface of the well regions, and the source regions have n-type doping.

[0009] The gallium oxide vertical trench MOSFET device has a first trench and a second trench, both of which are located in the epitaxial layer, and the depth of the first trench is less than the depth of the second trench in the direction of the film layer stack;

[0010] The gate dielectric layer is located on the inner wall of the first trench, the gate completely fills the first trench, and the gate protection layer covers the gate and at least part of the source region;

[0011] The electric field shielding layer is located on the inner wall of the second trench, the electric field shielding layer has a P-type doping, the source completely fills the second trench, and covers the source region, at least part of the well region and the gate protection layer.

[0012] In a possible implementation, the electric field shielding layer includes a first shielding layer with p-type ions, and the first shielding layer is formed by ion implantation.

[0013] In a possible implementation, the electric field shielding layer further includes a second shielding layer located on the surface of the first shielding layer, the material of the second shielding layer is a p-type oxide layer, and the electric field shielding capability of the second shielding layer is higher than that of the first shielding layer.

[0014] In a possible implementation, the implantation concentration of the p-type ions ranges from 10 17 cm -3 to 3 10 17 cm -3 .

[0015] In a possible implementation, the p-type oxide layer is a p-type nickel oxide or a p-type iridium gallium oxide.

[0016] In a possible implementation, the electric field shielding layer further includes a dielectric layer located on the surface of the second shielding layer.

[0017] In a possible implementation, the first trench is a single-stage trench, and the second trench is a multi-stage trench, and the width of the second trench decreases in the direction of the epitaxial layer pointing to the gallium oxide substrate.

[0018] In a possible implementation, the plurality of well regions includes a first well region and a second well region arranged at intervals, and the distance between the first well region and the first trench is greater than a preset distance in the direction of the gallium oxide substrate extension.

[0019] The first well region, a source region located in the first well region and part of the epitaxial layer, and the epitaxial layer are used to form an auxiliary conduction region.

[0020] In a possible implementation, the distance between the second well region and the first trench in the extension direction of the gallium oxide substrate is greater than a preset distance.

[0021] The second well region, the source region located in the second well region and part of the epitaxial layer, and the epitaxial layer are used to form an auxiliary conduction region.

[0022] In another aspect, the embodiments of the present application also provide a preparation method of a gallium oxide vertical trench MOSFET device, characterized by being used for preparing the gallium oxide vertical trench MOSFET device, and the method comprises the following steps:

[0023] forming an epitaxial layer on a first side of a gallium oxide substrate, the gallium oxide substrate and the epitaxial layer having n-type doping;

[0024] performing ion implantation in the epitaxial layer to form a plurality of well regions located in the epitaxial layer; the well regions have p-type doping;

[0025] performing ion implantation in the well regions and the epitaxial layer to form a plurality of source regions; at least part of the source regions are located in the well regions, and the surfaces of the source regions are flush with the surfaces of the well regions, and the source regions have n-type doping;

[0026] forming a first trench and a second trench, both of which are located in the epitaxial layer, and the depth of the first trench is less than the depth of the second trench in the direction of the film layer stack;

[0027] forming an electric field shielding layer on the inner wall of the second trench, the electric field shielding layer having p-type doping;

[0028] forming a gate dielectric layer on the inner wall of the first trench, and completely filling a gate material in the first trench to form a gate, and forming a gate protection layer on the surface of the gate and at least part of the source regions;

[0029] completely filling a source material in the second trench, and covering the source regions, at least part of the well regions, and the gate protection layer to form a source electrode;

[0030] forming a drain electrode on a second side of the gallium oxide substrate.

[0031] The embodiment of the present application provides a gallium oxide vertical trench MOSFET device and a preparation method thereof, the gallium oxide vertical trench MOSFET device comprises a gallium oxide substrate, an epitaxial layer, a plurality of well regions, a plurality of source regions, a gate dielectric layer, a gate electrode, a gate protection layer, a source electrode and an electric field shielding layer located on the first side of the gallium oxide substrate, and a drain electrode located on the second side of the gallium oxide substrate; the gallium oxide substrate and the epitaxial layer have n-type doping, the well regions are located in the epitaxial layer, and the well regions have p-type doping; at least part of the source regions are located in the well regions, and the surface of the source regions is flush with the surface of the well regions; the source regions have n-type doping; the gallium oxide vertical trench MOSFET device has a first trench and a second trench, both the first trench and the second trench are located in the epitaxial layer, and the depth of the first trench is smaller than the depth of the second trench in the direction of the film layer stack; the gate dielectric layer is located on the inner wall of the first trench, the gate electrode completely fills the first trench, and the gate protection layer covers the gate electrode and at least part of the source regions; the electric field shielding layer is located on the inner wall of the second trench, the electric field shielding layer has P-type doping, the source electrode completely fills the second trench, and covers the source regions, at least part of the well regions and the gate protection layer. In this way, the first trench can be used to form a trench gate (i.e., the gate electrode), and the second trench can be used to form an electric field shielding layer; when the device is in reverse voltage, the P-type doped electric field shielding layer can form a reverse-biased PN junction with the n-type doped epitaxial layer, form a reverse depletion region in the n-type doped epitaxial layer, and because the left and right sides of the first trench usually have the second trench, the two reverse-biased PN junctions can expand the reverse depletion region formed in the n-type doped epitaxial layer, clamp the bottom region of the trench gate, form an electric field shielding for the trench gate region, thereby avoiding the occurrence of reverse leakage current from the drain electrode to the gate electrode in the device, increasing the reliability of the trench gate, and avoiding device failure. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort.

[0033] Figure 1 A sectional view of a gallium oxide vertical trench MOSFET device provided by an embodiment of the present application is shown;

[0034] Figure 2 A flowchart of a preparation method of a gallium oxide vertical trench MOSFET device provided by an embodiment of the present application is shown;

[0035] Figure 3 A sectional view of another gallium oxide vertical trench MOSFET device provided by an embodiment of the present application is shown;

[0036] Figure 4 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0037] Figure 5 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0038] Figure 6 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0039] Figure 7 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0040] Figure 8 A flowchart of a method for manufacturing a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0041] Figure 9 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0042] Figure 10 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application;

[0043] Figure 11 A sectional view of a gallium oxide vertical trench MOSFET device is shown according to an embodiment of the present application.

[0044] Reference signs

[0045] Gallium oxide substrate-101, epitaxial layer-102, well region-103, source region-104, gate dielectric layer-105, gate-106, gate protection layer-107, source-108, drain-109, first shielding layer-201, second shielding layer-202, dielectric layer-203. DETAILED DESCRIPTION

[0046] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0047] In the following description, a lot of specific details are set forth in order to facilitate a full understanding of the present application, but the present application can also be implemented in other ways different from those described herein, and those skilled in the art can make similar generalizations without departing from the spirit of the present application, therefore the present application is not limited to the specific embodiments disclosed below.

[0048] Secondly, the application is described in detail in combination with the schematic diagram, in the detailed description of the embodiments of the application, for the convenience of description, the sectional view of the device structure will be partially enlarged without the general proportion, and the schematic diagram is only an example, which should not limit the scope of protection of the application herein. In addition, the three-dimensional spatial dimensions including length, width and depth should be included in actual manufacturing.

[0049] As described in the background, when the gallium oxide vertical trench MOSFET device is in reverse bias, the trench gate cannot be constructed to form an effective high electric field shielding, and the high reverse voltage critical electric field of up to 8 MV / cm in the gallium oxide epitaxial layer is easy to break down the trench gate dielectric layer, and the device is easy to have a large reverse leakage current, resulting in device failure.

[0050] Based on the above technical problems, the embodiments of the application provide a gallium oxide vertical trench MOSFET device and a preparation method thereof. The first trench can be used to form a trench gate (i.e. gate), and the second trench can be used to form an electric field shielding layer. When the device is in reverse voltage, the p-type doped electric field shielding layer can form a reverse biased PN junction with the n-type doped epitaxial layer, and a reverse depletion region is formed in the n-type doped epitaxial layer. Since the first trench has a second trench on both sides, the two reverse biased PN junctions can expand the reverse depletion region formed in the n-type doped epitaxial layer, and the trench gate bottom region is clamped, which can form an electric field shielding for the trench gate region, thereby avoiding the occurrence of reverse leakage current from the drain to the gate in the device, increasing the reliability of the trench gate, and avoiding device failure.

[0051] In order to facilitate understanding, the gallium oxide vertical trench MOSFET device and the preparation method thereof provided by the embodiments of the application will be described in detail below in combination with the drawings.

[0052] Reference Figure 1 As shown in the figure, a sectional view of a gallium oxide vertical trench MOSFET device provided by the embodiments of the application is shown. The device includes a gallium oxide substrate 101, an epitaxial layer 102 located on the first side of the gallium oxide substrate 101, a plurality of well regions 103, a plurality of source regions 104, a gate dielectric layer 105, a gate 106, a gate protection layer 107, a source 108 and an electric field shielding layer, and a drain 109 located on the second side of the gallium oxide substrate 101.

[0053] Specifically, the epitaxial layer 102 can be formed on the gallium oxide substrate 101, and both the gallium oxide substrate 101 and the epitaxial layer 102 have n-type doping, thereby forming an n-type doped gallium oxide epitaxial wafer. In forming the epitaxial layer 102, a hydride vapor phase epitaxy (HVPE) method can be used, and other methods can also be used. The doping concentration in the gallium oxide substrate 101 and the epitaxial layer 102 is not limited, and as an example, the doping concentration in the gallium oxide substrate 101 can be 2.2 10 18 cm -3 .

[0054] The well region 103 can be formed in the epitaxial layer 102 by ion implantation or the like, and the well region 103 is located in the epitaxial layer 102 and has p-type doping. Therefore, the well region 103 can also be referred to as a p-well region. In actual applications, p-type ions such as nitrogen or magnesium can be implanted on the epitaxial wafer to form a high-resistance well region 103. The implantation concentration of the p-type ions can be in the range of 5 10 16 cm -3 to 8 10 17 cm -3 .

[0055] Then, n-type ions such as silicon ions or germanium ions are implanted in the epitaxial layer 102 to form a source region 104 with n-type doping. The implantation concentration of the n-type ions can be in the range of 1 10 18 cm -3 to 5 10 19 cm -3 . In addition, after ion implantation, a high-temperature annealing process can be performed to activate the ions, and the high-temperature condition is, for example, a temperature of 700 degrees Celsius or higher.

[0056] In addition, at least part of the source region 104 can be located in the well region 103, that is, part of the source region 104 can be located in the well region 103, and another part of the source region 104 can be located in the epitaxial layer 102, and the surface of the source region 104 is flush with the surface of the well region 103. As an example, as shown in FIG. 1B, the device includes two well regions 103, the first well region 103 on the left and the second well region 103 on the right. Part of the source region 104 on the left is located in the first well region 103, and another part is located in the epitaxial layer 102, while the source region 104 on the right is completely located in the second well region 103. Figure 1

[0057] ​The gallium oxide vertical trench MOSFET device has a first trench and a second trench, both of which are located in the epitaxial layer 102. In the film layer stacking direction, the depth of the first trench is less than the depth of the second trench. The two trenches are specifically shown in Figure 1 That is, the bottoms of the two trenches are both located in the epitaxial layer 102, and the openings of the trenches are both located on the surface of the well region 103. Among them, the film layer stacking direction is, for example, the vertical direction, in the film layer stacking direction, the depth of the first trench is shallower, and the depth of the second trench is deeper, so that the electric field shielding layer formed in the deeper second trench can better shield the electric field.

[0058] The gate dielectric layer 105 is located on the inner wall of the first trench, the gate electrode 106 completely fills the first trench, and the gate protection layer 107 covers the gate electrode 106 and at least part of the source region 104. That is, the gate dielectric layer 105 and the gate electrode 106 are sequentially overlapped in the first trench. In addition, in order to protect the gate electrode 106, the gate protection layer 107 is provided above the gate electrode 106, the material of the gate protection layer 107 is, for example, silicon oxide, and the gate protection layer 107 can cover the gate electrode 106 and part of the source region 104.

[0059] In order to avoid the gate dielectric layer 105 being broken down when the device is in reverse bias, causing a reverse leakage current between the drain 109 and the gate electrode 106, in the present application, an electric field shielding layer can be formed on the inner wall of the second trench, the electric field shielding layer has a P-type doping, the source electrode 108 completely fills the second trench, and covers the source region 104, at least part of the well region 103 and the gate protection layer 107.

[0060] That is, the p-type electric field shielding layer can be formed on the inner wall of the second trench first, and then the source electrode 108 material is filled to form the source electrode 108. In addition, by setting the source electrode 108 to cover the source region 104, at least part of the well region 103 and the gate protection layer 107, the n-type source region 104 is short-circuited with the p-type well region 103 (i.e. the body region), the source electrode 108 is made to be in the same potential as the body region, and the left and right source electrodes 108 are electrically connected.

[0061] Next, the reverse voltage blocking process of the device is described. When the device is in reverse voltage, that is, the gate electrode 106 is at zero voltage or negative voltage, and the drain 109 is at high voltage relative to the source electrode 108, a reverse-biased PN junction can be formed between the p-type electric field shielding layer and the n-type gallium oxide epitaxial layer 102, a reverse depletion region is formed in the epitaxial layer 102 and expands to connect, clamping the bottom region of the trench gate electrode 106, and realizing the electric field shielding of the trench gate electrode 106 region. Referring to Figure 1In the figure, the red dotted line is the reverse shielding electric field line. It can be found that the electric field line is far away from the trench gate 106 region, and there is no electric field near the trench gate 106 region, so the electric field shielding can be realized, and the gate dielectric layer 105 is prevented from being broken down by the electric field.

[0062] In this way, the first trench can be used to form the trench gate 106 (i.e. the gate 106), and the second trench can be used to form the electric field shielding layer. When the device is in reverse voltage, the p-type doped electric field shielding layer can form a reverse biased PN junction with the n-type doped epitaxial layer 102, and a reverse depletion region is formed in the n-type doped epitaxial layer 102. Since the first trench has a second trench on both sides, the two reverse biased PN junctions can expand the reverse depletion region formed in the n-type doped epitaxial layer 102, and pinch off the bottom region of the trench gate 106, so as to form an electric field shielding for the trench gate 106 region, thereby avoiding the occurrence of reverse leakage current from the drain 109 to the gate 106 in the device, increasing the reliability of the trench gate 106, and avoiding device failure.

[0063] In a possible implementation, the electric field shielding layer includes a first shielding layer 201 having p-type ions, and the first shielding layer 201 is formed by ion implantation.

[0064] Specifically, the first shielding layer 201 can be formed by ion implantation, and the p-type ions are, for example, nitrogen ions and the like. In addition, the ions can be activated by a high-temperature annealing process after ion implantation, for example, high-temperature annealing treatment at 700 DEG C or above. The first shielding layer 201 can also be referred to as a p-type high-resistance layer. The thickness of the first shielding layer 201 is, for example, 10 nm-10 um.

[0065] In this way, the first shielding layer 201 is formed by p-type ion doping, and the first shielding layer 201 can form a reverse biased PN junction with the n-type epitaxial layer 102, thereby realizing the electric field shielding of the trench gate 106 and avoiding the breakdown of the device under reverse bias.

[0066] In a possible implementation, the p-type ion implantation concentration ranges from 10 17 cm -3 to 3 10 17 cm -3 . In this way, it can be avoided that too few p-type ions cannot form a reverse depletion region, or the width of the reverse depletion region is small, and too many p-type ions can also be avoided to be not conducive to the formation of the reverse biased PN junction.

[0067] In a possible implementation, the electric field shielding layer further includes a second shielding layer 202, the second shielding layer 202 is located on the surface of the first shielding layer 201, and the material of the second shielding layer 202 is a p-type oxide layer, and the electric field shielding capability of the second shielding layer 202 is higher than that of the first shielding layer 201.

[0068] To further improve the electric field shielding effect, a second shielding layer 202 can be further formed on the surface of the first shielding layer 201, the material of the second shielding layer 202 can be a p-type oxide layer, and the concentration of p-type ions in the p-type oxide layer is higher, so that the electric field shielding capability of the second shielding layer 202 is better than that of the first shielding layer 201.

[0069] In this way, the presence of the second shielding layer 202 can further improve the electric field shielding effect, and better electric field shielding can be achieved through the first shielding layer 201 and the second shielding layer 202, so as to avoid breakdown of the gallium oxide vertical trench MOSFET device under reverse bias. In addition, the second shielding layer 202 can be directly connected to the source electrode 108, the source electrode 108 can be better connected to the P-type heterojunction (i.e., the heterojunction formed by the first shielding layer 201 and the second shielding layer 202), and the P-type heterojunction can form a PN junction with the n-type epitaxial layer 102 to form a better freewheeling diode during the third quadrant operation of the power switch tube.

[0070] In a possible implementation, the p-type oxide layer is a p-type nickel oxide (NiO) or a p-type iridium gallium oxide (IrGa)2O3. These materials can be more easily obtained as the p-type oxide layer to form the second shielding layer 202, and the device preparation cost can be reduced. In addition, the thickness of the p-type oxide layer is, for example, 10 nm-200 nm.

[0071] In a possible implementation, the electric field shielding layer further includes a dielectric layer 203, and the dielectric layer 203 is located on the surface of the second shielding layer 202. To avoid the second shielding layer 202 from having a hole due to process manufacturing problems, causing a risk of electric leakage, a dielectric layer 203 can be further formed on the second shielding layer 202, the dielectric layer 203 can fill the hole in the second shielding layer 202, so as to avoid the risk of electric leakage and improve the reliability of the gallium oxide trench MOSFET device. The material of the dielectric layer 203 can be one or a stacked structure of several of aluminum oxide Al2O3, hafnium oxide HfO2, HfSiO, SiO2, or SiN.

[0072] In a possible implementation, the first trench is a single-stage trench, and the second trench is a multi-stage trench, and the width of the second trench decreases in the direction in which the epitaxial layer 102 points to the gallium oxide substrate 101. That is, the multi-stage second trench has different trench widths at different positions, and the part of the second trench close to the well region 103 has a larger trench width, and the part of the second trench close to the substrate has a smaller trench width, as shown in FIG. 1. Figure 1 Therefore, when the device is in a forward bias, a larger area in the n-type epitaxial layer 102 can pass current, and the current passing capacity of the forward conduction is improved. Of course, Figure 1 The second trench in the above embodiment is a two-stage trench, and the second trench can also be a three-stage trench or even more stages.

[0073] Since the well region 103 of the gallium oxide trench MOSFET device is a high-resistance region, it lacks sufficient electron or hole carrier density, and the device has poor current passing capacity. Specifically, when nitrogen N ion implantation and high-temperature annealing are used to form the P-well well region 103 and the channel of the gallium oxide trench MOSFET device, since the nitrogen ions are in a deep energy level in the gallium oxide material, it is difficult to activate even at high temperatures, and it is impossible to form sufficient carrier concentration. The high-resistance P-well region 103 has low electron carrier concentration of the channel inversion layer formed under the gate 106 positive bias voltage, and the device has weak current passing capacity.

[0074] In order to improve the forward conduction capacity of the device, in a possible implementation, the plurality of well regions 103 includes a first well region 103 and a second well region 103 arranged at intervals, and the distance between the first well region 103 and the first trench is greater than a preset distance in the extension direction of the gallium oxide substrate 101; the first well region 103, the source region 104 located in the first well region 103 and part of the epitaxial layer 102, and the epitaxial layer 102 are used to form an auxiliary conduction region.

[0075] Specifically, in the gallium oxide trench MOSFET device, the well region 103 located on the left can be referred to as the first well region 103, and the well region 103 located on the right can be referred to as the second well region 103. The extension direction of the gallium oxide substrate 101 can be a lateral direction, in which the distance between the first well region 103 and the first trench is greater than a preset distance, that is, the first well region 103 and the first trench have part of the epitaxial layer 102 therebetween, as shown in FIG. 1. Figure 1

[0076] ​Thus, the first well region 103, the source region 104 located in the first well region 103 and part of the epitaxial layer 102, and the epitaxial layer 102 are used to form an auxiliary conduction region. The auxiliary conduction region is specifically a junction field-effect transistor (JFET) structure. When no voltage is applied to the gate 106, the auxiliary conduction region is also in the conduction state, thereby enhancing the current carrying capacity of the device and having the freewheeling function when the device is operating in the third quadrant.

[0077] To further improve the current carrying capacity of the device, in one possible implementation, the distance between the second well region 103 and the first trench is greater than a preset distance in the extension direction of the gallium oxide substrate 101; the second well region 103, the source region 104 located in the second well region 103 and part of the epitaxial layer 102, and the epitaxial layer 102 are used to form an auxiliary conduction region.

[0078] In other words, each of the two well regions 103 on either side of the first trench forms an auxiliary conduction region. The second well region 103 can also form another auxiliary conduction region of the JFET structure with the surrounding epitaxial layer 102 and source region 104. In short, the second well region 103 also has a certain distance from the first trench, thereby further improving the current carrying capacity of the device during forward conduction.

[0079] refer to Figure 2 As shown, this application provides a method for fabricating a gallium oxide vertical trench MOSFET device, which includes steps S101-S108.

[0080] S101, an epitaxial layer 102 is formed on the first side of a gallium oxide substrate 101, and the gallium oxide substrate 101 and the epitaxial layer 102 are n-type doped.

[0081] Specifically, refer to Figure 3 As shown, an epitaxial layer 102 can be formed on the first side of a gallium oxide substrate 101. Both the gallium oxide substrate 101 and the epitaxial layer 102 are n-type doped, thereby forming an n-type doped gallium oxide epitaxial wafer. The epitaxial layer 102 can be prepared using hydride vapor phase epitaxy, but other methods can also be used. The doping concentration in the gallium oxide substrate 101 and the epitaxial layer 102 is not limited; as an example, the doping concentration in the gallium oxide substrate 101 can be 2.2. 10 18 cm -3 .

[0082] S102, Ion implantation is performed in the epitaxial layer 102 to form multiple well regions 103 located in the epitaxial layer 102; the well regions 103 are p-type doped.

[0083] Specifically, refer to Figure 4 As shown, a well region 103 can be formed in the epitaxial layer 102 through methods such as ion implantation. The well region 103 is located in the epitaxial layer 102 and is p-type doped. In practical applications, high-resistivity well regions 103 can be formed by ion implantation of p-type ions such as nitrogen or magnesium on the epitaxial wafer. The implantation concentration of p-type ions can be in the range of 5%. 10 16 cm -3 Up to 8 10 17 cm -3 .

[0084] S103, Ion implantation is performed in the well region 103 and the epitaxial layer 102 to form a plurality of source regions 104; at least a portion of the source regions 104 are located within the well region 103, and the surface of the source region 104 is flush with the surface of the well region 103, and the source region 104 has n-type doping.

[0085] Next, continue to refer to Figure 4 As shown, n-type ion implantation is performed in the epitaxial layer 102 to form an n-type doped source region 104. The source region 104 may be located within the well region 103. The n-type ions are, for example, silicon ions or germanium ions, and the implantation concentration of the n-type ions can be in the range of 1. 10 18 cm -3 Up to 5 10 19 cm -3 Additionally, after ion implantation, the ions can be activated through a high-temperature annealing process, with high-temperature conditions such as temperatures above 700 degrees Celsius.

[0086] S104, forming a first trench and a second trench, both of which are located within the epitaxial layer 102. In the film stacking direction, the depth of the first trench is less than the depth of the second trench.

[0087] Specifically, refer to Figure 5 As shown, a first trench in the middle and two second trenches on either side are formed in a gallium oxide vertical trench MOSFET device. The first trench is shallower and the second trenches are deeper. The trenches can be formed, for example, by ion beam etching, but other methods can also be used.

[0088] S105, an electric field shielding layer is formed on the inner wall of the second trench, and the electric field shielding layer has P-type doping.

[0089] Specifically, an electric field shielding layer can be formed on the sidewalls and bottomwalls of the second trench. The electric field shielding layer has P-type doping to achieve the electric field masking effect.

[0090] More specifically, when the first shielding layer 201 is included in the electric field shielding layer, the first shielding layer 201 can be formed by ion implantation, for example, p-type ions such as nitrogen ions, etc. In addition, after ion implantation, the ions can be activated by a high-temperature annealing process, for example, high-temperature annealing treatment at 700°C or higher. Referring to Figure 6 As shown, the first shielding layer 201 of p-type is shown to be formed in the second trench.

[0091] In addition, if the second shielding layer 202 is also included in the electric field shielding layer, the second shielding layer 202 can be formed by deposition, for example, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etc. The thickness of the second shielding layer 202 can be 10 nm to 200 nm. Referring to Figure 7 As shown, the second shielding layer 202 is shown to be formed on the first shielding layer 201.

[0092] S106, a gate dielectric layer 105 is formed on the inner wall of the first trench, and a gate 106 material is completely filled in the first trench to form the gate 106, and a gate protection layer 107 is formed on the surface of the gate 106 and at least part of the source region 104.

[0093] Specifically, a layer of dielectric material can be deposited on the sidewall and bottom wall of the first trench as the gate dielectric layer 105, and the material of the gate dielectric layer 105 is, for example, aluminum oxide. In addition, at the same time, the dielectric material can also be formed in the second trench, thereby forming a dielectric layer 203 in the second trench, which also serves as part of the electric field shielding layer. Referring to Figure 8 As shown, the dielectric layer 203 is formed in the second trench, and the gate dielectric layer 105 is formed in the first trench.

[0094] Specifically, referring to Figure 9 As shown, the gate 106 material can be completely filled in the first trench to form the gate 106, and the gate 106 material is, for example, polycrystalline silicon or metal material, and the metal material is, for example, Ti / Au laminated material. Referring to Figure 10 As shown, the gate protection layer 107 can be formed above the first trench, and the material of the gate protection layer 107 is, for example, silicon oxide.

[0095] S107, the source 108 material is completely filled in the second trench, and covers the source region 104, at least part of the well region 103 and the gate protection layer 107, to form the source 108.

[0096] Specifically, referring to Figure 11 As shown, the source 108 material can be filled in the second trench to form the source 108, and the source 108 covers the second trench and part of the well region 103 and the gate protection layer 107, thereby forming the source 108 ohmic contact. The source 108 material is, for example, metal material such as Ti / Al or Ti / Au, etc.

[0097] S108, forming a drain 109 on the second side of the gallium oxide substrate 101.

[0098] Specifically, referring to FIG. 1, a drain 109 material, such as a metal material of Ti / Al or Ti / Au, etc., can be formed on the second side surface of the gallium oxide substrate 101, and an ohmic contact of the drain 109 is formed by a rapid thermal annealing (RTA) process to achieve preparation of the drain 109, thereby completing the gallium oxide vertical trench MOSFET device. Figure 1

[0099] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the method embodiments, since they are basically similar to the device embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the device embodiments.

[0100] The above only describes the preferred embodiments of the present application. Although the preferred embodiments of the present application are disclosed as above, the present application is not intended to be limited to the above. Any person skilled in the art can make many possible changes and modifications to the technical solutions of the present application or modify equivalent embodiments without departing from the scope of the technical solutions of the present application. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present application without departing from the technical solutions of the present application shall still fall within the scope of protection of the technical solutions of the present application.​

Claims

1. A gallium oxide vertical trench MOSFET device, characterized in that, It includes a gallium oxide substrate, an epitaxial layer located on a first side of the gallium oxide substrate, multiple well regions, multiple source regions, a gate dielectric layer, a gate, a gate protection layer, a source and an electric field shielding layer, and a drain located on a second side of the gallium oxide substrate; The gallium oxide substrate and the epitaxial layer are n-type doped, and the well region is located within the epitaxial layer and is p-type doped. At least a portion of the source region is located within the well region, and the surface of the source region is flush with the surface of the well region, wherein the source region is n-type doped; The gallium oxide vertical trench MOSFET device has a first trench and a second trench, both of which are located within the epitaxial layer. In the film stacking direction, the depth of the first trench is less than the depth of the second trench. The gate dielectric layer is located on the inner wall of the first trench, the gate completely fills the first trench, and the gate protective layer covers the gate and at least a portion of the source region; The electric field shielding layer is located on the inner wall of the second trench. The electric field shielding layer is P-type doped. The source completely fills the second trench and covers the source region, at least part of the well region, and the gate protection layer.

2. The gallium oxide vertical trench MOSFET device according to claim 1, characterized in that, The electric field shielding layer includes a first shielding layer with p-type ions, which is formed by ion implantation.

3. The gallium oxide vertical trench MOSFET device according to claim 2, characterized in that, The electric field shielding layer further includes a second shielding layer located on the surface of the first shielding layer. The material of the second shielding layer is a p-type oxide layer, and the electric field shielding capability of the second shielding layer is higher than that of the first shielding layer.

4. The gallium oxide vertical trench MOSFET device according to claim 2, characterized in that, The implantation concentration range of the p-type ions is 10. 17 cm -3 Up to 3 10 17 cm -3 .

5. The gallium oxide vertical trench MOSFET device according to claim 3, characterized in that, The p-type oxide layer is p-type nickel oxide or p-type iridium gallium oxide.

6. The gallium oxide vertical trench MOSFET device according to claim 1, characterized in that, The electric field shielding layer further includes a dielectric layer, which is located on the surface of the second shielding layer.

7. The gallium oxide vertical trench MOSFET device according to claim 1, characterized in that, The first trench is a single-level trench, and the second trench is a multi-level trench. The width of the second trench decreases in the direction from the epitaxial layer to the gallium oxide substrate.

8. The gallium oxide vertical trench MOSFET device according to claim 1, characterized in that, The plurality of well regions include a first well region and a second well region that are spaced apart. In the gallium oxide substrate extension direction, the distance between the first well region and the first trench is greater than a preset distance. The first well region, the source region located within the first well region and a portion of the epitaxial layer, and the epitaxial layer are used to form an auxiliary conduction region.

9. The gallium oxide vertical trench MOSFET device according to claim 8, characterized in that, In the gallium oxide substrate extension direction, the distance between the second well region and the first trench is greater than a preset distance; The second well region, the source region located within the second well region and a portion of the epitaxial layer, and the epitaxial layer for forming an auxiliary conduction region.

10. A method for fabricating a gallium oxide vertical trench MOSFET device, characterized in that, A method for fabricating a gallium oxide vertical trench MOSFET device as described in any one of claims 1-9 includes: An epitaxial layer is formed on a first side of a gallium oxide substrate, wherein the gallium oxide substrate and the epitaxial layer are n-type doped. Ion implantation is performed in the epitaxial layer to form multiple well regions located in the epitaxial layer; the well regions are p-type doped. Ion implantation is performed in the well region and the epitaxial layer to form a plurality of source regions; at least a portion of the source regions are located within the well region, and the surface of the source region is flush with the surface of the well region, and the source region has n-type doping; A first trench and a second trench are formed, both of which are located within the epitaxial layer. In the film stacking direction, the depth of the first trench is less than the depth of the second trench. An electric field shielding layer is formed on the inner wall of the second trench, the electric field shielding layer having P-type doping; A gate dielectric layer is formed on the inner wall of the first trench, and a gate material is completely filled in the first trench to form a gate. A gate protection layer is formed on the surface of the gate and at least a portion of the source region. The source material is completely filled into the second trench and covers the source region, at least part of the well region and the gate protection layer to form a source. A drain electrode is formed on the second side of the gallium oxide substrate.

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