ESD device and manufacturing method thereof
By connecting a low-capacitance diode and a glass wafer dielectric layer in series with the anode of the ESD chip, the problems of high cost and complex processes in ESD chip production are solved, realizing an ESD device with low capacitance and high holding voltage, reducing production costs and cycle time, and improving device performance.
Patent Information
- Application Number
- CN202511043535.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-28
- Publication Date
- 2025-11-04
AI Technical Summary
In current ESD chip manufacturing, the use of thick dielectric layers combined with buried layer processes results in high wafer material costs and complex processes, and the high capacitance of ESD devices affects the performance of integrated circuits.
By using glass wafers as the dielectric layer and connecting low-capacitance diodes with a lateral structure in series with the anode of the ESD chip, combined with laser aperture opening and atomic layer deposition processes, the traditional SiO2 deposition process is omitted, reducing production costs and cycle time.
This achieves low capacitance and high sustaining voltage performance for ESD devices, reducing production costs and cycle time, while also minimizing the impact of parasitic capacitance on high-frequency integrated circuits and avoiding latch-up phenomena.
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Figure CN120897516A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of ESD device technology, and in particular to an ESD device with low capacitance and high sustaining voltage and its fabrication method. Background Technology
[0002] With the continuous development of IC manufacturing processes and the gradual increase in integrated circuit operating frequencies, the application of radio frequency (RF) integrated circuits is becoming increasingly widespread. Consequently, research on ESD protection for RF circuits is receiving increasing attention. RF circuits not only have stringent requirements regarding the parasitic effects of ESD chips, but also require ESD chips to have flyback characteristics. Therefore, ESD protection devices for this application condition require special design.
[0003] The operating frequencies of integrated circuits manufactured using advanced processes are increasing daily, which necessitates that the capacitance of ESD protection modules be as low as possible to avoid affecting the performance of integrated circuits. Therefore, low-capacitance optimization of ESD devices is required. The capacitance of an ESD transistor mainly consists of junction capacitance and parasitic capacitance. Manufacturers can reduce junction capacitance by reducing chip area, using GGNMOS or SCR structures, and further reduce parasitic capacitance by selecting low-dielectric-constant dielectrics or increasing dielectric layer thickness during ESD chip manufacturing. SCR structures have received widespread attention in ESD protection due to their strong robustness. However, their Vhold value in the flyback characteristic is low, generally lower than VDD, making them prone to latch-up risks.
[0004] Currently, most ESD chip manufacturers choose SiO2 with a low dielectric constant as the dielectric layer, and increase the thickness of the dielectric layer by depositing a SiO2 layer of about 10μm to reduce the parasitic capacitance of the ESD transistor. However, in the manufacturing process, the thick SiO2 layer is not deposited in one go, but requires dozens or even hundreds of depositions to achieve the desired thickness. The SiO2 deposited during ESD chip fabrication has a maximum thickness of 10 μm due to the need to consider uniformity and step coverage. Furthermore, the deposition process requires numerous photolithography, etching, CMP, and reflow processes to achieve flatness and density. Most ESD chip manufacturers employ buried layer technology to improve the Vhold value in the ESD scan profile. However, introducing buried layer technology significantly increases the cost of wafer materials and the number of fabrication steps. While increasing the dielectric layer thickness and introducing buried layer technology can reduce ESD chip capacitance and improve Vhold value, this not only increases wafer material costs but also requires more fabrication steps, significantly increasing production costs and time. Summary of the Invention
[0005] This application provides an ESD device and its fabrication method, which solves the problems of high wafer material cost and complex processes caused by the thick dielectric layer combined with buried layer process in the prior art. It achieves low capacitance and high holding voltage performance of ESD device, which greatly reduces production cost and production cycle.
[0006] This application provides an ESD device, including:
[0007] A heavily doped P-type single crystal is divided into a first region and a second region on the upper part. The second region is provided with a number of anode regions and cathode regions that are arranged alternately at intervals. The first region and the anode region are respectively provided with lightly doped N-type implantation regions. The lightly doped P-type implantation region is provided above the lightly doped N-type implantation region in the first region. The anode region and the cathode region in the second region are respectively provided with a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells arranged alternately at intervals.
[0008] A glass wafer is disposed above the heavily doped P-type single crystal wafer. The glass wafer has a plurality of glass vias. The glass vias are respectively connected to the lightly doped N-type implantation region and the lightly doped P-type implantation region in the first region, and respectively connected to each heavily doped P-type implantation well and the heavily doped N-type implantation well in the second region. The glass vias are filled with metal.
[0009] The cathode front metal is disposed above the glass wafer and connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each cathode region through the glass through-hole.
[0010] Interconnect metal is disposed above the glass wafer and connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each of the anode regions through the glass vias. The interconnect metal is also connected to the lightly doped N-type implantation region in the first region through the glass vias.
[0011] The anode front metal is disposed above the glass wafer and connected to the lightly doped P-type implantation region in the first region through the glass via.
[0012] The beneficial effects of the above embodiments are as follows: 1. The ESD device is provided with a first region and a second region. The lightly doped N-type implanted region and the lightly doped P-type implanted region of the first region constitute a low-capacitance diode. The diode is connected in series with the second region (ESD chip). The cathode of the diode is electrically connected to the anode of the second region (ESD chip). The anode serves as the anode lead of the entire device, and the cathode of the second region (ESD chip) serves as the cathode lead of the entire device. By connecting the low-capacitance diode with a lateral structure in series with the anode of the second region (ESD chip), the ESD device greatly reduces the junction capacitance of the entire device and improves the Vf of the sweep curve during operation. holdValue. 2. This ESD device directly uses a glass wafer as the dielectric layer, eliminating the need for dozens or even hundreds of steps in the traditional manufacturing process to achieve a thickness of [missing information]. The SiO2 deposition eliminates the need for multiple photolithography, etching, CMP, and reflow processes required for flatness and density during the deposition process, greatly reducing production costs and production cycle.
[0013] Based on the above embodiments, this application can be further improved as follows:
[0014] In one embodiment of this application, the resistivity of the heavily doped P-type monocrystalline wafer is 0.01 Ω·cm. This resistivity parameter ensures that the monocrystalline wafer has low series resistance, reducing signal transmission loss during ESD device operation and improving the response speed to electrostatic pulses.
[0015] In one embodiment of this application, the glass wafer has a thickness ≥20μm and a dielectric constant of 3.8–4.1. Replacing deposited SiO2 with a glass wafer ≥20μm thick as the dielectric layer eliminates the limitation of 10μm SiO2 as the dielectric layer in traditional processes, significantly reducing the parasitic capacitance of ESD devices and also greatly reducing the impact of ESD transistors on high-frequency integrated circuits.
[0016] In one embodiment of this application, the glass wafer is bonded to the heavily doped P-type single crystal wafer via anodic bonding. Anodic bonding enables a tight bond between the glass wafer and the single crystal wafer, avoiding defects such as delamination and bubbles that are prone to occur in the dielectric layer in traditional deposition processes, thereby improving the structural stability and long-term reliability of the device.
[0017] In one embodiment of this application, the glass via is formed by laser drilling, with a depth of 20 μm and a width of 1 μm. Laser drilling can achieve high-precision via forming (depth tolerance ≤ ±0.5 μm, width tolerance ≤ ±0.1 μm), ensuring uniform metal filling of the via, reducing interconnect resistance, and improving the current carrying capacity of the device.
[0018] In one embodiment of this application, the metal filling the glass via is formed by atomic layer deposition and then subjected to CMP treatment to achieve chip surface planarization. Atomic layer deposition can achieve void-free metal filling of the via, and the chip surface flatness after CMP treatment is ≤0.1μm, avoiding the decrease in photolithography accuracy caused by surface unevenness and improving the reliability of subsequent metal wiring.
[0019] In one embodiment of this application, the impurity implanted into the lightly doped N-type implantation region is Ph, and the implantation dose and energy are 1e. 14 ~5e 14100keV. This injection parameter can form a shallow junction depth (≤0.5μm) and low doping concentration N-type region, ensuring that the forward conduction voltage VF of the diode is stable at 0.7~0.9V, in order to improve V... hold Value provides the foundation.
[0020] In one embodiment of this application, the impurity implanted into the lightly doped P-type implantation region is B, and the implantation dose and energy are 1e. 14 ~5e 14 60keV. A shallow P-type region is formed by low-energy B injection, which forms a lateral PN junction with the underlying N-type region. The diode junction capacitance can be controlled between 0.05 and 0.15 pF, significantly reducing the overall junction capacitance of the device.
[0021] In one embodiment of this application, the heavily doped P-type implanted well is implanted with impurity B, and the implantation dose and energy are 1e. 16 ~3e 16 40 keV; the heavily doped N-type implantation well is implanted with Ph impurity, and the implantation dose and energy are 1e 16 ~3e 16 40keV. High-dose injection forms ohmic contacts with low contact resistance, ensuring efficient current transfer between the anode, cathode, and metal layers, and avoiding localized heating problems caused by excessive contact resistance.
[0022] This application also provides a method for fabricating the above-mentioned ESD device, including the following steps:
[0023] S1: Ph is implanted into the first region and the anode region of the heavily doped P-type single crystal wafer, respectively, with implantation dose and energy of 1e. 14 ~5e 14 100 keV, followed by high-temperature annealing to form the lightly doped N-type implantation region;
[0024] S2: B is implanted into the lightly doped N-type implantation region of the first region, with an implantation dose and energy of 1e. 14 ~5e 14 60 keV, after implantation, high-temperature annealing is performed to form the lightly doped P-type implantation region;
[0025] S3: Implant B into the lightly doped N-type implantation regions of the cathode and anode regions, with an implantation dose and energy of 1e. 16 ~3e 16 40 keV; Ph is implanted into the lightly doped N-type implantation regions of the cathode and anode regions, with implantation dose and energy of 1e. 16 ~3e 16 40 keV; rapid annealing activation is performed to form the heavily doped P-type implantation well and the heavily doped N-type implantation well;
[0026] S4: Bond the glass wafer onto the heavily doped P-type single crystal wafer; form the glass via using laser drilling; fill the glass via with metal using atomic layer deposition; and remove excess metal from the surface using CMP.
[0027] S5: The cathode front metal, interconnect metal, and anode front metal are formed on the glass wafer by photolithography and etching. The cathode front metal is connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each cathode region. The interconnect metal is connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each anode region. The interconnect metal is also connected to the lightly doped N-type implantation region in the first region. The anode front metal is connected to the lightly doped P-type implantation region in the first region.
[0028] One or more technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:
[0029] 1. This ESD device significantly reduces the junction capacitance of the entire device by using a low-capacitance diode with a lateral structure connected in series with the anode in the second region (ESD chip), while simultaneously improving the Vf of the ESD device's flyback curve during operation. hold value.
[0030] 2. This ESD device directly uses a glass wafer as the dielectric layer, eliminating the need for the dozens or even hundreds of steps required in traditional manufacturing processes to achieve a thickness of [missing information]. The SiO2 deposition eliminates the need for multiple photolithography, etching, CMP, and reflow processes required for flatness and density during the deposition process, greatly reducing production costs and production cycle. Attached Figure Description
[0031] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the accompanying drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. In all the drawings, similar elements or parts are generally identified by similar reference numerals. In the drawings, the elements or parts are not necessarily drawn to scale.
[0032] Figure 1 This is a schematic diagram of the structure of an ESD device in an embodiment of this application;
[0033] Figure 2 This is a schematic diagram of the front metal structure of an ESD device according to an embodiment of this application (for ease of representation). Figure 2 The positions of the diode region and the metal on the front of the anode have been deformed, but the internal connection relationship remains unchanged.
[0034] Figure 3This is a schematic diagram of the equivalent circuit of an ESD device in an embodiment of this application;
[0035] Figure 4 This is a schematic diagram illustrating the fabrication process of an ESD device in an embodiment of this application. Figure 1 ;
[0036] Figure 5 This is a schematic diagram illustrating the fabrication process of an ESD device in an embodiment of this application. Figure 2 ;
[0037] Figure 6 This is a schematic diagram illustrating the fabrication process of an ESD device in an embodiment of this application. Figure 3 ;
[0038] Figure 7 This is a schematic diagram illustrating the fabrication process of an ESD device in an embodiment of this application. Figure 4 .
[0039] Among them, 1. heavily doped P-type single crystal wafer, 2. lightly doped N-type implantation region, 3. lightly doped P-type implantation region, 4. heavily doped P-type implantation well, 5. heavily doped N-type implantation well, 6. glass wafer, 7. glass via, 8. cathode front metal, 9. interconnect metal, and 10. anode front metal. Detailed Implementation
[0040] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. After reading the present invention, any modifications of the present invention in various equivalent forms by those skilled in the art will fall within the scope defined by the appended claims.
[0041] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.
[0042] In the description of this invention, it should be noted that the terms "vertical," "outer peripheral surface," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of the invention is in use. These terms are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.
[0043] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0044] In the description of this invention, the illustrative expressions of the terms used above do not necessarily refer to the same embodiments or examples. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, those skilled in the art can combine and integrate the different embodiments or examples described in this invention, as well as the features of those different embodiments or examples, without contradiction.
[0045] This application provides an ESD device and its fabrication method, which solves the problems of high wafer material cost and complex processes caused by the thick dielectric layer combined with buried layer process in the prior art. It achieves low capacitance and high holding voltage performance of ESD device, greatly reducing production cost and production cycle.
[0046] The technical solution in this application is to solve the above problems, and the overall approach is as follows:
[0047] Example 1:
[0048] like Figure 1-2 As shown, an ESD device includes:
[0049] A heavily doped P-type single crystal 1 is divided into a first region and a second region on its upper part. Several anode regions and cathode regions are arranged alternately in the second region. Lightly doped N-type implantation regions 2 are arranged in the first region and the anode region respectively. Lightly doped P-type implantation regions 3 are arranged above the lightly doped N-type implantation regions in the first region. A pair of heavily doped P-type implantation wells 4 and heavily doped N-type implantation wells 5 are arranged alternately above the anode region and the cathode region in the second region respectively.
[0050] A glass wafer 6 is disposed above a heavily doped P-type single crystal wafer 1. Multiple glass vias 7 are disposed in the glass wafer. The glass vias 7 are respectively connected to the lightly doped N-type implantation region 2 and the lightly doped P-type implantation region 3 in the first region, and respectively connected to the heavily doped P-type implantation wells 4 and the heavily doped N-type implantation wells 5 in the second region. The glass vias 7 are filled with metal.
[0051] The cathode front metal 8 is disposed above the glass wafer 6 and connected to a pair of heavily doped P-type implantation wells 4 and heavily doped N-type implantation wells 5 in each cathode region through glass through-holes 7.
[0052] Interconnect metal 9 is disposed above glass wafer 6 and connected to a pair of heavily doped P-type implantation wells 4 and heavily doped N-type implantation wells 5 in each anode region through glass via 7. Interconnect metal 9 is also connected to lightly doped N-type implantation region 2 in the first region through glass via 7.
[0053] The anode front metal 10 is disposed above the glass wafer 6 and connected to the lightly doped P-type implantation region 3 in the first region through the glass via 7.
[0054] Furthermore, glass wafer 6 is bonded to heavily doped P-type single crystal wafer 1 via anodic bonding. Glass wafer 6 has a thickness ≥20μm and a dielectric constant of 3.8–4.1.
[0055] Furthermore, the metal filling the glass via 7 is formed by atomic layer deposition and then subjected to CMP treatment to achieve chip surface planarization.
[0056] This ESD device comprises a first region and a second region. The lightly doped N-type and P-type implanted regions in the first region form a low-capacitance diode, which is connected in series with the second region (ESD chip). The cathode of the diode is electrically connected to the anode of the second region (ESD chip), with the anode serving as the anode lead of the entire device. The cathode of the second region (ESD chip) serves as the cathode lead of the entire device. Its equivalent circuit diagram is shown below. Figure 3 As shown.
[0057] Example 2:
[0058] A method for fabricating an ESD device as described in Example 1 includes the following steps:
[0059] S1: Ph is implanted into the anode regions of the first and second regions of a heavily doped P-type single crystal wafer 1 with a resistivity of 0.01 Ω·cm, respectively, with implantation dose and energy of 1e. 14 ~5e 14 100keV. After implantation, high-temperature annealing is performed to further advance the N-type doped polysilicon to form a lightly doped N-well and a PN junction within the ESD parasitic SCR, i.e., the lightly doped N-type implantation region 2, such as... Figure 4 As shown.
[0060] S2: B is implanted into the lightly doped N-type implantation region 2 in the first region, with an implantation dose and energy of 1e. 14 ~5e 14 60keV. After implantation, high-temperature annealing is performed to further promote the formation of a low-capacitance diode PN junction in P-type doped polysilicon, i.e., the lightly doped P-type implantation region 3, such as... Figure 5 As shown.
[0061] S3: B is implanted into the lightly doped N-type implantation region 2 in the cathode and anode regions, with an implantation dose and energy of 1e. 16 ~3e 16 40 keV; Ph was implanted into the lightly doped N-type implantation region 2 in the cathode and anode regions, with implantation dose and energy of 1e, respectively. 16 ~3e 16 40 keV; rapid annealing activates the B and Ph impurities implanted in step S3 above to form heavily doped N-type and P-type shallow wells in the parasitic SCR N-type and P-type doped regions, namely heavily doped P-type implantation well 4 and heavily doped N-type implantation well 5, as shown. Figure 6 As shown.
[0062] S4: A glass wafer 6 with a thickness of 20 μm and a dielectric constant of 3.8–4.1 is bonded to the heavily doped P-type single-crystal 1 via anodic bonding; a glass via 7 with a depth of 20 μm and a width of 1 μm is formed using laser aperture; the glass via 7 is filled with metal using atomic layer deposition; and excess metal is removed using CMP to smooth the chip surface. Figure 7 As shown.
[0063] S5: A front-side metal structure, consisting of cathode front-side metal 8, interconnect metal 9, and anode front-side metal 10, is formed on the glass wafer 6 through photolithography and etching. The cathode PAD region of the entire device is interconnected with the cathode front-side metal 8 of the ESD chip (second region). The (anode) interconnect metal 9 of the ESD chip is connected to the cathode of the series diode (first region). The anode region of the entire device is interconnected with the anode of the series diode. The front-side metal interconnect structure is as follows: Figure 2 As shown in the diagram, the overall device structure is as follows: Figure 1 As shown.
[0064] The technical solutions described in the embodiments of this application have at least the following technical effects or advantages:
[0065] 1. This ESD device uses a glass wafer with a thickness ≥20μm to replace deposited SiO2 as the dielectric layer, thus overcoming the limitation of 10μm SiO2 as the dielectric layer in traditional processes. According to the capacitance calculation formula, if a 20μm thick glass wafer with a dielectric constant of 3.8–4.1 is used instead of a 10μm thick SiO2 with a dielectric constant of 3.9 as the dielectric layer of the ESD transistor, its parasitic capacitance value is reduced by at least 47%, significantly reducing the parasitic capacitance C0 of the ESD device and also greatly reducing the impact of the ESD transistor on high-frequency integrated circuits. Simultaneously, the use of a glass wafer in this ESD device also reduces the parasitic capacitance of the lateral diode, further reducing the overall parasitic capacitance of the device.
[0066]
[0067] Where ε0 is the vacuum permittivity; ε r denoted as the relative permittivity; A is the effective area of the parallel plates; d is the distance between the two electrodes.
[0068] 2. This ESD device uses a glass wafer as the dielectric layer, eliminating the need for the dozens or even hundreds of steps required in traditional manufacturing processes to achieve a thickness of [missing information]. The SiO2 deposition eliminates the need for multiple photolithography, etching, CMP, and reflow processes required for flatness and density during the deposition process, greatly reducing production costs and production cycle.
[0069] 3. This ESD device uses a low-capacitance diode with a lateral structure connected in series with the anode of the ESD chip. According to the formula for calculating series capacitance, the junction capacitance of the ESD chip and the diode connected in series is less than the junction capacitance of each chip individually. Since the diode is small in size and has a low doping concentration in the PN junction, its junction capacitance is much smaller than that of the ESD chip. Therefore, by using a low-capacitance diode with a lateral structure connected in series, the junction capacitance C1 of the entire device is greatly reduced.
[0070]
[0071] Among them, C ESD The junction capacitance of the ESD chip; C Diode This is the junction capacitance of the diode.
[0072] 4. This ESD device features a diode with a lateral structure connected in series with the anode of the ESD chip, which can improve the Vfollow-back of the ESD device during operation. hold Value. According to the voltage calculation formula, the voltage of the entire ESD device during operation is V. hold The value should be higher than the V of the ESD chip. ESDhold This reduces the latch-up phenomenon that can occur when ESD devices are operating. Compared with existing buried layer processes, it effectively reduces production costs and production cycle.
[0073] V hold =V ESDhold +VF (3);
[0074] Among them, V hold V is the sustaining voltage of the entire device. ESDhold V is the sustaining voltage of the ESD chip; VF is the forward conduction voltage of the diode.
[0075] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
[0076] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.
Claims
1. An ESD device, characterized in that, include: A heavily doped P-type single crystal is divided into a first region and a second region on the upper part. The second region is provided with a number of anode regions and cathode regions that are arranged alternately at intervals. The first region and the anode region are respectively provided with lightly doped N-type implantation regions. The lightly doped P-type implantation region is provided above the lightly doped N-type implantation region in the first region. The anode region and the cathode region in the second region are respectively provided with a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells arranged alternately at intervals. A glass wafer is disposed above the heavily doped P-type single crystal wafer. The glass wafer has a plurality of glass vias. The glass vias are respectively connected to the lightly doped N-type implantation region and the lightly doped P-type implantation region in the first region, and respectively connected to each heavily doped P-type implantation well and the heavily doped N-type implantation well in the second region. The glass vias are filled with metal. The cathode front metal is disposed above the glass wafer and connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each cathode region through the glass through-hole. Interconnect metal is disposed above the glass wafer and connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each of the anode regions through the glass vias. The interconnect metal is also connected to the lightly doped N-type implantation region in the first region through the glass vias. The anode front metal is disposed above the glass wafer and connected to the lightly doped P-type implantation region in the first region through the glass via.
2. The ESD device according to claim 1, characterized in that: The resistivity of the heavily doped P-type single crystal is 0.01 Ω·cm.
3. The ESD device according to claim 1, characterized in that: The glass wafer has a thickness ≥20μm and a dielectric constant of 3.8 to 4.
1.
4. The ESD device according to claim 1, characterized in that: The glass wafer is bonded to the heavily doped P-type single crystal wafer via anodic bonding.
5. The ESD device according to claim 4, characterized in that: The glass through-hole is formed by laser drilling, with a depth of 20μm and a width of 1μm.
6. The ESD device according to claim 5, characterized in that: The metal filling the glass vias is formed by atomic layer deposition and then surface planarized by CMP treatment.
7. The ESD device according to claim 1, characterized in that: The lightly doped N-type implantation region is implanted with Ph as the impurity, and the implantation dose and energy are 1e. 14 ~5e 14 100keV.
8. The ESD device according to claim 7, characterized in that: The lightly doped P-type implantation region is implanted with B as the impurity, and the implantation dose and energy are 1e. 14 ~5e 14 60KeV.
9. The ESD device according to claim 8, characterized in that: The heavily doped P-type implantation well is implanted with B as the impurity, and the implantation dose and energy are 1e. 16 ~3e 16 40 keV; the heavily doped N-type implantation well is implanted with Ph impurity, and the implantation dose and energy are 1e 16 ~3e 16 40 keV.
10. A method for fabricating an ESD device as described in any one of claims 1-9, characterized in that, Includes the following steps: S1: Ph is implanted into the first region and the anode region of the heavily doped P-type single crystal wafer, respectively, with implantation dose and energy of 1e. 14 ~5e 14 100 keV, followed by high-temperature annealing to form the lightly doped N-type implantation region; S2: B is implanted into the lightly doped N-type implantation region of the first region, with an implantation dose and energy of 1e. 14 ~5e 14 60 keV, after implantation, high-temperature annealing is performed to form the lightly doped P-type implantation region; S3: Implant B into the lightly doped N-type implantation regions of the cathode and anode regions, with an implantation dose and energy of 1e. 16 ~3e 16 40 keV; Ph is implanted into the lightly doped N-type implantation regions of the cathode and anode regions, with implantation dose and energy of 1e. 16 ~3e 16 40 keV; Rapid annealing is performed to activate and form the heavily doped P-type implantation well and the heavily doped N-type implantation well. S4: Bond the glass wafer onto the heavily doped P-type single crystal wafer; form the glass via using laser drilling; fill the glass via with metal using atomic layer deposition; and remove excess metal from the surface using CMP. S5: The cathode front metal, interconnect metal, and anode front metal are formed on the glass wafer by photolithography and etching. The cathode front metal is connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each cathode region. The interconnect metal is connected to a pair of heavily doped P-type implantation wells and heavily doped N-type implantation wells in each anode region. The interconnect metal is also connected to the lightly doped N-type implantation region in the first region. The anode front metal is connected to the lightly doped P-type implantation region in the first region.