Heterojunction solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system

Abstract

The invention relates to the technical field of solar cells, in particular to a heterojunction solar cell, a manufacturing method thereof, a photovoltaic module and a photovoltaic system. According to the embodiment of the invention, the backlight surface is set to be the polished surface, and the conductive transition layer and the metal layer are adopted to replace a transparent conductive layer in the related technology, so that the cost is reduced, the short-circuit current can be improved on the whole, and the photoelectric conversion efficiency of the solar cell is improved.

Description

[0001] This application is a divisional application of application No. 202311141131.7 (name: heterojunction solar cell and its manufacturing method, photovoltaic module and photovoltaic system, filing date: September 5, 2023). TECHNICAL FIELD

[0002] The present application relates to the technical field of solar cells, in particular to a heterojunction solar cell and its manufacturing method, a photovoltaic module and a photovoltaic system. BACKGROUND

[0003] In the related art, the heterojunction solar cell sequentially arranges an intrinsic amorphous silicon layer, a doped layer and a transparent conductive layer on both sides, which can form a symmetrical structure with high bifaciality. However, the heterojunction solar cell not only has the problem of high cost due to high usage of paste material and transparent conductive material, but also has the problem of difficult improvement of solar cell conversion efficiency due to low short-circuit current. SUMMARY

[0004] Therefore, it is necessary to provide a heterojunction solar cell and its manufacturing method, a photovoltaic module and a photovoltaic system to reduce the cost while improving the conversion efficiency of the solar cell.

[0005] According to one aspect of the present application, the embodiments of the present application provide a heterojunction solar cell, comprising:

[0006] a substrate having a back light surface; the back light surface is configured as a polished surface;

[0007] a first intrinsic amorphous silicon layer arranged on the back light surface;

[0008] a first doped layer arranged on a side surface of the first intrinsic amorphous silicon layer away from the back light surface;

[0009] a laminated structure comprising a conductive transition layer and a metal layer, the conductive transition layer being arranged on a side surface of the first doped layer away from the first intrinsic amorphous silicon layer, and the metal layer being arranged on a side surface of the conductive transition layer away from the first doped layer; and

[0010] a first grid line electrode located on a side of the laminated structure away from the first doped layer; at least one of the conductive transition layer and the metal layer is electrically connected to the first grid line electrode.

[0011] In one embodiment, the first grid line electrode is located on a side surface of the metal layer away from the conductive transition layer.

[0012] The first grid line electrode is electrically connected to the metal layer.

[0013] In one embodiment, the first grid line electrode is located on a side surface of the conductive transition layer away from the first doped layer.

[0014] At least a portion of the metal layer is located on the side of the conductive transition layer opposite to the first doped layer.

[0015] The first gate electrode is electrically connected to the conductive transition layer and the metal layer, respectively.

[0016] In one embodiment, a portion of the metal layer is located on the side surface of the conductive transition layer opposite to the first doped layer, and another portion covers at least a portion of the first gate electrode.

[0017] In one embodiment, the orthographic projection of the first gate electrode on the side surface of the conductive transition layer opposite to the first doped layer is located within the orthographic projection of the metal layer on the side surface of the conductive transition layer opposite to the first doped layer.

[0018] In one embodiment, the conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer.

[0019] In one embodiment, the conductive transition layer includes a first transparent conductive layer, the thickness of which is 5 nm-120 nm; or...

[0020] The conductive transition layer includes a tunneling layer with a thickness of 0.5 nm to 2 nm; or,

[0021] The conductive transition layer includes a first transparent conductive layer and a tunneling layer. The thickness of the first transparent conductive layer is 5nm-120nm, and the thickness of the tunneling layer is 0.5nm-2nm.

[0022] In one embodiment, the metal layer is a single-layer structure; or,

[0023] The metal layer has a multi-layer structure.

[0024] In one embodiment, the thickness of the conductive transition layer is 0.5 nm-122 nm; and / or,

[0025] The thickness of the metal layer is 20nm-200nm.

[0026] In one embodiment, the heterojunction solar cell further includes an insulating layer;

[0027] The insulating layer must at least cover the sides of the heterojunction solar cell.

[0028] In one embodiment, the substrate has a light-receiving surface disposed opposite to the backlight surface;

[0029] Heterojunction solar cells also include a second intrinsic amorphous silicon layer, a second doped layer, a second transparent conductive layer, and a second grid electrode, which are sequentially stacked on the light-receiving surface.

[0030] The insulating layer also covers an edge region of a side surface of the conductive transition layer away from the first doped layer; and / or

[0031] The insulating layer also covers an edge region of a side surface of the second transparent conductive layer away from the second doped layer.

[0032] According to another aspect of the present application, the embodiments of the present application provide a manufacturing method of a heterojunction solar cell, comprising:

[0033] providing a substrate; the substrate has a back light surface, and the back light surface is configured as a polished surface;

[0034] forming a first intrinsic amorphous silicon layer and a first doped layer on the back light surface in sequence;

[0035] forming a stack structure and a first grid electrode on a side surface of the first doped layer away from the first intrinsic amorphous silicon layer; the first grid electrode is located on a side of the stack structure away from the first doped layer;

[0036] The stack structure comprises a conductive transition layer and a metal layer, the conductive transition layer is arranged on a side surface of the first doped layer away from the first intrinsic amorphous silicon layer, and the metal layer is arranged on a side surface of the conductive transition layer away from the first doped layer.

[0037] At least one of the conductive transition layer and the metal layer is electrically connected with the first grid electrode.

[0038] In one of the embodiments, forming the stack structure and the first grid electrode on the side surface of the first doped layer away from the first intrinsic amorphous silicon layer comprises:

[0039] forming the conductive transition layer on the side surface of the first doped layer away from the first intrinsic amorphous silicon layer;

[0040] forming the metal layer and the first grid electrode on a side surface of the conductive transition layer away from the first doped layer in sequence;

[0041] The first grid electrode is electrically connected with the metal layer.

[0042] In one of the embodiments, before forming the metal layer and the first grid electrode on the side surface of the conductive transition layer away from the first doped layer in sequence, the method further comprises:

[0043] forming an insulating layer on a side of the heterojunction solar cell to cover at least the side of the heterojunction solar cell.

[0044] In one of the embodiments, forming the stack structure and the first grid electrode on the side surface of the first doped layer away from the first intrinsic amorphous silicon layer comprises:

[0045] forming the conductive transition layer on the side surface of the first doped layer away from the first intrinsic amorphous silicon layer;

[0046] a first gate line electrode and a metal layer are sequentially formed on a side surface of the conductive transition layer away from the first doped layer;

[0047] At least part of the metal layer is located on the side surface of the conductive transition layer away from the first doped layer; the first gate line electrode is electrically connected with the conductive transition layer and the metal layer respectively.

[0048] In one of the embodiments, before the first gate line electrode and the metal layer are sequentially formed on the side surface of the conductive transition layer away from the first doped layer, the method further comprises:

[0049] An insulating layer is formed on the side surface of the heterojunction solar cell to cover at least the side surface of the heterojunction solar cell.

[0050] In one of the embodiments, the conductive transition layer comprises at least one of a first transparent conductive layer and a tunneling layer; and / or,

[0051] The metal layer is formed by a preset process; the preset process comprises a physical vapor deposition process or an electron beam evaporation process.

[0052] According to still another aspect of the present application, the embodiments of the present application provide a photovoltaic module, comprising the heterojunction solar cell in any of the above embodiments; or,

[0053] The heterojunction solar cell is manufactured by the manufacturing method of the heterojunction solar cell in any of the above embodiments.

[0054] According to still another aspect of the present application, the embodiments of the present application provide a photovoltaic system, comprising the photovoltaic module in any of the above embodiments.

[0055] In the above heterojunction solar cell, manufacturing method thereof, photovoltaic module and photovoltaic system, the heterojunction solar cell comprises at least a substrate, a first intrinsic amorphous silicon layer, a first doped layer, a laminated structure and a first gate line electrode arranged on the back surface side of the substrate, and the laminated structure comprises a conductive transition layer and a metal layer. Compared with the related art which only provides a transparent conductive layer, the conductive transition layer and the metal layer are used to replace the transparent conductive layer in the embodiments of the present application, so that the amount of the transparent conductive material can be reduced. In the case where the metal layer is provided, since the metal layer has a certain contact area with the transition conductive layer, the path for collecting current can be increased, so that the number of the provided first gate line electrode can be reduced, the amount of the paste material can be reduced, and the short-circuit current can be improved. In addition, by setting the back surface of the substrate as a polished surface, the contact between the layers arranged on the back surface can be better, the uniformity and the film forming quality of the layers can be improved, the thickness of the conductive transition layer and the metal layer can be thinner, i.e., the amount of the related material can be reduced, the light incident on the back surface from the front surface can be reflected, the light absorption of the substrate can be increased, and the short-circuit current can be improved.

[0056] Therefore, the heterojunction solar cell provided by the embodiment of the present application can improve the short-circuit current as a whole while reducing the cost, and further improve the photoelectric conversion efficiency of the solar cell.

[0057] Additional aspects and advantages of the embodiments of the present application will be in part apparent and in part pointed out hereinafter. BRIEF DESCRIPTION OF DRAWINGS

[0058] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are intended to depict only preferred embodiments of the application, and therefore should not be considered to narrow the scope of the present application. Rather, the claims should be accorded the broadest possible interpretation. Like reference numerals have been used, where possible, to designate identical components that are common to the figures. In the drawings:

[0059] Figure 1 FIG. 1 is a structural schematic diagram of a heterojunction solar cell according to an embodiment of the present application;

[0060] Figure 2 FIG. 2 is a structural schematic diagram of a heterojunction solar cell according to another embodiment of the present application;

[0061] Figure 3 FIG. 3 is a structural schematic diagram of a heterojunction solar cell according to yet another embodiment of the present application;

[0062] Figure 4 FIG. 4 is a structural schematic diagram of a heterojunction solar cell according to still another embodiment of the present application;

[0063] Figure 5 FIG. 5 is a structural schematic diagram of a heterojunction solar cell according to yet another embodiment of the present application;

[0064] Figure 6 FIG. 6 is a structural schematic diagram of a heterojunction solar cell according to yet another embodiment of the present application;

[0065] Figure 7 FIG. 7 is a flowchart of a manufacturing method of a heterojunction solar cell according to an embodiment of the present application;

[0066] Figure 8 FIG. 8 is a flowchart of step S130 according to an embodiment of the present application;

[0067] Figure 9 FIG. 9 is a flowchart of step S130 according to another embodiment of the present application.

[0068] REFERENCE NUMERALS

[0069] Substrate 100, back light surface m1, light receiving surface m2;

[0070] The first intrinsic amorphous silicon layer 200a, the second intrinsic amorphous silicon layer 200b;

[0071] The first doped layer 300a, the second doped layer 300b;

[0072] The laminated structure 400a, the conductive transition layer 410a, the first transparent conductive layer 411a, the tunneling layer 412a, the metal layer 420a, the second transparent conductive layer 400b, the insulating layer J;

[0073] The first gate line electrode 500a, the second gate line electrode 500b. DETAILED DESCRIPTION

[0074] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced in a number of different ways beyond the specific embodiments described and it is therefore contemplated to cover all such modifications as fall within the scope of the application. It is to be understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application.

[0075] In the description of the present application, it is to be understood that the orientation or positional relationship indicated by these terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like is based on the orientation or positional relationship shown in the drawings, and is only for the purpose of facilitating the description of the present application and simplifying the description, and is not intended to indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application.

[0076] In addition, if these terms "first", "second" appear, these terms are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implying the number of the technical features indicated. Therefore, the features limited by "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, if the term "plurality" appears, the meaning of "plurality" is at least two, for example, two, three, etc., unless otherwise specifically limited.

[0077] In the present application, unless specifically defined otherwise and limited, if there are terms "mount", "connect", "connect", "fix" and the like, these terms should be interpreted in a broad sense. For example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. It should be noted that in the following description and the appended claims, one feature is "electrically connected" to another feature, which not only includes direct contact between one feature and another feature to form an electric energy transmission or current transmission channel, but also includes intermediate features between one feature and another feature. One feature, another feature and the intermediate features therebetween form an electric energy transmission channel or a current transmission channel to achieve electric energy transmission or transmission. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0078] In the present application, unless specifically defined otherwise and limited, if there are terms "mount", "connect", "connect", "fix" and the like, these terms should be interpreted in a broad sense. For example, it can be fixedly connected, or it can be detachably connected, or it can be integrated; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium; it can be the internal communication of two elements or the interaction relationship between two elements, unless otherwise specifically limited. It should be noted that in the following description and the appended claims, one feature is "electrically connected" to another feature, which not only includes direct contact between one feature and another feature to form an electric energy transmission or current transmission channel, but also includes intermediate features between one feature and another feature. One feature, another feature and the intermediate features therebetween form an electric energy transmission channel or a current transmission channel to achieve electric energy transmission or transmission. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0079] It should be noted that if an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can be a mediating element. If an element is considered to be "connected" to another element, it can be directly connected to the other element or there can be a mediating element. If present, the terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used in the present application are for illustrative purposes only and do not represent the only implementation.

[0080] Figure 1 The structure of the heterojunction solar cell in an embodiment of the present application is shown. For ease of illustration, only the content related to the embodiment of the present application is shown.

[0081] Please refer to Figure 1 The embodiment of the present application provides a heterojunction solar cell, which comprises a substrate 100, a first intrinsic amorphous silicon layer 200a, a first doped layer 300a, a laminated structure 400a and a first grid electrode 500a.

[0082] The substrate 100 can be selected according to actual needs. For example, the substrate 100 can be a silicon substrate. The doping type of the substrate 100 is not specifically limited. For example, the substrate 100 can be an N-type doped silicon substrate, or can be a P-type doped silicon substrate. In the embodiments of the present application, the substrate 100 can be an N-type single crystal silicon wafer.

[0083] The substrate 100 has a back light surface m1 configured as a polished surface. Of course, the substrate 100 also has a light receiving surface m2 opposite the back light surface m1. It can be understood that the light receiving surface m2 and the back light surface m1 are relative, and the light receiving surface m2 specifically refers to the surface on which the sunlight mainly irradiates on the substrate 100 in the solar cell or in the photovoltaic module. The light receiving surface m2 is usually provided with a textured structure, which can increase the light absorption area, improve the photo-generated current, and help to improve the efficiency of the heterojunction solar cell. In the embodiments of the present application, the back light surface m1 can be formed by a polishing process to form a polished surface.

[0084] The first intrinsic amorphous silicon layer 200a, the first doped layer 300a, the laminated structure 400a and the first gate line electrode 500a are arranged on the back light surface m1 side of the substrate 100. Specifically, the first intrinsic amorphous silicon layer 200a is arranged on the back light surface m1, the first doped layer 300a is arranged on the side surface of the first intrinsic amorphous silicon layer 200a away from the back light surface m1, and the laminated structure 400a is arranged on the side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a. Further, the laminated structure 400a includes a conductive transition layer 410a arranged on the side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a, and a metal layer 420a arranged on the side surface of the conductive transition layer 410a away from the first doped layer 300a. The conductive transition layer 410a is a transition structure for connecting the first doped layer 300a and the metal layer 420a and can conduct electricity. The first gate line electrode 500a is located on the side of the laminated structure 400a away from the first doped layer 300a. That is, the first gate line electrode 500a can be located on the side surface of the conductive transition layer 410a away from the first doped layer 300a, or can be located on the side surface of the metal layer 420a away from the conductive transition layer 410a.

[0085] Of course, the second intrinsic amorphous silicon layer 200b, the second doped layer 300b, the second transparent conductive layer 400b and the second gate line electrode 500b are sequentially arranged on the light receiving surface m2 of the substrate 100 to correspondingly realize photoelectric conversion on the light receiving surface m2.

[0086] The first doped layer 300a and the second doped layer 300b are of different doping types. The first doped layer 300a can be an N-type doped semiconductor layer, and the second doped layer 300b can be a P-type doped semiconductor layer. Of course, the first doped layer 300a can also be a P-type doped semiconductor layer, and the second doped layer 300b can also be an N-type doped semiconductor layer. In the embodiments of the present application, the first doped layer 300a is one of a P-type amorphous silicon layer, a P-type microcrystalline silicon layer, or a P-type nanocrystalline silicon layer, and the second doped layer 300b is one of an N-type amorphous silicon layer, an N-type microcrystalline silicon layer, or an N-type nanocrystalline silicon layer. The specific configuration can be flexibly set according to the specific use, and the embodiments of the present application do not make specific limitations thereto. The first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can achieve chemical passivation. In the case where the substrate 100 is an N-type single crystal silicon wafer, the first doped layer 300a is a P-type doped semiconductor layer, and the second doped layer 300b is an N-type doped semiconductor layer, the first doped layer 300a can serve as an emitter, and the second doped layer 300b can achieve field passivation.

[0087] Compared with the manner of only providing a transparent conductive layer in the related art, the conductive transition layer 410a and the metal layer 420a are used to replace the transparent conductive layer in the embodiments of the present application, which can reduce the amount of transparent conductive material used. In the case where the metal layer 420a is provided, since the metal layer 420a is a layer structure composed of a metal material and does not contain organic components, the compactness, adhesion, and conductive performance of the metal layer 420a will be better. On the basis of the foregoing, the metal layer 420a has a certain contact area with the transition conductive layer, which can increase the path of collecting current, not only can reduce the number of the first gate line electrode 500a provided, thereby reducing the amount of paste material used, but also can improve the short-circuit current.

[0088] In addition, by setting the back light surface m1 of the substrate 100 as a polished surface, not only can the contact between each layer provided on the back light surface m1 be better, the uniformity and film formation quality of each layer be improved, but also the thickness of the conductive transition layer 410a and the metal layer 420a can be made thinner, that is, the amount of related materials can be reduced, and the light incident from the light receiving surface m2 to the back light surface m1 can be reflected, the light absorption of the substrate 100 can be increased, and the short-circuit current can be improved.

[0089] It can be understood that in the case where the first doped layer 300a is a microcrystalline silicon layer or a nanocrystalline silicon layer, by setting the back light surface m1 as a polished surface, the crystallization rate of the first doped layer 300a can be improved. In the case where the first doped layer 300a is an emitter, by setting the back light surface m1 as a polished surface, it is more conducive to the adjustment of the band gap of the emitter.

[0090] Therefore, the heterojunction solar cell provided in the embodiments of the present application can not only reduce the cost, but also improve the short-circuit current as a whole, thereby improving the photoelectric conversion efficiency of the solar cell.

[0091] In some embodiments, please continue to refer to Figure 1 The first gate line electrode 500a is located on a side surface of the metal layer 420a away from the conductive transition layer 410a, and the first gate line electrode 500a is electrically connected to the metal layer 420a. That is, the conductive transition layer 410a, the metal layer 420a, and the first gate line electrode 500a are sequentially stacked on a side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a.

[0092] In this way, by directly arranging the first gate line electrode 500a on the metal layer 420a, not only the current can be collected, but also the reliability of the first gate line electrode 500a can be improved.

[0093] Figure 2 A structure diagram of a heterojunction solar cell in another embodiment of the present application is shown. For ease of illustration, only the content related to the embodiments of the present application is shown.

[0094] In some embodiments, please refer to Figure 2 The first gate line electrode 500a is located on a side surface of the conductive transition layer 410a away from the first doped layer 300a, and at least part of the metal layer 420a is located on the side surface of the conductive transition layer 410a away from the first doped layer 300a, and the first gate line electrode 500a is electrically connected to the conductive transition layer 410a and the metal layer 420a. That is, the first gate line electrode 500a and at least part of the metal layer 420a are both located on the side surface of the conductive transition layer 410a away from the first doped layer 300a.

[0095] Specifically, the metal layer 420a can be entirely located on the side surface of the conductive transition layer 410a away from the first doped layer 300a, and the side wall of the metal layer 420a is connected to the side wall of the first gate line electrode 500a. The metal layer 420a can also be partially located on the side surface of the conductive transition layer 410a away from the first doped layer 300a, and the other part covers at least part of the first gate line electrode 500a. It can be understood that the other part of the metal layer 420a can completely cover the first gate line electrode 500a, or at least cover the side wall of the gate line electrode, as long as the metal layer 420a can be electrically connected between the conductive transition layer 410a and the first gate line electrode 500a, and the embodiments of the present application do not make specific limitations thereon. For example, Figure 2For example, the other part of the metal layer 420a is shown to completely cover the first gate line electrode 500a, in which case, the orthographic projection of the first gate line electrode 500a on the side surface of the conductive transition layer 410a facing away from the first doped layer 300a is located within the orthographic projection of the metal layer 420a on the side surface of the conductive transition layer 410a facing away from the first doped layer 300a. That is, the conductive transition layer 410a, the first gate line electrode 500a and the metal layer 420a can be sequentially stacked on the side surface of the first doped layer 300a facing away from the first intrinsic amorphous silicon layer 200a.

[0096] In this way, by electrically connecting the first gate line electrode 500a with the conductive transition layer 410a and the metal layer 420a respectively, the reliability of the first gate line electrode 500a can be improved. By covering at least part of the first gate line electrode 500a with the other part of the metal layer 420a, the reliability of the first gate line electrode 500a can be further improved, and the contact area between the first gate line electrode 500a and the metal layer 420a can be further increased, which is more conducive to the first gate line electrode 500a collecting current via the metal layer 420a. It can be understood that, in the case where the metal layer 420a completely covers the exposed surface of the first gate line electrode 500a and the exposed surface of the side of the conductive transition layer 410a facing away from the first doped layer 300a, the exposed surface of the first gate line electrode 500a is wrapped in the metal layer 420a, which further increases the contact area between the first gate line electrode 500a and the metal layer 420a, which is more conducive to collecting current and further improves the reliability of the first gate line electrode 500a.

[0097] It should be noted that the "exposed surface of the first gate line electrode 500a" refers to the surface of the first gate line electrode 500a excluding the surface in contact with the conductive transition layer 410a, and the "exposed surface of the side of the conductive transition layer 410a facing away from the first doped layer 300a" refers to the remaining part of the side surface of the conductive transition layer 410a facing away from the first doped layer 300a excluding the part in contact with the first gate line electrode 500a.

[0098] Figure 3 A structure diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 4 A structure diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 5 A structure diagram of a heterojunction solar cell in another embodiment of the present application is shown; Figure 6 A structure diagram of a heterojunction solar cell in another embodiment of the present application is shown; only the content related to the embodiments of the present application is shown for ease of illustration.

[0099] In some embodiments, the conductive transition layer 410a comprises at least one of the first transparent conductive layer 411a and the tunneling layer 412a.

[0100] As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a. Figure 1 and Figure 2 As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a. Figure 3 and Figure 4 As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a. Figure 5 As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a. Figure 6 As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a. Figure 5 As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a.

[0101] As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a.

[0102] As shown in FIG. 4A, the conductive transition layer 410a can comprise the first transparent conductive layer 411a; as shown in FIG. 4B, the conductive transition layer 410a can comprise the tunneling layer 412a; as shown in FIG. 4C, the conductive transition layer 410a can comprise the first transparent conductive layer 411a and the tunneling layer 412a.

[0103] In some embodiments, the thickness of the conductive transition layer 410a is 0.5 nm-122 nm. For example, the thickness of the conductive transition layer 410a can be 0.5 nm, 1 nm, 10 nm, 23 nm, 30 nm, 46 nm, 50 nm, 66 nm, 78 nm, 85 nm, 90 nm, 95 nm, 100 nm, 110 nm, 118 nm or 122 nm.

[0104] In this way, by controlling the thickness of the conductive transition layer 410a, the interface contact and optical absorption can be improved while reducing the series resistance.

[0105] In some embodiments, please continue to refer to Figure 1 and Figure 2 In the case that the conductive transition layer 410a comprises the first transparent conductive layer 411a, the thickness of the first transparent conductive layer 411a is 5nm-120nm. Exemplarily, the thickness of the first transparent conductive layer 411a can be 5nm, 7nm, 8nm, 10nm, 26nm, 32nm, 48nm, 50nm, 63nm, 75nm, 87nm, 93nm, 95nm, 100nm, 110nm, 118nm or 120nm.

[0106] In this way, by controlling the thickness of the first transparent conductive layer 411a, the optical absorption and the series resistance can be improved on the basis of having certain electrical properties and anti-reflection properties.

[0107] In some embodiments, please continue to refer to Figure 3 and Figure 4 In the case that the conductive transition layer 410a comprises the tunneling layer 412a, the thickness of the tunneling layer 412a is 0.5nm-2nm. Exemplarily, the thickness of the tunneling layer 412a can be 0.5nm, 0.6nm, 0.9nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm.

[0108] In this way, by controlling the thickness of the tunneling layer 412a, the optical absorption and the series resistance can be improved while covering as much as possible the side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a.

[0109] In some embodiments, please continue to refer to Figure 5 and Figure 6 The conductive transition layer 410a comprises the first transparent conductive layer 411a and the tunneling layer 412a, the thickness of the first transparent conductive layer 411a is 5nm-120nm, and the thickness of the tunneling layer 412a is 0.5nm-2nm. Exemplarily, the thickness of the first transparent conductive layer 411a can be 5nm, 7nm, 8nm, 10nm, 26nm, 32nm, 48nm, 50nm, 63nm, 75nm, 87nm, 93nm, 95nm, 100nm, 110nm, 118nm or 120nm, and the thickness of the tunneling layer 412a can be 0.5nm, 0.6nm, 0.9nm, 1nm, 1.2nm, 1.5nm, 1.8nm or 2nm. The corresponding advantages can be referred to the content of some of the foregoing embodiments, which will not be described here again. In combination with the content illustrated in some of the foregoing embodiments, the object covered by the tunneling layer 412a can be the first transparent conductive layer 411a or the first doped layer 300a.

[0110] It can be understood that, in the case of being provided with the tunneling layer 412a, the contact resistivity can be improved by means of the tunneling layer 412a. In the case of the tunneling layer 412a being arranged between the first transparent conductive layer 411a and the metal layer 420a, the interface performance between the first transparent conductive layer 411a and the metal layer 420a can be further improved by means of the tunneling layer 412a.

[0111] It can be understood that the material of the first transparent conductive layer 411a (i.e. the TCO layer) is selected from one or more of indium tin oxide (ITO), tungsten-doped indium oxide (IWO), cesium-doped indium oxide (ICO), tin oxide, gallium-doped zinc oxide (GZO), gallium-aluminum-doped zinc oxide (GAZO), aluminum zinc oxide (AZO), and VTTO target material. Accordingly, the second transparent conductive layer 400b (i.e. the TCO layer) can also be considered in this regard. The materials of the first transparent conductive layer 411a and the second transparent conductive layer 400b can be the same or different. The material of the tunneling layer 412a is selected from one or more of aluminum oxide, silicon oxide, and titanium oxide. The selection can be made according to specific use cases, which are not specifically limited in the embodiments of the present application.

[0112] In some embodiments, please continue to refer to Figures 1 to 6 The thickness of the metal layer 420a is 20 nm-200 nm. Exemplarily, the thickness of the metal layer 420a can be 20 nm, 22 nm, 30 nm, 35 nm, 40 nm, 45 nm, 55 nm, 58 nm, 60 nm, 65 nm, 70 nm, 73 nm, 80 nm, 90 nm, 100 nm, 110 nm, 130 nm, 140 nm, 150 nm, 170 nm, 175 nm, 180 nm, 190 nm, 200 nm, or 200 nm.

[0113] In this way, by controlling the thickness of the metal layer 420a, the path of collecting current can be increased while covering the conductive transition layer 410a as much as possible. In combination with the content shown in some of the foregoing embodiments, in the case of the metal layer 420a being wrapped around the first gate line electrode 500a in cooperation with the conductive transition layer 410a, the reliability of the first gate line electrode 500a can be further improved.

[0114] In some embodiments, the metal layer 420a is a single-layer structure; or, the metal layer 420a is a multi-layer structure. Exemplarily, the material of the metal layer 420a can be one or more of copper, silver, aluminum, tin, nickel, or titanium. In the case of the metal layer 420a being a multi-layer structure, the materials of the layers can be the same or different. The structure of the corresponding metal layer 420a can be set according to specific use cases, which are not specifically limited herein.

[0115] In some embodiments, please continue to refer to Figures 1 to 6The heterojunction solar cell further comprises an insulating layer J covering at least the side surface of the heterojunction solar cell. In this way, the insulating layer J can play a role of side surface gas and oxygen barrier on the side surface of the heterojunction solar cell, which is conducive to improving the stability of the heterojunction solar cell.

[0116] It should be noted that the side surface of the heterojunction solar cell refers to the side surface of the substrate 100 and the side surface of each layer arranged on the back light surface m1 and the light receiving surface m2. The side surface of the substrate 100 is the surface connected to the light receiving surface m2 and the back light surface m1, and the side surface of each layer can be understood with reference to this, and will not be described in detail.

[0117] It can be understood that the insulating layer J can be made before the metal layer 420a is formed. In this case, the situation that the metal is deposited to the side surface of the heterojunction solar cell to form a recombination center when the metal layer 420a is made can also be improved, and the influence of the making of the metal layer 420a on the performance of the heterojunction solar cell is also improved.

[0118] In some embodiments, please continue to refer to Figures 1 to 6 The insulating layer J also covers the edge area of the side surface of the conductive transition layer 410a away from the first doped layer 300a, and / or the insulating layer J also covers the edge area of the side surface of the second transparent conductive layer 400b away from the second doped layer 300b. In this way, the reliability of the adhesion of the insulating layer J can be improved.

[0119] It can be understood that the edge area of the side surface of the conductive transition layer 410a away from the first doped layer 300a is the area connected to the side surface of the conductive transition layer 410a, and the edge area of the side surface of the second transparent conductive layer 400b away from the second doped layer 300b is the area connected to the side surface of the second transparent conductive layer 400b.

[0120] In some embodiments, the material of the insulating layer J includes an insulating material such as silicon oxide, an organic insulating material or an inorganic insulating material. The specific use case can be set, and the embodiments of the present application do not make specific limitations.

[0121] Figure 7 The flowchart of the manufacturing method of the heterojunction solar cell in an embodiment of the present application is shown; only the content related to the embodiments of the present application is shown for the convenience of description.

[0122] Based on the same inventive concept, please refer to Figure 7 , and in combination with Figures 1 to 6 The embodiments of the present application further provide a manufacturing method of a heterojunction solar cell, comprising the following steps:

[0123] In step S110, a substrate 100 is provided; the substrate 100 has a back light surface m1, and the back light surface m1 is configured as a polished surface.

[0124] In step S120, a first intrinsic amorphous silicon layer 200a and a first doped layer 300a are sequentially formed on the back light surface m1.

[0125] In step S130, a laminated structure 400a and a first gate line electrode 500a are formed on a side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a; the first gate line electrode 500a is located on a side of the laminated structure 400a away from the first doped layer 300a; the laminated structure 400a comprises a conductive transition layer 410a and a metal layer 420a; the conductive transition layer 410a is arranged on a side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a; the metal layer 420a is arranged on a side surface of the conductive transition layer 410a away from the first doped layer 300a; at least one of the conductive transition layer 410a and the metal layer 420a is electrically connected to the first gate line electrode 500a.

[0126] In step S110, the back light surface m1 of the substrate 100 can be polished by a polishing process, so that the back light surface m1 is a polished surface. The polishing process can be a chemical polishing process or a physical polishing process. For example, the back light surface m1 can be alkali polished, and the solution for alkali polishing can be KOH. The selection can be made according to specific use, which is not specifically limited in the embodiments of the present application. Correspondingly, the substrate 100 also has a light receiving surface m2 arranged opposite to the back light surface m1, and the light receiving surface m2 of the substrate 100 can be textured by a texturing process to form a textured structure on the light receiving surface m2.

[0127] The step of providing the substrate 100 can include a step of pretreating the substrate 100. The pretreatment process includes cleaning and other processes to facilitate subsequent processes. The required pretreatment process can be selected according to the use, which is not specifically limited in the embodiments of the present application.

[0128] In step S120, the first intrinsic amorphous silicon layer 200a can be formed on the back light surface m1 at the same time as the second intrinsic amorphous silicon layer 200b is formed on the light receiving surface m2; the first doped layer 300a is formed on a side surface of the first intrinsic amorphous silicon layer 200a away from the back light surface m1 at the same time as the second doped layer 300b is formed on a side surface of the second intrinsic amorphous silicon layer 200b away from the light receiving surface m2. Of course, the operations can also be performed at different times, which is not specifically limited herein.

[0129] The first intrinsic amorphous silicon layer 200a and the second intrinsic amorphous silicon layer 200b can be deposited on the corresponding surfaces by a chemical vapor deposition method (for example, plasma enhanced chemical vapor deposition, PECVD for short). The first doped layer 300a and the second doped layer 300b can be deposited on the corresponding surfaces by a chemical vapor deposition method (for example, plasma enhanced chemical vapor deposition, PECVD for short). The specific use can be set, and the embodiments of the present application do not make specific limitations.

[0130] In step S130, the conductive transition layer 410a is a transition structure for connecting the first doped layer 300a and the metal layer 420a and can conduct electricity. The conductive transition layer 410a can include at least one of the first transparent conductive layer 411a and the tunneling layer 412a. The first gate line electrode 500a is located on the side of the stack structure 400a away from the first doped layer 300a. That is, the first gate line electrode 500a can be located on the side surface of the conductive transition layer 410a away from the first doped layer 300a, or on the side surface of the metal layer 420a away from the conductive transition layer 410a.

[0131] The advantages of the heterojunction solar cell shown in some of the above embodiments are also possessed by the heterojunction solar cell obtained by the manufacturing method of the heterojunction solar cell. Therefore, the embodiments of the related layers are not described again. In addition, the embodiments of the related layers can also refer to the ways shown in some of the above embodiments, and are not described again.

[0132] Figure 8 The flowchart of step S130 in an embodiment of the present application is shown; for convenience, only the content related to the embodiment of the present application is shown.

[0133] In some embodiments, please refer to Figure 8 , and in combination with Figure 1 , Figure 3 and Figure 5 , step S130 includes the following steps:

[0134] Step S131a, forming a conductive transition layer 410a on the side surface of the first doped layer 300a away from the first intrinsic amorphous silicon layer 200a;

[0135] Step S132a, sequentially forming a metal layer 420a and a first gate line electrode 500a on the side surface of the conductive transition layer 410a away from the first doped layer 300a; wherein the first gate line electrode 500a is electrically connected with the metal layer 420a.

[0136] In step S131a, if the conductive transition layer 410a includes a first transparent conductive layer 411a, a second transparent conductive layer 400b may also be formed simultaneously on the surface of the second doped layer 300b facing away from the second intrinsic amorphous silicon layer 200b while the first transparent conductive layer 411a is being formed. Alternatively, the first transparent conductive layer 411a and the second transparent conductive layer 400b may not be formed simultaneously. The materials of the first transparent conductive layer 411a and the second transparent conductive layer 400b may be the same or different. As illustrated in some of the aforementioned embodiments, since a metal layer 420a is also formed on the backlight surface m1 side, the thickness of the first transparent conductive layer 411a may be less than the thickness of the second transparent conductive layer 400b. The first transparent conductive layer 411a and the second transparent conductive layer 400b can be formed on the surface of the corresponding layer by a physical vapor deposition method (e.g., magnetron sputtering). This can be configured according to specific applications, and the embodiments of this application do not impose specific limitations on this. If the conductive transition layer 410a includes a tunneling layer 412a, it can be formed on the surface of the corresponding layer by atomic layer deposition (ALD).

[0137] In step S132a, the following can be formed: Figure 1 , Figure 3 and Figure 5 The structure shown is a combination of the stacked structure 400a and the first gate electrode 500a.

[0138] Figure 9 A flowchart of step S130 in another embodiment of this application is shown; for ease of explanation, only the content related to the embodiment of this application is shown.

[0139] In some embodiments, please refer to Figure 9 and in conjunction with reference Figure 2 , Figure 4 and Figure 6 Step S130 includes the following steps:

[0140] Step S131b: A conductive transition layer 410a is formed on the surface of the first doped layer 300a on the side opposite to the first intrinsic amorphous silicon layer 200a.

[0141] Step S132b: A first gate electrode 500a and a metal layer 420a are sequentially formed on the side surface of the conductive transition layer 410a facing away from the first doped layer 300a; wherein at least a portion of the metal layer 420a is located on the side surface of the conductive transition layer 410a facing away from the first doped layer 300a; the first gate electrode 500a is electrically connected to the conductive transition layer 410a and the metal layer 420a respectively.

[0142] In step S131b, the structure and arrangement of the metal layer 420a can refer to the embodiments described above, and will not be repeated here.

[0143] In step S132b, the structure and arrangement of the metal layer 420a can refer to the embodiments described above, and will not be repeated here.

[0144] In this way, the metal layer 420a can be made by different manufacturing methods according to the structure of the stack structure 400a. The structure of the different metal layer 420a and the first grid line electrode 500a and the advantages thereof can refer to the embodiments described above, and will not be repeated here.

[0145] In the above-mentioned manufacturing method of the stack structure 400a, the metal layer 420a can be formed by a preset process, which includes a physical vapor deposition process or an electron beam evaporation process. In the case where the heterojunction solar cell further comprises an insulating layer J arranged on the side surface of the heterojunction solar cell, the insulating layer J can be formed on the side surface of the heterojunction solar cell before the metal layer 420a is formed, so as to cover at least the side surface of the heterojunction solar cell. The insulating layer J can be formed simultaneously with the conductive transition layer 410a, or can be formed by an edge printing process or a coating process, which can be selected according to specific use, and will not be limited here. Other embodiments of the insulating layer J and the advantages thereof can refer to the embodiments described above, and will not be repeated here.

[0146] It should be noted that in combination with the above-mentioned embodiments, the first grid line electrode 500a and the second grid line electrode 500b can be formed on the corresponding steps and corresponding layers by a screen printing process, a laser transfer process or an electroplating process.

[0147] In this way, by the embodiments described above, the required heterojunction solar cell can be obtained.

[0148] The performance of the heterojunction solar cell provided in the embodiments of the present application will be described below based on the embodiments described above and the related comparative examples.

[0149] In Comparative Examples 1 to 4 of this application, both the light-receiving and back-light-receiving surfaces of the substrate are texturized to form a textured structure. The first gate electrode on the back-light-receiving side includes 12 first main gate electrodes and 164 first sub-gate electrodes. The linewidth of the first main gate electrode is 100µm and the line height is 18µm. The linewidth of the first sub-gate electrode is 40µm and the line height is 15µm. The second gate electrode 500b on the light-receiving side includes 12 second main gate electrodes and 74 second sub-gate electrodes. The linewidth of the second main gate electrode is 100µm and the line height is 18µm. The linewidth of the second sub-gate electrode is 40µm and the line height is 15µm. The thickness of the second transparent conductive layer (using an ITO layer) on the light-receiving side is 75nm.

[0150] In Comparative Example 1, the transparent conductive layer located on the backlight side is an ITO layer formed by PVD process, with a thickness of 80nm.

[0151] In Comparative Example 2, a first transparent conductive layer, a first gate electrode, and a metal layer are formed sequentially, with the metal layer covering the first gate electrode. The first transparent conductive layer, located on the backlight side, is an ITO layer fabricated using a PVD process, with a thickness of 80 nm. The metal layer, a silver layer fabricated by vapor deposition, is disposed on the surface of the first transparent conductive layer away from the first doped layer, and has a thickness of 100 nm. No insulating layer is provided.

[0152] In Comparative Example 3, compared to Comparative Example 2, an insulating layer J is provided.

[0153] In Embodiments 1 to 8 of this application, the backlight surface m1 of the substrate 100 is a polished surface, and an insulating layer J is formed on the side of the heterojunction solar cell. The metal layer 420a is a silver layer fabricated by vapor deposition with a thickness of 100 nm.

[0154] In Example 1, the following method is used: Figure 2 The structure shown has the same parameters as the aforementioned comparative example for the first gate electrode 500a and the second gate electrode 500b. The conductive transition layer 410a located on the backlight surface m1 side is the first transparent conductive layer 411a, which is an ITO layer formed by PVD process with a thickness of 80nm.

[0155] In Example 2, the following method is used: Figure 4 The structure shown has the same parameters as the aforementioned comparative example for the first gate electrode 500a and the second gate electrode 500b. The conductive transition layer 410a located on the backlight side m1 is a tunneling layer 412a, which is a silicon oxide layer formed by ALD process with a thickness of 1.5nm.

[0156] In Example 3, the following method is used:Figure 6 The structure shown in the embodiment 4, on the basis of the embodiment 3, the number of the first sub gate line electrodes located at the backlight m1 side is reduced to 82.

[0157] In the embodiment 4, the structure shown in the embodiment 3 is adopted, and the related parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the foregoing comparative example. Figure 6 The structure shown in the embodiment 5, on the basis of the embodiment 4, the number of the first sub gate line electrodes located at the backlight m1 side is reduced to 82.

[0158] In the embodiment 5, the structure shown in the embodiment 4 is adopted, and the related parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the foregoing comparative example. Figure 5 The structure shown in the embodiment 6, on the basis of the embodiment 5, the number of the first sub gate line electrodes located at the backlight m1 side is reduced to 82.

[0159] In the embodiment 6, the structure shown in the embodiment 5 is adopted, and the related parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the foregoing comparative example. Figure 1 The structure shown in the embodiment 7, on the basis of the embodiment 6, the number of the first sub gate line electrodes located at the backlight m1 side is reduced to 82.

[0160] In the embodiment 7, the structure shown in the embodiment 6 is adopted, and the related parameters of the first gate line electrode 500a and the second gate line electrode 500b are the same as those of the foregoing comparative example. Figure 5 The structure shown in the embodiment 8, on the basis of the embodiment 7, the number of the first sub gate line electrodes located at the backlight m1 side is reduced to 82.

[0161] The heterojunction solar cells in the foregoing comparative examples and embodiments are tested, and the experimental results are shown in Table 1.

[0162]

[0163] From Table 1, it can be seen that, compared with Comparative Example 1, the optical loss of the metal layer 420a and the first transparent conductive layer 411a interface is larger in Comparative Example 2, the short-circuit current is reduced by 0.15 A, but the side is not protected, which leads to leakage, and the parallel resistance is reduced obviously. The series resistance is slightly reduced, and the efficiency is reduced by 0.13%. In Comparative Example 3, after adding the insulating layer J, the parallel resistance is not significantly reduced, and the efficiency is only reduced by 0.05%, mainly due to the reduction of the short-circuit current. Example 1 is similar to Comparative Example 3, because the back surface m1 is set as a polished surface, the multiple reflection and absorption loss of the interface can be reduced, and the short-circuit current is higher. In addition, because the back surface m1 is a polished surface, the metal layer 420a obtained by the same evaporation process is thicker, and because the polished surface is smoother, the carrier transport path is shorter, so the series resistance is lower, and the efficiency is increased by 0.06%. In Example 2, only 1.5 nm of silicon oxide layer is used, which can improve the potential barrier between the metal layer 420a and the substrate 100 to a certain extent, and also ensure a certain short-circuit current, while the series resistance is increased to a certain extent, and the efficiency is also decreased to a certain extent due to the damage, but overall it can reduce the cost while meeting certain efficiency requirements. In Example 3, the interface optical loss is smaller, the contact resistance and series resistance are slightly better, and the efficiency is increased by 0.1% compared with Comparative Example 1. In Example 4, the efficiency is still 0.04% higher than that of Comparative Example 1 under the condition that half of the back surface sub-grid is reduced. In Example 5, similar to Example 3, the metal layer 420a is below the first grid line electrode 500a, and the results are similar. In Example 6, the thickness of the first transparent conductive layer 411a is thinned to 10 nm, the parasitic absorption of the first transparent conductive layer 411a is reduced, and the short-circuit current is basically flat. The convergence effect is mainly borne by the metal layer 420a, the series resistance is flat, and the use of ITO can be effectively reduced. In Example 7, the tunneling layer 412a is added on the basis of Example 6, which improves the interface contact and optical absorption effect, and the efficiency is higher.

[0164] It can be seen that the heterojunction solar cell provided by the embodiments of the present application reduces the cost while improving the conversion efficiency of the solar cell. Further, through the cooperation of the first transparent conductive layer 411a, the tunneling layer 412a, the metal layer 420a and the insulating layer J, better results are further obtained.

[0165] Based on the same inventive concept, the embodiments of the present application provide a photovoltaic module, which includes the heterojunction solar cell in any of the above embodiments; or the heterojunction solar cell obtained by the manufacturing method of the heterojunction solar cell in any of the above embodiments.

[0166] Further, the heterojunction solar cells can be arranged in multiple, and the heterojunction solar cells can be electrically connected to form multiple cell strings in a whole piece or multiple pieces, and the multiple cell strings are electrically connected in series and / or parallel. The photovoltaic module can further include an encapsulation layer and a cover plate, the encapsulation layer is used to cover the surface of the cell string, and the cover plate is used to cover the surface of the encapsulation layer away from the cell string. Specifically, in some embodiments, the multiple cell strings can be electrically connected through a conductive belt. The encapsulation layer covers the surface of the solar cell. For example, the encapsulation layer can be an organic encapsulation film such as an ethylene-vinyl acetate copolymer film, a polyethylene octene elastomer film, or a polyethylene terephthalate film. The cover plate can be a glass cover plate, a plastic cover plate, or a cover plate with a light transmission function.

[0167] The photovoltaic module also has the advantages of the heterojunction solar cell in any of the above embodiments or the heterojunction solar cell obtained by the manufacturing method of the heterojunction solar cell in any of the above embodiments, and details are not repeated here.

[0168] Based on the same inventive concept, the embodiments of the present application provide a photovoltaic system including the photovoltaic module in any of the above embodiments. The photovoltaic system also has the advantages of the photovoltaic module, and details are not repeated here.

[0169] It can be understood that the photovoltaic system can be applied in a photovoltaic power station, for example, a ground power station, a roof power station, a water surface power station, etc., and can also be applied in a device or apparatus that uses solar energy to generate electricity, for example, a user solar power source, a solar street lamp, a solar car, a solar building, etc. Of course, it can be understood that the application scenarios of the photovoltaic system are not limited to this, that is, the photovoltaic system can be applied in all fields that need to use solar energy to generate electricity. Taking a photovoltaic power generation system network as an example, the photovoltaic system can include a photovoltaic array, a combiner box, and an inverter, the photovoltaic array can be an array combination of multiple photovoltaic modules, for example, multiple photovoltaic modules can form multiple photovoltaic arrays, the photovoltaic array is connected to the combiner box, the combiner box can combine the current generated by the photovoltaic array, the combined current flows through the inverter to convert into alternating current required by the power grid, and then is connected to the power network to realize solar power supply.

[0170] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but as long as the combinations of the technical features do not exist, they should be considered as within the scope of the present disclosure.

[0171] The above embodiments only express several implementation ways of the present application, and the description is relatively specific and detailed, but it should not be understood as a limitation to the patent scope of the application. It should be pointed out that for ordinary skilled persons in the art, several modifications and improvements can be made without departing from the concept of the present application, which all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A heterojunction solar cell, characterized in that, include: The substrate has a backlight side; A first intrinsic amorphous silicon layer is disposed on the backlight surface; The first doped layer is disposed on the side of the first intrinsic amorphous silicon layer facing away from the backlight surface; A stacked structure includes a conductive transition layer and a metal layer, wherein the conductive transition layer is disposed on the side surface of the first doped layer opposite to the first intrinsic amorphous silicon layer, and the metal layer is disposed on the side surface of the conductive transition layer opposite to the first doped layer. and The first gate electrode is located on the side of the stacked structure opposite to the first doped layer; at least one of the conductive transition layer and the metal layer is electrically connected to the first gate electrode. The heterojunction solar cell also includes an insulating layer; The insulating layer covers the side of the heterojunction solar cell; The insulating layer also covers the edge region of the conductive transition layer on the side surface opposite to the first doped layer.

2. The heterojunction solar cell according to claim 1, characterized in that, The first gate electrode is located on the side surface of the metal layer opposite to the conductive transition layer; The first gate electrode is electrically connected to the metal layer.

3. The heterojunction solar cell according to claim 1, characterized in that, The first gate electrode is located on the side surface of the conductive transition layer opposite to the first doped layer; At least a portion of the metal layer is located on the side surface of the conductive transition layer opposite to the first doped layer. The first gate electrode is electrically connected to the conductive transition layer and the metal layer, respectively.

4. The heterojunction solar cell according to claim 3, characterized in that, A portion of the metal layer is located on the side surface of the conductive transition layer opposite to the first doped layer, and another portion covers at least a portion of the first gate electrode.

5. The heterojunction solar cell according to claim 4, characterized in that, The orthographic projection of the first gate electrode on the side surface of the conductive transition layer opposite to the first doped layer is located within the orthographic projection of the metal layer on the side surface of the conductive transition layer opposite to the first doped layer.

6. The heterojunction solar cell according to any one of claims 1-5, characterized in that, The conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer.

7. The heterojunction solar cell according to claim 6, characterized in that, The conductive transition layer includes a first transparent conductive layer, the thickness of which is 5nm-120nm; or... The conductive transition layer includes a tunneling layer, the thickness of which is 0.5 nm to 2 nm; or, The conductive transition layer includes a first transparent conductive layer and a tunneling layer. The thickness of the first transparent conductive layer is 5nm-120nm, and the thickness of the tunneling layer is 0.5nm-2nm.

8. The heterojunction solar cell according to any one of claims 1-5, characterized in that, The metal layer is a single-layer structure; or... The metal layer has a multi-layer structure.

9. The heterojunction solar cell according to any one of claims 1-5, characterized in that, The thickness of the conductive transition layer is 0.5 nm-122 nm; and / or, The thickness of the metal layer is 20nm-200nm.

10. The heterojunction solar cell according to claim 1, characterized in that, The substrate has a light-receiving surface disposed opposite to the backlight surface; The heterojunction solar cell further includes a second intrinsic amorphous silicon layer, a second doped layer, a second transparent conductive layer, and a second grid electrode, which are sequentially stacked on the light-receiving surface. The insulating layer also covers the edge region of the second transparent conductive layer on the side surface opposite to the second doped layer.

11. The heterojunction solar cell according to any one of claims 1-5, characterized in that, The backlight surface is constructed as a polished surface.

12. A method for fabricating a heterojunction solar cell, characterized in that, include: Provide a base; The substrate has a backlight side; A first intrinsic amorphous silicon layer and a first doped layer are sequentially formed on the backlight surface; A stacked structure and a first gate electrode are formed on the surface of the first doped layer that is away from the first intrinsic amorphous silicon layer; The first gate electrode is located on the side of the stacked structure opposite to the first doped layer; The stacked structure includes a conductive transition layer and a metal layer. The conductive transition layer is disposed on the side surface of the first doped layer that is away from the first intrinsic amorphous silicon layer, and the metal layer is disposed on the side surface of the conductive transition layer that is away from the first doped layer. At least one of the conductive transition layer and the metal layer is electrically connected to the first gate electrode; The step of forming a stacked structure and a first gate electrode on the surface of the first doped layer opposite to the first intrinsic amorphous silicon layer includes: The conductive transition layer is formed on the side of the first doped layer that is away from the first intrinsic amorphous silicon layer; The metal layer and the first gate electrode are formed on the side of the conductive transition layer opposite to the first doped layer; Before forming a metal layer and a first gate electrode on the side of the conductive transition layer opposite to the first doped layer, the method further includes: An insulating layer is formed on the side surface of the heterojunction solar cell and on the edge region of the conductive transition layer facing away from the first doped layer.

13. The method for fabricating a heterojunction solar cell according to claim 12, characterized in that, The method of forming the metal layer and the first gate electrode on the side surface of the conductive transition layer opposite to the first doped layer includes: The metal layer and the first gate electrode are sequentially formed on the side of the conductive transition layer opposite to the first doped layer; The first gate electrode is electrically connected to the metal layer.

14. The method for fabricating a heterojunction solar cell according to claim 12, characterized in that, The formation of the metal layer and the first gate electrode on the side of the conductive transition layer opposite to the first doped layer includes: The first gate electrode and the metal layer are sequentially formed on the side of the conductive transition layer opposite to the first doped layer. Wherein, at least a portion of the metal layer is located on the side surface of the conductive transition layer opposite to the first doped layer; the first gate electrode is electrically connected to the conductive transition layer and the metal layer respectively.

15. The method for fabricating a heterojunction solar cell according to any one of claims 12-14, characterized in that, The conductive transition layer includes at least one of a first transparent conductive layer and a tunneling layer; and / or, The metal layer is formed by a preset process; the preset process includes physical vapor deposition or electron beam evaporation.

16. A photovoltaic module, characterized in that, Including the heterojunction solar cell as described in any one of claims 1-11; or, The heterojunction solar cell includes the heterojunction solar cell fabricated by the method described in any one of claims 12-15.

17. A photovoltaic system, characterized in that, Including the photovoltaic module as described in claim 16.

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