Memory device with low power write high thermal stability factor and method of fabrication thereof

Abstract

The application provides a memory device with low power consumption and high thermal stability factor and a preparation method thereof, the device comprising, from bottom to top, a substrate, a spin / orbit flow generation layer, a ferromagnetic functional layer, a SiO2 layer, an electrode sheet and a regulation layer; the material of the spin / orbit flow generation layer is two-dimensional transition metal chalcogenide material TaIrTe4, the material of the ferromagnetic functional layer is two-dimensional ferromagnetic material Fe 3+x GaTe2, x=0-2, and the material of the regulation layer is two-dimensional ferroelectric material CuVP2S6; an electric field is applied to the left and right ends of the regulation layer. The vertical magnetic crystal anisotropy of the ferromagnetic functional layer is changed by regulating the ferroelectric material CuVP2S6 through the external electric field, the writing process of a large current of the device is reduced, so that the power consumption is reduced and the thermal stability is improved, and the durability is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a memory device with low power consumption and high thermal stability factor and a preparation method thereof. BACKGROUND

[0002] The application of spin-orbit torque (SOT) and orbital torque (OT) in magnetic tunnel junction (MTJ) has a great impact on the development of magnetic electronic devices, including magnetic resistance random access memory (MRAM), radio frequency sensors, microwave generators, etc., and most of the magnetic tunnel junctions are written by current repeated tunneling or high current density, which requires high durability of the material. The emergence of two-dimensional (2D) van der Waals materials provides more process possibilities for magnetic tunnel junctions, especially two-dimensional materials with high spin polarization are expected to be applied to the next generation of nanoscale devices. The existing scheme requires repeated writing and reading of current, which consumes more energy and generates more heat, which will have a certain impact on adjacent structures, making it difficult to break through the size and accuracy limitations and requiring high durability of the material. It is difficult to avoid the impact on other devices, and each writing has a strong wear on the material, and the repeatability is not good enough, resulting in a decline in storage performance or errors. SUMMARY

[0003] Therefore, the present application aims to provide a memory device with low power consumption and high thermal stability factor to solve the above problems.

[0004] To achieve the above purpose, the technical scheme of the present application is as follows:

[0005] A memory device with low power consumption and high thermal stability factor, comprising a substrate, a spin / orbit current generating layer, a ferromagnetic functional layer, a SiO2 layer, an electrode sheet and a control layer arranged in order from bottom to top; the material of the spin / orbit current generating layer is two-dimensional transition metal chalcogenide material TaIrTe4, the material of the ferromagnetic functional layer is two-dimensional ferromagnetic material Fe 3+x GaTe2, x=0-2, the material of the control layer is two-dimensional ferroelectric material CuVP2S6, the electrode sheet is strip-shaped and has a plurality of electrode sheets, and the plurality of electrode sheets are distributed in a radial manner on the upper surface of the SiO2 layer; an electric field is applied to the left and right ends of the control layer, and the field strength is 0.1-10kV / cm.

[0006] Fe 3+xGaTe2 can adjust its Curie temperature (Tc) and the size of perpendicular magnetic anisotropy (PMA) by adjusting x (the amount of Fe doping). Especially when x>0, excess Fe atoms will occupy the interstitial positions in the lattice or replace part of the Ga atom sites, causing local distortion of the crystal structure (such as slight expansion of the lattice constant), but still maintaining the overall stability of the layered skeleton, allowing the material to form a more stable oxide layer (Fe-O bond) on the surface, thereby improving the storage stability of the material in air and the long-term working reliability of the device. By introducing excess Fe atoms, the Curie temperature, perpendicular magnetic anisotropy, and stability are significantly improved without destroying the layered two-dimensional structure, which is particularly suitable for the needs of spintronic devices for high-temperature stability and high control efficiency.

[0007] The spin / orbit current generation layer (TaIrTe4), the ferromagnetic functional layer (Fe 3+x GaTe2), and the regulation layer (CuVP2S6) are all two-dimensional materials with higher lattice matching degree and lower interface defect density, reducing spin scattering and charge loss and significantly improving the magnetization switching efficiency.

[0008] Further, the substrate is a SiO2 / Si substrate, and the thickness of the substrate is 0.2-5mm.

[0009] Further, the thickness of the spin / orbit current generation layer is 5-20nm.

[0010] Further, the thickness of the ferromagnetic functional layer is 8-20nm.

[0011] Further, the thickness of the SiO2 layer is 0.1-5nm.

[0012] The thickness of the SiO2 layer is limited to 0.1-5nm, which not only avoids direct charge crosstalk between the ferromagnetic functional layer and the regulation layer, but also ensures that the high potential energy of CuVP2S6 efficiently penetrates to the Fe 3+x GaTe2 layer.

[0013] And after adding the SiO2 layer regulation, the switching current density is reduced, the power consumption is reduced, the durability is stable, and after writing, the CuVP2S6 will return to the initial state after a period of time, and the coercivity of Fe 3+x GaTe2 returns to the initial state, and the durability is increased.

[0014] Further, the thickness of the regulation layer is 200-500nm. The regulation layer cannot be regulated if the thickness is too thin, and it is not conducive to transfer if the thickness is too thick.

[0015] Further, the electrode sheet is Ti / Pt, and the thickness is 5 / 15nm.

[0016] The electrode sheet is arranged between the SiO2 layer and the regulation layer, and the left and right ends are arranged in a manner of applying an electric field, so that the ion migration direction of the CuVP2S6 layer is more easily regulated along the in-plane, and the electric field is more uniform.

[0017] Further, the substrate, the spin / orbit current generation layer and the ferromagnetic functional layer have the same size, the SiO2 layer has a size larger than that of the ferromagnetic functional layer, so that the outer periphery of the SiO2 layer extends out of the ferromagnetic functional layer; the length of the regulation layer is greater than that of the ferromagnetic functional layer, and the left end of the regulation layer is aligned with the left end of the ferromagnetic functional layer, and the right end of the regulation layer extends out of the SiO2 layer.

[0018] The substrate, the spin / orbit current generation layer and the ferromagnetic functional layer have the same size, and are completely aligned in the vertical direction, so that the spin orbit moment generated by the spin / orbit current generation layer can be vertically and efficiently transmitted to the ferromagnetic functional layer, and the spin scattering caused by edge misalignment is reduced. At the same time, the uniform size can reduce the interfacial stress and avoid interfacial peeling caused by uneven stress at high temperature.

[0019] The size of the SiO2 layer is greater than that of the ferromagnetic layer, so that the electrode sheet only contacts the SiO2 layer (insulation) and the regulation layer (CuVP2S6), and the problem of conductor voltage regulating CuVP2S6 caused by direct contact between the electrode and the conductive ferromagnetic functional layer and the spin / orbit current generation layer below is completely avoided.

[0020] The left end of the regulation layer is aligned with the ferromagnetic functional layer, so that the polarization electric field can accurately act on the core area of the ferromagnetic layer; the right end extends out of the SiO2 layer, so that the electrode at the right end of the regulation layer provides a contact site, and the electric field path of the left and right electrodes is completely limited in the regulation layer (to avoid the electric field diffusing to the SiO2 layer or the layer below), which significantly improves the utilization rate of the electric field.

[0021] The application also provides a preparation method of the low-power-consumption memory device with a high heat stability factor.

[0022] I. Clean the substrate and dry it;

[0023] II. Prepare the spin / orbit current generation layer, the ferromagnetic functional layer and the SiO2 layer on the substrate in sequence;

[0024] III. Prepare the electrode sheet on the upper surface of the SiO2 layer by combining the photolithography and the magnetron sputtering process;

[0025] IV. Prepare the regulation layer above the electrode sheet.

[0026] Further, the method for preparing the spin / orbit current generation layer, the ferromagnetic functional layer and the regulation layer is any one of the magnetron sputtering, the molecular beam epitaxy, the pulsed laser deposition, the physical vapor deposition, the chemical vapor deposition and the mechanical exfoliation;

[0027] The SiO2 layer is prepared by a magnetron deposition method.

[0028] Compared with the prior art, the memory device with low power consumption and high thermal stability factor has the following advantages:

[0029] Compared with the traditional magnetic tunnel junction manufacturing process, the memory device with low power consumption and high thermal stability factor greatly increases the fault tolerance rate of work and better protects the two-dimensional material. The application changes the intrinsic electric field of CuVP2S6 by electric field regulation, thereby regulating Fe 3+x GaTe2, and further changes the Hall signal, current density, coercivity and other signals of the overall device. Compared with the traditional SOT device, the application reduces the write current, reduces energy consumption and heat, better protects the device itself, and greatly improves the durability of the device. The two-dimensional magnetic material Fe 3+x GaTe2 has a high Curie temperature and good perpendicular magnetic anisotropy at room temperature, which can greatly reduce the size of the device and improve the integration. The preparation environment of the application needs to be mechanically peeled off under a protective gas to prevent oxidation, and the preparation process is relatively simple. The thickness can be flexibly used, and the adjacent device is less affected by the vertical magnetic structure, resulting in better yield. BRIEF DESCRIPTION OF DRAWINGS

[0030] The accompanying drawings, which form a part of the present application, are intended to provide further understanding of the present application, and the illustrative embodiments thereof and their descriptions serve to explain the present application, and do not constitute improper limitations on the present application. In the drawings:

[0031] Figure 1 The structure schematic diagram of the low-power-consumption high-thermal-stability-factor memory device described in the embodiments of the present application;

[0032] Figure 2 The top view optical picture of the low-power-consumption high-thermal-stability-factor memory device described in the embodiments of the present application, and the purple strip is an electrode sheet;

[0033] Figure 3 The front view structure diagram of the low-power-consumption high-thermal-stability-factor memory device described in the embodiments of the present application;

[0034] Figure 4 The abnormal Hall effect diagram of the memory device prepared in Example 1 of the present application;

[0035] Figure 5 The magnetization flip diagram of the memory device prepared in Example 1 of the present application;

[0036] Figure 6 The abnormal Hall effect diagram of the memory device prepared in Comparative Example 2 of the present application;

[0037] Figure 7 Anomalous Hall effect plot of the memory device prepared for Inventive Example 3;

[0038] Figure 8 Anomalous Hall effect plot of the memory device prepared for Inventive Example 4;

[0039] Figure 9 Anomalous Hall effect plot of the memory device prepared for Inventive Example 5.

[0040] BRIEF DESCRIPTION OF DRAWINGS

[0041] 1, substrate; 2, spin / orbit current generation layer; 3, ferromagnetic functional layer; 4, SiO2 layer; 5, regulation layer; 6, electrode sheet. DETAILED DESCRIPTION

[0042] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

[0043] In the description of the present application, it should be understood that the terms "center", "longitudinal", "transverse", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation of the present application. In addition, the terms "first", "second" and the like are only for the purpose of description and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" and the like can explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more.

[0044] In the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "mounting", "connecting", "connection" should be understood broadly, for example, it can be fixed connection, or detachable connection, or integrally connected; it can be mechanical connection, or electrical connection; it can be directly connected, or indirectly connected through intermediate medium, or the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood through specific circumstances.

[0045] With reference to the drawings of the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative effort belong to the scope of the present application.

[0046] Embodiment 1

[0047] A memory device with low power consumption and high thermal stability factor, comprising, from bottom to top, a substrate 1, a spin / orbit current generation layer 2, a ferromagnetic functional layer 3, a SiO2 layer 4, an electrode sheet 6 and a regulation layer 5; the substrate 1 is a SiO2 / Si substrate, the thickness of the substrate 1 is 1 mm; the material of the spin / orbit current generation layer 2 is two-dimensional transition metal chalcogenide material TaIrTe4, the thickness is 5 nm; the material of the ferromagnetic functional layer 3 is two-dimensional ferromagnetic material Fe 3+x GaTe2, x=0, the thickness is 9 nm; the thickness of the SiO2 layer 4 is 1 nm; the material of the regulation layer 5 is two-dimensional ferroelectric material CuVP2S6, the thickness is 200 nm; an electric field is applied to the left and right ends of the regulation layer 5, the field strength is 0.17 kV / cm; the electrode sheet 6 is Ti / Pt, the thickness is 5 / 15 nm, the electrode sheet is in the form of a strip and is provided with a plurality of electrode sheets, and the plurality of electrode sheets are distributed in a radial manner on the upper surface of the SiO2 layer.

[0048] The preparation method of the above device is as follows:

[0049] S1: cleaning the SiO2 / Si substrate

[0050] The substrate is sequentially ultrasonically cleaned in acetone, ethanol and deionized water for 10 mins and then dried by nitrogen air gun.

[0051] S2: preparing a two-dimensional transition metal chalcogenide material TaIrTe4 layer

[0052] The solid material TaIrTe4 is directly exfoliated on the surface of polydimethylsiloxane (PDMS) to form a TaIrTe4 / PDMS combination; the TaIrTe4 in the obtained TaIrTe4 / PDMS combination is contacted with the substrate, so that the TaIrTe4 is separated from the PDMS, the TaIrTe4 is laid on the surface of the substrate to form a TaIrTe4 layer.

[0053] S3: preparing a two-dimensional ferromagnetic material Fe 3+x GaTe2 layer

[0054] Similarly to S2, the solid material Fe 3+x GaTe2 is directly exfoliated on the surface of PDMS to form a Fe 3+xGaTe2 / PDMS composite; Fe in the resulting Fe3GaTe2 / PDMS composite 3+x GaTe2 and TaIrTe4 layers are in contact, allowing Fe 3+x GaTe2 decomposes from PDMS to form Fe 3+x GaTe2 layer.

[0055] S4: The structure obtained in S3 is rapidly placed into magnetron-deposited SiO2 to form a SiO2 layer.

[0056] S5: Preparation of electrode sheets

[0057] By combining photolithography and magnetron sputtering processes, electrode patterns are used for exposure and development, and Ti / Pt electrodes with a thickness of 5 / 15 nm are obtained by magnetron sputtering at room temperature.

[0058] S6: Fabrication of a two-dimensional ferroelectric material CuVP2S6 layer

[0059] Similar to S2, CuVP2S6 was exfoliated using PDMS via mechanical stripping to form a CuVP2S6 / PDMS composite, and a CuVP2S6 layer was formed on top of the electrode sheet.

[0060] Finally, the complete magnetic TaIrTe4 / Fe was obtained. 3+x GaTe2 / SiO2 / CuVP2S6 devices.

[0061] Structure as Figure 1 Figure 3 As shown, Figure 2 This is a top-down optical image. The purple bars represent electrode plates, I represents current, V represents detection voltage, and E represents applied electric field.

[0062] Figure 4 The image shows the anomalous Hall effect of the memory device prepared in Example 1. When a negative voltage is applied (blue), its coercivity is about 950 Oe, and its stability is higher. When a positive voltage is applied (red), its coercivity is about 400 Oe, and its coercivity is reduced by about 58%.

[0063] Figure 5 This is a magnetization reversal diagram of the memory device prepared in Example 1; the blue lines have higher coercivity and higher reversal current density, resulting in higher stability, while the red lines have lower coercivity and lower reversal current density, thus further reducing power consumption.

[0064] This demonstrates that the CuVP2S6 in this memory modulates Fe through potential. 3+x The coercivity of GaTe2, thereby modulating Fe 3+ x The switching current density of GaTe2 is high, and the effect is good.

[0065] Embodiment 2

[0066] A memory device with low power consumption and high thermal stability factor, comprising, from bottom to top, a substrate 1, a spin / orbit current generation layer 2, a ferromagnetic functional layer 3, a SiO2 layer 4, an electrode sheet 6 and a regulation layer 5; the substrate 1 is a SiO2 / Si substrate, the thickness of the substrate 1 is 3mm; the material of the spin / orbit current generation layer 2 is two-dimensional transition metal chalcogenide material TaIrTe4, the thickness is 10nm; the material of the ferromagnetic functional layer 3 is two-dimensional ferromagnetic material Fe 3+x GaTe2, x=1.8, the thickness is 20nm; the thickness of the SiO2 layer 4 is 4nm; the material of the regulation layer 5 is two-dimensional ferroelectric material CuVP2S6, the thickness is 500nm; an electric field is applied to the left and right ends of the regulation layer 5, the field strength is 0.3kV / cm; the electrode sheet 6 is Ti / Pt, the thickness is 5 / 15nm, the electrode sheet is in strip shape and is provided with a plurality of electrode sheets, and the plurality of electrode sheets are distributed in a radial manner on the upper surface of the SiO2 layer.

[0067] The preparation method of the device is as shown in Embodiment 1.

[0068] The abnormal Hall effect and magnetization reversal of the device prepared in this embodiment are similar to those of the device prepared in Embodiment 1. Figure 4 and Figure 5 Approximately, in the case of applying a negative voltage, the coercive force is higher, the reversal current density is larger, and the stability is higher; in the case of applying a positive voltage, the coercive force becomes smaller, the reversal current density becomes smaller, and thus the power consumption is further reduced.

[0069] Embodiment 3

[0070] A memory device with low power consumption and high thermal stability factor, comprising, from bottom to top, a substrate 1, a spin / orbit current generation layer 2, a ferromagnetic functional layer 3, a SiO2 layer 4, an electrode sheet 6 and a regulation layer 5; the substrate 1 is a SiO2 / Si substrate, the thickness of the substrate 1 is 5mm; the material of the spin / orbit current generation layer 2 is two-dimensional transition metal chalcogenide material TaIrTe4, the thickness is 18nm; the material of the ferromagnetic functional layer 3 is two-dimensional ferromagnetic material Fe 3+x GaTe2, x=1.8, the thickness is 20nm; the thickness of the SiO2 layer 4 is 4nm; the material of the regulation layer 5 is two-dimensional ferroelectric material CuVP2S6, the thickness is 500nm; an electric field is applied to the left and right ends of the regulation layer 5, the field strength is 0.3kV / cm; the electrode sheet 6 is Ti / Pt, the thickness is 5 / 15nm, the electrode sheet is in strip shape and is provided with a plurality of electrode sheets, and the plurality of electrode sheets are distributed in a radial manner on the upper surface of the SiO2 layer.

[0071] The preparation method of the device is as shown in Embodiment 1.

[0072] The abnormal Hall effect, magnetization flip of the device prepared in this example, and the magnetization flip of the device prepared in Example 1 are shown in FIG. 1. Figure 4 and Figure 5 Approximately, in the case of applying a negative voltage, the coercivity is higher, the flip current density is larger, and the stability is higher. In the case of applying a positive voltage, the coercivity becomes smaller, the flip current density becomes smaller, and thus the power consumption is further reduced.

[0073] Comparative Example 1: No SiO2 layer

[0074] The difference from Example 1 described above is that the SiO2 layer is absent, and the other conditions are the same as in Example 1.

[0075] The device prepared in this comparative example is unstable and is prone to burning out.

[0076] Comparative Example 2: Thickness of the SiO2 layer

[0077] The difference from Example 1 described above is that the thickness of the SiO2 layer is 10 nm, and the other conditions are the same as in Example 1.

[0078] The abnormal Hall effect of the memory device prepared in this comparative example is shown in FIG. 2. Figure 6 As shown in FIG. 2, the coercivity in the positive and negative voltage curves does not change substantially, indicating that the thickness of the SiO2 layer is too thick and causes the regulation to fail.

[0079] Comparative Example 3: Thickness of the regulation layer CuVP2S6

[0080] The difference from Example 1 described above is that the thickness of the regulation layer CuVP2S6 is 80 nm, and the other conditions are the same as in Example 1.

[0081] The abnormal Hall effect of the memory device prepared in this comparative example is shown in FIG. 3. Figure 7 As shown in FIG. 3, when the thickness of CuVP2S6 is thinned, the coercivity and the saturated magnetoresistance regulation in the abnormal Hall resistance of Fe 3+x GaTe2 layer do not change substantially and are not suitable for regulation.

[0082] Comparative Example 4: Thickness of the ferromagnetic functional layer Fe 3+x GaTe2

[0083] The difference from Example 1 described above is that the thickness of the ferromagnetic functional layer Fe 3+x GaTe2 is 5 nm, and the other conditions are the same as in Example 1.

[0084] The abnormal Hall effect of the memory device prepared in this comparative example is shown in FIG. 4. Figure 8 As shown in FIG. 4, under the thickness in this comparative example, the perpendicular magnetic crystalline anisotropy of Fe 3+ x GaTe2 is poor, the coercivity is substantially lost, the residual magnetoresistance is substantially 0, the anti-interference ability is weakened, and the information storage is not conducive.

[0085] Comparative Example 5 Ferromagnetic functional layer Fe 3+x Thickness of GaTe2

[0086] The difference from Example 1 above is that the ferromagnetic functional layer Fe 3+x The thickness of GaTe2 is 25 nm, and the rest is the same as Example 1.

[0087] The abnormal Hall effect of the memory device prepared in this comparative example is as shown in Figure 9 At the thickness of this comparative example, Fe 3+ x The coercivity of GaTe2 is enhanced, the coercivity is basically increased to about 2000 Oe, the anti-interference ability is enhanced, and a larger current is required for flipping, which is not suitable for low-power consumption storage.

[0088] The above only describes the preferred embodiments of the present application and is not used to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory device with low power consumption and high write thermal stability factor, characterized by: The device comprises, from bottom to top, a substrate, a spin / orbit current generation layer, a ferromagnetic functional layer, a SiO2 layer, an electrode sheet and a regulation layer; the material of the spin / orbit current generation layer is two-dimensional transition metal chalcogenide material TaIrTe4, and the material of the ferromagnetic functional layer is two-dimensional ferromagnetic material Fe 3+ x GaTe2, x=0-2, the material of the regulation layer is two-dimensional ferroelectric material CuVP2S6, the electrode sheet is in strip shape and is provided with a plurality of electrode sheets, and the plurality of electrode sheets are distributed in a radial manner on the upper surface of the SiO2 layer; an electric field is applied to the left and right ends of the regulation layer, and the field strength is 0.1-10 kV / cm.

2. The memory device of claim 1, wherein: The substrate is SiO2 / Si substrate, and the thickness of the substrate is 0.2-5mm.

3. The memory device of claim 1, wherein: the low power write high thermal stability factor is a low power write high thermal stability factor (LPWHTSF) of 0.5 or less. The thickness of the spin / orbit current generating layer is 5-20nm.

4. The memory device of claim 1, wherein: the low power write high thermal stability factor is a low power write high thermal stability factor (LPWHTSF) of 0.5 or less. The thickness of the ferromagnetic functional layer is 8-20nm.

5. The memory device of claim 1, wherein: the low power write high thermal stability factor is a low power write high thermal stability factor (LPWHTSF). The thickness of the SiO2 layer is 0.1-5nm.

6. The memory device of claim 1, wherein: The thickness of the regulating layer is 200-500nm.

7. The memory device of claim 1, wherein: the low power write high thermal stability factor is a low power write high thermal stability factor. The electrode sheet is Ti / Pt, and the thickness is 5 / 15nm.

8. The memory device of claim 1, wherein: The substrate, the spin / orbit current generating layer and the ferromagnetic functional layer have the same size, and the size of the SiO2 layer is larger than that of the ferromagnetic functional layer, so that the outer periphery of the SiO2 layer extends out of the ferromagnetic functional layer; The length of the regulating layer is larger than that of the ferromagnetic functional layer, and the left end of the regulating layer is aligned with the left end of the ferromagnetic functional layer, and the right end of the regulating layer extends out of the SiO2 layer.

9. A method of producing a memory device having a low power consumption and a high write endurance factor as claimed in any one of claims 1 to 8, characterized in that: The method comprises the following steps: I. cleaning the substrate and blowing dry; II. preparing the spin / orbit current generating layer, the ferromagnetic functional layer and the SiO2 layer on the substrate in sequence; III. preparing the electrode sheet on the upper surface of the SiO2 layer by combining the photolithography and the magnetron sputtering process; IV. preparing the regulating layer above the electrode sheet.

10. The method of claim 9, wherein the method further comprises: depositing a first dielectric layer on the substrate; depositing a first conductive layer on the first dielectric layer; depositing a second dielectric layer on the first conductive layer; and depositing a second conductive layer on the second dielectric layer. The method for preparing the spin / orbit current generating layer, the ferromagnetic functional layer and the regulating layer is any one of the magnetron sputtering, the molecular beam epitaxy, the pulsed laser deposition, the physical vapor deposition, the chemical vapor deposition and the mechanical peeling; The SiO2 layer is prepared by the magnetron deposition method.

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