Three-dimensional memory device containing phosphorus-doped silicon oxide ion gettering structure and forming method thereof

Abstract

A three-dimensional memory device, the three-dimensional memory device comprising: a pair of alternating stacks of insulating layers and conductive layers, where the pair of alternating stacks are laterally spaced apart from each other by lateral isolation trenches; a memory opening extending vertically through a respective one of the pair of alternating stacks; a memory opening filling structure in a respective one of the memory openings and including a respective vertical stack of vertical semiconductor channels and memory elements; and a lateral isolation trench filling structure, wherein the lateral isolation trench filling structure is located in the lateral isolation trench. The phosphorus-doped silicon oxide portion is located within or on a sidewall of the lateral isolation trench at a stage of the insulating layer.

Description

[0001] Cross-references to related applications

[0002] This application claims the benefit of the entire contents of U.S. Nonprovisional Application No. 18 / 479,432, filed October 2, 2023, with the United States Patent and Trademark Office, entitled “THREE-DIMENSIONALMEMORY DEVICE CONTAINING PHOSPHORUS-DOPED SILICON OXIDE ION-GETTERING STRUCTURES AND METHODS OF FORMING THE SAME,” which is incorporated herein by reference for all purposes. Technical Field

[0003] This disclosure relates generally to the field of semiconductor devices, and more particularly to a three-dimensional memory device including a phosphorus-doped silicon oxide ion-removal structure surrounding a lateral isolation trench and a method for manufacturing the same. Background Technology

[0004] A three-dimensional vertical NAND string with one bit per cell was disclosed in an article by T. Endoh et al. entitled “Novel Ultra High Density Memory With AStacked-Surrounding Gate Transistor (S-SGT) Structured Cell”, IEDM Proceedings (2001), pp. 33-36. Summary of the Invention

[0005] According to one aspect of this disclosure, a three-dimensional memory device includes: a pair of alternating stacks of insulating and conductive layers, wherein the pair of alternating stacks are laterally spaced apart from each other by lateral isolation trenches; a memory opening extending vertically through a corresponding alternating stack in the pair of alternating stacks; a memory opening filling structure located in a corresponding memory opening and including a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; and a lateral isolation trench filling structure located in a lateral isolation trench. A phosphorus-doped silicon oxide portion is located within or on the sidewall of the lateral isolation trench at a stage of the insulating layer.

[0006] According to another aspect of this disclosure, a method for forming a three-dimensional memory device is provided. The method includes: forming two alternating stacks of an insulating layer and a conductive layer, wherein the two alternating stacks are laterally spaced apart from each other by a lateral isolation trench; forming a memory opening through each of the two alternating stacks; forming a memory opening-filled structure in the respective memory opening of a respective vertical stack including a respective vertical semiconductor channel and memory elements; forming a phosphorus-doped silicon oxide portion at a level of the insulating layer within or on the sidewall of the lateral isolation trench; and forming a lateral isolation trench-filled structure in the lateral isolation trench. Attached Figure Description

[0007] Figure 1 This is a schematic vertical cross-sectional view of a first exemplary structure for forming a memory die after alternating stacking of a barrier insulating layer, a source electrode material layer, and an insulating layer and a sacrificial material layer over a carrier substrate, according to a first embodiment of the present disclosure.

[0008] Figure 2 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of a stepped surface and an inverse stepped dielectric material portion, according to a first embodiment of the present disclosure.

[0009] Figure 3A This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the memory opening and the support opening, according to a first embodiment of the present disclosure.

[0010] Figure 3B yes Figure 3A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 3A The cutting plane of the vertical cross-section diagram.

[0011] Figure 4 This is a schematic vertical cross-sectional view of a first exemplary structure after the formation of the support column structure, according to a first embodiment of the present disclosure.

[0012] Figures 5A to 5D This is a vertical cross-sectional view of the memory opening sequence during the formation of the memory opening filling structure according to a first embodiment of the present disclosure.

[0013] Figure 6A This is a vertical cross-sectional view of a first exemplary structure after the formation of a memory opening filling structure, according to a first embodiment of the present disclosure.

[0014] Figure 6B yes Figure 6A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 6A The cutting plane of the vertical cross-section diagram.

[0015] Figure 7A This is a vertical cross-sectional view of a first exemplary structure after the formation of a transverse isolation trench, according to a first embodiment of the present disclosure.

[0016] Figure 7B yes Figure 7A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 7A The cutting plane of the vertical cross-section diagram.

[0017] Figure 8 This is a vertical cross-sectional view of a first exemplary structure after the formation of the source stage cavity according to a first embodiment of the present disclosure.

[0018] Figure 9 This is a vertical cross-sectional view of a first exemplary structure after the formation of the source contact layer according to a first embodiment of the present disclosure.

[0019] Figure 10 This is a vertical cross-sectional view of a first exemplary structure after the formation of the lateral extension cavity, according to a first embodiment of the present disclosure.

[0020] Figures 11A to 11D This is a sequential vertical cross-sectional view of the regions of a first exemplary structure during the formation of an external barrier dielectric layer and a conductive layer in each of the lateral extension cavities according to a first embodiment of the present disclosure.

[0021] Figure 12 This is a vertical cross-sectional view of a first exemplary structure after the formation of a conductive layer, according to a first embodiment of the present disclosure.

[0022] Figure 13 This is a vertical cross-sectional view of a first exemplary structure after the formation of an optional insulating liner layer and a phosphorus-doped silicate glass layer, according to a first embodiment of the present disclosure.

[0023] Figure 14 This is a vertical cross-sectional view of a first exemplary structure after forming an insulating liner and a phosphorus-doped silicate glass spacer in each transverse isolation trench according to a first embodiment of the present disclosure.

[0024] Figure 15 This is a vertical cross-sectional view of a first exemplary structure after the formation of a transverse isolation trench filling structure, according to a first embodiment of the present disclosure.

[0025] Figure 16A This is a vertical cross-sectional view of a first exemplary structure after various contact via structures have been formed, according to a first embodiment of the present disclosure.

[0026] Figure 16B yes Figure 16AThe top view of the first exemplary structure. Vertical plane A-A' is... Figure 16A The cutting plane of the vertical cross-section diagram.

[0027] Figure 17A This is a vertical cross-sectional view of a first exemplary structure after the formation of bit lines and bit line-level metal lines, according to a first embodiment of the present disclosure.

[0028] Figure 17B yes Figure 17A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 17A The cutting plane of the vertical cross-section diagram.

[0029] Figure 18 This is a vertical cross-sectional view of a first exemplary structure after forming a memory die, according to a first embodiment of the present disclosure.

[0030] Figure 19 It is a vertical cross-sectional view of a logic die according to the first embodiment of this disclosure.

[0031] Figure 20 This is a vertical cross-sectional view of a first exemplary structure after the bonding components of the memory die and logic die have been formed, according to a first embodiment of the present disclosure.

[0032] Figure 21 This is a vertical cross-sectional view of a first exemplary structure after the carrier substrate has been removed from the memory die, according to a first embodiment of the present disclosure.

[0033] Figure 22 It is a vertical cross-sectional view of a first alternative configuration of the first exemplary structure.

[0034] Figure 23 This is a vertical cross-sectional view of a first alternative configuration of a first exemplary structure following the alternating stacking of insulating and sacrificial material layers according to a first embodiment of the present disclosure.

[0035] Figure 24 This is a vertical cross-sectional view of a first alternative configuration of a first exemplary structure after forming a memory die, according to a first embodiment of the present disclosure.

[0036] Figure 25 This is a vertical cross-sectional view of a second alternative configuration of a first exemplary structure after the formation of an optional insulating liner layer and a phosphorus-doped silicate glass layer, according to a first embodiment of the present disclosure.

[0037] Figure 26 This is a vertical cross-sectional view of a second alternative configuration of a first exemplary structure after forming an insulating liner and a phosphorus-doped silicate glass filling structure in each transverse isolation trench according to a first embodiment of the present disclosure.

[0038] Figure 27A This is a vertical cross-sectional view of a second alternative configuration of a first exemplary structure after forming various contact via structures, according to a first embodiment of the present disclosure.

[0039] Figure 27B yes Figure 27A The top view of the first exemplary structure. Vertical plane A-A' is... Figure 27A The cutting plane of the vertical cross-section diagram.

[0040] Figure 28 This is a vertical cross-sectional view of a second alternative configuration of a first exemplary structure following the bonding of a memory die to a logic die, removal of a carrier substrate, and formation of back-side contact pads, according to a first embodiment of the present disclosure.

[0041] Figure 29 This is a vertical cross-sectional view of a third alternative configuration of a first exemplary structure according to a first embodiment of the present disclosure.

[0042] Figure 30A This is a vertical cross-sectional view of a second exemplary structure following the implantation of carbon atoms around a transverse isolation trench and in the upper portion of the contact-level dielectric layer, according to a second embodiment of the present disclosure.

[0043] Figure 30B yes Figure 30A An enlarged view of the area surrounding the transverse isolation trench and memory opening filling structure of the second exemplary structure.

[0044] Figure 30C Is Figure 30A An enlarged view of an alternative embodiment of the second exemplary structure following the processing steps.

[0045] Figure 31A This is a vertical cross-sectional view of a second exemplary structure following the implantation of phosphorus atoms around a transverse isolation trench and in the upper portion of the contact-level dielectric layer, according to a first embodiment of the present disclosure.

[0046] Figure 31B yes Figure 31A An enlarged view of the area surrounding the transverse isolation trench and memory opening filling structure of the second exemplary structure.

[0047] Figure 31C Is Figure 31A An enlarged view of an alternative embodiment of the second exemplary structure following the processing steps.

[0048] Figure 32A This is a vertical cross-sectional view of a second exemplary structure after the formation of the transverse isolation trench filling structure, according to a first embodiment of the present disclosure.

[0049] Figure 32B yes Figure 32A An enlarged view of the area surrounding the transverse isolation trench and memory opening filling structure of the second exemplary structure.

[0050] Figure 32C Is Figure 32A An enlarged view of an alternative embodiment of the second exemplary structure following the processing steps.

[0051] Figure 33A This is a vertical cross-sectional view of a second exemplary structure after various contact via structures have been formed, according to a first embodiment of the present disclosure.

[0052] Figure 33B yes Figure 33A The top view of the second exemplary structure. Vertical plane A-A' is... Figure 33A The cutting plane of the vertical cross-section diagram.

[0053] Figure 34 This is a vertical cross-sectional view of a second exemplary structure according to a first embodiment of the present disclosure, after bonding the memory die to the logic die, removing the carrier substrate, and forming the back-side contact pads.

[0054] Figure 35 This is a vertical cross-sectional view of an alternative embodiment of the second exemplary structure. Detailed Implementation

[0055] As discussed above, embodiments of this disclosure relate to three-dimensional semiconductor devices and methods of manufacturing the same, the three-dimensional semiconductor devices including phosphorus-doped or phosphorus and carbon-doped silicon oxide ion-removal structures surrounding lateral isolation trenches, various aspects of which are described below. Embodiments of this disclosure can be used to form various structures including multi-level memory structures, non-limiting examples of which include semiconductor devices, such as three-dimensional memory array devices including multiple memory strings.

[0056] The accompanying drawings are not to scale. Multiple instances of an element may be reproduced where only a single instance is illustrated, unless otherwise explicitly described or clearly indicated that a reproduction of the element does not exist. Ordinal numbers such as “first,” “second,” and “third” are used only to identify similar elements, and different ordinal numbers may be used in the specification and claims of this disclosure. The term “at least one” element refers to all possibilities, including the possibility of a single element and the possibility of multiple elements.

[0057] Like reference numerals denote the same or similar elements. Unless otherwise specified, elements with the same reference numerals are considered to have the same composition and the same function. Unless otherwise specified, “contact” between elements means direct contact between elements providing an edge or surface shared by these elements. If two or more elements are not in direct contact with each other or are not in direct contact with each other, the two elements are “separated” from each other or “separated” from each other. As used herein, an element located “on” a second element may be located on the outer side of the surface of the second element or on the inner side of the second element. As used herein, if there is physical contact between the surface of an element and the surface of a second element, the element is “directly” located “on” the second element. As used herein, if there is a conductive path consisting of at least one conductive material between an element and a second element, the element is “electrically connected” to the second element. As used herein, a “prototype” structure or a “process” structure refers to a transient structure whose shape or composition is subsequently modified.

[0058] As used herein, a “layer” refers to a portion of material comprising a region of thickness. A layer may extend throughout the entire underlying or overlying structure, or its extent may be less than that of the underlying or overlying structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, and may include one or more layers, or may have one or more layers on, above, and / or below it.

[0059] Typically, a semiconductor die or semiconductor package can include a memory chip. Each semiconductor package contains one or more dies (e.g., one, two, or four). A die is the smallest unit capable of independently executing commands or reporting status. Each die contains one or more planes (typically one or two). Despite some limitations, the same concurrent operations can be performed on each plane. Each plane contains multiple blocks, which are the smallest units that can be erased in a single erase operation. Each block contains multiple pages, which are the smallest programmable units, i.e., the smallest units on which read operations can be performed.

[0060] As used in this article, "semiconductor material" refers to a material with an electrical conductivity of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 5 Materials in the S / m range. As used herein, "semiconductor material" refers to a material in which the electrical conductivity is in the absence of electrical dopants and is 1.0 × 10⁻⁶. -5Materials with electrical conductivity ranging from S / m to 1.0 S / m, and which, after appropriate doping with an electrical dopant, can produce conductivity ranging from 1.0 S / m to 1.0 × 10⁻⁶. 7 Doped materials in the S / m range. As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band within the band structure, or an n-type dopant that adds electrons to the conduction band within the band structure. As used herein, “conductive material” refers to a material with a conductivity greater than 1.0 × 10⁻⁶. 5 Materials with a conductivity of S / m. As used herein, "insulating material" or "dielectric material" refers to a conductivity less than 1.0 × 10⁻⁶. -5 Materials with a S / m ratio. As used herein, "heavily doped semiconductor material" refers to a semiconductor material doped with an electrically conductive agent at a sufficiently high atomic concentration to become a conductive material, which is formed as a crystalline material or transformed into a crystalline material through an annealing process (e.g., from an initial amorphous state), i.e., providing a value greater than 1.0 × 10⁻⁶. 5 The conductivity is S / m. "Doped semiconductor material" can be a heavily doped semiconductor material, or it can be a semiconductor material comprising electrically dopants (i.e., p-type dopants and / or n-type dopants) at a concentration of 1.0 × 10⁻⁶. -5 S / m to 1.0×10 7 Conductivity in the S / m range. "Intrinsic semiconductor material" refers to a semiconductor material that is not doped with an electrically conductive agent. Therefore, a semiconductor material can be semiconductor or conductive, and can be intrinsic or doped. A doped semiconductor material can be semiconductor or conductive, depending on the atomic concentration of the electrically conductive agent therein. As used herein, "metallic material" refers to a conductive material that includes at least one metallic element. All conductivity measurements were performed under standard conditions.

[0061] refer to Figure 1 This illustrates a first exemplary structure according to a first embodiment of the present disclosure. The first exemplary structure includes a carrier substrate 9, which may be a semiconductor substrate or a conductive substrate. For example, the carrier substrate 9 may include a commercially available silicon wafer. Alternatively, the carrier substrate 9 may include any material that can be selectively removed relative to the insulating layer 32 and the dielectric material portion to be subsequently formed.

[0062] An insulating material layer may be formed on the top surface of the carrier substrate 9. This insulating material layer may subsequently be used as a barrier layer for processes removing the carrier substrate 9, and is referred to herein as barrier insulating layer 106, or back-side pad dielectric layer. If a polishing process, such as chemical mechanical polishing, is subsequently used to remove the carrier substrate 9, barrier insulating layer 106 may be used as a polishing barrier layer. If an etching process, such as wet etching, is subsequently used to remove the carrier substrate 9, barrier insulating layer 106 may be used as an etching barrier layer. In one embodiment, barrier insulating layer 106 comprises a dielectric material, such as undoped silicate glass, doped silicate glass, or silicon nitride. The thickness of barrier insulating layer 106 may range from 50 nm to 600 nm, such as 100 nm to 300 nm, but smaller and larger thicknesses are also possible.

[0063] During the process, the source level material layer 110' may be formed over the barrier insulating layer 106. The source level material layer 110' may include various layers subsequently modified to form the source level material layer. During formation, the source level material layer includes a source contact layer serving as the common source region of the vertical field-effect transistor in a three-dimensional memory device. In one embodiment, the source level material layer 110' may include, from bottom to top, a lower source level semiconductor layer 112, an optional lower sacrificial pad (not shown), a source level sacrificial layer 104, an optional upper sacrificial pad (not shown), and an upper source level semiconductor layer 116.

[0064] The lower source semiconductor layer 112 and the upper source semiconductor layer 116 may comprise doped semiconductor materials, such as doped polycrystalline silicon or doped amorphous silicon. The conductivity type of the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may be opposite to the conductivity of the vertical semiconductor channel to be formed subsequently. For example, if the vertical semiconductor channel to be formed subsequently has a first conductivity type of doping, then the lower source semiconductor layer 112 and the upper source semiconductor layer 116 have a second conductivity type of doping opposite to the first conductivity type. The thickness of each of the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may range from 10 nm to 300 nm, such as 20 nm to 150 nm, but smaller and larger thicknesses are also possible.

[0065] In one embodiment, the first conductivity type may be p-type, and the second conductivity type may be n-type. In one embodiment, the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may include arsenic or phosphorus atoms as n-type dopants. The atomic concentration of arsenic or phosphorus atoms in the lower source semiconductor layer 112 and the upper source semiconductor layer 116 may be independently between 1.0 × 10⁻⁶. 18 / cm 3Up to 1.0×10 20 / cm 3 Within the range, such as 5.0×10 18 / cm 3 Up to 5.0×10 20 / cm 3 However, smaller and larger atomic concentrations can also be used.

[0066] The source-level sacrificial layer 104 includes a sacrificial material that can be selectively removed relative to the lower sacrificial pad (or relative to the lower source-level semiconductor layer 112) and the upper sacrificial pad (or relative to the upper source-level semiconductor layer 116). In one embodiment, the source-level sacrificial layer 104 may include a semiconductor material, such as undoped amorphous silicon or a silicon-germanium alloy with a germanium atomic concentration greater than 20%. The thickness of the source-level sacrificial layer 104 may be in the range of 30 nm to 400 nm, such as 60 nm to 200 nm, but smaller and larger thicknesses may also be used. The lower sacrificial pad (if present) and the upper sacrificial pad (if present) include materials that can be used as etch-stopping materials during the removal of the source-level sacrificial layer 104. For example, the lower and upper sacrificial pads may include silicon oxide, silicon nitride, and / or dielectric metal oxides. In one embodiment, each of the lower and upper sacrificial pads may include a silicon oxide layer having a thickness in the range of 2 nm to 30 nm, but smaller and larger thicknesses may also be used.

[0067] Alternating stacks of the first and second material layers can be formed over the process source level material layer 110'. In an alternative embodiment, the process source level material layer 110' and the barrier insulating layer 106 can be omitted, and the alternating stacks are formed directly on the surface of the carrier substrate 9. (See below for more details.) Figure 20 In another alternative embodiment described, the peripheral circuitry is formed on the same substrate as the alternating stack. For example, the peripheral circuitry may include word line driver regions, bit line driver regions, sense amplifier regions, input / output buffers, etc. In this alternative embodiment, a separate logic die containing the peripheral circuitry described below with respect to FIG16 may be omitted. In this alternative embodiment, the alternating stack may be deposited on the process source material layer 110', or the process source material layer 110' may be omitted, and the alternating stack may be deposited on the barrier insulating layer 106.

[0068] In an alternating stack, the first material layer may be an insulating layer, and the second material layer may be a spacer material layer. In one embodiment, the spacer material layer may include a sacrificial material layer 42. In this case, an alternating stack (32, 42) of insulating layer 32 and sacrificial material layer 42 may be formed on the process source level material layer 110'. Insulating layer 32 comprises an insulating material such as undoped silicate glass or doped silicate glass, and sacrificial material layer 42 comprises a sacrificial material such as silicon nitride or a silicon-germanium alloy. In one embodiment, insulating layer 32 (i.e., the first material layer) may include a silicon oxide layer, and sacrificial material layer 42 (i.e., the second material layer) may include a silicon nitride layer. The alternating stack (32, 42) may include multiple repetitions of a unit layer stack comprising insulating layer 32 and sacrificial material layer 42. The total number of repetitions of the unit layer stack within the alternating stack (32, 42) may be, for example, in the range of 8 to 1,024, such as 32 to 256, but smaller and larger repetitions may also be used. Hereinafter, the topmost insulating layer in the insulating layer 32 will be referred to as the topmost insulating layer 32T. The bottommost insulating layer in the insulating layer 32 is the insulating layer 32 closest to the carrier substrate 9, and this insulating layer will be referred to herein as the bottommost insulating layer 32B.

[0069] Each insulating layer in the insulating layers 32, except for the topmost insulating layer 32T, may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. Each sacrificial material layer in the sacrificial material layers 42 may have a thickness ranging from 20 nm to 100 nm, such as 30 nm to 60 nm, but smaller and larger thicknesses are also possible. In one embodiment, the topmost insulating layer 32T may have a thickness approximately half that of the other insulating layers 32.

[0070] The first exemplary structure includes a memory array region 100 and a contact region 300, in which a three-dimensional array of memory elements will subsequently be formed, and in which a layer contact via structure for contact word lines will subsequently be formed.

[0071] refer to Figure 2 A stepped surface is formed in the contact area 300. As used herein, a “stepped surface” refers to a set of surfaces comprising at least two horizontal surfaces and at least two vertical surfaces, such that each horizontal surface is adjacent to a first vertical surface extending upward from a first edge of the horizontal surface and to a second vertical surface extending downward from a second edge of the horizontal surface. A stepped cavity is formed within the volume from which portions of the alternating stacks (32, 42) are removed by forming the stepped surface. A “stepped cavity” refers to a cavity having a stepped surface.

[0072] The stepped cavity can have various stepped surfaces, such that the horizontal cross-sectional shape of the stepped cavity changes stepwise according to the vertical distance from the top surface of the source stage material layer 110' during the process. In one embodiment, the stepped cavity can be formed by repeatedly performing a set of processing steps. This set of processing steps may include, for example, a first type of etching process and a second type of etching process, the first type of etching process vertically increasing the depth of the cavity by one or more stages, and the second type of etching process laterally extending the area vertically etched in a subsequent first type of etching process. As used herein, a “stage” comprising alternating multiple structures is defined as the relative position of a pair of first and second material layers within the structure.

[0073] Each sacrificial material layer 42 within the alternating stack (32,42), except for the topmost sacrificial material layer 42, extends laterally further than any overlying sacrificial material layer 42 within the alternating stack (32,42) in the stepped region. The stepped surface of the alternating stack (32,42) extends continuously from the bottommost layer (such as the bottommost insulating layer 32B) within the alternating stack (32,42) to the topmost layer (such as the topmost insulating layer 32T) within the alternating stack (32,42).

[0074] A reverse-stepped dielectric material portion 65 (i.e., an insulating-filling portion) can be formed in a stepped cavity by depositing a dielectric material in the stepped cavity. For example, a dielectric material such as silicon oxide can be deposited in the stepped cavity. Excess portions of the deposited dielectric material can be removed, for example, from the top surface of the topmost insulating layer 32T by chemical mechanical planarization (CMP). The remaining portion of the deposited dielectric material filling the stepped cavity constitutes the reverse-stepped dielectric material portion 65. As used herein, a “reverse-stepped” element refers to an element having a stepped surface and a horizontal cross-sectional area that monotonically increases with the vertical distance from the top surface of the substrate on which the element is situated. If silicon oxide is used for the reverse-stepped dielectric material portion 65, the silicon oxide of the reverse-stepped dielectric material portion 65 may or may not be doped with dopants such as B, P, and / or F.

[0075] Optionally, a drain selection stage isolation structure (not shown) may be formed through a subset of the topmost insulating layer 32T and the sacrificial material layer 42 located at the drain selection stage. For example, the drain selection stage isolation structure may be formed by forming a drain selection stage lateral isolation trench and filling the drain selection stage lateral isolation trench with a dielectric material such as silicon oxide. Excess dielectric material may be removed from above the top surface of the topmost insulating layer 32T.

[0076] refer to Figure 3AReferring to Figure 3C, an etch mask layer (not shown) can be formed on the alternating stack (32, 42), and this etch mask layer can be photolithographically patterned to form various openings therein. An anisotropic etching process can be performed to transfer the pattern of the openings in the etch mask layer through the alternating stack (32, 42). Various openings can be formed through the alternating stack (32, 42). The various openings may include memory openings 49 formed in the memory array region 100 and support openings 19 formed in the contact region 300. Each of the memory openings 49 and support openings 19 may extend vertically through the alternating stack (32, 42) and into the in-process source level material layer 110'. In one embodiment, the bottom surfaces of the memory openings 49 and support openings 19 may be formed within the lower source level semiconductor layer 112 or at the interface between the lower source level semiconductor layer and the barrier insulating layer 106.

[0077] The support opening 19 may have a diameter in the range of 60 nm to 400 nm (e.g., 120 nm to 300 nm), but may employ smaller and larger thicknesses. The memory opening 49 may have a diameter in the range of 60 nm to 400 nm (e.g., 120 nm to 300 nm), but may employ smaller and larger thicknesses.

[0078] In one embodiment, the memory array region 100 may be laterally spaced from the contact region 300 along a first horizontal direction hd1. The memory openings 49 may include rows of memory openings 49 arranged along the first horizontal direction hd1 and laterally spaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd2. Multiple clusters of memory openings 49 may be formed in the memory array region 100, each cluster comprising a corresponding two-dimensional periodic array of memory openings 49. The clusters of memory openings 49 may be laterally spaced along the second horizontal direction hd2.

[0079] refer to Figure 4Optional etch-stop pads (not shown) and sacrificial filler materials (not shown) may be deposited in the memory opening 49 and the support opening. Optional etch-stop pads (if present) comprise a thin dielectric material layer containing silicon oxide, silicon nitride, or a dielectric metal oxide and having a thickness in the range of 1 nm to 6 nm. The sacrificial filler material may comprise a carbon-based material (such as amorphous carbon or diamond-like carbon), a semiconductor material (such as amorphous silicon or polycrystalline silicon), a dielectric filler material (such as borosilicate glass or organosilicon glass), or a polymer material. Excess sacrificial filler material may be removed from above a horizontal plane comprising the alternating stack (32, 42) by a planarization process (such as an etch-back process). The filling of the remaining portions of the memory opening 49 and the support opening 19 by the sacrificial filler material constitutes a sacrificial memory opening filling structure (not shown) and a sacrificial support opening filling structure (not shown).

[0080] A photoresist layer (not shown) can be applied to the alternating stacks (32, 42) and the inverse step dielectric material portions 65, and can be photolithographically patterned to cover the memory array region 100 but not the contact region 300. Portions of the optional etch-stop pads and the sacrificial support opening-fill structure in the contact region 300 can be selectively removed relative to the materials of the inverse step dielectric material portions 65 and the alternating stacks (32, 42). For example, etching or ashing processes can be used to remove the portions of the optional etch-stop pads and the sacrificial support opening-fill structure in the contact region 300. The photoresist layer can then be removed.

[0081] A dielectric filler material (such as silicon oxide) can be deposited in the support opening 19 using a conformal deposition process. Excess portions of the dielectric filler material can be removed, for example, from the top surface of the topmost insulating layer 32T using a recess etching process. The filling of each portion of the corresponding support opening 19 with dielectric filler material constitutes a support pillar structure 20, which can be used to provide structural support to the insulating layer 32 and the inverse stepped dielectric material portion 65 during the replacement of the sacrificial material layer 42 with a conductive layer.

[0082] Subsequently, portions of the optional etch-stop pads and the sacrificial memory opening fill structure in the memory array region 100 can be selectively removed relative to the inverse stepped dielectric material portion 65 and the alternating stacked (32, 42) materials. For example, etching or ashing processes can be used to remove portions of the optional etch-stop pads and the sacrificial memory opening fill structure in the memory array region 100. A void is formed in the volume of the memory opening 49.

[0083] Figures 5A to 5DIt is a sequential vertical cross-sectional view of a memory opening 49 during the formation of a NAND string (e.g., a dummy NAND string or a data storage NAND string) according to an embodiment of the present disclosure, the NAND string being referred to below as a "memory opening filling structure" 58.

[0084] refer to Figure 5A Examples are shown in Figure 4 The memory opening 49 after the processing steps.

[0085] refer to Figure 5B A layer stack including a memory material layer 54 can be conformally deposited. In an exemplary example, the layer stack may include an optional barrier dielectric layer 52, a memory material layer 54, and an optional dielectric pad 56. The memory material layer 54 includes a memory material, i.e., a material in which data bits can be stored. The memory material layer 54 may include a charge storage material (such as silicon nitride). Where the memory material layer 54 includes a charge storage material, the optional dielectric pad 56 may include a tunneling dielectric layer.

[0086] The semiconductor channel material layer 60L can be deposited on top of the layer stack (52, 54, 56) by performing a conformal deposition process. If the semiconductor channel material layer 60L is doped, it can have a first conductivity type of doping, which can be p-type or n-type. In one embodiment, the first semiconductor material comprises a first doped silicon material having a first conductivity type of doping. In an exemplary example, the atomic concentration of the first conductivity type of dopant in the semiconductor channel material layer 60L can be 1.0 × 10⁻⁶. 13 / cm 3 Up to 3.0×10 17 / cm 3 Within the range, such as 1.0 × 10 14 / cm 3 Up to 3.0×10 16 / cm 3 However, smaller and larger atomic concentrations can also be used. A dielectric core layer 62L, comprising dielectric filling material, can be deposited in the remaining volume of the memory opening 49 and over the alternating stack (32,42).

[0087] refer to Figure 5C The dielectric core layer 62L may be vertically recessed, such that each remaining portion of the dielectric core layer 62L has a top surface at or near a horizontal plane including the bottom surface of the topmost insulating layer 32T. Each remaining portion of the dielectric core layer 62L constitutes a dielectric core 62.

[0088] refer to Figure 5DA doped semiconductor material having a second conductivity type can be deposited in each recessed region above the dielectric core 62. The second conductivity type is the opposite of the first conductivity type. For example, if the first conductivity type is p-type, then the second conductivity type is n-type, and vice versa. The dopant concentration in the deposited semiconductor material can be 5.0 × 10⁻⁶. 18 / cm 3 Up to 2.0×10 21 / cm 3 Within a certain range, but smaller or larger dopant concentrations can also be used. The doped semiconductor material can be, for example, doped polysilicon.

[0089] Excess portions of the deposited semiconductor material doped with a second conductivity type and the horizontal portion of the semiconductor channel material layer 60L can be removed, for example, from a horizontal plane above the top surface, including the top insulating layer 32T, using chemical mechanical planarization (CMP) or recess etching processes. Each remaining portion of the doped semiconductor material with the second conductivity type constitutes a drain region 63. Each remaining portion of the semiconductor channel material layer 60L (which has doping with a first conductivity type) constitutes a vertical semiconductor channel 60.

[0090] Each portion of the layer stack, including the memory material layer 54 retained in the respective memory opening 49, constitutes a memory film 50. In one embodiment, the memory film 50 may include an optional barrier dielectric layer 52, the memory material layer 54, and an optional dielectric pad 56. Each adjacent combination of the memory film 50 and the vertical semiconductor channel 60 constitutes a memory stack structure 55. Each combination of the memory stack structure 55, the dielectric core 62, and the drain region 63 within the memory opening 49 constitutes a memory opening fill structure 58. Each memory opening fill structure 58 includes a respective vertical stack of memory elements, which may include a portion of the memory material layer 54 located at the level of the sacrificial material layer 42.

[0091] refer to Figure 6A and Figure 6B This illustrates a first exemplary structure after a memory opening fill structure 58 is formed within a memory opening 49. Each memory opening fill structure in the memory opening fill structure 58 may include a memory film 50 and a vertical semiconductor channel 60. In summary, it may be a combination of alternating stacks (32, 42) of insulating layers 32 and sacrificial material layers 42, a memory opening 49 extending vertically through the alternating stacks (32, 42), and a memory opening fill structure 58 located within the memory opening 49. Each memory opening fill structure in the memory opening fill structure 58 includes a corresponding vertical stack of memory elements, such as a portion of a memory material layer 54 located at a level of the sacrificial material layer 42.

[0092] refer to Figure 7A and Figure 7B A dielectric material, such as undoped or doped silicate glass, can be deposited over the alternating stacks (32,42) to form a contact-level dielectric layer 80. The thickness of the contact-level dielectric layer 80 can be in the range of 100 nm to 600 nm, such as 200 nm to 400 nm, but smaller and larger thicknesses are also possible.

[0093] A photoresist layer (not shown) may be applied to the contact-level dielectric layer 80 and may be photolithographically patterned to form elongated openings extending laterally along a first horizontal direction hd1 between adjacent clusters of the memory aperture filling structure 58. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80, the alternating stacks (32, 42), the inverse stepped dielectric material portion 65, and the in-process source level material layer 110'. Lateral isolation trenches 79 extending laterally along the first horizontal direction hd1 may be formed through the alternating stacks (32, 42), the inverse stepped dielectric material portion 65, the contact-level dielectric layer 80, and the in-process source level material layer 110'. Each lateral isolation trench 79 may include a corresponding pair of longitudinal sidewalls parallel to the first horizontal direction hd1 and extending vertically from the barrier insulating layer 106 to the top surface of the contact-level dielectric layer 80. The top surface of the insulating layer 106 is prevented from being physically exposed beneath each lateral isolation trench 79. The lateral isolation trenches 79 isolate adjacent memory blocks from each other along the second horizontal direction hd2. The photoresist layer can then be removed, for example, by ashing.

[0094] refer to Figure 8 An etchant can be introduced into the lateral isolation trench 79 by performing an isotropic etching process. This etchant selectively etches the material of the source sacrificial layer 104 relative to the alternating stacks (32,42), contact-level dielectric layer 80, inverse step dielectric material portion 65, lower source-level semiconductor layer 112, upper source-level semiconductor layer 116, upper sacrificial pad 105 (if present), and lower sacrificial pad 103 (if present). For example, if the source sacrificial layer 104 comprises undoped amorphous silicon or a silicon-germanium alloy, a wet etching process using thermal trimethyl-2-hydroxyethyl ammonium hydroxide (“thermal TMY”) or tetramethyl ammonium hydroxide (TMAH) can be used to selectively remove the source sacrificial layer 104 relative to the alternating stacks (32,42), contact-level dielectric layer 80, inverse step dielectric material portion 65, lower source-level semiconductor layer 112, and upper source-level semiconductor layer 116. The source cavity 109 is formed in the volume from which the source level sacrificial layer 104 is removed.

[0095] Wet etching chemicals such as thermal TMY and TMAH are selective for doped semiconductor materials, such as p-doped and / or n-doped semiconductor materials of the upper source semiconductor layer 116 and the lower source semiconductor layer 112. Therefore, using selective wet etching chemicals (such as thermal TMY and TMAH) for the wet etching process forming the source cavity 109 provides a large process window to resist variations in etching depth during the formation of the lateral isolation trench 79. Specifically, even if the sidewalls of the upper source semiconductor layer 116 are physically exposed, or even if the surface of the lower source semiconductor layer 112 is physically exposed during the formation of the source cavity 109, the incidental etching of the upper source semiconductor layer 116 and / or the lower source semiconductor layer 112 is minimal, and structural changes to the first exemplary structure caused by accidental physical exposure of the surfaces of the upper source semiconductor layer 116 and / or the lower source semiconductor layer 112 during the manufacturing steps do not lead to device failure. Each memory opening fill structure in memory opening fill structure 58 is physically exposed to source cavity 109. Specifically, each memory opening fill structure in memory opening fill structure 58 includes sidewalls and is physically exposed to source cavity 109.

[0096] A series of isotropic etchants (such as wet etchants) can be applied to the physically exposed portions of the memory film 50 to sequentially etch the various component layers of the memory film 50 from the outside in, and physically expose the cylindrical surface of the vertical semiconductor channel 60 at the stage of the source cavity 109. The upper sacrificial pad 105 (if present) and the lower sacrificial pad 103 (if present) can be incidentally etched during the removal of the portion of the memory film 50 located at the stage of the source cavity 109. The volume of the source cavity 109 can be increased by removing the portions of the memory film 50 at the stages of the source cavity 109 and the upper and lower sacrificial pads. The top surface of the lower source stage semiconductor layer 112 and the bottom surface of the upper source stage semiconductor layer 116 can be physically exposed to the source cavity 109. The source cavity 109 is formed by selectively and isotropically etching the bottom portion of each memory film in the source sacrificial layer 104 and memory film 50 relative to at least one source semiconductor layer (such as the lower source semiconductor layer 112 and the upper source semiconductor layer 116) and the vertical semiconductor channel 60.

[0097] refer to Figure 9A doped semiconductor material of a second conductivity type can be deposited on the physically exposed semiconductor surface surrounding the source cavity 109. The physically exposed semiconductor surface includes the bottom portion of the outer sidewall of the vertical semiconductor channel 60 and a horizontal surface of at least one source semiconductor layer (such as the bottom surface of the upper source semiconductor layer 116 and / or the top surface of the lower source semiconductor layer 112). For example, the physically exposed semiconductor surface may include the bottom portion of the outer sidewall of the vertical semiconductor channel 60, the top horizontal surface of the lower source semiconductor layer 112, and the bottom surface of the upper source semiconductor layer 116.

[0098] In one embodiment, a doped semiconductor material of a second conductivity type can be deposited on a physically exposed semiconductor surface surrounding a source cavity 109 using a selective semiconductor deposition process. During the selective semiconductor deposition process, a semiconductor precursor gas, an etchant gas, and a dopant gas can be simultaneously introduced into a process chamber including the first exemplary structure. For example, the semiconductor precursor gas may include silane, dichlorosilane, or dichlorosilane, the etchant gas may include gaseous hydrogen chloride, and the dopant gas may include hydrides of dopant atoms, such as phosphine, arsine, antimony, or diborane. In this case, the selective semiconductor deposition process grows a doped semiconductor material of a second conductivity type from the physically exposed semiconductor surface surrounding the source cavity 109. The deposited doped semiconductor material forms a source contact layer 114 that contacts the sidewalls of the vertical semiconductor channel 60. The atomic concentration of the dopant of the second conductivity type in the deposited semiconductor material can be 1.0 × 10⁻⁶. 20 / cm 3 Up to 2.0×10 21 / cm 3 Within the range, such as 2.0 × 10 20 / cm 3 Up to 8.0×10 20 / cm 3 The initially formed source contact layer 114 may consist substantially of semiconductor atoms and dopant atoms of a second conductivity type. Alternatively, at least one non-selective doping semiconductor material deposition process may be used to form the source contact layer 114. Optionally, one or more etch-back processes may be combined with multiple selective or non-selective deposition processes to provide a seamless and / or void-free source contact layer 114.

[0099] The duration of the selective semiconductor deposition process can be selected such that the source cavity 109 is filled with the source contact layer 114. In one embodiment, the source contact layer 114 can be formed by selectively depositing a doped semiconductor material having a second conductivity type from the semiconductor surface surrounding the source cavity 109. In one embodiment, the doped semiconductor material may include doped polysilicon. Therefore, the source level sacrificial layer 104 can be replaced by the source contact layer 114. A stack of layers including a lower source level semiconductor layer 112, a source contact layer 114, and an upper source level semiconductor layer 116 constitutes a source layer 110, which replaces the source level material layer 110' during the process. The source layer 110 contacts the end portion of each vertical semiconductor channel 60.

[0100] refer to Figure 10 An isotropic etching process can be performed to selectively remove the sacrificial material layer 42 relative to the insulating layer 32, the barrier insulating layer 106, the memory opening-fill structure 58, the sacrificial etch stop pad 71, and the source layer 110. A lateral extension cavity 43 can be formed in the volume from which the sacrificial material layer 42 is removed. Sidewall surface segments of the memory opening-fill structure 58 can be physically exposed to the lateral extension cavity 43. In an exemplary example, if the sacrificial material layer 42 comprises silicon nitride, the isotropic etching process may include a wet etching process employing hot phosphoric acid, which is a process in which a first exemplary structure is immersed in phosphoric acid at or near the boiling point of phosphoric acid. Suitable cleaning processes can be performed as needed. In summary, the lateral extension cavity 43 can be formed by selectively removing the sacrificial material layer 42 relative to the insulating layer 32 and the memory opening-fill structure 58.

[0101] Figures 11A to 11D This is a sequential vertical cross-sectional view of a region of a first exemplary structure during the formation of an external barrier dielectric layer 44 and a conductive layer 46 in each of the lateral extension cavities 43 according to an embodiment of the present disclosure.

[0102] refer to Figure 11A Examples are shown in Figure 10 The area of ​​the first exemplary structure following the processing steps. Each memory opening fills the cylindrical outer surface segment of structure 58 and the horizontally extending surface of insulating layer 32, which can be exposed to the lateral extending cavity 43.

[0103] refer to Figure 11BAn external barrier dielectric layer 44 is deposited in the laterally extended cavity 43. The external barrier dielectric layer 44 comprises a dielectric metal oxide material (such as alumina) and / or is substantially composed of such a dielectric metal oxide material. The external barrier dielectric layer 44 can be deposited using a conformal deposition process and can always have a uniform thickness. In one embodiment, an atomic layer deposition (ALD) process or a chemical vapor deposition (CVD) process can be used to deposit the external barrier dielectric layer 44. The external barrier dielectric layer 44 can have a thickness in the range of 1 nm to 10 nm (such as 2 nm to 5 nm), but smaller or larger thicknesses are also possible. The external barrier dielectric layer 44 can contact the cylindrical surface segment of the memory opening fill structure 58.

[0104] refer to Figure 11C A diffusion barrier layer 46A containing conductive tungsten nitride can be conformally deposited on the surface that physically exposes the external dielectric layer 44. The tungsten nitride-containing diffusion barrier layer 46A may consist substantially of tungsten nitride, or may contain doped tungsten nitride, such as boron-doped tungsten nitride (e.g., boron tungsten nitride).

[0105] In one embodiment, the tungsten nitride-containing diffusion barrier layer 46A may comprise stoichiometric tungsten nitride and / or may consist substantially of stoichiometric tungsten nitride, wherein the atomic ratio between tungsten atoms and nitrogen atoms is 1:1. Alternatively, the tungsten nitride-containing diffusion barrier layer 46A may comprise other atoms, such as boron atoms in an atomic percentage ranging from 1% to 40% (e.g., 5% to 33%), but smaller and larger atomic percentages are also possible. The tungsten nitride-containing diffusion barrier layer 46A may be deposited by a conformal deposition process (e.g., atomic layer deposition or chemical vapor deposition). The thickness of the tungsten nitride-containing diffusion barrier layer 46A may range from 1 nm to 8 nm, such as 2 nm to 5 nm, but smaller or larger thicknesses are also possible.

[0106] refer to Figure 11D and Figure 12 A metal layer 46B comprising an atomic percentage greater than 95%, and / or greater than 99%, and / or greater than 99.8% of a metal can be deposited in the remaining volume of the lateral extension cavity 43. In one embodiment, the metal may include tungsten, molybdenum, ruthenium, or cobalt. The metal layer 46B can be deposited by a conformal deposition process (such as chemical vapor deposition) and can fill the remaining volume of the lateral extension cavity 43. In one embodiment, the metal layer 46B comprises tungsten deposited on a tungsten nitride-containing diffusion barrier layer 46A by a two-step process, which includes a first B₂H₆ or silane (SiH₄) gas pretreatment step to form a silicon- or boron-containing nucleation layer, followed by a second step using tungsten hexafluoride or another suitable tungsten precursor to deposit the tungsten layer. The tungsten precursor gas may also optionally be provided during the first step.

[0107] An anisotropic etching process can be performed to remove portions of the metal layer 46B and the tungsten nitride diffusion barrier layer 46A, as well as optionally the external barrier dielectric layer 44, from within the volume of the lateral isolation trench 79 and above the contact-level dielectric layer 80. Each consecutive remaining portion of the combination of the metal layer 46B and the tungsten nitride diffusion barrier layer 46A within the volume of the respective lateral extension cavity 43 constitutes a conductive layer 46. Each conductive layer 46 is spaced apart from the memory opening filling structure 58, the corresponding overlying insulating layer in the insulating layer 32, and the corresponding underlying insulating layer in the insulating layer 32 by the external barrier dielectric layer 44. This forms an alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46. The alternating stack (32, 46) of the insulating layer 32 and the conductive layer 46 can be laterally spaced apart from each other along the second horizontal direction hd2 via the lateral isolation trench 79.

[0108] In summary, multiple alternating stacks (32, 46) of insulating layer 32 and conductive layer 46 may be formed over at least one semiconductor material layer (such as source level material layer 110). The multiple alternating stacks (32, 46) are laterally spaced from each other by lateral isolation trenches 79. A memory opening 49 extends vertically through a corresponding alternating stack (32, 46). A memory opening-filling structure 58, comprising a corresponding vertical stack of memory elements, is located within the memory opening 49.

[0109] refer to Figure 13 Optional insulating liner layer 73L and phosphorus-doped silicate glass layer (i.e., phosphorus-doped silicon oxide layer, such as phosphosilicate glass (PSG)) 74L may be formed in the lateral isolation trench 79 and above the contact-level dielectric layer 80. The insulating liner layer 73L (if used) comprises an insulating material, such as undoped silicate glass (i.e., undoped silicon oxide, such as SiO2), silicon nitride, or a dielectric metal oxide material. The insulating liner layer 73L can be deposited using conformal deposition processes such as chemical vapor deposition or atomic layer deposition. The thickness of the insulating liner layer 73L can range from 3 nm to 30 nm, such as 6 nm to 20 nm, but smaller and larger thicknesses are also possible.

[0110] The phosphorus-doped silicate glass layer 74L comprises a phosphorus-doped silicate glass material having a material composition including silicon oxide, wherein the silicon oxide is doped with a concentration of at least 1.0 × 10⁻⁶. 20 / cm 3Phosphorus atoms can be present in atomic percentages ranging from 0.1% to 15% (e.g., 2% to 10% and / or 4% to 8%), but smaller and larger atomic percentages are also possible. Phosphorus-doped silicate glass materials can be deposited, for example, by a chemical vapor deposition process performed in a process chamber. The chemical vapor deposition process can utilize the decomposition of organosilicon precursors (such as tetraethyl orthosilicate (TEOS), bis(trimethylsilyl)acetamide (BTBAS), bis(trimethylsilyl)acetamide (TMOS), octamethylcyclotetrasiloxane (OMCTS), etc.) or by introducing silicon-containing precursor gases (such as silanes or dichlorosilanes) and oxidant gases (such as oxygen or ozone) into the process chamber. Phosphorus-doped silicate glass materials can be continuously or intermittently introduced into the process chamber to in-situ dope the deposited silicate glass material with phosphorus atoms, thereby forming phosphorus-doped silicate glass materials. Chemical vapor deposition (CVD) processes may include plasma-enhanced CVD or low-pressure CVD. Alternatively, atomic layer deposition (ALD) or another deposition process may be used instead of CVD.

[0111] When depositing phosphorus-doped silicate glass materials using organic precursors (e.g., TEOS), the deposited phosphorus-doped silicate glass material may contain carbon atoms in the range of 0.0001% to 1.0% (e.g., 0.001% to 0.1%). Furthermore, the deposited phosphorus-doped silicate glass material may contain hydrogen atoms in the range of 0.0005% to 5.0% (e.g., 0.005% to 0.5%).

[0112] The phosphorus-doped silicate glass material of the phosphorus-doped silicate glass layer 74L may optionally contain additional dopant atoms other than phosphorus, carbon, and / or hydrogen. In one embodiment, the phosphorus-doped silicate glass material of the phosphorus-doped silicate glass layer 74L may comprise boron phosphosilicate glass (BPSG) containing boron atoms in an atomic concentration ranging from 0.001% to 10% (such as 1% to 8% and / or 3% to 6%).

[0113] Generally, the phosphorus-doped silicate glass layer 74L contains phosphorus atoms as mobile ion trapping atoms, i.e., as adsorbent atoms for trapping mobile ions drifting into the phosphorus-doped silicate glass material. Therefore, the presence of additional atoms (such as carbon, hydrogen, and boron atoms) does not affect the functionality of the phosphorus-doped silicate glass layer 74L as a mobile ion trapping material. Without being bound by any particular theory, it is believed that the presence of carbon in the phosphorus-doped silicate glass layer 74L reduces or prevents the diffusion of phosphorus atoms outward from the phosphorus-doped silicate glass layer 74L. This enhances the function of the phosphorus-doped silicate glass layer 74L as a mobile ion adsorbent. The thickness of the phosphorus-doped silicate glass layer 74L is chosen such that an unfilled lateral extension cavity (referred to herein as a lateral isolation cavity) exists within each lateral isolation trench 79.

[0114] refer to Figure 14 An anisotropic etching process can be performed to remove the horizontal extensions of the phosphorus-doped silicate glass layer 74L and the optional insulating pad layer 73L. Each remaining vertical extension of the phosphorus-doped silicate glass layer 74L within a corresponding lateral isolation trench 79 includes a phosphorus-doped silicate glass spacer 74. Each remaining portion of the insulating pad layer 73L within a corresponding lateral isolation trench 79 includes an insulating pad 73. The insulating pad 73 and the phosphorus-doped silicate glass spacer 74 may be formed in each lateral isolation trench 79.

[0115] Phosphorus-doped silicon oxide portions are formed at each stage of insulating layer 32 in the peripheral region of each lateral isolation trench 79. In this embodiment, the phosphorus-doped silicon oxide portions include portions of continuous phosphorus-doped silicate glass spacers 74 located at each stage of insulating layer 32. The continuous phosphorus-doped silicate glass spacers 74 may extend vertically from a horizontal plane including the top surface of the contact stage dielectric layer 80 to at least one semiconductor material layer (such as the source stage material layer 110). Thus, phosphorus-doped silicon oxide portions (such as portions embodied in phosphorus-doped silicate glass spacers 74) may be formed at each stage of insulating layer 32 within each lateral isolation trench 79.

[0116] refer to Figure 15At least one conductive filler material (such as a combination of a metal barrier material and a metal filler material) can be deposited in the remaining volume of the lateral isolation trench 79. Excess portions of the at least one conductive filler material can be removed from above a horizontal plane including the top surface of the contact-level dielectric layer 80 by a planarization process. The planarization process may include a chemical mechanical polishing process and / or a trench etching process. Each remaining portion of the at least one conductive filler material retained in the lateral isolation trench constitutes a conductive filler structure 76. In one embodiment, each conductive filler structure 76 may include a metal barrier pad 76A and a metal filler material portion 76B, the metal barrier pad comprising a metal barrier material (such as TiN, TaN, WN, MoN, or combinations thereof), and the metal filler material portion comprising a metal filler material (such as W, Ti, Ta, Co, Ru, Mo, Cu, etc.).

[0117] The combination of all material portions filling the lateral isolation trench 79 constitutes a lateral isolation trench filling structure (73, 74, 76). In one embodiment, each lateral isolation trench filling structure (73, 74, 76) includes a conductive filling structure 76 formed within and laterally surrounded by phosphorus-doped silicon oxide portions located at each level of the insulating layer 32. In this embodiment, the phosphorus-doped silicon oxide portion includes portions of a continuous phosphorus-doped silicate glass spacer 74. In one embodiment, the phosphorus-doped silicate glass spacer 74 in the lateral isolation trench 79 may include a single opening therethrough and may be topologically homeomorphic toroidal (i.e., may be continuously deformed into a toroidal without creating any new holes and without destroying any existing holes). Each conductive via structure 76 may be electrically connected to at least one semiconductor material layer (such as source level material layer 110). In summary, each lateral isolation trench filling structure (73, 74, 76) may include an insulating spacer 74 and a conductive filling structure 76 contacting the top surface of at least one semiconductor material layer (such as source level material layer 110).

[0118] refer to Figure 16A and Figure 16BA photoresist layer (not shown) may be applied over the contact-level dielectric layer 80 and may be photolithographically patterned to form openings above each memory opening-fill structure in the memory opening-fill structure 58, above the horizontally extending surface of the stepped surface in the contact region. An anisotropic etching process may be performed to transfer the pattern of the openings in the photoresist layer through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65. Drain contact via cavities may be formed over the memory opening-fill structure 58 through the contact-level dielectric layer 80. Layer contact via structures may be formed through the contact-level dielectric layer 80 and the inverse stepped dielectric material portion 65 on the top surface of a corresponding conductive layer in the conductive layer 46. The photoresist layer may subsequently be removed, for example, by ashing.

[0119] At least one conductive material (such as a combination of a metal barrier material and a metal filler material) can be deposited in the drain contact via cavity and the layer contact via cavity. Excess of the at least one conductive material can be removed from above a horizontal plane including the top surface of the contact dielectric layer 80 by a planarization process, which can employ a recess etching process and / or a chemical mechanical polishing process. The remaining portion of the at least one conductive material filling the drain contact via cavity forms a drain contact via structure 88, which contacts the top surface of a corresponding drain region in the drain region 63. The remaining portion of the at least one conductive material filling the layer contact via cavity forms a layer contact via structure 86 contacting the top surface of a corresponding conductive layer in the conductive layer 46.

[0120] refer to Figure 17A and Figure 17B A connection level dielectric layer 90 may be formed above the contact level dielectric layer 80. A connection via cavity may be formed through the connection level dielectric layer 90 and may be filled with at least one conductive material (which may include at least one metallic material) to form a connection level via structure (98, 96). The connection level via structures (98, 96) include a drain connection via structure 98 of a corresponding drain contact via structure in the contact drain contact via structures 88, and a layer connection via structure 96 of a corresponding layer contact via structure in the contact layer contact via structures 86.

[0121] Bit-line level dielectric layer 120 may be formed on top of interconnect level dielectric layer 90. Bit-line level cavities may be formed through bit-line level dielectric layer 120 and may be filled with at least one conductive material (which may include at least one metallic material) to form bit-line level metal lines (128, 126). Bit-line level metal lines may include bit lines 128 extending laterally along a second horizontal direction hd2, and bit-line level interconnect metal lines 126 (not shown separately) for providing electrical connections to layer interconnect via structure 96.

[0122] refer to Figure 18 Additional dielectric material layers and additional metal interconnect structures may be formed above the contact-level dielectric layer 80. The additional dielectric material layers may include at least one via-level dielectric layer, at least one additional line-level dielectric layer, and / or at least one additional line and via-level dielectric layer. The additional metal interconnect structures may include metal via structures, metal line structures, and / or integrated metal line and via structures. The additional dielectric material layer formed above the contact-level dielectric layer 80 is referred to herein as memory-side dielectric material layer 960. The additional metal interconnect structures are collectively referred to as memory-side dielectric material layer 960. Memory-side dielectric material layer 960 includes bit-line level dielectric material layers with embedded bit lines 128, which are a subset of memory-side metal interconnect structures 980.

[0123] Metal bonding pads (referred to herein as memory-side bonding pads 988) can be formed at the topmost level of the memory-side dielectric material layer 960. The memory-side bonding pads 988 can be electrically connected to the memory-side metal interconnect structure 980 and various nodes of the three-dimensional memory array, which includes alternating stacks of insulating layers 32 and conductive layers 46 and memory opening-filling structures 58. Thus, a memory die 900 can be provided.

[0124] A memory-side dielectric material layer 960 is formed over alternating stacks (32, 46). A memory-side metal interconnect structure 980 is embedded in the memory-side dielectric material layer 960. Memory-side bonding pads 988 may be embedded within the memory-side dielectric material layer 960, and specifically embedded in the topmost layer of the memory-side dielectric material layer 960. The memory-side bonding pads 988 may be electrically connected to the memory-side metal interconnect structure 980.

[0125] In one embodiment, the memory die 900 may include: a three-dimensional memory array comprising alternating stacks (32, 46) of insulating layer 32 and conductive layer 46; a two-dimensional array of memory openings 49 extending vertically through the alternating stacks (32, 46); and a two-dimensional array of memory opening-filling structures 58 located within the two-dimensional array of memory openings 49 and comprising corresponding vertical stacks of memory elements and corresponding vertical semiconductor channels 60; a two-dimensional array of drain contact via structures 88 electrically connected to a corresponding vertical semiconductor channel 60 in the vertical semiconductor channel 60; and a two-dimensional array of layer contact via structures 86 electrically connected to a corresponding conductive layer 46, a subset of the conductive layers serving as word lines of the three-dimensional memory array.

[0126] Therefore, the memory die 900 includes a memory array, a memory-side metal interconnect structure 980, and memory-side bonding pads 988 embedded within a memory-side dielectric material layer 960. The memory die 900 includes a memory device that may include a three-dimensional memory array comprising alternating stacks of insulating layer 32 and conductive layer 46, and a two-dimensional array of NAND strings (e.g., memory aperture-filled structure 58) extending vertically through the alternating stacks (32, 46). In one embodiment, the conductive layer 46 includes word lines of the two-dimensional array of NAND strings. In one embodiment, the memory-side metal interconnect structure 980 includes bit lines 128 of the two-dimensional array of NAND strings.

[0127] refer to Figure 19 A logic die 700 is provided. The logic die 700 includes peripheral circuitry 720 formed on a logic-side substrate 709. According to one aspect of this disclosure, the peripheral circuitry 720 may be configured to control the operation of a memory array within the memory die 900. For example, the peripheral circuitry 720 may include word line driver regions, bit line driver regions, sense amplifier regions, input / output buffers, etc. A logic-side metal interconnect structure 780 embedded within a logic-side dielectric material layer 760 may be formed above the peripheral circuitry 720. The logic die 700 includes logic-side bonding pads 788 embedded within the logic-side dielectric material layer 760.

[0128] refer to Figure 20 A bonding assembly can be formed by bonding logic die 700 to memory die 900. For example, logic die 700 can be attached to memory die 900 by bonding logic-side bonding pads 788 to memory-side bonding pads 988. The bonding between memory die 900 and logic die 700 can be performed using wafer-to-wafer bonding (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by die-to-die bonding, or by die-to-die bonding. Logic-side bonding pads 788 within each logic die 700 can be bonded to memory-side bonding pads 988 within the corresponding memory die 900.

[0129] Logic die 700 can be attached to memory die 900, for example, by bonding logic-side bonding pads 788 to memory-side bonding pads 988. The bonding between memory die 900 and logic die 700 can be performed using wafer-to-wafer bonding (in which a two-dimensional array of memory dies 900 is bonded to a two-dimensional array of logic dies 700), by die-to-die bonding, or by die-to-die bonding. Logic-side bonding pads 788 within each logic die 700 can be bonded to memory-side bonding pads 988 within the corresponding memory die 900.

[0130] refer to Figure 21 The carrier substrate 9 can be optionally removed, for example, by grinding, polishing, cleaving, isotropic etching, and / or anisotropic etching processes. If a polishing process, such as chemical mechanical polishing, is used to remove the carrier substrate 9, a barrier insulating layer 106 can then be used as a polishing barrier material layer. If an etching process, such as wet etching, is used to remove the carrier substrate 9, a barrier insulating layer 106 can then be used as an etching barrier material layer. Optional electrical contacts can be formed on the bottom side of the bonding assembly of the memory die 900 and the logic die 700.

[0131] Figure 22 A first alternative configuration of the first exemplary structure according to an alternative embodiment is illustrated. The alternative configuration of the first exemplary structure may be provided by forming a semiconductor device 620 on a semiconductor substrate 609, the semiconductor device including peripheral circuitry for controlling the operation of a three-dimensional memory device; and forming a metal interconnect structure 680 embedded in a dielectric material layer 660 above the semiconductor device 620. In other words, a combination of the semiconductor substrate 609, the semiconductor device 620, the dielectric material layer 660, and the metal interconnect structure 680 may be used instead of the carrier substrate 9 and the barrier insulating layer 106.

[0132] refer to Figure 23 Executable reference Figure 1 The described processing steps involve forming a source level material layer 110' and alternating stacks (32, 42) over the metal interconnect structure 680 and the dielectric material layer 660.

[0133] refer to Figure 24 Executable reference Figures 2 to 18 The described processing steps provide a memory die 900, which is optionally bonded to a logic die 700. Figure 24 When the memory die is bonded to the logic die 700, the semiconductor device 620 may include a first subset of peripheral circuitry for controlling the operation of the three-dimensional memory device, and the logic die 700 may include a second subset of peripheral circuitry for controlling the operation of the three-dimensional memory device.

[0134] refer to Figure 25 The second alternative configuration of the first exemplary structure can be obtained from the following operations: Figure 13 The first exemplary structure illustrated herein derives from increasing the thickness of the phosphorus-doped silicate glass layer 74L such that the phosphorus-doped silicate glass layer 74L fills each of the lateral isolation trenches 79. In some embodiments, air gaps may be formed in the phosphorus-doped silicate glass layer 74L. Generally, the thickness of the phosphorus-doped silicate glass layer 74L may be greater than half the width of each lateral isolation trench 79.

[0135] refer to Figure 26 An anisotropic etching process can be performed to remove horizontal extensions of the phosphorus-doped silicate glass layer 74L and optional insulating pad layer 73L from a horizontal plane including the top surface of the contact-level dielectric layer 80. Each remaining portion of the phosphorus-doped silicate glass layer 74L within a corresponding lateral isolation trench 79 includes a phosphorus-doped silicate glass filling structure 75. Each remaining portion of the insulating pad layer 73L (if present) within a corresponding lateral isolation trench 79 includes an insulating pad 73. The insulating pad 73 and the phosphorus-doped silicate glass filling structure 75 may be formed in each lateral isolation trench 79.

[0136] The combination of all material portions filling the lateral isolation trench 79 constitutes the lateral isolation trench filling structure (72, 75). Each lateral isolation trench filling structure (73, 75) includes a phosphorus-doped silicon oxide portion at each stage of the insulating layer 32 (including the portion of the phosphorus-doped silicate glass filling structure 75 located at the stage of the insulating layer 32).

[0137] refer to Figure 27A and Figure 27B Executable reference Figure 16A and Figure 16B The described processing steps are used to form various contact via structures (88, 86).

[0138] refer to Figure 28 Executable reference Figures 17A to 28 The described processing steps are to form a memory die 900, to bond the memory die 900 to a logic die 700, and optionally to remove the substrate 9.

[0139] refer to Figure 29 A third alternative configuration of the first exemplary structure can be derived from a second alternative configuration of the first exemplary structure by: forming a semiconductor device 620 on a semiconductor substrate 609, the semiconductor device including peripheral circuitry for controlling the operation of a three-dimensional memory device; forming a metal interconnect structure 680 embedded in a dielectric material layer 660 above the semiconductor device 620; and then performing a reference... Figures 1 to 12 and Figures 25 to 28 The processing steps described in B. In other words, a combination of semiconductor substrate 609, semiconductor device 620, dielectric material layer 660 and metal interconnect structure 680 can be used instead of carrier substrate 9 and barrier insulating layer 106.

[0140] refer to Figures 30A to 30C The second exemplary structure according to the second embodiment of this disclosure can be obtained from the following operations: Figure 9The first exemplary structure illustrated herein derives from the following: optionally performing at least one angled ion implantation process, which implants carbon atoms around the lateral isolation trench 79 and in the upper portion of the contact-level dielectric layer 80. Figure 30A It is a vertical cross-sectional view, Figure 30 is Figure 30A An enlarged view of the area surrounding the lateral isolation trench 79 and the memory opening filling structure 58 of the second exemplary structure, and Figure 30C This is an enlarged view of a region of an alternative embodiment of the second exemplary structure, which is related to... Figure 30B The difference in the second exemplary structure illustrated herein is the presence of vertical width modulation in the transverse isolation trench 79. Generally, the sidewalls of the transverse isolation trench 79 may have, for example, […]. Figure 30B The illustrated straight vertical cross-sectional profile may have, for example, the following: Figure 30C The illustrated example includes an undulating vertical cross-sectional profile comprising an inverted conical upper portion and a conical lower portion. Figure 30C In the example illustrated, the variable width of the lateral isolation trench 79 may increase in the lower portion of the lateral isolation trench 79 with increasing vertical distance from the horizontal plane including the top surface of the carrier substrate 9, and may decrease in the upper portion of the lateral isolation trench 79 with increasing vertical distance from the horizontal plane including the top surface of the carrier substrate 9.

[0141] At least one angled ion implantation process implants carbon atoms into the surface portion of the insulating layer 32, the surface portion of the sacrificial material layer 42 near the lateral isolation trench 79, the portion of the lower source semiconductor layer 112 lying beneath the lateral isolation trench 79, and the surface portion of the contact dielectric layer 80. In one embodiment, the insulating layer 32 comprises a silicon oxide material, such as undoped silicate glass. In this case, the carbon-implanted portion of the insulating layer 32 comprises a carbon-doped silicon oxide portion 32C. The carbon-implanted surface portions of the source contact layer 114 and the upper source semiconductor layer 116 are referred to herein as carbon-doped semiconductor material portions 171C.

[0142] In one embodiment, a carbon-doped portion 161 (such as an implanted portion of the lower source semiconductor layer 112) of at least one semiconductor material layer underlying a lateral isolation trench 79 is doped with carbon atoms and is referred to herein as a carbon-doped semiconductor material portion. In one embodiment, a source material layer 110 doped with arsenic or phosphorus atoms and a carbon-doped portion 171C of at least one semiconductor material layer (such as the source material layer 110) may be doped with both carbon atoms and arsenic or phosphorus atoms.

[0143] In one embodiment, a contact-level dielectric layer 80 is overlaid with alternating stacks (32, 46), and a lateral isolation trench 79 extends through the contact-level dielectric layer 80. Carbon-doped silicon oxide portions may be formed at the levels of the contact-level dielectric layer 80 surrounding the lateral isolation trench 79. In this case, the unimplanted carbon portion of the contact-level dielectric layer 80 is referred to as a base contact-level dielectric sublayer 80B laterally spaced from the lateral isolation trench 79, and the carbon-implanted portion of the contact-level dielectric layer 80 includes a carbon-doped contact-level dielectric sublayer 80C containing a higher carbon atom concentration than that of the base contact-level dielectric sublayer 80B.

[0144] The carbon-doped silicon oxide portion 32C, the carbon-doped semiconductor material portion 171C, the carbon-doped portion 161, and the carbon-doped contact-level dielectric sublayer 80C may have corresponding thicknesses in the range of 10 nm to 200 nm (e.g., 20 nm to 100 nm), and may contain a concentration of at least 1.0 × 10⁻⁶. 16 / cm 3 Such as an atomic percentage of carbon atoms in the range of 0.01% to 10% (e.g., 0.3% to 3%), but smaller and larger atomic percentages are also possible.

[0145] refer to Figures 31A to 31C It can perform at least one additional angled ion implantation process to implant phosphorus atoms around the lateral isolation trench 79 and into the carbon-doped contact-level dielectric sublayer 80C. Figure 31B An example is shown where the transverse isolation trench 79 has a configuration with straight sidewalls, and Figure 31C An example is shown of the configuration in which the transverse isolation trench 79 has undulating sidewalls.

[0146] At least one additional angled ion implantation process implants phosphorus atoms into carbon-doped silicon oxide portions 32C (which are surface portions of insulating layer 32), the upper region of each carbon-doped portion 161, the carbon-doped contact-level dielectric sublayer 80C, and the carbon-doped semiconductor material portion 171C. In one embodiment, insulating layer 32 comprises silicon oxide material (such as undoped silicate glass), and the carbon-doped silicon oxide portions 32C can be converted into carbon and phosphorus-doped silicon oxide portions 32CP, which may also be referred to as doped silicon oxide portions. The carbon-doped semiconductor material portion 171C is converted into carbon and phosphorus-doped semiconductor material portion 171CP.

[0147] At least one semiconductor material layer is additionally doped with phosphorus atoms in the upper region of each carbon-doped portion 161 underlying the corresponding lateral isolation trench 79 (such as the implanted portion of the lower source semiconductor layer 112), and is converted into a carbon and phosphorus-doped portion 162, or into a carbon and phosphorus-doped semiconductor material portion. The ion-implanted region can be activated by activation annealing (such as annealing at a temperature of 900 to 1100 degrees Celsius).

[0148] Unbound by any particular theory, it is believed that the carbon and phosphorus doped silicon portion 162 can reduce the number of crystal defects (such as dislocations) in the monocrystalline or polycrystalline silicon located below the lateral isolation trench 79 compared to the heavily arsenic-doped silicon region below the trench 79. Such defects may arise from crystallization mismatch between the arsenic-doped and boron-doped silicon regions during thermal processing of the memory device, especially when the source layer 110 is omitted and the p-type silicon substrate 9 is located directly below the lateral isolation trench 79. In this case, an arsenic ion implantation is performed through the lateral isolation trench 79 to form a pn junction between the p-type silicon substrate 9 and the n-type arsenic-doped silicon source region formed in the p-type silicon substrate 9. The reduction in defects may result in lower leakage current in the silicon material located below the lateral isolation trench 79 (e.g., at the source region).

[0149] In one embodiment, a contact-level dielectric layer 80 is overlaid with alternating stacks (32, 46), and a lateral isolation trench 79 extends through the contact-level dielectric layer 80. Carbon and phosphorus-doped silicon oxide portions may be formed around the lateral isolation trench 79 at the levels of the contact-level dielectric layer 80. In this case, the base contact-level dielectric sublayer 80B is not implanted with carbon or phosphorus atoms, and the carbon and phosphorus-implanted portions of the contact-level dielectric layer 80 include a carbon and phosphorus-doped contact-level dielectric sublayer 80CP containing a higher atomic concentration of carbon atoms and a higher atomic concentration of phosphorus atoms than the base contact-level dielectric sublayer 80B.

[0150] The carbon and phosphorus doped silicon oxide portion 32CP, the carbon and phosphorus doped semiconductor material portion 171CP, the carbon and phosphorus doped portion 162, and the carbon and phosphorus doped contact-level dielectric sublayer 80CP may have corresponding thicknesses in the range of 10 nm to 200 nm (e.g., 20 nm to 100 nm), and may contain a concentration of at least 1.0 × 10⁻⁶. 16 / cm 3 Phosphorus atoms, such as atomic percentages in the range of 0.01% to 15% (e.g., 2% to 10%, and / or 4% to 8%), but smaller and larger atomic percentages may also be used.

[0151] Generally, a phosphorus-doped silicon oxide portion (such as a carbon and phosphorus-doped silicon oxide portion 32CP) may be formed around each lateral isolation trench 79 at each level of the insulating layer 32. In one embodiment, the phosphorus-doped silicon oxide portion includes a phosphorus implantation portion of the insulating layer 32. At least one surface portion of a semiconductor material layer (such as a source level material layer 110) underlying the lateral isolation trench 79 is doped with carbon atoms during at least one angled ion implantation process for implanting carbon atoms, and doped with phosphorus atoms during at least one angled ion implantation process for implanting phosphorus atoms.

[0152] In one embodiment, the insulating layer 32 comprises undoped silicon oxide material, and the carbon and phosphorus doped silicon oxide portion 32CP comprises a portion of the insulating layer 32 near the lateral isolation trench 79. The carbon and phosphorus doped silicon oxide portion 32CP has a higher atomic concentration of phosphorus and carbon atoms than the non-carbon and phosphorus doped silicon oxide portion 32CP of the insulating layer 32.

[0153] In one embodiment, the carbon and phosphorus doped silicon oxide portions 32CP are doped with carbon atoms at an atomic percentage of at least 0.001%. In one embodiment, the carbon and phosphorus doped silicon oxide portions 32CP are located outside the lateral isolation trench 79 and are vertically spaced apart from each other.

[0154] refer to Figures 32A to 32C The sacrificial material layer 42 is replaced by the conductive layer 42, as described above relative to... Figures 10 to 12 As described above. The insulating spacer material can then be conformally deposited using a conformal deposition process, such as chemical vapor deposition. The insulating spacer material layer may comprise undoped silicate glass, or may comprise a phosphorus-doped silicate glass material suitable for use in the phosphorus-doped silicate glass layer 74L as described above. The thickness of the insulating spacer material layer is less than half the width of each lateral isolation trench 79. An anisotropic etching process can be performed to remove the horizontal extensions of the insulating spacer material layer. Each remaining vertical extension of the insulating spacer material layer constitutes an insulating spacer 174. The insulating spacer 174 may comprise undoped silicate glass or a phosphorus-doped silicate glass containing phosphorus atoms.

[0155] Then, as described above, a conductive fill structure 76 as described above is formed over the insulating spacer 174. The combination of all material portions filling the lateral isolation trench 79 constitutes the lateral isolation trench fill structure (174, 76). In one embodiment, each lateral isolation trench fill structure (174, 76) includes a conductive fill structure 76 formed within and laterally surrounded by phosphorus-doped silicon oxide portions (such as carbon and phosphorus-doped silicon oxide portions 32CP) and electrically connected to at least one semiconductor material layer (such as source level material layer 110).

[0156] refer to Figure 33A and Figure 33B Executable reference Figure 16A and Figure 16B The described processing steps are used to form various contact via structures (88, 86).

[0157] refer to Figure 34 Executable reference Figures 17A to 28 The described processing steps form a memory die 900 and bond the memory die 900 to a logic die 700.

[0158] refer to Figure 35 An alternative configuration of the second exemplary structure can be derived from the second exemplary structure by: forming a semiconductor device 620 on a semiconductor substrate 609, the semiconductor device including peripheral circuitry for controlling the operation of a three-dimensional memory device; forming a metal interconnect structure 680 embedded in a dielectric material layer 660 above the semiconductor device 620; and then performing a reference... Figures 1 to 9 and Figures 30A to 33B The described processing steps. In other words, a combination of semiconductor substrate 609, semiconductor device 620, dielectric material layer 660 and metal interconnect structure 680 can be used instead of carrier substrate 9 and barrier insulating layer 106.

[0159] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a three-dimensional memory device includes: a pair of alternating stacks (32, 46) of insulating layer 32 and conductive layer 46, the pair of alternating stacks being laterally spaced apart from each other by a lateral isolation trench 79; a memory opening 49 extending vertically through a corresponding alternating stack (32, 46) of the pair of alternating stacks (32, 46); a memory opening filling structure 58 located in a corresponding memory opening in the memory opening 49 and including a corresponding vertical semiconductor channel 50 and a corresponding vertical stack of memory elements (e.g., portions of a memory film); and a lateral isolation trench filling structure {(73, 74, 76), (73, 75), (174, 76)} located in the lateral isolation trench 79, wherein phosphorus-doped silicon oxide portions (74, 75, 32CP) are located within or on the sidewalls of the lateral isolation trench 79 at the level of the insulating layer 32.

[0160] In a second embodiment, the vertical semiconductor channel 60 comprises p-type silicon (e.g., boron-doped polysilicon); and an n-type silicon source region 162 doped with phosphorus atoms is located below the lateral isolation trench filling structure (174, 76). In the second embodiment, the n-type silicon source region 162 is also doped with carbon atoms. In the second embodiment, a phosphorus-doped silicon oxide portion 32CP is located on the sidewall of the lateral isolation trench 79.

[0161] In one embodiment, the three-dimensional memory device further includes a contact-level dielectric layer 80 overlying an alternating stack (32, 46). Lateral isolation trenches 79 extend through the contact-level dielectric layer 80; and additional phosphorus-doped silicon oxide portions are located within or around the lateral isolation trenches 79 at the level of the contact-level dielectric layer 80. In a second embodiment, the contact-level dielectric layer 80 includes: a base contact-level dielectric sublayer 80B, which is laterally spaced from the lateral isolation trench filling structure {(73, 74, 76), (73, 75), (174, 76)}; and a doped contact-level dielectric sublayer 80CP, which overlying the base contact-level dielectric sublayer 80B and containing a higher concentration of phosphorus atoms than the base contact-level dielectric sublayer 80B.

[0162] In one embodiment, the insulating layer 32 comprises a silicon oxide material; and the phosphorus-doped silicon oxide portions (74, 75, 32CP) comprise portions of the insulating layer 32 adjacent to the lateral isolation trench filling structure {(73, 74, 76), (73, 75), (174, 76)}. In one embodiment, the phosphorus-doped silicon oxide portions (74, 75, 32CP) have a higher phosphorus atomic concentration than the portions of the insulating layer 32 adjacent to the phosphorus-doped silicon oxide portions (74, 75, 32CP). In a second embodiment, the phosphorus-doped silicon oxide portions 32CP are located outside the lateral isolation trench 79 and are vertically spaced apart from each other.

[0163] In one embodiment, the phosphorus-doped silicon oxide portion (74,75,32CP) is doped with carbon atoms at an atomic percentage of at least 0.001%.

[0164] In a first embodiment, phosphorus-doped silicon oxide portions (74, 75) are located within a lateral isolation trench 79. The phosphorus-doped silicon oxide portions (74, 75) are portions of a single continuous insulating structure (74, 75) located within the lateral isolation trench 79 and extending vertically from the bottommost layer of a pair of alternating stacks (32, 46) to the topmost layer of the alternating stacks (32, 46). In one embodiment, the lateral isolation trench filling structure {(73, 74, 76), (73, 75), (174, 76)} includes insulating spacers (74, 174) and conductive filling structure 76.

[0165] Various embodiments of this disclosure can be used to provide a phosphorus-doped silicate glass material within or around each lateral isolation trench 79 between adjacent pairs of alternating stacks of insulating layer 32 and conductive layer 46. Phosphorus atoms in the phosphorus-doped silicate glass material can act as effective mobile ion trapping atoms, capturing mobile ions diffusing into the phosphorus-doped silicate glass material. For example, fluorine or chlorine atoms diffusing out of conductive layer 46 or conductive fill structure 76 can be effectively trapped by phosphorus atoms. Therefore, damage to the external barrier dielectric 44 caused by mobile ions and / or penetration of mobile ions into the memory opening fill structure 58 (especially memory opening fill structures positioned adjacent to the lateral isolation trench 79) can be reduced or avoided. This improves data retention in the memory device.

[0166] While the foregoing relates to specific preferred embodiments, it should be understood that this disclosure is not limited thereto. Those skilled in the art will envision various modifications that can be made to the disclosed embodiments, and such modifications are intended to fall within the scope of this disclosure. Compatibility is assumed between all embodiments that are not mutually exclusive. Unless otherwise expressly stated, the words “comprising” or “including” contemplate that the words “substantially constitute…” or “consist of…” replace all embodiments for which the words “comprising” or “including” are used. Whenever two or more elements are listed as alternatives in the same or different paragraphs, a Markush group comprising the list of two or more elements is also implicitly disclosed. Whenever the auxiliary verb “capable” is used in this disclosure to describe the formation of an element or the execution of a processing step, it is also clearly envisioned that embodiments in which such elements or such processing steps are not performed are included, provided that the resulting apparatus or device is capable of providing equivalent results. Therefore, whenever omitting the formation or processing step of an element can provide the same or equivalent result, the auxiliary verb "can" applied to the formation of such an element or the execution of such a processing step should also be interpreted as "can" or "may, or may not," with these equivalent results including slightly better and slightly worse results. Where embodiments employing specific structures and / or configurations are illustrated in this disclosure, it should be understood that this disclosure can be practiced with any other functionally equivalent compatible structures and / or configurations, provided that such substitutions are not expressly prohibited or otherwise known to be impossible for a person skilled in the art. If any publications, patent applications, and / or patents are cited herein, each of such documents is incorporated herein by reference in its entirety.

Claims

1. A three-dimensional memory device, the three-dimensional memory device comprising: A pair of alternating stacks of insulating and conductive layers, wherein the pair of alternating stacks are laterally spaced apart from each other by lateral isolation trenches; A memory opening that extends vertically through the respective alternating stacks of the pair of alternating stacks; A memory aperture filling structure, wherein the memory aperture filling structure is located in a corresponding memory aperture and includes a corresponding vertical semiconductor channel and a corresponding vertical stack of memory elements; and A transverse isolation trench filling structure is located in the transverse isolation trench, wherein the phosphorus-doped silicon oxide portion is located within or on the sidewall of the transverse isolation trench at the level of the insulating layer.

2. The three-dimensional memory device according to claim 1, wherein: The vertical semiconductor channel comprises p-type silicon; and The phosphorus-doped n-type silicon source region is located below the lateral isolation trench filling structure.

3. The three-dimensional memory device according to claim 2, wherein the n-type silicon source region is also doped with carbon atoms.

4. The three-dimensional memory device according to claim 3, wherein the three-dimensional memory device further comprises a carbon-doped silicon region located below the n-type silicon source region.

5. The three-dimensional memory device of claim 1, wherein the phosphorus-doped silicon oxide portion is located on the sidewall of the lateral isolation trench.

6. The three-dimensional memory device of claim 5, further comprising an overlying contact-level dielectric layer on the alternatingly stacked contact layers, wherein: The transverse isolation trench extends through the contact-level dielectric layer; and The additional phosphorus-doped silicon oxide portion is located within or around the lateral isolation trench at the level of the contact level dielectric layer.

7. The three-dimensional memory device of claim 6, wherein the contact-level dielectric layer comprises: A base contact dielectric sublayer, wherein the base contact dielectric sublayer is laterally spaced from the lateral isolation trench filling structure; and A doped contact-level dielectric sublayer, wherein the doped contact-level dielectric sublayer is overlaid on the base contact-level dielectric sublayer and contains phosphorus atoms with a higher atomic concentration than the base contact-level dielectric sublayer.

8. The three-dimensional memory device according to claim 5, wherein: The insulating layer comprises silicon oxide material; and The phosphorus-doped silicon oxide portion includes the portion of the insulating layer near the lateral isolation trench filling structure.

9. The three-dimensional memory device of claim 8, wherein the phosphorus-doped silicon oxide portion has a higher atomic concentration of phosphorus atoms than the portion of the insulating layer adjacent to the phosphorus-doped silicon oxide portion.

10. The three-dimensional memory device of claim 8, wherein the phosphorus-doped silicon oxide portions are located outside the lateral isolation trenches and are vertically spaced apart from each other.

11. The three-dimensional memory device of claim 1, wherein the phosphorus-doped silicon oxide portion is doped with carbon atoms at an atomic percentage of at least 0.001%.

12. The three-dimensional memory device of claim 1, wherein the phosphorus-doped silicon oxide portion is located within the lateral isolation trench.

13. The three-dimensional memory device of claim 12, wherein the phosphorus-doped silicon oxide portion includes a portion of a single continuous insulating structure located in the lateral isolation trench and extending vertically from the bottommost layer of the pair of alternating stacks to the topmost layer of the alternating stacks.

14. The three-dimensional memory device of claim 1, wherein the lateral isolation trench filling structure comprises an insulating spacer and a conductive filling structure.

15. A method for forming a three-dimensional memory device, the method comprising: Two alternating stacks forming an insulating layer and a conductive layer, wherein the two alternating stacks are laterally spaced from each other by lateral isolation trenches. A memory opening is formed by passing through each of the two alternating stacks; A corresponding vertically stacked memory opening filling structure, including corresponding vertical semiconductor channels and memory elements, is formed in the corresponding memory opening; Phosphorus-doped silicon oxide portions are formed at the level of the insulating layer within or on the sidewall of the transverse isolation trench; as well as A transverse isolation trench filling structure is formed in the transverse isolation trench.

16. The method of claim 15, wherein: The insulating layer comprises silicon oxide; and The step of forming the phosphorus-doped silicon oxide portion on the sidewall of the lateral isolation trench includes performing at least one ion implantation process that implants phosphorus atoms into a surface portion of the insulating layer near the lateral isolation trench, wherein the phosphorus-doped silicon oxide portion includes the implanted portion of the insulating layer.

17. The method of claim 16, further comprising performing at least one additional ion implantation process, the at least one additional ion implantation process implanting carbon atoms into the phosphorus-doped silicon oxide portion.

18. The method of claim 17, wherein the surface portion of at least one semiconductor material underlying the lateral isolation trench is doped with the phosphorus atoms during the at least one ion implantation process and with the carbon atoms during the at least one additional ion implantation process.

19. The method of claim 15, wherein the step of forming the phosphorus-doped silicon oxide portion within the transverse isolation trench comprises depositing a phosphorus-doped silicate glass spacer in at least the peripheral region of the transverse isolation trench, wherein the phosphorus-doped silicon oxide portion comprises a portion of the phosphorus-doped silicate glass spacer.

20. The method of claim 15, wherein the lateral isolation trench filling structure comprises a conductive filling structure formed within the phosphorus-doped silicon oxide portion and laterally surrounded by the phosphorus-doped silicon oxide portion.

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