MEMS pressure sensor wafer and preparation method thereof

Abstract

The invention relates to the technical field of MEMS micromachining, and discloses an MEMS pressure sensor wafer and a preparation method thereof. The wafer comprises a substrate (1), and a silicon wafer (2), a first insulating layer (3), a first protective layer (4) and a sensitive film layer (5) which are sequentially arranged on the substrate (1), wherein the sensitive film layer (5) comprises a ZnO film (51) and a TiO2 film (52) arranged on the ZnO film (51), and the ZnO film (51) is in contact with the first protection layer (4). The wafer has the advantages of being good in high-temperature stability, ultralow in power consumption characteristic, high in sensitivity, good in environmental aging resistance, long in service life and the like, and is particularly suitable for industrial high-pressure, medical implantation and other extreme scenes.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of MEMS micromachining technology, and in particular to a MEMS pressure sensor wafer and a preparation method thereof. BACKGROUND

[0002] The MEMS pressure sensor wafer is a pressure sensitive element wafer based on micro-electro-mechanical system (MEMS) technology. It converts mechanical pressure signals into electrical signals through semiconductor processes to realize pressure measurement.

[0003] The core sensing structure of the MEMS pressure sensor wafer is usually piezoresistive or capacitive, and is made of traditional semiconductor materials such as single crystal silicon. It measures pressure by detecting physical deformation or charge accumulation, and then converts it into an electrical signal for processing. The current MEMS pressure sensor wafer mainly has the problems of poor high-temperature stability, high power consumption, low energy efficiency, and the need for further improvement of sensitivity and service life. SUMMARY

[0004] In view of the problems in the background art, the present application provides a MEMS pressure sensor wafer and a preparation method thereof. The MEMS pressure sensor wafer in the present application has the advantages of good high-temperature stability, ultra-low power consumption characteristics, high sensitivity, good environmental aging resistance, long service life, and is especially suitable for extreme scenarios such as industrial high pressure and medical implantation.

[0005] The first aspect of the present application provides a MEMS pressure sensor wafer, comprising a substrate 1, and a silicon wafer 2, a first insulating layer 3, a first protective layer 4 and a sensitive film layer 5 arranged in sequence on the substrate 1; wherein the sensitive film layer 5 comprises a ZnO film 51 and a TiO2 film 52 arranged on the ZnO film 51, and the ZnO film 51 is in contact with the first protective layer 4.

[0006] The second aspect of the present application provides a preparation method of a MEMS pressure sensor wafer, wherein the method comprises the following steps:

[0007] (1) ion implantation is performed on the front surface of the silicon wafer to form an ion implantation region comprising an N+ implantation region, a P+ implantation region and a P- implantation region;

[0008] (2) after the ion implantation is completed, a first insulating layer, a first protective layer and a sensitive film layer are grown in sequence on the front surface of the silicon wafer; wherein the sensitive film layer comprises a ZnO film and a TiO2 film arranged on the ZnO film, and the ZnO film is in contact with the first protective layer;

[0009] (3) first etching is performed on the sensitive film layer, and then second etching is performed on the first protective layer and the first insulating layer, thereby forming a second through hole in the first protective layer and a first through hole in the first insulating layer; wherein the first through hole and the second through hole are communicated;

[0010] (4) after the second etching is completed, a metal layer is grown on the sensitive film layer and fills the second through hole and the first through hole;

[0011] (5) after the metal layer is grown, third etching is performed on the metal layer to form a metal lead;

[0012] (6) after the third etching is completed, a second insulating layer and a second protective layer are sequentially grown on the surface where the metal lead is generated;

[0013] (7) after the second protective layer is grown, fourth etching is performed on the second protective layer and the second insulating layer, thereby forming a fourth through hole in the second protective layer and a third through hole in the second insulating layer; wherein the second through hole, the third through hole and the fourth through hole are communicated;

[0014] (8) after the fourth etching is completed, fifth etching is performed on the back surface of the silicon wafer to form a cavity silicon cup structure;

[0015] (9) after the fifth etching is completed, the back surface of the silicon wafer is anodically bonded with a substrate to obtain a MEMS pressure sensor wafer.

[0016] Compared with the prior art, the MEMS pressure sensor wafer provided by the present application has the following beneficial technical effects:

[0017] 1) the MEMS pressure sensor wafer provided by the present application uses ZnO film and TiO2 film as the sensitive film layer, which not only offsets the difference in thermal expansion coefficient of a single material, greatly improves the high-temperature stability of the MEMS pressure sensor, but also constructs a stepwise energy band structure from bottom to top, greatly reduces power consumption and improves energy efficiency, and the interface polarization effect of the heterojunction between the ZnO film and the TiO2 film helps to improve the sensitivity of the wafer;

[0018] 2) the MEMS pressure sensor wafer provided by the present application uses ZnO film and TiO2 film as the sensitive film layer, and the TiO2 film is arranged above the ZnO film, and the TiO2 serves as a top layer, which can prevent the ZnO from being hydrolyzed in a humid environment on the one hand, and the hardness of the TiO2 film is higher, which can reduce the damage of the film layer caused by friction or particle impact, thereby helping to improve the environmental aging resistance of the wafer and prolong the service life;

[0019] 3) The MEMS pressure sensor wafer provided in the present application uses ZnO film and TiO2 film as the sensitive film layer, and the wide band gap characteristic of TiO2 itself can block the leakage current, which can improve the signal-to-noise ratio of piezoelectric / piezoresistive response by at least 40%, thereby further improving the sensitivity of the wafer;

[0020] 4) The preparation method of the MEMS pressure sensor wafer provided in the present application, which forms a ZnO film on the first protective layer and then forms a TiO2 film on the ZnO film, can reduce the lattice stress when ZnO and TiO2 are directly mixed;

[0021] 5) The preparation method of the MEMS pressure sensor wafer provided in the present application is simple to operate, and the prepared wafer has the advantages of good high-temperature stability, ultra-low power consumption characteristics, high sensitivity, good environmental aging resistance, long service life, etc., and is especially suitable for extreme scenes such as industrial high pressure and medical implantation. BRIEF DESCRIPTION OF DRAWINGS

[0022] Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The accompanying drawings are included to provide a description of the preferred embodiments and are not intended to limit the scope of the present application. Moreover, like reference numerals designate like parts throughout the several views in the drawings. In the drawings:

[0023] Figure 1 is the overall structure schematic diagram of the MEMS pressure sensor wafer in the present application;

[0024] Figure 2 is the overall structure schematic diagram of the MEMS pressure sensor wafer prepared in Comparative Example 1 of the present application.

[0025] BRIEF DESCRIPTION OF DRAWINGS

[0026] 1, base;

[0027] 2, silicon wafer; 21, cavity; 22, ion implantation region;

[0028] 221, N+ implantation region; 222, P- implantation region; 223, P+ implantation region;

[0029] 3, first insulating layer;

[0030] 4, first protective layer;

[0031] 5, sensitive film layer; 51, ZnO film; 52, TiO2 film;

[0032] 6, second insulating layer;

[0033] 7, second protective layer;

[0034] 8. Metal lead. DETAILED DESCRIPTION

[0035] It should be noted that the described embodiments are merely a part of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor fall within the scope of protection of the present application.

[0036] In the following description, the same reference numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments are not meant to be representative of all implementations consistent with the present application. Rather, they are simply examples of apparatuses and methods consistent with some aspects of the present application as detailed in the appended claims.

[0037] In the description of the present application, it should be understood that the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances. In addition, in the description of the present application, unless otherwise specified, "a plurality of" means two or more. The association between the associated objects described by "and / or" indicates that there can be three relationships, for example, A and / or B can represent the following three cases: A exists alone, A and B exist together, and B exists alone. The character " / " generally represents that the associated objects before and after are in an "or" relationship.

[0038] A first aspect of the present application provides a MEMS pressure sensor wafer, comprising a substrate 1, and a silicon wafer 2, a first insulating layer 3, a first protective layer 4 and a sensitive film layer 5 arranged in sequence on the substrate 1; wherein the sensitive film layer 5 comprises a ZnO film 51 and a TiO2 film 52 arranged on the ZnO film 51, and the ZnO film 51 is in contact with the first protective layer 4.

[0039] In the sensitive film layer in the application, first, the ZnO film and the TiO2 film can produce a synergistic effect through an interface coupling effect, greatly reduce the temperature drift, offset the difference in thermal expansion coefficient of a single material, avoid non-uniform expansion of the wafer when the temperature changes, and thus cause stress concentration and device failure, thereby greatly improving the high-temperature stability of the MEMS pressure sensor. Second, the work function of TiO2 is 4.9 eV, and the work function of ZnO is 4.5 eV. The sensitive film layer in the application presents a stepwise energy band structure from bottom to top, can inhibit electron back injection, reduce the leakage current by an order of magnitude, greatly reduce power consumption, and improve energy efficiency. Third, the interface polarization effect of the heterojunction between the ZnO film and the TiO2 film helps to improve the sensitivity of the wafer. Moreover, the wide band gap of TiO2 itself can block the leakage current, and the signal-to-noise ratio of the piezoelectric / piezoresistive response can be improved by at least 40%, thereby further improving the sensitivity of the wafer. In addition, compared with the poly film, the high chemical inertness of TiO2 can effectively solve the problems of stress relaxation and interface oxidation of the poly film in long-term humid and hot environment, prolonging the service life. Therefore, the wafer in the application has the advantages of good high-temperature stability, ultra-low power consumption characteristics, high sensitivity, good environmental aging resistance, long service life, and is especially suitable for extreme scenarios such as industrial high pressure and medical implantation.

[0040] In some embodiments of the application, the thickness of the substrate 1 is 1000±30 μm; the substrate 1 is selected from glass, preferably double-sided polished glass, and more preferably anodically bonded double-sided polished glass. In the application, the substrate and the silicon wafer are connected and fixed by anodic bonding.

[0041] In some embodiments of the application, the silicon wafer 2 is a hollow cavity silicon cup structure, and the hollow cavity 21 is arranged on the side facing the substrate 1; wherein the size of the hollow cavity 21 is (700-900) μm*(300-500) μm.

[0042] In the application, the hollow cavity is a stress cavity, which is a hollow cavity silicon cup structure formed after etching. The hollow cavity silicon cup structure is fixed after anodic bonding with the glass. The size of the hollow cavity is not specially limited in the application, and persons skilled in the art can reasonably select according to actual needs. For example, the size of the hollow cavity can be 750 μm*350 μm, 750 μm*400 μm, 750 μm*450 μm, 800 μm*350 μm, 800 μm*450 μm, 850 μm*350 μm, 850 μm*400 μm, 850 μm*450 μm, etc.

[0043] In some embodiments of the present application, the side of the silicon wafer 2 facing away from the substrate 1 is provided with an ion implantation region 22; the ion implantation region 22 comprises an N+ implantation region 221, a P- implantation region 222 and a P+ implantation region 223. In the present application, the ion implantation region is not particularly limited, and the N+ implantation region, the P- implantation region and the P+ implantation region can be provided on the surface layer of the side of the silicon wafer facing away from the substrate according to the known methods in the art.

[0044] In some embodiments of the present application, the first insulating layer 3 is selected from a SiO2 insulating layer, and the thickness of the first insulating layer 3 is The first insulating layer 3 is provided with a first via hole.

[0045] In the present application, the thickness of the first insulating layer is not particularly limited, for example, the thickness of the first insulating layer can be equal to 10 -10 nm. The thickness of the first insulating layer in the present application is not particularly limited, for example, the thickness of the first insulating layer can be and any number between these values. The first via hole, i.e. the VIA opening, has a minimum CD of 10 ± 2 μm, providing a metal electrical connection channel.

[0046] In some embodiments of the present application, the first protective layer 4 is selected from a SiN protective layer, and the thickness of the first protective layer 4 is The first protective layer 4 is provided with a second via hole, wherein the second via hole is in communication with the first via hole.

[0047] In the present application, the thickness of the first protective layer is not particularly limited, for example, the thickness of the first protective layer can be and any number between these values. The second via hole, i.e. the VIA opening, has a minimum CD of 10 ± 2 μm, providing a metal electrical connection channel.

[0048] In some embodiments of the present application, the sensitive film layer 5 covers part of the surface of the first protective layer 4.

[0049] In some embodiments of the present application, in the sensitive film layer 5, the thickness of the ZnO film 51 is the thickness of the TiO2 film 52 is

[0050] The thickness of the ZnO film and the TiO2 film in the present application is not particularly limited, for example, the thickness of the ZnO film and the TiO2 film is independently and and any number between these values.

[0051] In some embodiments of the present application, the thickness of the ZnO film 51 is greater than the thickness of the TiO2 film 52; wherein the thickness of the ZnO film 51 is The thickness of the TiO2 film 52 is

[0052] In the present application, the thicker ZnO layer (piezoelectric coefficient d 33 ≈12.4 pm / V) can ensure sufficient strain sensitivity, while the slightly thinner TiO2 layer (elastic modulus ~ 280 GPa) can both enhance mechanical strength through interfacial stress coupling and suppress thermal stress concentration due to the difference in thermal expansion coefficients (ZnO: 4.5 x 10 -6 / K, TiO2: 8.4 x 10 -6 / K). This thickness combination can further improve the sensitivity and environmental aging resistance of the wafer.

[0053] In some embodiments of the present application, the wafer further comprises a second insulating layer 6 and a second protective layer 7; wherein the second insulating layer 6 is arranged on the sensitive film layer 5 and in contact with the first protective layer 4, and the second protective layer 7 is arranged on the second insulating layer 6.

[0054] In some embodiments of the present application, the second insulating layer 6 is selected from a SiO2 insulating layer, and the thickness of the second insulating layer 6 is A third through hole is arranged on the second insulating layer 6; wherein the third through hole is in communication with the second through hole.

[0055] In the present application, the thickness of the second insulating layer is not particularly limited, for example, the thickness of the second insulating layer can be and any number between these values. The third through hole is also a pad opening, with a minimum CD of 80 ± 5 μm.

[0056] In some embodiments of the present application, the second protective layer 7 is selected from a SiN protective layer, and the thickness of the second protective layer 7 is A fourth through hole is arranged on the second protective layer 7; wherein the fourth through hole is in communication with the third through hole.

[0057] In the present application, the thickness of the second protective layer is not particularly limited, for example, the thickness of the second protective layer can be and any number between these values. The fourth through hole is also a pad opening, with a minimum CD of 80 ± 5 μm.

[0058] In some embodiments of the present application, the wafer further comprises a metal lead 8; wherein the metal lead 8 is used to connect the silicon wafer 2, the first insulating layer 3, the first protective layer 4, the sensitive film layer 5 and the second insulating layer 6.

[0059] In some embodiments of the present application, the metal lead 8 is arranged in the first through hole of the first insulating layer, the second through hole of the first protective layer and the third through hole of the second insulating layer; wherein the metal lead 8 fills the first through hole and the second through hole and is partially filled in the third through hole.

[0060] In some embodiments of the present application, the metal lead 8 is further arranged between the first protective layer 4 and the second insulating layer 6; wherein in the present application, the metal lead arranged between the first protective layer and the second insulating layer is in communication with the metal lead arranged between the first through hole, the second through hole and the third through hole.

[0061] In some embodiments of the present application, the fourth through hole on the second insulating layer is in communication with the third through hole for placing an electrode.

[0062] The second aspect of the present application provides a preparation method of a MEMS pressure sensor wafer, wherein the method comprises the following steps:

[0063] (1) ion implantation is performed on the front surface of the silicon wafer to form an ion implantation region comprising an N+ implantation region, a P+ implantation region and a P- implantation region;

[0064] (2) after the ion implantation is completed, a first insulating layer, a first protective layer and a sensitive film layer are sequentially grown on the front surface of the silicon wafer; wherein the sensitive film layer comprises a ZnO film and a TiO2 film arranged on the ZnO film, and the ZnO film is in contact with the first protective layer;

[0065] (3) the sensitive film layer is first etched, and then the first protective layer and the first insulating layer are secondly etched to form a second through hole in the first protective layer and a first through hole in the first insulating layer; wherein the first through hole and the second through hole are in communication;

[0066] (4) after the second etching is completed, a metal layer is grown on the sensitive film layer and fills the second through hole and the first through hole;

[0067] (5) after the growth of the metal layer is completed, the metal layer is thirdly etched to form a metal lead;

[0068] (6) after the third etching is completed, a second insulating layer and a second protective layer are sequentially grown on the surface where the metal lead is generated;

[0069] (7) after the growth of the second protective layer is completed, the second protective layer and the second insulating layer are fourthly etched to form a fourth through hole in the second protective layer and a third through hole in the second insulating layer; wherein the second through hole, the third through hole and the fourth through hole are in communication;

[0070] (8) After the fourth etching is completed, a fifth etching is performed on the back surface of the silicon wafer to form a cavity silicon cup structure;

[0071] (9) After the fifth etching is completed, the back surface of the silicon wafer is anodically bonded to a substrate to obtain a MEMS pressure sensor wafer.

[0072] In step (1):

[0073] In an embodiment of the present application, the ion implantation operation conditions for forming the N+ implantation region include: implanting Phos at a dose of 5e15-7e15 cm -2 , energy of 80-85 keV, tilt angle of 5-7°, and implantation junction depth of 30-50 μm;

[0074] In an embodiment of the present application, the ion implantation operation conditions for forming the P+ implantation region include: implanting Boron at a dose of 1e16-3e16 cm -2 , energy of 55-60 keV, tilt angle of 5-7°, and implantation junction depth of 20-30 μm;

[0075] In an embodiment of the present application, the ion implantation operation conditions for forming the P- implantation region include: implanting Boron at a dose of 3e14-5e14 cm -2 , energy of 40-50 keV, tilt angle of 5-7°, and implantation junction depth of 10-20 μm.

[0076] In step (2):

[0077] In an embodiment of the present application, the method for growing the first insulating layer includes: contacting the silicon wafer after the ion implantation with oxygen to perform an oxidation reaction at 1000-1200 °C to grow the first insulating layer on the side of the ion implantation region of the silicon wafer.

[0078] In the present application, at high temperature, oxygen reacts with silicon atoms on the surface of the silicon wafer to generate silicon dioxide (SiO2). By controlling the operation conditions of the oxidation reaction, the first insulating layer with a thickness of can be grown.

[0079] In an embodiment of the present application, the method for growing the first protective layer includes: contacting the silicon wafer after the growth of the first insulating layer with dichlorodihydrogen silicon (SiH2Cl2) and ammonia (NH3) to perform a redox reaction at a growth temperature of 600-800 °C and a growth pressure of 20-30 pa to grow the first protective layer on the first insulating layer.

[0080] In the present application, dichlorodihydrogen silane (SiH2Cl2) and ammonia (NH3) undergoes a redox reaction to generate silicon nitride. By controlling the conditions of the redox reaction, a ZnO film and a TiO2 film with a thickness of The first protective layer has a stress requirement of <1000 MPa.

[0081] In an embodiment of the present application, the method for growing the sensitive film layer is selected from sputtering film formation; wherein the sputtering film formation operation comprises: first forming a ZnO film and then forming a TiO2 film.

[0082] In the present application, a ZnO film is first formed on the first protective layer, and then a TiO2 film is formed on the ZnO film, which is deposited in layers, thereby reducing the lattice stress when ZnO and TiO2 are directly mixed.

[0083] Preferably, the sputtering film formation operation conditions of the ZnO film include: a sputtering temperature of 500-550°C, a sputtering pressure of vacuum, an inert gas selected from argon, and a target material selected from high-purity (e.g., purity ≥99.99%, 4N grade) Zn target material.

[0084] Preferably, the sputtering film formation operation conditions of the TiO2 film include: a sputtering temperature of 450-500°C, a sputtering pressure of vacuum, an inert gas selected from argon, and a target material selected from high-purity (e.g., purity ≥99.995%, 4N5 grade) Ti target material.

[0085] In the present application, by controlling the operation conditions of sputtering, a ZnO film and a TiO2 film with a thickness of each independently can be formed. Further preferably, the thickness of the ZnO film is greater than the thickness of the TiO2 film, for example, the thickness of the ZnO film is and the thickness of the TiO2 film is

[0086] In step (3):

[0087] In an embodiment of the present application, both the first etching and the second etching are photoresist etching; wherein the photoresist etching is preferably dry etching.

[0088] In the present application, without special instructions, the present application does not have special limitations on dry etching and its operation conditions, and a conventional method can be used, i.e., first image the photoresist, and then etch with etching gas.

[0089] In an embodiment of the present application, the etching gas in the first etching is selected from Cl2 and HBr, and the minimum CD (i.e., critical dimension) after the first etching is 50±5 μm, serving as a pad bottom structure support layer.

[0090] In one embodiment of the present application, the etching gas in the second etching includes Cl2 and CF4, the first protective layer is etched by Cl2 to form the second via hole, and then the first insulating layer is etched by CF4 to form the first via hole; the minimum CD of the second etching is 10±2 μm. In the present application, the first via hole and the second via hole are VIA openings, which are used to set metal leads and provide metal electrical connection channels.

[0091] In step (4):

[0092] In one embodiment of the present application, the method for growing the metal layer is selected from magnetron sputtering; wherein the operating conditions of the magnetron sputtering include: the target material is selected from an aluminum target, the sputtering power is 100-500 W, and the deposition rate is 0.1-1.0 μm / min. The gas pressure is 2-10 mTorr.

[0093] In the present application, by adjusting the operating conditions of the magnetron sputtering, a metal layer with a thickness of 0.1-1.0 μm can be grown, and the metal (for example, aluminum) can fill the second via hole and the first via hole.

[0094] In step (5):

[0095] In one embodiment of the present application, the third etching is photoresist etching; wherein the photoresist etching is preferably dry etching.

[0096] In the present application, the etching gas in the third etching is selected from Cl2, and the minimum CD after the third etching is 30±2 μm. The third etching is used to etch a circuit pattern on the metal layer, that is, to set metal leads between the first protective layer and the second insulating layer.

[0097] In step (6):

[0098] In one embodiment of the present application, the method for growing the second insulating layer includes: contacting the silicon wafer after the third etching with oxygen, and performing an oxidation reaction at 200-400 °C to grow the second insulating layer on the metal layer. By controlling the operating conditions of the oxidation reaction, a second insulating layer with a thickness of 0.1-1.0 μm can be grown.

[0099] In one embodiment of the present application, the method for growing the second protective layer includes: contacting the silicon wafer after the growth of the second insulating layer with SiH4, and performing a redox reaction at a growth temperature of 200-400 °C and a growth pressure of 50-100 pa to grow the second protective layer on the second insulating layer. By controlling the operating conditions of the redox reaction, a second protective layer with a thickness of 0.1-1.0 μm can be grown.

[0100] ​​​In step (7):

[0101] In an embodiment of the present application, the fourth etching is photoresist etching; wherein the photoresist etching is preferably dry etching.

[0102] In the present application, the etching gas in the fourth etching includes Cl2 and CF4, the second protective layer is etched by Cl2 to form the fourth through hole, and then the second insulating layer is etched by CF4 to form the third through hole; the minimum CD after the fourth etching is 80±5 μm. In the present application, the third through hole and the fourth through hole are pad openings, which are used to absorb mechanical stress during chip packaging, reduce the risk of bond wire falling off, and provide a metal electrical connection channel.

[0103] In step (8):

[0104] In an embodiment of the present application, the fifth etching is KOH wet etching.

[0105] In the present application, the KOH wet etching is not specially limited, and the KOH wet etching method known in the art can be used for etching. Through KOH wet etching, a cavity silicon cup structure, i.e. a silicon cup structure, can be formed on the back of the silicon wafer. The etching depth of the cavity is 300-500 μm, and the etching width is 700-900 μm.

[0106] In step (9):

[0107] In an embodiment of the present application, the thickness of the substrate is 1000±30 μm, and the substrate is selected from glass, preferably double-sided polished glass.

[0108] The preparation method of the MEMS pressure sensor described above in the present application will be further described below in combination with specific examples.

[0109] Example 1:

[0110] (1) The surface of the silicon wafer is ion implanted with N+, with a Phos dose of 5e15 cm -2 , an energy of 80 keV, an inclination angle of 7°, and an implantation junction depth of 40 μm; ion implanted with P+, with a Boron dose of 1e16 cm -2 , an energy of 60 keV, an inclination angle of 7°, and an implantation junction depth of 25 μm; ion implanted with P-, with a Boron dose of 3e14 cm -2 , an energy of 40 keV, an inclination angle of 7°, and an implantation junction depth of 15 μm, to form an ion implantation block doped layer.

[0111] (2) After the ion implantation is completed, O2 is introduced into the furnace tube, and the temperature is adjusted to 1100℃, to grow a thickness of SiO2 film as the first insulating layer;

[0112] After the first insulating layer is grown, SIH2Cl2 and NH3 are introduced into the furnace tube, the temperature is adjusted to 700°C, the growth pressure interval is 25 pa, and the growth thickness is SiN film as the first protective layer, the stress requirement of the first protective layer is <1000 Mpa;

[0113] After the first protective layer is grown, a PVD technology is used, a high-purity Zn target is selected and placed in a sputtering machine to generate a sensitive film layer. In a vacuum environment, argon is ionized into ions, argon ions are made to bombard the Zn target by applying a voltage, the deposition temperature is 550°C, and a ZnO film with a thickness of is formed; After that, a high-purity titanium target is replaced, a TiO2 film with a thickness of is formed at a deposition temperature of 450°C;

[0114] (3) After the sensitive film layer is grown, a photoetching image is formed, and Cl2 and HBr gases are used for the first dry etching of the sensitive film layer. The minimum CD after etching is 50±5 μm, which is used as the pad bottom structure support layer;

[0115] After the sensitive film layer is etched, a photoetching image is formed, and Cl2 and CF4 are used for the second dry etching of the first insulating layer and the first protective layer, respectively. The VIA opening (i.e., the first via and the second via) is left after etching, the minimum CD is 10±2 μm, and a metal electrical connection channel is provided;

[0116] (4) After the second dry etching is completed, a magnetron sputtering technology is used for deposition. Under the conditions of a sputtering power of 300 W, a deposition rate of , and a gas pressure of 7 mTorr, an aluminum metal layer with a thickness of is generated to fill the VIA channel (i.e., the first via and the second via);

[0117] (5) After the aluminum metal layer is grown, a photoetching image is formed, and Cl2 is used for the third dry etching of the aluminum metal layer to etch out the circuit diagram of the aluminum metal layer to form a metal lead. The minimum CD after the third dry etching is 30±2 μm;

[0118] (6) After the third dry etching is completed, the furnace tube temperature is adjusted to 300°C, O2 is introduced, and a SiO2 film with a thickness of is grown as the second insulating layer;

[0119] After the second insulating layer is grown, the furnace tube temperature is adjusted to 300°C, SiH4 is introduced, and a SiN film with a thickness of is grown as the second protective layer;

[0120] (7) After the second protective layer is grown, it is patterned by photolithography. Cl2 and CF4 are used to perform the fourth dry etching on the second insulating layer and the second protective layer respectively. After etching, the pad opening of the aluminum metal layer (i.e. the third and fourth through holes) is opened, and the minimum CD is 80±5μm.

[0121] (8) After the fourth dry etching is completed, KOH wet etching is performed on the back of the silicon wafer to form a cavity silicon cup structure. The cavity has an etching depth of 400 μm and a width of 800 μm.

[0122] (9) The back side of the silicon wafer, that is, the side with the cavity silicon cup structure, is anodicly bonded to a bonding glass with a thickness of 1000μm to obtain a MEMS pressure sensor wafer.

[0123] Example 2

[0124] Similar to Example 1, except that a thickness of [missing information] is formed. The ZnO film and its thickness are TiO2 film.

[0125] Comparative Example 1

[0126] Similar to Example 1, the difference lies in the sensitive film layer in step (2), where a phosphorus-doped Dpoly layer is used instead of the ZnO film and TiO2 film as the sensitive film layer.

[0127] Step (2): After the first protective layer has grown, SiH4 and PH3 are introduced into the furnace tube, and the temperature is adjusted to 620℃. The growth thickness is [missing information]. A phosphorus-doped D-poly membrane was used as the sensitive membrane layer.

[0128] Comparative Example 2

[0129] Similar to Example 1, except that the TiO2 film is omitted in step (2), and only the ZnO film is used in the sensitive film layer.

[0130] Step (2): After the first protective layer has grown, PVD technology is used to select a high-purity Zn target and place it in a sputtering machine to generate a sensitive film. In a vacuum environment, argon gas is ionized into ions, and a voltage is applied to bombard the Zn target with these ions. The deposition temperature is 550℃, forming a film with a thickness of [missing information]. ZnO membrane.

[0131] Test case

[0132] The high-temperature stability, power consumption, and piezoelectric / piezoresistive signal-to-noise ratio of the MEMS pressure sensor wafers prepared in Examples 1-2 and Comparative Examples 1-2 were tested. The test methods and results are shown in Table 1.

[0133] The temperature drift rate of the wafer in Example 1-2 and Comparative Example 1-2 is tested with reference to GB / T 2423.22 (Environmental testing for electrotechnical products - Part 2: Tests - Test 2b: Change in temperature), and the temperature test interval is 85℃-150℃. The smaller the temperature drift is, the better the high-temperature stability of the wafer is.

[0134] The static power consumption of the wafer in Example 1-2 and Comparative Example 1-2 is tested with reference to GBT·30269.8-2019 (Information technology - Sensor networks - Part 8: Power consumption test methods). The lower the static power consumption is, the higher the energy efficiency of the wafer is.

[0135] The piezoelectric / piezoresistive response signal-to-noise ratio (SNR) of the wafer in Example 1-2 and Comparative Example 1-2 is tested with reference to GB / T 34070-2018 Performance test methods for MEMS piezoresistive pressure sensors. The larger the SNR is, the higher the sensitivity of the wafer is.

[0136] Table 1

[0137]

[0138] As shown in Table 1, the MEMS pressure sensor wafer in the application has the advantages of good high-temperature stability, ultra-low power consumption characteristics and high sensitivity. By comparing Example 1 and Comparative Example 1-2, it can be seen that the MEMS pressure sensor wafer provided in the application can greatly improve the high-temperature resistance, energy efficiency and sensitivity of the MEMS pressure sensor by using ZnO film and TiO2 film as the sensitive film layer.

[0139] Test Example 2

[0140] The environmental aging resistance performance of the wafer in Example 1-2 and Comparative Example 1-2 is tested in a constant temperature and humidity test chamber (85℃ / 85%RH) with reference to GB / T 2423.3-2016 Environmental testing for electrotechnical products - Part 2: Test methods - Test Cab: Constant humidity test, and the piezoelectric material sensitivity d 33 of the wafer is recorded after 1000 hours of aging test. The performance retention rate is calculated according to the formula: performance retention rate = (piezoelectric material sensitivity d 33 after aging / piezoelectric material sensitivity d 33 initial) * 100%, and the test results are shown in Table 2.

[0141] Table 2

[0142] initial d 33 (pC / N) After aging d 33 (pC / N) Performance retention Example 1 350 346.5 99％ Example 2 345 327.8 95％ Comparative Example 1 340 312.8 92％ Comparative Example 2 320 272.0 85％

[0143] As shown in Table 2, the sensitivity of the MEMS pressure sensor wafer in the application can be maintained above 95% after 1000 hours of aging. By comparing Example 1 and Example 2, it can be seen that adjusting the thickness of the ZnO film and the TiO2 film helps to further improve the sensitivity and environmental aging resistance of the MEMS pressure sensor wafer.

[0144] By comparing Example 1 and Comparative Example 1-2, it can be seen that the MEMS pressure sensor wafer provided in the application, using ZnO film and TiO2 film as the sensitive film layer, helps to greatly improve the environmental aging resistance of the wafer.

[0145] The above is only a preferred specific embodiment of the application, but the protection scope of the application is not limited to this. Any changes or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed by the application should be covered within the protection scope of the application. Therefore, the protection scope of the application should be subject to the protection scope of the claims.

Claims

1. A MEMS pressure sensor wafer, comprising: The substrate (1), and the silicon wafer (2), the first insulating layer (3), the first protective layer (4) and the sensitive film layer (5) arranged on the substrate (1) in sequence, characterized in that the sensitive film layer (5) comprises a ZnO film (51) and a TiO2 film (52) arranged on the ZnO film (51), wherein the ZnO film (51) is in contact with the first protective layer (4).

2. The MEMS pressure sensor wafer of claim 1, wherein, The thickness of the substrate (1) is 1000±30μm; And / or, the substrate (1) is selected from glass, preferably double-sided polished glass.

3. The MEMS pressure sensor wafer of claim 1 or 2, wherein, The silicon wafer (2) is a hollow silicon cup structure, provided with a hollow cavity (21) on the side facing the substrate (1) and an ion implantation region (22) on the side away from the substrate (1); the ion implantation region (22) comprises an N+ implantation region (221), a P- implantation region (222) and a P+ implantation region (223).

4. The MEMS pressure sensor wafer of any of claims 1-3, wherein, The first insulating layer (3) is selected from a SiO2insulating layer; the thickness of the first insulating layer (3) is A first through hole is arranged on the first insulating layer (3); Preferably, said first protective layer (4) is selected from a SiN protective layer; the thickness of said first protective layer (4) is A second through hole is arranged on said first protective layer (4); wherein said second through hole is in communication with said first through hole.

5. The MEMS pressure sensor wafer of claim 4, wherein, The sensitive film layer (5) covers part of the surface of the first protective layer (4); Preferably, in the sensitive film layer (5), the thickness of the ZnO film (51) is the thickness of the TiO2 film (52) is 6. The MEMS pressure sensor wafer of claim 1, wherein, The wafer further comprises a second insulating layer (6) and a second protective layer (7); Wherein, the second insulating layer (6) is arranged on the sensitive film layer (5) and in contact with the first protective layer (4), and the second protective layer (7) is arranged on the second insulating layer (6).

7. The MEMS pressure sensor wafer of claim 6, wherein, The second insulating layer (6) is selected from a SiO2insulating layer, and the thickness of the second insulating layer (6) is A third through hole is arranged on the second insulating layer (6); wherein the third through hole is in communication with the second through hole; Preferably, said second protective layer (7) is selected from a SiN protective layer, the thickness of said second protective layer (7) being comprised between 50 nm and 200 nm, preferably between 70 nm and 150 nm, more preferably between 80 nm and 120 nm. A fourth through hole is arranged on the second protective layer (7); wherein the fourth through hole is in communication with the third through hole.

8. The MEMS pressure sensor wafer of claim 7, wherein, The wafer further comprises a metal lead (8); wherein the metal lead (8) is used to connect the silicon wafer (2), the first insulating layer (3), the first protective layer (4), the sensitive film layer (5) and the second insulating layer (6); Preferably, the metal lead (8) is arranged in a first through hole of the first insulating layer (3), a second through hole of the first protective layer (4) and a third through hole of the second insulating layer (7); Preferably, the metal lead (8) fills the first through hole and the second through hole, and is partially filled in the third through hole; Preferably, the metal lead (8) is further arranged between the first protective layer (4) and the second insulating layer (6).

9. A method of fabricating a MEMS pressure sensor wafer, the method comprising: The method comprises the following steps: (1) performing ion implantation on the front surface of the silicon wafer to form an ion implantation region comprising an N+ implantation region, a P+ implantation region and a P- implantation region; (2) after the ion implantation is completed, sequentially growing a first insulating layer, a first protective layer and a sensitive film layer on the front surface of the silicon wafer; wherein the sensitive film layer comprises a ZnO film and a TiO2 film arranged on the ZnO film, and the ZnO film is in contact with the first protective layer; (3) first etching the sensitive film layer, then second etching the first protective layer and the first insulating layer to form a second through hole in the first protective layer and a first through hole in the first insulating layer; wherein the first through hole and the second through hole are in communication; (4) after the second etching is completed, growing a metal layer on the sensitive film layer and filling the second through hole and the first through hole; (5) after the metal layer is grown, third etching the metal layer to form a metal lead; (6) after the third etching is completed, sequentially growing a second insulating layer and a second protective layer on the surface where the metal lead is generated. (7) After the second protective layer is grown, the second protective layer and the second insulating layer are etched for the fourth time to form a fourth through hole in the second protective layer and a third through hole in the second insulating layer; wherein the second through hole, the third through hole and the fourth through hole are communicated; (8) After the fourth etching is completed, the back surface of the silicon wafer is etched for the fifth time to form a cavity silicon cup structure; (9) After the fifth etching is completed, the back surface of the silicon wafer is anodically bonded to the base material to obtain a MEMS pressure sensor wafer.

10. The method of claim 9, wherein, The method for growing the sensitive film layer is selected from sputtering film coating; wherein the sputtering film coating operation comprises: first forming a ZnO film on the surface where the metal lead is generated, and then forming a TiO2 film on the ZnO film; Preferably, the sputtering film coating operation conditions of the ZnO film include: a sputtering temperature of 500-550 DEG C, a sputtering pressure of vacuum, an inert gas selected from argon, and a target material selected from high-purity Zn target material; Preferably, the sputtering film coating operation conditions of the TiO2 film include: a sputtering temperature of 450-500 DEG C, a sputtering pressure of vacuum, an inert gas selected from argon, and a target material selected from high-purity Ti target material.

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