Heterojunction-ferroelectric bimodal reconfigurable transistor

Abstract

The invention provides a dual-mode reconfigurable transistor based on heterojunction-ferroelectric. The dual-mode reconfigurable transistor comprises the following layer structures which are sequentially stacked from top to bottom: a top gate, an electrolytic layer, a porous contact layer, a heterojunction layer, a ferroelectric layer, a nanowire channel, a coupling capacitor, an isolation layer, a P-type substrate and a back gate, the two ends of the nanowire channel are connected with the source electrode and the drain electrode to form a current path, and the nanowire channel is surrounded by a ring gate; the heterojunction layer is used for adsorbing environmental ions and outputting a surface charge density change signal; the ferroelectric layer is used for amplifying an output signal of the heterojunction layer through a negative capacitance effect and generating a ferroelectric output voltage; the porous contact layer is used to allow ion permeation but block electron conduction. The system has the bimodal working capability, can realize the sensing-logic integration function in an integrated manner, and relieves the contradiction between the system efficiency and the power consumption in a traditional discrete scheme.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a heterojunction-ferroelectric dual-mode reconfigurable transistor. BACKGROUND

[0002] The traditional sensor and logic chip separation mode has the bottleneck of low system efficiency, high power consumption and poor real-time performance, and the bio-information security also faces the challenge of lack of key management and hardware encryption, and the Nernst limit and environmental adaptability of the traditional ISFET restrict the sensing performance. Although the two-dimensional material heterojunction sensor improves the sensitivity, the ferroelectric material shows the computing potential, and the reconfigurable transistor promotes the innovation of logic function, but the three have not realized functional integration.

[0003] Under this background, the present application focuses on the vertical integration of two-dimensional heterojunction and ferroelectric layer, aiming to break through the "sensing-computing" separation limitation, and build a dual-mode reconfigurable transistor with high sensitivity, fast response (<50ms) and hardware encryption capability, to provide an integrated solution for biomedical instant diagnosis, industrial intelligent control and Internet of Things security. SUMMARY

[0004] In view of the above situation, the main purpose of the present application is to provide a heterojunction-ferroelectric dual-mode reconfigurable transistor to solve the above technical problems.

[0005] The present application provides a heterojunction-ferroelectric dual-mode reconfigurable transistor, which comprises the following layer structures stacked from top to bottom in turn: Top gate, electrolyte layer, porous contact layer, heterojunction layer, ferroelectric layer, nanowire channel, coupling capacitor, isolation layer, P-type substrate and back gate; The two ends of the nanowire channel are connected with the source and the drain to form a current path, and the nanowire channel is surrounded by a ring gate; The heterojunction layer is used for adsorbing environmental ions and outputting surface charge density change signal; The ferroelectric layer is used for amplifying the output signal of the heterojunction layer through negative capacitance effect with the coupling capacitor, and generating a ferroelectric output voltage; The porous contact layer is used to allow ion penetration but block electron conduction; The transistor has dual-mode working capability: Sensing mode: when the environmental pH value is 5-9, the output voltage signal linearly related to pH is outputted; Logic mode: when the environmental pH value is <5 or >9, it switches to logic operation state, and outputs an alarm signal through the drain.

[0006] Compared with the prior art, the present application has the following advantages: The application provides a new solution for breaking through the technical bottleneck of low system efficiency and high power consumption in the traditional sensor and logic chip separate mode by the closed-loop design of "sensing signal-ferroelectric amplification-multi-gate regulation". Compared with the problem of large signal transmission loss and limited collaborative response speed caused by the independent work of sensors and logic chips in the traditional separate design, the design improves the electric field coupling efficiency between functional modules to a certain extent and reduces the power consumption overhead caused by the interconnection of separate devices by vertically integrating two-dimensional heterojunction and ferroelectric layer, thereby providing a more optimal physical architecture selection for realizing the integration of sensing and logic functions. The integrated mode is expected to alleviate the contradiction between system efficiency and power consumption in the traditional separate scheme in the scenes of biomedical instant diagnosis and industrial intelligent control, and provides an implementation path with reference value for the technical upgrading in the related field.

[0007] Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following description and drawings. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 An explosion diagram of the heterojunction-ferroelectric dual-mode reconfigurable transistor according to the application is provided; Figure 2 A cross-sectional view of the heterojunction-ferroelectric dual-mode reconfigurable transistor according to the application is provided; Figure 3 A signal flowchart of the heterojunction-ferroelectric dual-mode reconfigurable transistor according to the application is provided; Figure 4 A flowchart of the specific implementation process of the logic circuit in the logic mode according to the application is provided; 1. Top gate, 2. Electrolytic layer, 3. Porous contact layer, 4. Heterojunction layer, 5. Ferroelectric layer, 6. Ring gate, 7. Nanowire channel, 8. Source, 9. Drain, 10. Coupling capacitor, 11. Isolation layer, 12. P-type substrate, 13. Back gate, 14. Ion transfer path, 15. Coupling path. DETAILED DESCRIPTION

[0009] The embodiments of the application are described in detail below, and examples of the embodiments are shown in the drawings, wherein the same or similar reference signs represent the same or similar elements or elements having the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the application, and cannot be understood as a limitation of the application.

[0010] These and other aspects of embodiments of the present application will become clear from the following description and the accompanying drawings. In the description and drawings, particular embodiments of the application are disclosed in detail, which represent some ways of implementing the principles of the application, but it should be understood that the scope of the embodiments of the present application is not limited thereto.

[0011] Referring to Figure 1 and Figure 2 , the embodiment provides a heterojunction-ferroelectric dual-mode reconfigurable transistor, which comprises the following layer structures stacked from top to bottom in order: top gate 1, electrolyte layer 2, porous contact layer 3, heterojunction layer 4, ferroelectric layer 5, nanowire channel 7, coupling capacitor 10, isolation layer 11, P-type substrate 12 and back gate 13; The two ends of the nanowire channel are connected to the source 8 and the drain 9 to form a current path, and the nanowire channel is surrounded by a ring gate 6; Top gate, the material used in the embodiment is TiN, which is in physical contact with the upper surface of the ferroelectric layer; as an external voltage input port, the top gate voltage V G The polarization direction and intensity of the ferroelectric layer are controlled, and by changing the polarization direction and intensity of the ferroelectric layer, the surface charge distribution of the heterojunction is indirectly affected, and the electrical behavior of the entire device is controlled.

[0012] Electrolyte layer, the material used in the embodiment is KCL solution, and the lower surface is in direct contact with the porous SiO2 contact layer. Through the porous contact layer provided below, it is indirectly coupled (ion-permeable contact) with the heterojunction layer, providing an ion environment. When detecting the pH of the solution, the change in the concentration of H + The concentration change will drive the subsequent sensing and logic response, which is equivalent to providing the device with "environmental information" medium.

[0013] Porous contact layer, the material used in the embodiment is porous SiO2, with a thickness of 100 nm, and the upper surface is in contact with the electrolyte layer and the lower surface is in contact with the heterojunction layer; its porous structure allows ions in the KCl electrolyte layer to penetrate to the heterojunction surface, while blocking direct conduction of electrons, ensuring that "ion signals can be transmitted and electronic signals are not short-circuited", and creating conditions for the heterojunction to capture ion signals.

[0014] Heterojunction layer, the core "sensing unit"; in the embodiment, it is stacked by 3nm-thick WSe2 and 3nm-thick MoS2 two-dimensional materials, and the heterojunction surface charge adsorption effect parameters are: sensitivity 4.38V / pH, detection range pH 3-11. The lower surface of the heterojunction layer is in contact with the ferroelectric layer, and the upper side is indirectly coupled with the electrolyte layer through the porous SiO2 contact layer. By using the high surface energy and type II band alignment characteristics of two-dimensional materials, H +The adsorption will change the heterojunction interface dipole layer, change the surface charge density, convert the "ion environment stimulation" into "measurable electrical signal", and provide the original input for subsequent signal amplification and logic operation.

[0015] The ferroelectric layer; the material used in this embodiment is Al-doped HfO2 (Al-HfO2), with a thickness of 41 nm, and the upper surface is in contact with the heterojunction layer, and the lower surface is close to the SiO2 isolation layer. It is a signal amplification and coupling bridge. Based on the Landau-Khalatnikov equation, according to the polarization characteristics of the ferroelectric material itself, the weak charge signal from the heterojunction is amplified by using the negative capacitance effect, and the output voltage V FE = 4.38 x (7-pH) V, while the polarization charge is coupled with the heterojunction and nanowire channel electric field, realizing the transmission of "sensing signal to logic signal".

[0016] Nanowire channel; the material used in this embodiment is Si (with a diameter of 10 nm, n / p gradient doping, and the surface is n + type, and the core is p type), and the n / p gradient doping characteristics of the channel provide the basis for carrier transport and threshold voltage regulation, which is the physical carrier for executing logic operations. The nanowire channel is located in the center of the ring gate, and the two ends are connected to the source and the drain, respectively, forming a current path. The lower surface is close to the SiO2 isolation layer, which is the "logic operation core". By controlling the distribution and transport of carriers in the channel through multiple gates (top gate, back gate, ring gate), current on-off control is realized. When the sensing signal (ferroelectric output voltage V FE ) from the ferroelectric layer is coupled to the channel, the threshold voltage will change accordingly (0.4V / 0.8V / 1.2V), and then the logic operations such as AND, OR, and NOT are performed, converting "environmental sensing information" into "digital logic results".

[0017] Isolation layer; the material used in this embodiment is dense SiO2, with a thickness of 10 nm, and the upper surface is close to the ferroelectric layer and nanowire channel, and the lower surface is in contact with the P-type Si substrate, which is an "electrical isolation and electric field transmission layer". On the one hand, it isolates the Si nanowire channel from the P-type Si substrate to prevent direct short circuiting and ensure the stability of the electrical environment for logic operation; on the other hand, it allows the electric field of the ferroelectric layer and the back gate to penetrate, providing a physical basis for regulating the threshold voltage of the nanowire channel, realizing "non-contact electric field control".

[0018] P-type substrate; the material used in this embodiment is Si, with a doping concentration of 1 x 10 15 cm -3 , the upper surface is in contact with the SiO2 isolation layer, and the lower surface is in contact with the back gate, which is a "physical support and potential reference body". As the base of the entire device, it provides mechanical stability; at the same time, by connecting with the back gate, it provides a stable potential reference for the device, ensuring that the measurement and regulation of electrical signals of each layer have a unified reference.

[0019] Back gate; The material used in this embodiment is Al, which is in direct contact with the lower surface of the P-type Si substrate, serving as the "auxiliary threshold control end". An electric voltage V BG， Through the electric field coupling of the substrate and the SiO2 isolation layer, the threshold voltage of the Si nanowire channel is fine-tuned, mainly for temperature compensation and mode switching, to improve the stability and adaptability of device operation.

[0020] Source and drain; The material used in this embodiment is Al, which is connected to both ends of the Si nanowire channel, forming a current loop of "source → nanowire channel → drain", serving as the "input and output interface of logic signals". The source inputs the electrical signal to be operated (such as high and low levels), and the drain outputs the result after logic operation on the nanowire channel (such as outputting a high level alarm when pH is abnormal), realizing the "in" and "out" of electrical signals, and giving the logic operation practical application value.

[0021] Ring gate, the material used in this embodiment is TiN, in a closed ring structure, completely surrounding the Si nanowire channel, serving as a "uniform electric field controller". By applying a voltage to the ring electrode, a uniform electric field is formed around the nanowire channel in three-dimensional space, making up for the unevenness of the top gate and back gate electric field, ensuring more uniform distribution and transport of carriers in the channel, improving the precision and stability of logic operation, and avoiding logic errors caused by uneven electric field.

[0022] Coupling capacitor, the material used in this embodiment is TiN, with a unit of 10fF. The coupling capacitor has the function of efficiently coupling the electric field, helping to transfer the electric field through the induction effect, reducing signal attenuation during regulation, and making the ferroelectric layer output voltage V FE accurately become the logic operation instruction of the nanowire channel.

[0023] The transistor disclosed in this embodiment has a dual-mode working capability, including a sensing mode and a logic mode, as follows: Sensing mode: The device senses the environmental ion concentration (pH 5-9) and outputs an electrical signal linearly related to pH, with the core function of "environmental monitoring". In the sensing mode, the pH action range is 5≤pH≤9, the ferroelectric output voltage V FE is between -9.4V and 9.4V, the nanowire channel threshold V TH is 0.8V (default value), and the typical response time in the signal amplification stage is less than 10ms.

[0024] Logic mode: When the pH is abnormal (<5 or >9), the device switches to a logic operation state and outputs an alarm signal, with the core function of "abnormal response".

[0025] When in the logic mode (acidic pH <5), the pH action range is pH <5, and the ferroelectric output voltage VFE greater than 9.4V, nanowire channel threshold V TH is 1.2V, and the typical response time of the whole process is less than 50ms.

[0026] While the logic mode (alkaline pH>9), the pH action range is pH>9, and the ferroelectric output voltage V FE less than -9.4V, nanowire channel threshold V TH is 0.4V, and the typical response time of the whole process is also less than 50ms.

[0027] In order to more clearly illustrate the principles of the present application and the process of implementation, various components are divided into sensing module, electric field coupling interface and logic module.

[0028] The sensing module is composed of an electrolyte layer + WSe2 / MoS2 heterojunction layer (3nm / 3nm) + Al:HfO2 ferroelectric layer (41nm) + porous SiO2 contact layer (100nm), which functions to sense ion concentration and amplify the signal through negative capacitance effect, and output the ferroelectric output voltage V FE =4.38×(7-pH)V. As can be seen from the ion transmission path 14 of the electrolyte layer, the porous contact layer and the heterojunction layer, the electrolyte layer is located at the top as the input source of the environmental pH signal, and H + is transmitted to the porous SiO2 contact layer below through ion permeation, which is the starting point of the "ion environmental information" into the device.

[0029] The porous contact layer connects the electrolyte layer and the heterojunction layer, allowing H + to permeate to the surface of the heterojunction, while blocking the electron conduction, ensuring that the ion signal is transmitted to the sensing core in one direction. The heterojunction layer as the sensing core, adsorbs H + and changes the surface charge density, converting the "ion signal" into "charge signal", and directly transmitting it to the ferroelectric layer below. After receiving the charge signal of the heterojunction, the ferroelectric layer amplifies it through negative capacitance effect, and outputs the ferroelectric output voltage V FE =4.38×(7-pH)V, which is in physical contact with the top gate, providing the original amplified signal for the logic module.

[0030] As can be seen from the coupling path 15 of the heterojunction layer, the ferroelectric layer and the nanowire channel. The electric field coupling interface is the "signal bridge" between the sensing module and the logic module, which receives the ferroelectric output voltage V FE signal output by the ferroelectric layer on one hand, and receives the control voltage coupled by the top gate V G =0.1×V FE on the other hand, and transmits these signals to the Si nanowire channel below through electric field penetration, realizing "non-contact transmission of electrical signals from the sensing module to the logic module".

[0031] The logic module consists of a top gate, a ring gate, a back gate, a nanowire channel, an isolation layer, a source, and a drain. The top gate is in direct contact with the ferroelectric layer, transmitting the ferroelectric output voltage V. FE Proportional conversion to a top gate voltage V suitable for logic control G The input electric field coupling region participates in the threshold voltage regulation of the nanowire channel. A ring gate surrounds the nanowire channel, providing a uniform electric field to ensure uniform carrier distribution within the channel and improve logic operation accuracy. The back gate directly contacts the lower surface of the p-type Si substrate, fine-tuning the threshold voltage of the Si nanowire channel, compensating for temperature drift and mode switching, and working with the top gate to achieve multi-gate coordinated regulation. The nanowire channel is the core carrier for logic operations; after receiving the electric field signal transmitted from the coupling region, it adjusts the threshold voltage according to the top gate voltage V. G By varying the threshold voltage (0.4V / 0.8V / 1.2V), NAND / XOR logic operations are performed, and the result is output through a current loop formed by the source and drain. An isolation layer is located beneath the nanowire, providing electrical isolation while allowing electric field penetration, ensuring signal isolation and stable operation between the logic module and the underlying substrate. The source and drain are connected to the two ends of the nanowire, forming a current path. The source inputs the signal to be processed, and the drain outputs the logic operation result (such as an alarm signal in case of pH abnormality), completing the logical closed loop of "signal input-operation-output".

[0032] The transistor disclosed in this embodiment is in a sensing mode under normal conditions. During pH environment monitoring, the pH threshold trigger logic is triggered when the H+ in the electrolyte... + When the concentration exceeds the critical value: Acid trigger: pH < 5 → H + Concentration >10 -5 mol / L → Heterojunction surface charge density > 3 × 10 12 cm -2 →V FE >9.4V; At this point, it automatically switches to logic mode, triggering multi-gate collaborative modulation to regulate the threshold voltage steps of the Si nanowire channel; Alkaline trigger: pH>9→H + Concentration <10 -9 mol / L → Heterojunction surface charge density < -3×10 12 cm -2 →V FE When the voltage drops below -9.4V, the system automatically switches to logic mode, triggering multi-gate collaborative regulation to control the threshold voltage gradient of the Si nanowire channel.

[0033] The multi-gate coordinated modulation in mode switching is as follows: (1) Top gate: Signal mapping to the threshold voltage V of the Si nanowire channel TH Regulation of the control benchmark Voltage relationship: V G = 0.1 x V FE The amplified high voltage of the ferroelectric layer is mapped to a suitable voltage for nanowire regulation. Effect: Directly raise the nanowire threshold reference component, lay the foundation for threshold staging.

[0034] (2) Back gate: threshold staging fine-tuning and temperature compensation Voltage formula: V BG = c x (7 - pH), where c is 0.05V to 0.2V; when c is 0.05V, pH = 4, V BG = 0.15V; Dual function: fine-tune the threshold staging point; achieve temperature compensation coefficient through substrate electric field feedback.

[0035] In the above description, the example of the back gate voltage given by the embodiment is 0.05V, and under this voltage condition, the back gate is mainly used for threshold staging fine-tuning and temperature compensation. In order to ensure better results, after increasing the amplitude of the back gate voltage within 0.05V to 0.2V, the electric field of the back gate can more strongly penetrate the substrate and SiO2 isolation layer to act on the bottom of the Si nanowire channel, and cooperates with the ring gate to enhance the regulation effect, while retaining its temperature compensation and auxiliary mode switching functions; and the back gate applies electric field from the longitudinal direction, and the ring gate applies electric field from the radial direction, the two form a complement, further guaranteeing the uniformity of carrier distribution and the accuracy of threshold staging.

[0036] (3) Ring gate: channel carrier uniformity guarantee Structural effect: The closed ring electrode around the nanowire suppresses carrier distribution distortion through uniform electric field during mode conversion. Performance impact: Increases threshold staging accuracy and increases logic operation noise tolerance.

[0037] (4) Dynamic coupling mechanism of multi-gate cooperation The top gate, back gate, and ring gate do not work independently, but form a closed loop through "voltage linkage-electric field superposition-carrier cooperative regulation" to ensure the accuracy and stability of threshold staging during mode conversion: Voltage linkage logic: The top gate voltage V G = 0.1 x V FE is directly bound to the ferroelectric output voltage V FE , the back gate voltage V BG = 0.05 x (7 - pH) is indirectly proportional to the top gate through V FE = 4.38 x (7 - pH), realizing the voltage cooperation of "main regulation + fine-tuning".

[0038] Electric field superposition effect: the top gate electric field vertically penetrates the ferroelectric layer and the SiO2 isolation layer, and directly acts on the surface of the nanowire channel; the back gate electric field applies a longitudinal electric field from the bottom of the channel through the dielectric coupling of the substrate and the SiO2 isolation layer; the ring gate electric field uniformly wraps along the radial direction of the nanowire, forming a three-dimensional electric field superposition. The three work together to greatly reduce the standard deviation of the electric field intensity distribution in the channel, ensuring that the carrier concentration changes uniformly along the channel.

[0039] This multi-gate collaborative design not only realizes the precise mapping of "ferroelectric signal-logic threshold" through voltage linkage, but also guarantees the stability of mode conversion with the help of three-dimensional electric field superposition, which is the core support for the structure to realize the dual-mode reconfigurable function.

[0040] As shown in Figure 3 , Figure 3 the complete signal flow of the transistor dual-mode (sensing / logic) switching is presented: first, after the environmental pH value is input, the WSe2 / MoS2 heterojunction layer adsorbs H + ions, changes the surface charge density, and converts the chemical ion signal into an electrical charge signal; then, the Al:HfO2 ferroelectric layer amplifies the signal by negative capacitance effect and outputs V FE =4.38×(7-pH)V, the top gate adjusts the nanowire threshold reference component according to VG=0.1×V FE , the ring gate provides a radial uniform electric field to ensure stable carrier distribution, and the back gate applies a voltage V BG =0.05×(7-pH)V to adjust the voltage, fine-tune the threshold and compensate for temperature drift; the multi-gate collaboration makes the nanowire channel threshold step to 0.8V (pH 5-9), 1.2V (pH <5), and 0.4V (pH >9); finally, according to whether the pH is in the range of 5-9, the working mode is determined, the sensing mode is entered when the pH is normal to output the ferroelectric output voltage V FE monitors the environment, and the logic mode is entered when the pH is abnormal to perform NAND / XOR operation, and an alarm signal is output through the drain, forming a sensing-logic closed loop of "ion input-charge change-voltage amplification-threshold adjustment-mode switching" to realize dual-mode intelligent response.

[0041] As shown in Figure 4 , Figure 4 the specific implementation process of the logic circuit in the logic mode of the present application is shown, which is as follows: Core device: one dual-mode reconfigurable transistor is adopted, which integrates top gate, back gate, ring gate, nanowire channel, and source and drain, and is the basic hardware unit for realizing logic operation.

[0042] Input port: two logic input signals are set, which are mapped as back gate voltage V BG and ring gate voltage VRG , for inputting logic control information to the transistor.

[0043] Output port: with drain current I DS As output, the logic state is determined by judging the current size, when I DS >1μA is determined as logic "1", when I DS <0.1μA is determined as logic "0".

[0044] Trigger condition: when the solution pH<5, the transistor threshold voltage V TH =1.2V; when pH>9, V TH =0.4V, when the transistor meets this condition, it enters the logic mode and can perform logic operation.

[0045] Logic input A and back gate voltage: logic input A is used to control the back gate voltage offset, when A=1 (representing high level logic), V BG increases by 0.5V; when A=0 (representing low level logic), V BG decreases by 0.5V.

[0046] Logic input B and ring gate voltage: logic input B controls the ring gate voltage, when B=1, V RG =1.0V; when B=0, V RG =0V. The role of the ring gate is to provide a uniform electric field for the nanowire channel, ensuring the stability of the logic operation.

[0047] Top gate voltage: the top gate voltage V G is related to the output voltage V FE of the ferroelectric layer, and satisfies V G =0.1×V FE , while V FE is obtained by amplifying the pH signal by the ferroelectric layer, specifically V FE =4.38×(7-pH), which reflects the amplification effect of the ferroelectric layer on the pH signal.

[0048] NAND gate logic implementation (take pH=3 as an example, V TH =1.2V), when the solution pH=3, first calculate the output voltage V FE of the ferroelectric layer, according to the formula V FE =4.38×(7-3)=17.52V; and then get the top gate voltage V G =0.1×17.52=1.752V; the back gate basic voltage V BG（基础） =0.1×(7-3)=0.4V. The effective gate voltage V eff is obtained from V G , the offset back gate voltage V BG（偏移后） and the ring gate voltage V RGco-decision, i.e. V eff =V G +V BG（偏移后） +V RG , by comparing V eff with threshold voltage V TH =1.2V, to judge the on state of nanowire channel. The following is the logic input A and the logic input B different logic input signal logic result table.

[0049]

[0050] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent of the present application. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A heterojunction-ferroelectric dual-mode reconfigurable transistor, comprising: The structure comprises the following layers stacked from top to bottom: Top gate, electrolyte layer, porous contact layer, heterojunction layer, ferroelectric layer, nanowire channel, coupling capacitor, isolation layer, P-type substrate and back gate; The two ends of the nanowire channel are connected to the source and the drain to form a current path, and the nanowire channel is surrounded by a ring gate; The heterojunction layer is used to adsorb environmental ions and output surface charge density change signal; The ferroelectric layer is used to amplify the output signal of the heterojunction layer through negative capacitance effect and generate ferroelectric output voltage; The porous contact layer is used to allow ion penetration but block electron conduction; The transistor has a dual-mode working capability: Sensing mode: when the environmental pH value is between 5 and 9, the output is a voltage signal linearly related to pH; Logic mode: when the environmental pH value is <5 or >9, it switches to logic operation state and outputs an alarm signal through the drain.

2. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 1, wherein: The nanowire channel material is Si, the nanowire channel adopts n / p gradient doping, wherein the surface of the nanowire channel is n + type and the core is p type.

3. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 2, wherein the back gate cooperates with the top gate and the ring gate to regulate, which specifically includes: The bimodal of the transistor is cooperatively regulated by the back gate, top gate and ring gate according to the external environment pH value to regulate the threshold voltage V of the Si nanowire channel TH The corresponding relationship between the threshold voltage of the Si nanowire channel and the pH value is realized in stages: pH 5-9, V TH = 0.8 V; pH < 5, V TH = 1.2 V; pH > 9, V TH = 0.4 V.

4. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 3, wherein: The ring gate is used to suppress carrier distribution distortion through radial uniform electric field and lock the hierarchical value accuracy. Top gate voltage V G for providing a threshold voltage V TH Regulation reference; Back gate voltage V BG for fine tuning the threshold voltage V of Si nanowire channels TH of the stepwise points; 6. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 5, wherein:

5. The heterojunction-ferroelectric dual-mode reconfigurable transistor of claim 4, wherein: The voltage generated by the back gate satisfies V BG = c x (7 - pH), where c is 0.05 V to 0.2 V; When pH < 5 or pH > 9, the back gate cooperates with the top gate and the ring gate to regulate and drive the threshold voltage V of the Si nanowire channel TH Step to 1.2V or 0.4V, realize the switching of sensing mode to logic mode.

7. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 6, wherein: Top gate voltage V G Output voltage V of the ferroelectric layer FE Satisfies V G = 0.1 x V FE Output voltage of the ferroelectric layer satisfies V FE = k x (7 - pH), where k is 4.38 V / pH. The ring gate is a closed ring TiN electrode surrounding the Si nanowire channel, which is used to apply a uniform electric field in three-dimensional space to suppress carrier distribution distortion.

8. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 7, wherein: The surface charge density change triggers the ferroelectric layer to output a voltage VFE exceeding ±9.4V, which in turn activates the logic mode. The surface charge density of the heterojunction layer and H + The mapping relationship of the concentration is: pH < 5, H + Concentration > 10 -5 mol / L, heterojunction layer surface charge density > 3 x 10 12 cm -2 -2, ferroelectric layer output voltage V FE > 9.4 V; pH>9, H + Concentration <10 -9 mol / L, heterojunction layer surface charge density <-3×10 12 cm -2 , ferroelectric layer output voltage V FE <-9.4V; 9. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to claim 8, wherein: The logic mode supports NAND, XOR and inverter operations, and outputs a high-level alarm signal through the drain when the pH is abnormal; The response time of the sensing mode is <10ms, and the full-process response time of the logic mode is <50ms.

10. The heterojunction-ferroelectric dual-mode reconfigurable transistor according to any one of claims 1-9, wherein: The thickness of the porous contact layer is 100nm, the thickness of the ferroelectric layer is 41nm, and the heterojunction layer is composed of vertically stacked WSe2 and MoS2, wherein the thickness of WSe2 and MoS2 is 3nm. ​

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