Silicon capacitor wafer test system and test method
By integrating wafer acquisition and testing modules, automated parallel testing of silicon capacitor wafers is achieved, solving the problem of long testing time in existing technologies, improving testing efficiency and reducing the risk of damage, and making it suitable for mass production of silicon capacitor wafers.
Patent Information
- Application Number
- CN202511175812.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-21
- Publication Date
- 2025-11-07
AI Technical Summary
Existing silicon capacitor wafer testing solutions are time-consuming, resulting in low testing efficiency, especially for testing a large number of silicon capacitors on a single wafer.
The system employs an integrated wafer acquisition module and wafer testing module, including a control board, a digital bridge board, and a voltage and current source board, to achieve automated parallel testing, avoid interference from manual operation, and realize unmanned wafer management through a robotic arm and an automatic feeding device.
It improves the testing efficiency of silicon capacitor wafers, reduces testing time, and lowers the risk of damage caused by manual operation, making it suitable for mass production testing of silicon capacitor wafers.
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Figure CN120908633A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of wafer testing, in particular to a silicon capacitor wafer testing system and a testing method. BACKGROUND
[0002] A silicon capacitor wafer is a wafer material used for manufacturing silicon capacitors. In order to ensure the performance and reliability of the silicon capacitor wafer, the silicon capacitor wafer needs to be tested to find defective products, improve product yield, and ensure product quality and reliability.
[0003] For silicon capacitor wafer testing, the existing testing schemes are basically based on bench instruments and semi-automatic / manual probe stations. The bench instruments generally use LCR instruments and SMU instruments. During testing, the LCR instruments and the semi-automatic / manual probe stations are connected through signal connection cables, the wafer is manually placed on the tray of the probe station, and the needle is then poked into the wafer. The capacitance value of each capacitor is tested first, and after the entire wafer is tested, the SMU instruments and the semi-automatic / manual probe stations are connected, and the leakage current of each capacitor is tested.
[0004] However, with the continuous development of silicon capacitor technology and its wide application in the industry, a single wafer usually has 600,000-1,000,000 silicon capacitors. The number of silicon capacitors on a single wafer is large, and the existing testing scheme usually takes one to two days to test a single silicon capacitor wafer, which results in low testing efficiency of the silicon capacitor wafer. SUMMARY
[0005] In order to help solve the problem of long testing time of the silicon capacitor wafer, which results in low testing efficiency of the silicon capacitor wafer, the present application provides a silicon capacitor wafer testing system and a testing method.
[0006] In a first aspect, the present application provides a silicon capacitor wafer testing system, which adopts the following technical scheme: the silicon capacitor wafer testing system comprises a wafer acquisition module and a wafer testing module;
[0007] The wafer acquisition module is configured to automatically acquire a wafer to be tested when receiving a wafer testing instruction, and place the wafer to be tested at a preset testing position;
[0008] The wafer testing module is in communication connection with the wafer acquisition module, and is configured to test the wafer to be tested and output a testing result;
[0009] The wafer testing module comprises a control board card, a plurality of digital bridge board cards, and a plurality of voltage and current source board cards;
[0010] The control board card is in communication connection with the wafer acquisition module, and is configured to control the wafer testing module to test the wafer to be tested.
[0011] A plurality of the digital bridge board cards are in communication connection with the control board card for testing the capacitance value of the wafer under test in parallel;
[0012] A plurality of the voltage and current source board cards are in communication connection with the control board card for testing the leakage current of the wafer under test in parallel.
[0013] In a specific embodiment, the number of the digital bridge board cards is consistent with the number of the voltage and current source board cards.
[0014] In a specific embodiment, the wafer testing module further comprises a switch board card;
[0015] The switch board card is in communication connection with a plurality of the digital bridge board cards and a plurality of the voltage and current source board cards for switching the digital bridge board card test and the voltage and current source board card test.
[0016] In a specific embodiment, the switch board card comprises a plurality of relays, and the number of the relays is consistent with the number of the digital bridge board cards.
[0017] The communication connection between the switch board card and a plurality of the digital bridge board cards and a plurality of the voltage and current source board cards comprises:
[0018] Each of the relays comprises a common terminal and two contact terminals, one of the contact terminals is connected to one of the digital bridge board cards, the other of the contact terminals is connected to one of the voltage and current source board cards, and the common terminal is connected to the wafer acquisition module.
[0019] In a specific embodiment, the wafer acquisition module comprises a control device, a mechanical hand, and an automatic feeding device.
[0020] The control device is used to receive a wafer testing instruction and control the wafer acquisition module to automatically acquire a wafer under test according to the wafer testing instruction.
[0021] The automatic feeding device is in communication connection with the control device for storing and transmitting a wafer under test that needs to be tested.
[0022] The mechanical hand is in communication connection with the automatic feeding device for grabbing the wafer under test and placing the wafer under test at a preset testing position.
[0023] In a specific embodiment, the digital bridge board card is a single-channel LCR digital bridge board card, the frequency range of the single-channel LCR digital bridge board card is 40Hz-2MHz, the current sensitivity is 1fA, and the capacitance measurement accuracy is 0.15% @1pF.
[0024] In one specific implementation, the voltage current source board card is a single-channel SMU voltage current source board card, the voltage range of the single-channel SMU voltage current source board card is -200V-200V, and the current sensitivity is 10fA.
[0025] In one specific implementation, the silicon capacitor wafer test system further comprises a data recording module.
[0026] The data recording module is in communication connection with the wafer test module, and is configured to receive and record the test results of the wafer test module.
[0027] In a second aspect, the present application provides a silicon capacitor wafer test method, which adopts the following technical scheme: the method is applied to a silicon capacitor wafer test system, the silicon capacitor wafer test system comprises a wafer acquisition module, a wafer test module and a data recording module, and the method comprises the following steps:
[0028] Upon receiving a wafer test instruction, the wafer acquisition module is controlled to automatically acquire a wafer to be tested and place the wafer to be tested at a preset test position;
[0029] The wafer test module is controlled to test the wafer to be tested and generate test results;
[0030] The generated test results are transmitted to the data recording module for recording and storage.
[0031] In one specific implementation, the wafer test module comprises a plurality of digital bridge board cards, a plurality of voltage current source board cards and a switch board card.
[0032] The wafer test module is controlled to test the wafer to be tested and generate test results, which comprises the following steps:
[0033] The switch board card is controlled to connect a plurality of digital bridge board cards, a plurality of digital bridge board cards are used to perform parallel testing on the wafer to be tested, and a capacitance value result of the wafer to be tested is measured;
[0034] The switch board card is controlled to connect a plurality of voltage current source board cards, a plurality of voltage current source board cards are used to perform parallel testing on the wafer to be tested, and a leakage current value result of the wafer to be tested is measured;
[0035] The capacitance value result and the leakage current value result of the wafer to be tested are set as the test results.
[0036] In summary, the present application has the following beneficial technical effects:
[0037] 1. The wafer is automatically detected by integrating the wafer acquisition module and the wafer test module. During the detection process of the wafer, the user does not need to manually acquire the wafer, so as to avoid the risk of wafer damage, breakage, collision and contamination caused by manual acquisition of the wafer;
[0038] 2. By integrating the digital bridge board card and the voltage and current source board card, the continuity of the wafer can be tested, and the user does not need to reconnect the new board card for testing in the middle, avoiding the interference caused by manual operation, and improving the wafer test efficiency;
[0039] 3. By setting multiple digital bridge board cards and multiple voltage and current source board cards, the wafer can be tested in parallel by multiple board cards, so as to save time and improve the wafer test efficiency, which is suitable for mass production test of silicon capacitor wafers. BRIEF DESCRIPTION OF DRAWINGS
[0040] Figure 1 is a schematic diagram of a silicon capacitor wafer test system in the embodiment of the present application;
[0041] Figure 2 is a test machine configuration diagram in the embodiment of the present application;
[0042] Figure 3 is a schematic diagram of the test machine board card connection in the embodiment of the present application;
[0043] Figure 4 is a flowchart of the silicon capacitor wafer test method in the embodiment of the present application. DETAILED DESCRIPTION
[0044] The present application will be further described in detail below. Figures 1-4 The present application will be further described in detail below.
[0045] The embodiment of the present application discloses a silicon capacitor wafer test system. For silicon capacitor wafer test, especially for mass production test of silicon capacitor wafers, the current test method needs manual or semi-manual test. However, the number of silicon capacitors on the wafer is large, and the manual or semi-manual test method usually consumes a lot of time and manpower, and the test efficiency is low. In order to improve the test efficiency of the mass production of silicon capacitors, the present application provides a silicon capacitor wafer test system.
[0046] Referring to Figure 1 , the silicon capacitor wafer test system comprises a wafer acquisition module 100, a wafer test module 200 and a data recording module 300.
[0047] The wafer acquisition module 100 is configured to automatically acquire the wafer to be tested and place the wafer to be tested at a preset test position upon receiving a wafer test instruction; the wafer test module 200 is in communication connection with the wafer acquisition module 100 and is configured to test the wafer to be tested and output a test result; and the data recording module 300 is in communication connection with the wafer test module 200 and is configured to receive and record the test result of the wafer test module. In the embodiments of the present application, the data recording module 300 is taken as an example of a computer.
[0048] In the embodiments of the present application, the wafer acquisition module 100 is taken as an example of a full-automatic probe station and mainly includes a control device, a mechanical hand and an automatic feeding device. Referring to Figure 1 , the control device is configured to receive a wafer test instruction and control the wafer acquisition module to automatically acquire the wafer to be tested according to the wafer test instruction; the automatic feeding device is in communication connection with the control device and is configured to store and deliver the wafer to be tested that needs to be tested, referring to Figure 1 the wafer automatic feeding area; the mechanical hand (not shown in the figure) is in communication connection with the automatic feeding device and is configured to grab the wafer to be tested and place the wafer to be tested at a preset test position. The preset test position is also a tray in the full-automatic probe station. In the process of acquiring the wafer, the wafer is in the probe station device all the time and is in a dust-free environment, so as to avoid the risks of wafer damage, fragments, collision and dirt caused by manually placing the wafer as much as possible.
[0049] Referring to Figure 2The wafer test module 200 includes a control board, a plurality of digital bridge board cards, and a plurality of voltage and current source board cards and a switch board card. The control board is in communication connection with the wafer acquisition module and is used to control the wafer test module to test the wafer under test. The connection mode of the control board and the wafer acquisition module can be through a communication cable, and the communication cable is generally a GPIB or a LAN port. The full-automatic probe station and the test module interact through communication instructions to control the entire test process. The plurality of digital bridge board cards are in communication connection with the control board and are used to test the capacitance value of the wafer under test in parallel; the plurality of voltage and current source board cards are in communication connection with the control board and are used to test the capacitance leakage current of the wafer under test in parallel; the number of the digital bridge board cards is consistent with the number of the voltage and current source board cards. The digital bridge board card is a single-channel LCR digital bridge board card, the frequency range of the single-channel LCR digital bridge board card is 40 Hz-2 MHz, the current sensitivity is 1 fA, the capacitance measurement accuracy is 0.15% @ 1 pF, and the maximum voltage is 40 V, which can meet the high-precision test of most silicon capacitance values. The voltage and current source board card is a single-channel SMU voltage and current source board card, the voltage range of the single-channel SMU voltage and current source board card is -200 V-200 V, and the current sensitivity is 10 fA, which can meet the leakage current test requirement of the silicon capacitor <0.1 nA. It should be noted that the number of the digital bridge board card and the voltage and current source board card can be set according to the actual performance of the system, which is not limited here. In the embodiments of the present application, the number is taken as an example for description, that is, in the wafer test module, four LCR digital bridge board cards and four SMU voltage and current source board cards are integrated.
[0050] The switch board card is in communication connection with the plurality of digital bridge board cards and the plurality of voltage and current source board cards and is used to switch the digital bridge board card test and the voltage and current source board card test. The switch board card includes a plurality of relays, and the number of the relays is consistent with the number of the digital bridge board cards; the communication connection of the switch board card with the plurality of digital bridge board cards and the plurality of voltage and current source board cards includes that each relay includes one common end and two contact ends, one of the contact ends is connected with one digital bridge board card, the other contact end is connected with one voltage and current source board card, and the common end is connected with the wafer acquisition module. The connection mode of the common end and the wafer acquisition module can be direct connection or connection through a needle card through a connection cable.
[0051] Reference Figure 3In the embodiment of the present application, the LCR digital bridge board card and the SMU voltage and current source board card are switched by the relays on the low leakage multiplexing switch board card, and finally connected to the needle card, which leads the signal to the capacitor on the silicon capacitor wafer by the needle card. The number of needle card stations is consistent with the number of LCR digital bridge board cards and SMU voltage and current source board cards. The low leakage multiplexing switch board card carries low leakage relays, and the normally closed end of each relay is connected to an LCR digital bridge board card, the normally open end is connected to an SMU voltage and current source board card, and the common end is connected to a test station on the needle card. In actual testing, the LCR digital bridge board card can be switched to measure the capacitance value first, and then the SMU voltage and current source board card is switched to measure the leakage current value. The switch board card selects an 8-to-1 multiplexer switch integrated board card with an isolation resistor of 10Ω-13Ω, which is used to switch the LCR digital bridge board card and the SMU voltage and current source board card, and meets the leakage current test requirement of <0.1nA.
[0052] It should be noted that the integration of the controller board card, the LCR digital bridge board card, the SMU voltage and current source board card, and the switch board card can be realized by a PXIe chassis (PXI Express chassis). In the embodiment of the present application, the PXIe chassis selects an 18-slot desktop chassis for carrying the controller board card, the LCR digital bridge board card, the SMU voltage and current source board card, and the low leakage multiplexing switch board card, and the 18 slots can be conveniently expanded. The overall chassis size is 445.5mm*177.1mm*463.6mm (width*height*depth), which makes the whole system miniaturized and convenient. The controller board card selects a win10 / 64bit / 8-core configuration with a main frequency of 3.9GHz, which can handle burst parallel testing and real-time control of the full-automatic probe station, improving the testing efficiency.
[0053] In the scheme of the present application, the silicon capacitor wafer mass production test system integrates the switching board card, the LCR digital bridge board card and the SMU voltage and current source board card resources. The LCR digital bridge board card and the SMU voltage and current source board card are switched through the switching board card, so that the wafer can be continuously tested without the need to reconnect other functional board cards in the middle, avoiding the interference caused by manual operation. The system simultaneously carries a plurality of LCR digital bridge board cards and a plurality of SMU voltage and current source board cards, realizes parallel test of the capacitors, so as to improve the efficiency of the silicon capacitor wafer batch test and save manpower and time. In the embodiment of the present application, 4 LCR digital bridge board cards and 4 SMU voltage and current source board cards are used. A multi-station needle card is used for testing. Taking 4 stations as an example, the single-station test time is 140 ms, and the 4-station parallel test time of the system is also 140 ms. The total time for testing 4 capacitors is 140+200=340 ms. If there are 700,000 capacitors on a silicon capacitor wafer, the time for testing the whole wafer is 700,000 / 4*0.34 / 3600≈16.5 hours. Compared with the traditional test scheme which needs to test a silicon capacitor wafer for 1-2 days, the test efficiency can be greatly improved. If the number of LCR digital bridge board cards and SMU voltage and current source board cards is expanded on the basis of the system's supportable running carrying capacity, the test efficiency can continue to be improved.
[0054] In addition, the silicon capacitor wafer mass production test system uses a full-automatic probe station, which can realize automatic wafer loading and unloading, and the whole process is completed by a mechanical hand, avoiding the risks of damage, fragmentation, collision and dirt caused by manual wafer taking. The whole wafer test process realizes unmanned management, and an inkless map is automatically generated. The inkless map can also be understood as judging and marking the failed capacitors according to the capacitance values and leakage current values of the silicon capacitors obtained in the test process, obtaining the inkless map, improving the automation degree of the test, and being more suitable for the mass production test of silicon capacitors.
[0055] Based on the above system, the embodiment of the present application further discloses a silicon capacitor wafer test method.
[0056] Referring to Figure 4 The method comprises the following steps:
[0057] S10, when receiving a wafer test instruction, controlling the wafer acquisition module to automatically acquire a wafer to be tested and placing the wafer to be tested at a preset test position.
[0058] Specifically, the system receives a wafer test instruction issued by a user, controls the wafer acquisition module to automatically acquire a wafer to be tested and places the wafer to be tested at a preset test position. Specifically, the robot acquires the wafer to be tested from the automatic loading area according to the received instruction and places the wafer to be tested at the preset tray for testing. During the whole process, the operator does not need to manually acquire or place the wafer, thereby avoiding damage and interference to the wafer caused by manual operation.
[0059] S20, controlling the wafer test module to test the wafer to be tested and generating a test result.
[0060] Specifically, after the wafer is placed at the specified position, the wafer acquisition module is in communication connection with the wafer test module, the wafer is tested, and a test result is generated. Specifically, the wafer test module includes a plurality of digital bridge board cards, a plurality of voltage and current source board cards and a switch board card; the switch board card is controlled to connect the plurality of digital bridge board cards, the plurality of digital bridge board cards are used to perform parallel testing on the wafer to be tested, and a capacitance value result of the wafer to be tested is measured; then, the switch board card is switched, the switch board card is controlled to connect the plurality of voltage and current source board cards, the plurality of voltage and current source board cards are used to perform parallel testing on the wafer to be tested, and a leakage current value result of the wafer to be tested is measured; the capacitance value result and the leakage current value result of the wafer to be tested are set as the test result, an inkless map (wafer map without ink) can be generated according to the measured test result, and the tested capacitors and the tested capacitors are marked, so as to be sorted in the subsequent packaging link.
[0061] S30, transmitting the generated test result to the data recording module for recording and storage.
[0062] Specifically, the test module transmits the data result after the test through communication to the data recording module for recording and storage. The data recording module can be a computer, a computer host or other terminal equipment with recording and storage functions.
[0063] In the scheme, the LCR digital bridge board card and the SMU voltage and current source board card are integrated to realize batch testing of the silicon capacitor wafer, thereby greatly improving the testing efficiency, saving time and manpower; the whole process of automatic testing can avoid interference to the testing process caused by manual operation, thereby improving the testing efficiency and the accuracy of detection.
[0064] Figure 4 The flowchart of the silicon capacitor wafer testing method in one embodiment is shown. It should be understood that, although Figure 4The steps in the flowcharts are shown in sequence according to the arrows, but the steps are not necessarily executed in the order indicated by the arrows; unless otherwise specified herein, the steps are not strictly limited in sequence, and the steps can be executed in other sequences; and Figure 4 At least a part of the steps in the flowcharts can include a plurality of sub-steps or a plurality of stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution sequence of the sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least a part of other steps or sub-steps or stages of other steps.
[0065] The specific embodiments are only an explanation of the present application, and are not a limitation of the present application, and those skilled in the art can make modifications to the embodiments without creative contribution according to the needs after reading the specification, but as long as the modifications are within the scope of the claims of the present application, they are protected by the patent law.
Claims
1. A silicon capacitor wafer test system, characterized by: The silicon capacitor wafer test system comprises a wafer acquisition module and a wafer test module; The wafer acquisition module is configured to automatically acquire a wafer to be tested and place the wafer to be tested at a preset test position upon receiving a wafer test instruction; The wafer test module is in communication connection with the wafer acquisition module and is configured to test the wafer to be tested and output a test result; The wafer test module comprises a control board, a plurality of digital bridge board cards and a plurality of voltage and current source board cards; The control board is in communication connection with the wafer acquisition module and is configured to control the wafer test module to test the wafer to be tested; The plurality of digital bridge board cards are in communication connection with the control board and are configured to test the capacitance value of the wafer to be tested in parallel; The plurality of voltage and current source board cards are in communication connection with the control board and are configured to test the capacitance leakage current of the wafer to be tested in parallel.
2. The silicon capacitor wafer test system of claim 1, wherein: The number of the digital bridge board cards is consistent with the number of the voltage and current source board cards.
3. The silicon capacitor wafer test system of claim 2, wherein: The wafer test module further comprises a switch board card; The switch board card is in communication connection with the plurality of digital bridge board cards and the plurality of voltage and current source board cards and is configured to switch the digital bridge board card test and the voltage and current source board card test.
4. The silicon capacitor wafer test system of claim 3, wherein: The switch board card comprises a plurality of relays, and the number of the relays is consistent with the number of the digital bridge board cards; The communication connection between the switch board card and the plurality of digital bridge board cards and the plurality of voltage and current source board cards comprises: Each relay comprises one common terminal and two contact terminals, one of which is connected to one digital bridge board card, the other of which is connected to one voltage and current source board card, and the common terminal is connected to the wafer acquisition module.
5. The silicon capacitor wafer test system of claim 1, wherein: The wafer acquisition module comprises a control device, a mechanical hand and an automatic feeding device; The control device is configured to receive a wafer test instruction and control the wafer acquisition module to automatically acquire a wafer to be tested according to the wafer test instruction; The automatic feeding device is in communication connection with the control device and is configured to store and deliver the wafer to be tested; The mechanical hand is in communication connection with the automatic feeding device and is configured to grab the wafer to be tested and place the wafer to be tested at a preset test position.
6. The silicon capacitor wafer test system of claim 1, wherein: The digital bridge board card is a single-channel LCR digital bridge board card, the frequency range of the single-channel LCR digital bridge board card is 40 Hz-2 MHz, the current sensitivity is 1 fA, and the capacitance measurement accuracy is 0.15% @ 1 pF.
7. The silicon capacitor wafer test system of claim 1, wherein: The voltage and current source board card is a single-channel SMU voltage and current source board card, the voltage range of the single-channel SMU voltage and current source board card is -200 V-200 V, and the current sensitivity is 10 fA.
8. The silicon capacitor wafer test system of claim 1, wherein: The silicon capacitor wafer test system further comprises a data recording module; The data recording module is in communication connection with the wafer test module and is configured to receive and record the test result tested by the wafer test module.
9. A method for testing silicon capacitor wafers, characterized in that: The method is applied to a silicon capacitor wafer test system, the silicon capacitor wafer test system comprises a wafer acquisition module, a wafer test module and a data recording module, and the method comprises: When receiving a wafer test instruction, the wafer acquisition module is controlled to automatically acquire a wafer to be tested and place the wafer to be tested at a preset test position; The wafer test module is controlled to test the wafer to be tested and generate a test result; The generated test result is transmitted to the data recording module for recording and storage.
10. The method of claim 9, wherein: The wafer test module comprises a plurality of digital bridge board cards, a plurality of voltage and current source board cards and a switch board card; The wafer test module is controlled to test the wafer to be tested and generate a test result, which comprises: The switch board card is controlled to connect the plurality of digital bridge board cards, the plurality of digital bridge board cards are used to perform parallel testing on the wafer to be tested, and a capacitance value result of the wafer to be tested is measured; The switch board card is controlled to connect the plurality of voltage and current source board cards, the plurality of voltage and current source board cards are used to perform parallel testing on the wafer to be tested, and a leakage current value result of the wafer to be tested is measured; The capacitance value result and the leakage current value result of the wafer to be tested are set as the test result.