Memory device, chip, board card, apparatus, and processing method of memory device

Abstract

The invention discloses a memory device, a chip, a board card, equipment and a processing method of the memory device, and is applied to the technical field of chips. The memory device comprises a read-write unit, a first memory and a second memory, wherein the first memory and the second memory are connected with the read-write unit; the access speed of the first memory is greater than that of the second memory; the memory address of the memory device is obtained by firstly coding each memory block in the first memory and then coding each memory block in the second memory according to a unified coding mode; and a read-write unit for performing at least one of a read operation and a write operation on at least one memory block in the first memory and the second memory based on the memory address. According to the scheme, unified addressing and read-write operation of the first memory and the second memory in the memory device are realized, the program design is simplified, and the programming complexity is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and particularly relates to a memory device, a chip, a board card, an equipment and a processing method of the memory device. BACKGROUND

[0002] The chip includes a processor and a memory, and the memory is divided into a plurality of storage levels.

[0003] Taking an example that the memory is divided into two storage levels corresponding to a first level memory (L1 Buffer) and a second level memory (L2 Buffer), when the processor needs to process data, the data is first loaded into the chip from the memory outside the chip. In the loading process in the chip, the data is first loaded into the second level memory, and then loaded into the first level memory. The processor can read the data by directly accessing the first level memory.

[0004] However, due to the limited storage capacity of the first level memory, when the data amount of the above data exceeds the storage capacity of the first level memory, the data cannot be loaded into the first level memory at one time, but needs to be moved between different storage levels. For example, a part of the data is first loaded into the first level memory, and after the data is read by the processor, the data is moved to the second level memory, and then moved from the second level memory to the memory. Next, another part of the data is loaded into the first level memory in the above manner. For the division mode of the storage levels of the memory in the chip, the programmer needs to accurately formulate a data segmentation program according to the storage capacity of the first level memory, so that the segmented data is loaded and moved in different storage levels in turn, which makes the program design of the chip complex and the programming complexity too high. SUMMARY

[0005] The present application provides a memory device, a chip, a board card, an equipment and a processing method of the memory device. The technical solution is as follows: In one aspect, a memory device is provided, the memory device comprising: a read-write unit, a first memory and a second memory connected to the read-write unit respectively; The access speed of the first memory is greater than that of the second memory; the memory address of the memory device is obtained by encoding each storage block in the first memory and then encoding each storage block in the second memory according to a unified encoding mode; The read-write unit is configured to perform at least one of a read operation and a write operation on at least one storage block in the first memory and the second memory based on the memory address.

[0006] In another aspect, a chip is provided, the chip comprising the memory device as described above.

[0007] In another aspect, a board card is provided, which includes the memory device as described above.

[0008] In another aspect, a computer device is provided, which includes the memory device as described above, or includes the chip as described above, or includes the board card as described above.

[0009] In another aspect, a processing method of a memory device is provided, the memory device including a read-write unit, a first memory and a second memory connected to the read-write unit respectively; an access speed of the first memory being greater than an access speed of the second memory; a memory address of the memory device being obtained according to a unified encoding manner, by encoding each memory block in the first memory and then encoding each memory block in the second memory; and the method including: the read-write unit performing at least one of a read operation and a write operation on at least one memory block in the first memory and the second memory based on the memory address.

[0010] In some embodiments, the memory block allocation unit determines the first address and the first length corresponding to the memory block of the first storage capacity from the free memory blocks, to allocate the memory block of the first storage capacity, including: the memory block allocation unit further determines, based on the number of memory blocks corresponding to the first storage capacity, a first continuous address segment that satisfies an allocation condition from the memory addresses corresponding to the free memory blocks; and determines the first address and the first length corresponding to the memory block of the first storage capacity based on the continuous address segment. wherein the continuous address segment refers to address segments corresponding to at least two free memory blocks in sequence, and the allocation condition includes that the number of free memory blocks corresponding to the continuous address segment is equal to the number of memory blocks corresponding to the first storage capacity.

[0011] In some embodiments, the memory device further includes a free list register connected to the free list memory, the free list register being used to record the memory address and an occupancy status of each memory block in the first memory and each memory block in the second memory; and the method further includes: the memory block allocation unit further marks a corresponding position of the memory block of the first storage capacity in the free list register as a first value; wherein the first value is used to represent that the memory block is occupied.

[0012] In some embodiments, the memory device further comprises a memory block release unit distributed in parallel with the memory block allocation unit; the method further comprises: The memory block release unit receives a memory block release request sent by the processor, the memory block release request being used to request to release a second memory block in the memory device, and indicating a second address and a second length of the second memory block; based on the second address and the second length, the second memory block is released.

[0013] In some embodiments, the memory block release unit is connected with the free list memory; the method further comprises: The memory block release unit further marks a corresponding position of the second memory block in the free list register as a second value; Wherein, the second value is used to represent that the memory block is not occupied.

[0014] In some embodiments, the read-write unit comprises a request splitting unit, a dispatching unit, a first arbitration unit corresponding to the first memory, a second arbitration unit corresponding to the second memory, the request splitting unit is connected with the dispatching unit, the dispatching unit is connected with the first arbitration unit, the first arbitration unit is connected with the first memory, the dispatching unit is further connected with the second arbitration unit, and the second arbitration unit is connected with the second memory; the method further comprises: The request splitting unit receives a memory access request sent by the processor, splits the memory access request into a plurality of sub-access requests, and sends the plurality of sub-access requests to the dispatching unit based on memory addresses carried by the plurality of sub-access requests respectively; The dispatching unit sends a first type of sub-access request in the plurality of sub-access requests to the first arbitration unit, and sends a second type of sub-access request in the plurality of sub-access requests to the second arbitration unit, the first type of sub-access request being used to request to perform at least one of the read operation and the write operation on at least one memory block in the first memory, and the second type of sub-access request being used to request to perform at least one of the read operation and the write operation on at least one memory block in the second memory; The first arbitration unit arbitrates the first type of sub-access request, and sends the arbitrated first type of sub-access request to the first memory, so as to perform at least one of the read operation and the write operation on at least one memory block in the first memory based on a memory address carried by the first type of sub-access request; The second arbitration unit arbitrates the second type sub-access request, and sends the arbitrated second type sub-access request to the second memory to perform at least one of the read operation and the write operation on at least one storage block in the second memory based on a memory address carried by the second type sub-access request.

[0015] In some embodiments, the memory access request is used to indicate a write operation, the first type sub-access request is used to indicate writing first data into at least one storage block in the first memory, the first type sub-access request further carries the first data, the second type sub-access request is used to indicate writing second data into at least one storage block in the second memory, and the second type sub-access request further carries the second data. The first arbitration unit arbitrates the first type sub-access request, and sends the arbitrated first type sub-access request to the first memory to perform the write operation on at least one storage block in the first memory based on a memory address carried by the first type sub-access request, including: The first arbitration unit arbitrates the first type sub-access request, and sends the arbitrated first type sub-access request to the first memory to write the first data into at least one storage block in the first memory based on a memory address carried by the first type sub-access request. The second arbitration unit arbitrates the second type sub-access request, and sends the arbitrated second type sub-access request to the second memory to perform the write operation on at least one storage block in the second memory based on a memory address carried by the second type sub-access request, including: The second arbitration unit arbitrates the second type sub-access request, and sends the arbitrated second type sub-access request to the second memory to write the second data into at least one storage block in the second memory based on a memory address carried by the second type sub-access request.

[0016] In some embodiments, the read-write unit further includes a multiplexer and a data buffer, the first arbitration unit and the second arbitration unit are each further connected with the multiplexer, and the multiplexer is connected with the data buffer. The memory access request is used to indicate the read operation, the first type sub-access request is used to request reading first target data from at least one storage block in the first memory, the first type sub-access request further carries a first target length of the first target data, and the second type sub-access request is used to indicate reading second target data from at least one storage block in the second memory, and the second type sub-access request further carries a second target length of the second target data. The first arbitration unit arbitrates the first type of sub-access request, and sends the arbitrated first type of sub-access request to the first memory to perform the read operation on at least one memory block in the first memory based on a memory address carried by the first type of sub-access request, including: The first arbitration unit arbitrates the first type of sub-access request, and sends the arbitrated first type of sub-access request to the first memory to read the first target data from at least one memory block in the first memory based on a memory address carried by the first type of sub-access request and the first target length, and send the first target data to the multiplexer; The second arbitration unit arbitrates the second type of sub-access request, and sends the arbitrated second type of sub-access request to the second memory to perform the read operation on at least one memory block in the second memory based on a memory address carried by the second type of sub-access request, including: The second arbitration unit arbitrates the second type of sub-access request, and sends the arbitrated second type of sub-access request to the second memory to read the second target data from at least one memory block in the second memory based on a memory address carried by the second type of sub-access request and the second target length, and send the second target data to the multiplexer; The method further includes: The multiplexer selects target data from the first target data and the second target data, and sends the target data to the data buffer; The data buffer sequentially outputs the target data corresponding to the plurality of sub-access requests in the order of the plurality of sub-access requests in the memory access request.

[0017] In some embodiments, when the memory access request is used to request access to the first memory, the memory access request corresponds to a memory access timing sequence including all or part of the following levels in sequence: An input register level; the input register level is used to indicate registering the memory access request; An arbitration operation level; the arbitration operation level is used to indicate arbitrating the memory access request; A memory access request level; the memory access request level is used to request access to the first memory; A memory access level; the memory access level is used to indicate accessing the first memory; A memory output data register level; the memory output data register level is used to indicate registering the first target data read from different plate blocks of the first memory; a data selection stage; the data selection stage is configured to instruct to select the first target data from different plate blocks of the first memory; a register output stage; the memory output stage is configured to instruct to output the first target data.

[0018] In some embodiments, the memory access request is configured to request to access the second memory, and a memory access request corresponding access timing successively comprises all or part of the following levels: an input register stage; the input register stage is configured to register the memory access request; at least two arbitration operation stages; the at least two arbitration operation stages are configured to arbitrate the memory access request; at least two path delays; the at least two path delays are configured to represent a delay when accessing the second memory; a memory access request stage; the memory access request stage is configured to request to access the second memory; a memory access stage; the memory access stage is configured to instruct to access the second memory; a memory output data register stage; the memory output data register stage is configured to register the second target data read from different plate blocks of the second memory; the at least two path delays; at least two data selection stages; the at least two data selection stages are configured to instruct to select the second target data from different plate blocks of the second memory; a register output stage; the memory output stage is configured to instruct to output the second target data.

[0019] In another aspect, a computer device is provided, and the computer device comprises a processor and a memory, the memory stores a computer program, the computer program is loaded and executed by the processor to implement the processing method of the memory device as described above.

[0020] In another aspect, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, the computer program is loaded and executed by a processor to implement the processing method of the memory device as described above.

[0021] In another aspect, a computer program product is provided, and the computer program product comprises computer instructions stored in a computer readable storage medium, and a processor acquires the computer instructions from the computer readable storage medium, so that the processor is loaded and executed to implement the processing method of the memory device as described above.

[0022] The technical scheme provided by the embodiments of the present application has at least the following beneficial effects: The memory addresses of the memory device are obtained by encoding each memory block in the first memory and then encoding each memory block in the second memory in a unified encoding manner, thereby effectively reducing the programming burden of programmers and improving programming efficiency. The first memory and the second memory of the memory device are respectively connected with the read-write unit, and at least one of the first memory and the second memory can be executed at least one of the read operation and the write operation based on the memory address through the read-write unit, so that the first memory and the second memory can be directly read and written. Compared with the manner of reading and writing the memory in the related art in the order of the storage hierarchy, the read-write efficiency of the first memory and the second memory is improved, and the overall read-write efficiency of the memory device is improved. Compared with the manner of frequently moving data between the storage hierarchies in the related art, the data processing efficiency is improved, and the overall operation efficiency of the memory device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0024] Figure 1 is a schematic diagram of a computer system provided by an exemplary embodiment of the present application; Figure 2 is a schematic diagram of a storage hierarchy of the related art provided by an exemplary embodiment of the present application; Figure 3 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application; Figure 4 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application; Figure 5 is a schematic diagram of a chip provided by an exemplary embodiment of the present application; Figure 6 is a schematic diagram of encoding a memory block in a memory device provided by an exemplary embodiment of the present application; Figure 7 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application; Figure 8 is a schematic diagram of memory block allocation provided by an exemplary embodiment of the present application; Figure 9 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application; Figure 10 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application; Figure 11 is a schematic diagram of storage block release provided by an example embodiment of the present application; Figure 12 is a schematic diagram of a memory device provided by an example embodiment of the present application; Figure 13 is a schematic diagram of a memory device provided by an example embodiment of the present application; Figure 14 is a schematic diagram of memory access timing provided by an example embodiment of the present application; Figure 15 is a schematic diagram of memory access timing provided by an example embodiment of the present application; Figure 16 is a schematic diagram of the architecture of a memory device provided by an example embodiment of the present application; Figure 17 is a flowchart of a processing method of a memory device provided by an example embodiment of the present application; Figure 18 is a schematic diagram of a chip provided by an example embodiment of the present application; Figure 19 is a schematic diagram of a board provided by an example embodiment of the present application; Figure 20 is a structural block diagram of a computer device provided by an example embodiment of the present application; Figure 21 is a structural block diagram of a computer device provided by an example embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to make the objects, technical solutions and advantages of the present application clearer, the following will further describe the embodiments of the present application in detail with reference to the accompanying drawings.

[0026] The example embodiments will be described in detail below with reference to the accompanying drawings. The following description relates to the drawings, in which the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following example embodiments are not meant to represent all implementations consistent with the present application. Rather, they are merely examples with which some aspects of the present application can be implemented, as detailed in the appended claims.

[0027] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used in this application and the appended claims, the singular forms "a," "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.

[0028] It should be understood that although the terms first, second, etc. can be employed in this application to describe various information, such information should not be limited to these terms. These terms are only used to differentiate one piece of information from another. For example, a first parameter can also be termed a second parameter, and, similarly, a second parameter can also be termed a first parameter, without departing from the scope of the present application. Depending on the context, the word "if' as used herein can be interpreted to mean "when" or "in response to determining".

[0029] It should be noted that before collecting the relevant data of the user (for example, request data, response data, operation data, etc. related to the storage device, chip, board card, processor or AI processor in the computer device) and in the process of collecting the relevant data of the user, the application can display a prompt interface, a pop-up window or output voice prompt information, which prompts the user that the relevant data of the user is currently being collected, so that the application only starts to perform the relevant steps of obtaining the relevant data of the user after obtaining the confirmation operation of the user to the prompt interface or the pop-up window, otherwise (i.e. without obtaining the confirmation operation of the user to the prompt interface or the pop-up window), ending the relevant steps of obtaining the relevant data of the user, that is, not obtaining the relevant data of the user. In other words, all the user data collected by the application is collected with the consent and authorization of the user, and the collection, use and processing of the relevant user data need to comply with the relevant laws, regulations and standards of the country and region.

[0030] Artificial Intelligence (AI): is to use digital computer or digital computer controlled machine to simulate, extend and expand human intelligence, perceive environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology of computer science, which tries to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.

[0031] Artificial intelligence technology is a comprehensive discipline, involving a wide range of fields, both hardware and software technologies. Artificial intelligence basic technology generally includes sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-training model technology, operation / interaction system, mechatronics, etc. Among them, the pre-training model is also called large model, basic model, which can be widely applied to downstream tasks in various directions of artificial intelligence after fine-tuning. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology and machine learning / deep learning, etc.

[0032] Figure 1 is a structural block diagram of a computer system provided by an example embodiment of the present application. The computer system 100 can be implemented as a hardware architecture of a storage device, or can be implemented as a system architecture of a processing method of a storage device. The computer system 100 includes a terminal 120 and a server 140.

[0033] The terminal 120 can be provided with a storage device provided by an embodiment of the present application, or the terminal 120 can be provided with a chip provided with a storage device provided by an embodiment of the present application. The terminal 120 can be an electronic device such as a mobile phone, a tablet computer, a vehicle-mounted terminal (car machine), a wearable device, a PC (Personal Computer), an unmanned terminal, etc., which is not limited by an embodiment of the present application.

[0034] The server 140 can be provided with a storage device provided by an embodiment of the present application, or the server 140 can be provided with a board card provided with a storage device provided by an embodiment of the present application. In addition, the server 140 can be a stand-alone physical server, or a server cluster or a distributed system composed of multiple physical servers, or a cloud server providing cloud computing services, a cloud database, cloud computing, cloud functions, cloud storage, network services, cloud communication, middleware services, domain name services, security services, content distribution networks (CDN), and basic cloud computing services such as big data and artificial intelligence platforms. The server 140 can be a background server of the target application program, used to provide background services for the client of the target application program.

[0035] Among them, cloud technology refers to a kind of hosting technology that unifies a series of resources such as hardware, software and network in a wide area network or local area network to realize data calculation, storage, processing and sharing. Cloud technology is a general term for network technology, information technology, integration technology, management platform technology, application technology and other technologies based on cloud computing business model application, which can form a resource pool, and can be used on demand, flexibly and conveniently. Cloud computing technology will become an important support. The background service of the technical network system needs a large amount of calculation and storage resources, such as video websites, picture websites and more portal websites. With the high development and application of the Internet industry, in the future, every item may have its own identification mark, and needs to be transmitted to the background system for logical processing. Different levels of data will be processed separately, and various industry data will need strong system support, which can only be realized through cloud computing.

[0036] Optionally, the server 140 can also be implemented as a node in a blockchain system. Blockchain is a new application mode of distributed data storage, peer-to-peer transmission, consensus mechanism, encryption algorithm and other computer technologies. Blockchain is essentially a decentralized database, which is a series of data blocks associated using cryptographic methods, each data block containing information about a batch of network transactions, used to verify the validity of the information (anti-fake) and generate the next block. The blockchain can include a blockchain underlying platform, a platform product service layer, and an application service layer.

[0037] The terminal 120 and the server 140 can communicate through a network, such as a wired or wireless network. The storage device processing method provided by the embodiments of the present application can be executed by a storage device in a computer device, which can be the terminal 120 and / or the server 140 described above.

[0038] In the related art, a chip includes a processor and a memory, and the memory is divided into a plurality of storage levels. Figure 2 is a schematic diagram of the storage levels of the related technology provided by an exemplary embodiment of the present application.

[0039] Taking an example in which the memory is divided into two storage levels corresponding to a first-level memory (L1 Buffer) and a second-level memory (L2 Buffer), respectively. The processor 150 can include one or more AI cores (AI Core), and the processor 150 can directly access the first-level memory 160 (L1 Buffer) to obtain data in the first-level memory 160. The first-level memory 160 can directly access the second-level memory 170 (L2 Buffer) to obtain data in the second-level memory 170. Generally, the first-level memory 160 is close to the AI processor 150, the storage capacity of the first-level memory 160 is less than that of the second-level memory 170, and the access speed of the first-level memory 160 is faster than that of the second-level memory 170.

[0040] For example, when the processor 150 needs to process data, such as a large amount of feature map (Feature Map) and weight (Weight) data, these data are first loaded from the memory outside the chip into the chip. During the loading process in the chip, the data are first loaded into the second-level memory 170 and then loaded into the first-level memory 160. The processor 150 can directly access the first-level memory 160 to read the data.

[0041] However, due to the limited storage capacity of the first-level memory 160, when the data quantity of the above data exceeds the storage capacity of the first-level memory 160, the data cannot be loaded into the first-level memory 160 at one time, and needs to be moved between different levels of memories. For example, part of the data is first loaded into the first-level memory 160, and after the processor 150 reads the data, the data is moved out of the first-level memory 160 to the second-level memory 170, and then moved out of the second-level memory 170 to the memory. Next, another part of the data is loaded into the first-level memory 160 in the above manner.

[0042] However, in the programming system of the processor 150, the code quantity occupied by the operation operation is small, and most of the business logic is concentrated in how to move the data from the memory to the inside of the processor 150 step by step. According to the division manner of the memory storage hierarchy in the chip, the programmer needs to accurately formulate a data segmentation program according to the storage capacity of the first-level memory 160, so that the segmented data is loaded and moved out of the different levels of memories in turn. This way makes the program design of the memory and the chip complex, and the programming complexity is too high. A large amount of time is consumed in the data moving process, which leads to low overall running efficiency and low data processing efficiency of the processor 150 and the chip.

[0043] In summary, the related art at least has the following technical problems: 1) due to the division of the memory of the chip into levels of storage hierarchy, the program design of the chip is relatively complex, the programmer needs to accurately formulate a data segmentation program, which leads to high programming complexity of the chip; 2) the data moving consumes too much program running time, which leads to low overall running efficiency and low data processing efficiency of the chip.

[0044] Therefore, the embodiments of the present application provide a memory device. The memory device can be integrated in the same chip as the processor 150, and the memory device can at least achieve the following technical effects: 1) the memory addresses of the memory device are obtained by first encoding each storage block in the first memory and then encoding each storage block in the second memory according to a unified encoding manner, which effectively reduces the programming burden of the programmer and improves the programming efficiency; 2) the first memory and the second memory of the memory device are respectively connected to the read-write unit, and at least one of the read operation and the write operation on at least one storage block in the first memory and the second memory can be performed based on the memory address through the read-write unit, so that the first memory and the second memory can be read and written respectively. Compared with the way of reading and writing the memory in the related art according to the levels of storage hierarchy, the read-write efficiency of the first memory and the second memory is improved, and the overall read-write efficiency of the memory device is improved. Compared with the way of frequently moving data between the levels of storage hierarchy in the related art, the data processing efficiency is improved, and the overall running efficiency of the memory device is improved.

[0045] Next, the memory device of the embodiment of the present application is described.

[0046] Figure 3 is a schematic diagram of a memory device provided by an example embodiment of the present application. For example, the memory device 200 includes a read-write unit 300, a first memory 220 and a second memory 230 connected to the read-write unit 300 respectively.

[0047] The storage capacity is used to represent the amount of data of various types of data that the memory can accommodate. Optionally, the data can include at least one of image data, weight data, application data, video data, system operation data, and system configuration data. For example, the storage capacity is usually expressed in bytes (Byte). The storage capacity is also expressed in the number of storage blocks and the storage word length of each storage block. The storage word length refers to the number of bits of binary code stored in a storage block, and the storage word length is used to represent the size of the storage block. The storage word length can be 8 bits, 16 bits, 32 bits, etc. In an example, the storage capacity is calculated in bytes, and the storage capacity = the number of storage blocks * the storage word length. In this embodiment, it is described that one storage block corresponds to one byte (8 bits). In other embodiments, one storage block can also correspond to two bytes (16 bits) or four bytes (32 bits). The storage block in this embodiment can also be referred to as a storage unit.

[0048] In some embodiments, the storage capacity of the first memory 220 is smaller than the storage capacity of the second memory 230, in other words, the storage capacity of the first memory 220 is smaller, and the storage capacity of the second memory 230 is larger. The smaller storage capacity of the first memory 220 is reflected in at least one of the following aspects: 1) the first memory 220 has fewer banks. 2) the first memory 220 has a smaller bank depth. The bank is a physical memory bank. A memory can include multiple banks, and different banks can be connected through physical wiring. The more banks a memory contains, the larger the storage capacity of the memory. A bank can include multiple storage blocks, and the more storage blocks a bank contains, the larger the storage capacity of the bank. The bank depth is used to represent the storage capacity of the bank. The larger the bank depth of a bank, the larger the storage capacity of the bank. In some examples, the first memory 220 includes multiple banks, and the bank depth of each bank remains consistent. The larger storage capacity of the second memory 230 is reflected in at least one of the following aspects: 1) the second memory 230 has more banks. 2) the second memory 230 has a larger bank depth. In some examples, the second memory 230 includes multiple banks, and the bank depth of each bank remains consistent.

[0049] It should be noted that the foregoing quantity, depth, and the like are relative to a threshold value. For example, when the quantity is greater than the quantity threshold value, the quantity is considered to be large, and when the quantity is less than the quantity threshold value, the quantity is considered to be small. When the depth is greater than the depth threshold value, the depth is considered to be large, and when the depth is less than the depth threshold value, the depth is considered to be small. Alternatively, the foregoing quantity, depth, and the like are compared between the first memory 220 and the second memory 230. For example, when the quantity of the first memory 220 is less than the quantity of the second memory 230, the quantity of the first memory 220 is considered to be small, and the quantity of the second memory 230 is considered to be large. When the depth of the first memory 220 is less than the depth of the second memory 230, the depth of the first memory 220 is considered to be small, and the depth of the second memory 230 is considered to be large.

[0050] As an example, Figure 4 is a schematic diagram of a memory device provided by an example embodiment of the present application. For example, the first memory 220 includes four tiles, namely, tile 221, tile 222, tile 223, and tile 224. The tile depths of the tile 221, the tile 222, the tile 223, and the tile 224 are the same. For example, the second memory 230 includes six tiles, namely, tile 231, tile 232, tile 233, tile 234, tile 235, and tile 236. The tile depths of the tile 221, the tile 222, the tile 223, and the tile 224 are the same. In this case, the quantity of the first memory 220 is less than the quantity of the second memory 230, and the depth of the first memory 220 is less than the depth of the second memory 230.

[0051] It should be further noted that the first memory 220 includes four tiles and the second memory 230 includes six tiles in the embodiment, which is only an example. According to different application scenarios, the quantity of the tiles can be adjusted as needed, as long as the quantity of the first memory 220 is less than the quantity of the second memory 230. In an example, when the application scenario is a simple scenario in which the operation amount and the data amount are both less than a threshold value, for example, a game hall login scenario in a game program, a game settlement scenario after a game, an account login scenario in a photo album program, and a historical photo display scenario, the quantity of the tiles of the first memory 220 and the second memory 230 can be less. When the application scenario is a complex scenario in which at least one of the operation amount and the data amount is greater than a threshold value, for example, a picture rendering scenario in a game process in a game program, a team battle scenario, an online photo editing scenario in a photo album program, and a video generation scenario in which a video is generated from a photo, the quantity of the tiles of the first memory 220 and the second memory 230 can be more. The embodiment is not limited in this regard.

[0052] Access speed refers to the rate of reading data from a memory or writing data into a memory. By way of example, access speed can be characterized in terms of clock cycles. Typically, a memory has an access speed of N clock cycles, where N is greater than 0.

[0053] In some embodiments, the access speed of the first memory 220 is greater than the access speed of the second memory 230, in other words, the access speed of the first memory 220 is faster, and the access speed of the second memory 230 is slower. For example, the access speed of the first memory 220 is X clock cycles, where X is in the range of 0 to 10. The access speed of the second memory 230 is Y clock cycles, where Y is in the range of 10 to 90.

[0054] By way of example, Figure 5 is a schematic diagram of a chip according to an example embodiment of the present disclosure. The processor 410 and the memory device 200 are integrated together in the chip 400, and the memory device 200 is an on-chip cache. In order to further improve the access speed of the first memory 220, the first memory 220 can be placed close to the processor 410. Close means that the length of the physical wire between the interface of the first memory 220 and the interface of the processor 410 is less than a length threshold, or the length of the first physical wire between the interface of the first memory 220 and the interface of the processor 410 is less than the length of the second physical wire between the interface of the second memory 230 and the interface of the processor 410.

[0055] The memory address refers to the address coding of each storage block in the first memory 220 and each storage block in the second memory 230 in the memory device 200. In this embodiment, the memory address refers to the physical address. Corresponding to the physical address is the virtual address. The physical address and the virtual address at least have the following differences: 1) different definitions: the physical address is the actual effective address corresponding to the storage block in the memory, also known as the absolute address. The virtual address is the address generated by the processor during program execution, which is composed of segment selector and segment offset address. 2) different positions: the physical address corresponds to the actual existing physical position in the memory. The virtual address does not have a corresponding physical position in the memory. In some examples, after address mapping, the mapped virtual address can point to a certain physical position.

[0056] In some embodiments, the memory address of the memory device 200 is obtained by encoding each storage block in the first memory 220 and then encoding each storage block in the second memory 230 according to a unified encoding manner. It is equivalent to pre-performing address coding on each storage block in the first memory 220 and each storage block in the second memory 230 according to the order of the first memory 220 and the second memory 230 in a unified encoding manner.

[0057] As an example, Figure 6 A schematic diagram of the storage blocks in the encoding memory device provided by one example embodiment of the present application is shown. For example, the memory device 200 has M storage blocks in common; the first memory includes N storage blocks, and the N storage blocks correspond to memory addresses 0 to N-1; the second memory 230 includes M-N storage blocks, and the M-N storage blocks correspond to memory addresses N to M-1; wherein M is greater than N, M and N are integers, and M and N are greater than 0. Optionally, the memory address corresponding to each storage block can be represented as a number, a string of numbers, a string of characters, or a string of codes. For example, taking the memory address corresponding to each storage block as a number as an example, the encoding starts from 0, the first memory 220 includes N storage blocks, and the N storage blocks correspond to memory addresses 0, 1, 2, to N-1; the second memory 230 includes M-N storage blocks, and the M-N storage blocks correspond to memory addresses N, N+1, N+2, to M-1; M is greater than N, M and N are integers, and M and N are greater than 0.

[0058] In other examples, the first memory 220 can also be referred to as a close memory or a close memory device, the second memory 230 can also be referred to as a far memory or a far memory device, and the memory device 200 can also be referred to as a close far memory system. Wherein the access speed of the close memory is greater than the access speed of the far memory, and the memory addresses of the memory device are encoded in a unified encoding manner, first encoding the storage blocks in the close memory and then encoding the storage blocks in the far memory.

[0059] The read-write unit 300 is configured to perform at least one of a read operation and a write operation on at least one storage block in the first memory 220 and the second memory 230 based on the memory address.

[0060] The read operation refers to an operation of reading data from at least one storage block in the first memory 220 and / or the second memory 230. The write operation refers to an operation of writing data into at least one storage block in the first memory 220 and / or the second memory 230.

[0061] Optionally, the read-write unit 300 is configured to perform a read operation and / or a write operation on at least one storage block in the first memory 220 based on the memory address, and the read-write unit 300 is configured to perform a read operation and / or a write operation on at least one storage block in the second memory 230 based on the memory address. The specific manner of the read operation and the write operation will be described in subsequent embodiments.

[0062] In summary, the memory device provided by the embodiment of the present application has the memory address of the memory device obtained by encoding each memory block in the first memory and then encoding each memory block in the second memory in a unified encoding manner, thereby effectively reducing the programming burden of the programmer and improving the programming efficiency. The first memory and the second memory of the memory device are connected with the read-write unit, and at least one of the read operation and the write operation on at least one memory block in the first memory and the second memory can be performed based on the memory address through the read-write unit, so that the first memory and the second memory can be read and written respectively. Compared with the manner of reading and writing the memory in the related art according to the storage hierarchy, the read-write efficiency of the first memory and the second memory is improved, and the overall read-write efficiency of the memory device is improved. Compared with the manner of frequently moving data between the storage hierarchies in the related art, the data processing efficiency is improved, and the overall operation efficiency of the memory device is improved.

[0063] · Allocation of memory blocks In some embodiments, Figure 7 FIG. 1 is a schematic diagram of a memory device provided by an exemplary embodiment of the present application. The memory device 200 further includes a memory block allocation unit 210.

[0064] The memory block allocation unit 210 is configured to receive a memory block allocation request sent by a processor, the memory block allocation request being used to request allocation of a memory block of a first storage capacity in the memory device 200; allocate the memory block of the first storage capacity based on the memory address in the order from the low address to the high address; and send a first address and a first length corresponding to the memory block of the first storage capacity to the processor.

[0065] The memory block allocation unit 210 (Memory Allocate) is configured to receive a memory block allocation request and allocate a memory block of a first storage capacity based on the memory block allocation request. The memory block allocation request (Space_req) is used to request allocation of a memory block of a first storage capacity. Optionally, the memory block allocation request can be sent by a processor integrated in the same chip as the memory device 200. The memory block allocation request requests allocation of a memory block of a first storage capacity, which can be determined based on at least one of image data, weight data, application data, video data, system operation data, and system configuration data currently required to be processed by the processor.

[0066] In some embodiments, the first storage capacity of the storage blocks indicated by the storage block allocation request can be represented by at least one of a length, a number of bytes, or a number of storage blocks. For example, one storage block of the memory device 200 corresponds to one byte, and when the storage block allocation request is used to request allocation of 2 bytes of storage blocks, the storage block allocation request can indicate at least one of the following information related to the first storage capacity of the storage blocks: a number of bytes of 2, a length of 2, or a number of storage blocks of 2.

[0067] In some embodiments, the first address corresponding to the first storage capacity of the storage blocks includes a start address corresponding to the first storage capacity of the storage blocks, and the first length is determined based on at least one of a number of storage blocks and a number of bytes corresponding to the first storage capacity of the storage blocks. For example, the first storage capacity of the storage blocks is the 0th, 1st, and 2nd storage blocks, the first address is the start address 0 corresponding to the 0th storage block, and the first length is 3.

[0068] Since the memory addresses of the memory device 200 are encoded in a unified encoding manner, the storage blocks in the first memory 220 are encoded first, and then the storage blocks in the second memory 230 are encoded, the low-order address refers to the memory address corresponding to the storage block sorted first, and the high-order address refers to the memory address corresponding to the storage block sorted last. Referring to the memory addresses shown in the figure, the low-order address refers to the 0th address corresponding to the 0th storage block, and the high-order address refers to the xth address corresponding to the xth storage block after the 0th storage block. Then, the order from the low-order address to the high-order address refers to the order from the 0th address to the M-1th address. Then, the storage block allocation unit 210 is configured to allocate the first storage capacity of the storage blocks for the storage block allocation request in the order from the low-order address to the high-order address. Figure 6

[0069] In this embodiment, the storage block allocation unit 210 allocates the first storage capacity of the storage blocks based on the memory addresses in the order from the low-order address to the high-order address, and sends the first address corresponding to the first storage capacity of the storage blocks and the first length to the processor. Since the storage blocks in the first memory 220 are encoded first and the storage blocks in the second memory 230 are encoded last, the storage blocks in the first memory 220 can be allocated preferentially.

[0070] In some embodiments, the storage block allocation unit 210 needs to find the unoccupied free storage blocks first, and then allocate the first storage capacity of the storage blocks based on the unoccupied free storage blocks.

[0071] ​The storage block allocation unit 210 is configured to search for an unoccupied free storage block in the order from a low address to a high address based on the memory address, and determine a first address and a first length corresponding to the storage block of the first storage capacity from the free storage block to allocate the storage block of the first storage capacity.

[0072] The free storage block refers to an unoccupied storage block in the storage device 200, or refers to a storage block in an idle state in the storage device 200, or refers to a storage block without storing data in the storage device 200. In the case of a free storage block, the storage block can be allocated. Next, the storage block allocation unit 210 can determine a first address and a first length corresponding to the storage block of the first storage capacity from the free storage block to allocate the storage block of the first storage capacity.

[0073] In the embodiment, the storage block allocation unit 210 searches for an unoccupied free storage block in the order from a low address to a high address. Since each storage block in the first memory 220 is encoded first and each storage block in the second memory 230 is encoded later, the unoccupied free storage block in the first memory 220 can be searched first. Next, the storage block allocation unit 210 is configured to determine a first address and a first length corresponding to the storage block of the first storage capacity from the free storage block to allocate the storage block of the first storage capacity, which can realize the allocation of the storage block in the first memory 220 preferentially, i.e., the storage block allocation manner can ensure that the storage block in the first memory 220 is allocated preferentially. Since the access speed of the first memory 220 is greater than that of the second memory 230, the manner of the embodiment improves the data acquisition efficiency, and further facilitates the improvement of the subsequent data processing efficiency.

[0074] The storage block allocation unit 210 is further configured to determine a first address and a first length corresponding to the storage block of the first storage capacity based on the number of storage blocks corresponding to the first storage capacity from the memory address corresponding to the free storage block, and determine a first address and a first length corresponding to the storage block of the first storage capacity based on the continuous address segment. The continuous address segment refers to an address segment corresponding to at least two free storage blocks in succession, and the allocation condition includes the number of free storage blocks corresponding to the continuous address segment, which is equal to the number of storage blocks corresponding to the first storage capacity.

[0075] The continuous address segment refers to an address segment composed of memory addresses corresponding to at least two free storage blocks. In some examples, the continuous address segment is represented by a start address and an end address in the at least two free storage blocks. For example, the first memory 220 has four free storage blocks, and the memory addresses corresponding to the four free storage blocks are 2, 3, 4, and 5, respectively. The continuous address segment can be represented as a 2-5 address segment with a start address of 2 and an end address of 3. In other examples, the continuous address segment is represented by all addresses in the at least two free storage blocks. For example, the first memory 220 has four free storage blocks, and the memory addresses corresponding to the four free storage blocks are 2, 3, 4, and 5, respectively. The continuous address segment can be represented as a 2, 3, 4, and 5 address segment. In other examples, the continuous address segment is also represented by a start address and a length in the at least two free address segments. For example, the first memory 220 has four free storage blocks, and the memory addresses corresponding to the four free storage blocks are 2, 3, 4, and 5, respectively. The continuous address segment can be represented as an address segment with a start address of 2 and a length of 4.

[0076] The allocation condition refers to a condition that needs to be met by the free storage blocks when some of the free storage blocks are determined as the storage blocks of the first storage capacity. The allocation condition includes that the number of free storage blocks corresponding to the continuous address segment is equal to the number of storage blocks corresponding to the first storage capacity.

[0077] In some embodiments, the number of the at least two free storage blocks is greater than the number of storage blocks corresponding to the first storage capacity, and the allocation condition can be that the number of free storage blocks corresponding to a lower address segment in the continuous address segment is equal to the number of storage blocks corresponding to the first storage capacity. The storage block allocation unit 210 is configured to determine the lower address segment in the continuous address segment as the continuous address segment that meets the allocation condition, and determine the first address and the first length of the storage blocks corresponding to the first storage capacity based on the continuous address segment. For example, the first memory 220 has four free storage blocks, and the memory addresses corresponding to the four free storage blocks are 2-5 address segments. When the storage block allocation request is used to request allocation of a 2-byte storage block, the storage block allocation unit 210 is configured to determine the 2-3 address segment in the 2-5 address segment as the continuous address segment that meets the allocation condition, the first address is 2, and the first length is 2.

[0078] As an example, Figure 8 is a schematic diagram of storage block allocation provided by an exemplary embodiment of the present application. The white area indicates that the storage block corresponding to the memory address is not occupied, and the filled area indicates that the storage block corresponding to the memory address is occupied. Figure 8 The diagram shows memory addresses from 0 to 15, for reference Figure 8As shown in (a) of FIG. 10, the storage blocks corresponding to the memory addresses 0-1 and 7-11 are occupied, and the storage blocks corresponding to the memory addresses 2-6 and 12-15 are not occupied. The storage block allocation unit 210 is configured to receive a storage block allocation request, and the storage block allocation request is used to request allocation of a 2-byte storage block (Allocate 2Byte Space). Then, the storage block allocation unit 210 is configured to search from the low address 0 to the high address 15, find the first continuous address segment that meets the allocation condition, and determine the first address as 2 and the first length as 2 based on the continuous address segment 2-3, and send the first address and the first length to the processor. After allocation, the subsequent read-write unit 300 can write 2 bytes of data into the idle storage blocks corresponding to the continuous address segment 2-3. It is continued to refer to Figure 8 As shown in (b) of FIG. 10, after writing, the storage blocks corresponding to the memory addresses 0-3 and 7-11 are occupied, and the storage blocks corresponding to the memory addresses 4-6 and 12-15 are not occupied.

[0079] In some other embodiments, the continuous address segment composed of the memory addresses corresponding to the idle storage blocks includes a plurality of continuous address segments, and the allocation condition specifically includes that the idle storage blocks corresponding to the first continuous address segment in the plurality of continuous address segments are equal to the number of storage blocks corresponding to the first storage capacity. Then, the storage block allocation unit 210 is configured to determine the first continuous address segment in the plurality of continuous address segments as the continuous address segment that meets the allocation condition, and determine the first address and the first length of the storage block corresponding to the first storage capacity based on the continuous address segment. For example, the first memory 220 has 6 idle storage blocks, and the memory addresses corresponding to the 6 idle storage blocks are the address segment 2-5 and the address segment 9-10. When the storage block allocation request is used to request allocation of a 2-byte storage block, the storage block allocation unit 210 is configured to directly determine the address segment 9-10 as the continuous address segment that meets the allocation condition, determine the first address as 9 and the first length as 2 based on the continuous address segment 9-10, and send the first address and the first length to the processor.

[0080] In this embodiment, the storage block allocation unit 210 is configured to determine, based on the first storage capacity, a first continuous address segment from the memory addresses corresponding to the free storage blocks, which satisfies the allocation condition; and determine, based on the continuous address segment, a first address and a first length of the storage blocks corresponding to the first storage capacity. On one hand, the storage blocks in the first memory 220 can be preferentially allocated based on the storage block allocation request. On the other hand, the storage blocks in the first memory 220 and / or the second memory 230 can be as much as possible not wasted. For example, there are four free storage blocks in the first memory 220, and the memory addresses corresponding to the four free storage blocks are 2-5 address segments. When the storage block allocation request is used to request allocation of a 2-byte storage block, the storage block allocation unit 210 is configured to directly determine 2-3 address segments in the 2-5 address segments as the continuous address segment that satisfies the allocation condition. If 3-4 address segments are determined as the address segment that satisfies the allocation condition, the free storage block 2 may be wasted. If 4-5 address segments are determined as the address segment that satisfies the allocation condition, the two free storage blocks 2-3 may be wasted when the next storage block allocation request is used to request allocation of a 3-byte storage block.

[0081] Figure 9 FIG. 1 is a schematic diagram of a memory device according to an example embodiment of the present application. The memory device 200 further includes a free list register (Freelist) 240. The storage block allocation unit 210 is connected to the free list register 240. The free list register 240 is configured to record the memory addresses and the occupation status of each storage block in the first memory 220 and each storage block in the second memory 230. In this embodiment, the free list register 240 is described in byte granularity. A storage block in the memory device 200 corresponds to a position in the free list register 240. The value of the position is used to represent the occupation status of the storage block.

[0082] It should be noted that in different memory devices 200, the granularity of each bit in the free list register 240 can be set according to actual technical needs. In other examples, each bit in the free list register 240 can correspond to a granularity of 2 Kbyte.

[0083] The storage block allocation unit 210 is further configured to mark the corresponding position of the storage block of the first storage capacity in the free list register 240 as a first value. The first value is used to represent that the storage block is occupied.

[0084] For example, the first value is set as 1 and the second value is set as 0. When a corresponding position of a memory block in the free list memory 240 is marked as 1, it indicates that the memory block is occupied. When a corresponding position of a memory block in the free list memory 240 is marked as 0, it indicates that the memory block is not occupied.

[0085] In this embodiment, the memory block allocation unit 210 marks the corresponding position in the free list register 240 after performing memory block allocation, which can timely mark the occupation of the memory block in the memory device 200, facilitate the next memory block allocation or subsequent memory block release, and be beneficial to improving the data processing efficiency.

[0086] In summary, in the memory block allocation, the memory block allocation unit can automatically allocate each memory block in the first memory in priority, so that the programmer does not need to manually perform memory block allocation, which can significantly improve the memory block allocation efficiency. Further, since the access speed of the first memory is greater than that of the second memory, by performing memory block allocation in the order from the low address to the high address, each memory block in the first memory can be allocated in priority. In the case of storing data in the first memory subsequently, the processor of the chip can directly obtain the corresponding data from the first memory, the data obtaining speed is fast, and compared with the manner that the data needs to be frequently moved between the storage layers in the related art, the data obtaining efficiency can be improved, which is beneficial to improving the data processing efficiency, thereby improving the overall performance and processing efficiency of the memory device.

[0087] • Release of the memory block Figure 10 FIG. 1 is a schematic diagram of a memory device according to an example embodiment of the present application. The memory device 200 further comprises a memory block release unit 250 distributed in parallel with the memory block allocation unit 210.

[0088] The memory block release unit 250 is configured to receive a memory block release request sent by the processor, the memory block release request being used to request to release a memory block of the second storage capacity in the memory device 200 and indicate a second address and a second length of the memory block of the second storage capacity; and release the memory block of the second storage capacity based on the second address and the second length.

[0089] The memory block release unit 250 is configured to receive a memory block release request, and release the second memory capacity of the memory block based on the memory block release request. The memory block release request is configured to request to release the second memory capacity of the memory block, and indicate a second address and a second length of the second memory capacity of the memory block. The second address includes a start address corresponding to the second memory capacity of the memory block, and the second length is determined based on a number of memory blocks corresponding to the second memory capacity of the memory block. For example, one memory block of the memory device 200 corresponds to one byte, and when the memory block release request is configured to request to release 2 bytes of the memory block, the memory block release request can indicate the start address of the second memory capacity of the memory block, and the length of the second memory capacity of the memory block is 2.

[0090] As an example, Figure 11 is a schematic diagram of the memory block release provided by an example embodiment of the present application. The white area indicates that the memory address corresponds to the unoccupied memory block, and the filled area indicates that the memory address corresponds to the occupied memory block. Figure 11 The schematic diagram of the memory address 0-15 is shown, referring to Figure 11 , as shown in (a), the memory address 0-3, 7-11 corresponds to the occupied memory block, and the memory address 4-6, 12-15 corresponds to the unoccupied memory block. The memory block release unit 250 is configured to receive a memory block release request, and the memory block release request is configured to request to release 2 bytes of the memory block, and indicate that the start address is 2 and the length is 2. Then the memory block release unit 250 releases the memory block corresponding to the continuous address segment 2-3. After release, referring to Figure 11 , (b) is shown, then the memory address 0-1, 7-11 corresponds to the occupied memory block, and the memory address 2-6, 12-15 corresponds to the unoccupied memory block.

[0091] In this embodiment, the memory block release unit 250 can release the corresponding second memory capacity of the memory block after receiving the memory block release request, so as to reduce the occupation of the memory block in the memory device 200, and facilitate the implementation of the next memory block allocation.

[0092] In some embodiments, the memory device 200 further comprises a free list register 240, and the memory block release unit 250 is connected with the free list memory 240. In this embodiment, the free list memory 240 is described in byte granularity. Then one memory block in the memory device 200 corresponds to one position in the free list register 240, and the value of the position is used to represent the occupation of the memory block.

[0093] The storage block releasing unit 250 is further configured to mark the corresponding position of the storage block of the second storage capacity in the idle list register 240 as a second value; the second value is used to represent that the storage block is not occupied.

[0094] For example, the first value is set as 1 and the second value is set as 0. When the corresponding position of a storage block in the idle list register 240 is marked as 1, it indicates that the storage block is occupied. When the corresponding position of a storage block in the idle list register 240 is marked as 0, it indicates that the storage block is not occupied.

[0095] In this embodiment, after the storage block releasing unit 250 releases the storage block of the second storage capacity, the corresponding position in the idle list register 240 is marked, so that the occupation of the storage block in the storage device 200 can be marked in time, which is convenient for the next storage block allocation or subsequent storage block release, and is beneficial to improve the data processing efficiency.

[0096] In some embodiments, when all the storage blocks in the first memory 220 are temporarily occupied or the corresponding memory addresses of the storage blocks in the first memory 220 cannot meet the allocation condition, the storage block allocating unit 210 can only allocate the storage blocks in the second memory 230 based on the storage block allocation request, that is, the subsequent data can only be stored in the second memory 230. Next, after the storage block releasing unit 250 releases the storage block in the first memory 220, the storage block allocating unit 210 can automatically transfer the data in the second memory 230 to the first memory 220.

[0097] The storage block allocating unit 210 is further configured to transfer the target transfer data to the first memory 220 based on the storage capacity of the target transfer data in the second memory 230 and the memory address of the storage device 200.

[0098] The target transfer data refers to the data stored in the second memory 230, and the target transfer data needs to be transferred from the second memory 230 to the first memory 220. The storage block allocating unit 210 is further configured to transfer the target transfer data to at least one storage block in the first memory 220 based on the storage capacity of the target transfer data in the second memory 230 and the memory address of the storage device 200.

[0099] In this embodiment, the storage block allocation unit 210 can also automatically transfer data in the second memory 230 to the first memory 220. Since the access speed of the first memory 220 is greater than that of the second memory 230, this data transfer mode can also improve data processing efficiency. Compared with the mode in the related art in which data is frequently moved between storage levels, the mode of this embodiment also reduces the number of data moves as much as possible, thereby improving the overall performance of the storage device 200.

[0100] In some embodiments, the storage block allocation unit 210 determines the storage block allocated to the target transfer data based on the memory address in the order from the low-bit address to the high-bit address, so as to transfer the target transfer data to the first memory 220.

[0101] The storage block allocation unit 210 is configured to find, based on the memory address of the storage device 200, an unoccupied free storage block in the order from the low-bit address to the high-bit address, and determine, based on the storage capacity of the target transfer data, the storage block allocated to the target transfer data from the free storage block, so as to transfer the target transfer data to at least one storage block in the first memory 220.

[0102] The free storage block refers to an unoccupied storage block in the storage device 200, or a storage block in an idle state in the storage device 200, or a storage block in which no data is stored in the storage device 200. In the case where a storage block is a free storage block, the storage block can be allocated to the target transfer data.

[0103] In some embodiments, the storage block allocation unit 210 is further configured to determine, based on the number of storage blocks corresponding to the target transfer data, a first continuous address segment that meets a transfer condition from the memory addresses corresponding to the free storage blocks, and determine, as the storage block allocated to the target transfer data, the free storage block corresponding to the continuous address segment, so as to transfer the target transfer data to at least one storage block in the first memory 220. The continuous address segment refers to an address segment composed of the memory addresses corresponding to at least two free storage blocks in succession, and the transfer condition includes that the number of free storage blocks corresponding to the continuous address segment is equal to the number of storage blocks corresponding to the target transfer data.

[0104] The transfer condition refers to a condition required to be met when the free storage block in the first memory 220 is allocated to the target transfer data. In this embodiment, the transfer condition includes that the number of free storage blocks corresponding to the continuous address segment is equal to the number of storage blocks corresponding to the target transfer data.

[0105] In some embodiments, the number of the continuous at least two free storage blocks is greater than the number of the storage blocks corresponding to the target transfer data, and the transfer condition can be that the number of the free storage blocks corresponding to the lower address segment in the continuous address segment is equal to the number of the storage blocks corresponding to the target transfer data. Then the storage block allocation unit 210 is configured to allocate the free storage blocks corresponding to the lower address segment in the continuous address segment satisfying the transfer condition to the target transfer data. For example, the first memory 220 has four free storage blocks, and the memory addresses corresponding to the four free storage blocks are the 2-5 address segment. When the target transfer data needs two bytes of storage blocks, the storage block allocation unit 210 is configured to directly allocate the free storage blocks corresponding to the 2-3 address segment in the 2-5 address segment to the target transfer data, so as to transfer the target transfer data to the free storage blocks corresponding to the 2-3 address segment in the first memory 220.

[0106] In other embodiments, the continuous address segment composed of the memory addresses corresponding to the free storage blocks is a plurality of continuous address segments, and the transfer condition specifically includes that the free storage blocks corresponding to the second continuous address segment in the plurality of continuous address segments are equal to the number of the storage blocks corresponding to the target transfer data. Then the storage block allocation unit 210 is configured to allocate the free storage blocks corresponding to the second continuous address segment in the plurality of continuous address segments satisfying the transfer condition to the target transfer data. For example, the first memory 220 has six free storage blocks, and the memory addresses corresponding to the six free storage blocks are the 2-5 address segment and the 9-10 address segment. When the target transfer data needs two bytes of storage blocks, the storage block allocation unit 210 is configured to directly allocate the free storage blocks corresponding to the 9-10 address segment to the target transfer data, so as to transfer the target transfer data to the free storage blocks corresponding to the 9-10 address segment in the first memory 220.

[0107] In the embodiment, the principle of data transfer is basically consistent with the principle of storage block allocation. On the one hand, the target transfer data can be preferentially allocated to each storage block in the first memory 220. On the other hand, each storage block in the first memory 220 and / or the second memory 230 can be as much as possible not wasted. This is conducive to improving the overall performance of the memory device 200.

[0108] • Memory read and write Figure 12Figure 1 is a schematic diagram of a memory device according to an example embodiment of the present application. The read-write unit 300 in the memory device 200 includes a request splitting unit 310 (Burst To Single), a dispatch unit 320 (Disp), a first arbiter unit 330 corresponding to the first memory 220, and a second arbiter unit 340 corresponding to the second memory 230. The request splitting unit 310 is connected to the dispatch unit 320, the dispatch unit 320 is connected to the first arbiter unit 330, the first arbiter unit 330 is connected to the first memory 220, the dispatch unit 320 is also connected to the second arbiter unit 340, and the second arbiter unit 340 is connected to the second memory 230. In an example, both the first memory 220 and the second memory 230 support read-write operations.

[0109] The request splitting unit 310 is configured to receive a memory access request sent by a processor, split the memory access request into a plurality of sub-access requests, and send the plurality of sub-access requests to the dispatch unit 230 based on memory addresses carried by the plurality of sub-access requests.

[0110] The memory access request (Memory_req) is used to request access to the first memory 220, or to request access to the second memory 230, or to request access to both the first memory 220 and the second memory 230. It should be noted that the memory access request in this embodiment is a burst request, i.e., one memory access request includes a plurality of sub-access requests carrying consecutive addresses.

[0111] The request splitting unit 310 is configured to receive a memory access request sent by a processor, and split the memory access request into a plurality of sub-access requests, wherein different sub-access requests are used to request different memory addresses, i.e., a sub-access request can be used to request at least one of a read operation and a write operation on at least one memory block in the first memory 220, or can be used to request at least one of a read operation and a write operation on at least one memory block in the second memory 230. Optionally, the memory access request can be sent by a processor, and the processor and the memory device 200 are integrated in the same chip.

[0112] The dispatch unit 320 is configured to send a first type of sub-access request in the plurality of sub-access requests to the first arbiter unit 330, and send a second type of sub-access request in the plurality of sub-access requests to the second arbiter unit 340, wherein the first type of sub-access request is used to request at least one of a read operation and a write operation on at least one memory block in the first memory 220, and the second type of sub-access request is used to request at least one of a read operation and a write operation on at least one memory block in the second memory 230.

[0113] The dispatch unit 320 is a unit for sending the sub-access requests to the corresponding arbitration units according to the memory addresses requested by the sub-access requests respectively. The sub-access requests include at least one of the first type sub-access requests and the second type sub-access requests. The first type sub-access request is a sub-access request for accessing the first memory 220, and is specifically used for requesting to perform at least one of a read operation and a write operation on at least one storage block in the first memory 220, and carries a memory address corresponding to the storage block in the first memory 220. The second type sub-access request is a sub-access request for accessing the second memory 230, and is specifically used for requesting to perform at least one of a read operation and a write operation on at least one storage block in the second memory 230, and carries a memory address corresponding to the storage block in the second memory 230.

[0114] The first arbitration unit 330 is used for arbitrating the first type sub-access requests and sending the arbitrated first type sub-access requests to the first memory 220 to perform at least one of a read operation and a write operation on at least one storage block in the first memory 220 based on the memory address carried by the first type sub-access request.

[0115] Arbitration refers to determining which sub-access request should be responded to this time from multiple sub-access requests when the multiple sub-access requests are received at the same time. In an example, the arbitration mechanism can be round-robin arbitration, that is, deciding which sub-access request is preferentially responded to based on the priority of the sub-access request. The first arbitration unit 330 is a unit corresponding to the first memory 220 for performing a first arbitration operation. The first arbitration operation refers to arbitrating to decide which first type sub-access request performs at least one of a read operation and a write operation on at least one storage block in the first memory 220 in the case that there are two or more first type sub-access requests that need to perform at least one of a read operation and a write operation on at least one storage block in the first memory 220. The first arbitration unit 330 is used for sending the arbitrated first type sub-access requests to the first memory 220 to perform at least one of a read operation and a write operation on at least one storage block in the first memory 220 based on the memory address carried by the first type sub-access request, so as to realize accessing the first memory 220.

[0116] The second arbitration unit 340 is used for arbitrating the second type sub-access requests and sending the arbitrated second type sub-access requests to the second memory 230 to perform at least one of a read operation and a write operation on at least one storage block in the second memory 230 based on the memory address carried by the second type sub-access request.

[0117] The second arbitration unit 340 is a unit corresponding to the second memory 230 for performing a second arbitration operation. The second arbitration operation refers to a case where two or more second-type sub-access requests need to perform at least one of a read operation and a write operation on at least one memory block in the second memory 230, and the arbitration decides which second-type sub-access request performs at least one of the read operation and the write operation on the at least one memory block in the second memory 230. The second arbitration unit 340 is configured to send the arbitrated second-type sub-access request to the second memory 230, so as to perform at least one of the read operation and the write operation on the at least one memory block in the second memory 230 based on the memory address carried by the second-type sub-access request.

[0118] In the embodiment, the memory access request is used to request access to the first memory 220 and / or the second memory 230. Since the memory access request contains multiple sub-access requests carrying consecutive addresses, the memory access request can be split into multiple sub-access requests by the request splitting unit 310. Then, the dispatching unit 320, the arbitration units of the first memory 220 and the second memory 230 can realize the dispatching and arbitration of the sub-access requests, so that the sub-access requests can successfully access the first memory 220 and / or the second memory 230, and the diversified application of the memory device 200 is facilitated.

[0119] In some embodiments, the memory access request is used to indicate a write operation. The first-type sub-access request is used to indicate writing the first data into at least one memory block in the first memory 220, and the first-type sub-access request further carries the first data. The second-type sub-access request is used to indicate writing the second data into at least one memory block in the second memory 230, and the second-type sub-access request further carries the second data.

[0120] The first arbitration unit 330 is configured to arbitrate the first-type sub-access request and send the arbitrated first-type sub-access request to the first memory 220, so as to write the first data into at least one memory block in the first memory 220 based on the memory address carried by the first-type sub-access request.

[0121] Since the first-type sub-access request is used to request access to the memory address in the first memory 220, the first arbitration unit 330 is configured to send the arbitrated first-type sub-access request to the first memory 220, so as to write the first data carried by the first-type sub-access request into at least one memory block in the first memory 220 according to the memory address carried by the first-type sub-access request, and the at least one memory block is determined based on the memory address.

[0122] The second arbitration unit 340 is configured to arbitrate the second type of sub-access request, and send the arbitrated second type of sub-access request to the second memory 230, so as to write the second data carried by the second type of sub-access request into at least one storage block in the second memory 230 based on a memory address carried by the second type of sub-access request.

[0123] Since the second type of sub-access request is used to access a memory address in the second memory 230, the second arbitration unit 340 is configured to send the arbitrated second type of sub-access request to the second memory 230, so as to write the second data carried by the second type of sub-access request into at least one storage block in the second memory 230 according to the memory address carried by the second type of sub-access request, the at least one storage block being determined based on the memory address.

[0124] The embodiment describes a specific access process when the memory access request is used to indicate a write operation, and can realize successful writing of the data carried by the memory access request into at least one storage block in the corresponding memory.

[0125] In some embodiments, the memory access request is used to indicate a read operation, the first type of sub-access request is used to read first target data from at least one storage block in the first memory 220, and the second type of sub-access request is used to indicate reading of second target data from at least one storage block in the second memory 230. The memory address carried by the first type of sub-access request is used to indicate a starting address of the first target data, and the first type of sub-access request further carries a first target length of the first target data. The memory address carried by the second type of sub-access request is used to indicate a starting address of the second target data, and the second type of sub-access request further carries a second target length of the second target data.

[0126] Figure 13 The figure is a schematic diagram of a memory device provided by an example embodiment of the present application, and the memory device 200 further includes a data buffer 350 and a multiplexer (MUX) 360. The first arbitration unit 330 and the second arbitration unit 310 are each further connected with the multiplexer 360, and the multiplexer 360 is connected with the data buffer 350. The multiplexer 360 is configured to select target data to be output, wherein for the first type of sub-access request, the target data is the first target data, and for the second type of sub-access request, the target data is the second target data. The data buffer 350 is configured to temporarily store the first target data and / or the second target data, and is further configured to output the target data corresponding to each sub-access request in the memory access request.

[0127] The first arbitration unit 330 is configured to arbitrate the first-type sub-access request, and send the arbitrated first-type sub-access request to the first memory 220 to read the first target data from at least one memory block in the first memory 220 based on the memory address and the first target length carried by the first-type sub-access request, and send the first target data to the multiplexer 360.

[0128] Since the memory address of the first-type sub-access request is used to indicate the start address of the first target data to be read, and the first-type sub-access request further carries the first target length of the first target data, the first arbitration unit 330 is configured to send the arbitrated first-type sub-access request to the first memory 220 to read the first target data from at least one memory block in the first memory 220 based on the memory address and the first target length carried by the first-type sub-access request. Next, the first arbitration unit 330 is configured to send the first target data to the multiplexer 360.

[0129] The second arbitration unit 340 is configured to arbitrate the second-type sub-access request, and send the arbitrated second-type sub-access request to the second memory 230 to read the second target data from at least one memory block in the second memory 230 based on the memory address and the second target length carried by the second-type sub-access request, and send the second target data to the multiplexer 360.

[0130] Since the memory address of the second-type sub-access request is used to indicate the start address of the second target data to be read, and the second-type sub-access request further carries the second target length of the second target data, the second arbitration unit 340 is configured to send the arbitrated second-type sub-access request to the second memory 230 to read the second target data from at least one memory block in the second memory 230 based on the memory address and the second target length carried by the second-type sub-access request. Next, the second arbitration unit 340 is configured to send the second target data to the multiplexer 360.

[0131] The multiplexer 360 is configured to select target data from the first target data and the second target data, and send the target data to the data buffer 350.

[0132] For example, the multiplexer 360 is an N-to-1 selector. Since the memory device 200 in the embodiment includes the first memory 220 and the second memory 230, the multiplexer 360 is a 2-to-1 selector, which is configured to select target data to be output, wherein for the first-type sub-access request, the target data is the first target data, and for the second-type sub-access request, the target data is the second target data.

[0133] The data buffer 350 is configured to output target data corresponding to each of the plurality of sub-memory access requests in sequence according to the sequence of the plurality of sub-memory access requests in the memory access request.

[0134] The sequence of the plurality of sub-memory access requests in the memory access request refers to the sequence of the plurality of sub-memory access requests when the memory access request is split, or refers to the sequence of the plurality of sub-memory access requests entering the dispatch unit 320, or refers to the sequence of the plurality of sub-memory access requests being arbitrated, or refers to the sequence of the target data corresponding to the plurality of sub-memory access requests entering the data buffer 350. The data buffer 350 is configured to output the target data corresponding to each of the plurality of sub-memory access requests in sequence according to the sequence. The first target data corresponding to the first type of sub-memory access request is output, and the second target data corresponding to the second type of sub-memory access request is output.

[0135] The embodiment describes a specific access process when the memory access request is used to indicate a read operation, and the target data requested by the memory access request can be output.

[0136] Memory access timing In some embodiments, the memory access request is used to request access to the first memory 220, that is, at least one of a read operation and / or a write operation is performed on at least one storage block in the first memory 220. When the memory device 200 receives the memory access request, the relevant information of the memory access request needs to be registered first, for example, at least one of the memory address of the memory access request, the first data carried, the first target data requested to be read, and the starting address and length thereof. Next, the memory access request needs to be arbitrated. In the case of arbitrating the memory access request, the memory access request is sent to the first memory 220 to access the first memory 220 based on the memory access request. It can be understood that, in the case that the memory access request is used to request a write operation, the first data is written into the first memory 220. In the case that the memory access request is used to request a read operation, the first target data is read in different blocks in the first memory 220, and then the first target data is registered and selected by the data selector to output the first target data required to be read.

[0137] Figure 14 FIG. 1 is a schematic diagram of the memory access timing provided by an example embodiment of the present application. The memory access timing is used to represent the sequence of each type of operation when accessing the memory, and is also used to represent the delay between each type of operation.

[0138] For example, the memory access request is used to request access to the first memory 220, and the memory access timing corresponding to the memory access request includes all or part of the following levels in sequence: 1. Register In; the Register In is configured to register a memory access request. For example, the Register In is configured to register information associated with the memory access request, such as at least one of a memory address of the memory access request, first data carried by the memory access request, first target data requested to be read, a start address of the first target data, and a length of the first target data.

[0139] 2. Arbiter; the Arbiter is configured to arbitrate the memory access request. Since the number of the blocks in the first memory 220 is small, the number of the Arbiter configured in the embodiment is also small. For example, as shown in FIG. 2, one Arbiter is configured. Figure 14 It can be understood that the number of the Arbiter corresponding to the first memory 220 can also be set according to actual technical needs and the number of the blocks, as long as the number of the Arbiter corresponding to the first memory 220 is less than the number of the Arbiter corresponding to the second memory 230.

[0140] 3. Memory_req; the Memory_req is configured to request to access the first memory 220, and specifically configured to request to perform at least one of a read operation and a write operation on at least one block in the first memory 220.

[0141] 4. Memory Access; the Memory Access is configured to indicate to access the first memory 220, and specifically configured to perform at least one of a read operation and a write operation on at least one block in the first memory 220.

[0142] 5. Memory Access; the Memory Access is configured to indicate to access the first memory 220, and specifically configured to perform at least one of a read operation and a write operation on at least one block in the first memory 220.

[0143] 6. Data Select; the Data Select is configured to indicate to select the first target data currently output from different blocks in the first memory 220. Since the number of the blocks in the first memory 220 is small, the number of the Data Select configured in the embodiment is also small. For example, as shown in FIG. 2, one Data Select is configured. Figure 14 It can be understood that the number of the Data Select corresponding to the first memory 220 can also be set according to actual technical needs and the number of the blocks, as long as the number of the Data Select corresponding to the first memory 220 is less than the number of the Data Select corresponding to the second memory 230.

[0144] 7. Register Out; the Register Out is configured to output the first target data.

[0145] It should be noted that since the memory access request can be used to indicate a read operation or a write operation, in the case where the memory access request is used to request access to the first memory 220 and is used to indicate a write operation, the memory access timing corresponding to the memory access request is 1-4 in the above memory access timing. In the case where the memory access request is used to request access to the first memory 220 and is used to indicate a read operation, the memory access timing corresponding to the memory access request is 1-7 in the above memory access timing.

[0146] In this embodiment, the memory access timing of the memory access request when accessing the first memory 220 is listed. From the above memory access timing, it can be seen that the access speed of the first memory 220 is faster and the access delay is smaller relative to the second memory 230. It can be further proved by this embodiment that in the case where the storage blocks in the first memory 220 are preferentially allocated during storage block allocation, the data processing efficiency can be significantly improved.

[0147] In some embodiments, the memory access request is used to request access to the second memory 230. When the memory device 200 receives the memory access request, the relevant information of the memory access request needs to be registered first, for example, at least one of the memory address of the memory access request, the second data carried, the second target data requested to be read and its starting address and length. Next, the memory access request needs to be arbitrated. In the case where the memory access request is arbitrated, the memory access request is sent to the second memory 230 to access the second memory 230 based on the memory access request. Since the physical distribution of different blocks in the second memory 230 is dispersed, there is also a path delay in the sending process of the memory access request. It can be understood that in the case where the memory access request is used to request a write operation, the second data is written into the second memory 230. In the case where the memory access request is used to request a read operation, after the second target data is read in different blocks in the second memory 230, the second target data needs to be registered and selected before being output. Since the physical distribution of different blocks in the second memory 230 is dispersed, there is also a path delay in the data sending process.

[0148] Figure 15 is a schematic diagram of the memory access timing provided by an exemplary embodiment of the present application. For example, the memory access request is used to request access to the second memory 230, and the memory access timing corresponding to the memory access request includes all or part of the following levels in turn: 1、Input Register In; the input register is used to indicate the register memory access request. For example, the input register is used to register information related to the memory access request, such as the memory address of the memory access request, the second data carried, the second target data requested to read, and at least one of the starting address and length.

[0149] 2、At least two levels of arbiter operation stage (Arbiter); at least two levels of arbiter operation stage are used to indicate the arbitration of memory access request. Since the number of plates in the second memory 230 is large, the number of arbitration operation stages set in this embodiment is also large, which is set to at least two levels of arbiter operation stage. Figure 15 The first level of arbiter operation stage (Arbiter1) and the second level of arbiter operation stage (Arbiter2) are shown. It can be understood that the number of arbiter operation stages corresponding to the second memory 230 can also be set according to actual technical needs and the number of plates, as long as the number of arbiter operation stages corresponding to the first memory 220 is less than the number of arbiter operation stages corresponding to the second memory 230.

[0150] 3、At least two times of path delay (Path Delay); at least two times of path delay are used to represent the delay between different plates of the second memory 230. Since the physical distribution of different plates of the second memory 230 is scattered, long physical wires are needed to connect each plate, so there will be path delay between different plates. In the process of path delay, a beat operation will be performed on these long physical wires. Among them, the beat can also be understood as register, which means that the signal of the register access request is registered under the clock domain to be used. Figure 15 The first path delay (Path Delay1) and the second path delay (Path Delay) are shown. It can be understood that according to the number of plates actually existing in the second memory 230 and the length of the physical wires between the plates, the specific number of path delays can be adaptively set.

[0151] 4、Memory access request stage (Memory Access); the memory access request stage is used to request access to the second memory 230, and is specifically used to request to perform at least one of read operation and write operation on at least one storage block in the second memory 230.

[0152] 5、Memory access stage (Memory Access); the memory access stage is used to indicate access to the second memory 230, and is specifically used to perform at least one of read operation and write operation on at least one storage block in the second memory 230.

[0153] 6、Memory Out; Memory Out is used to indicate the storage of the second target data read from the different blocks of the second memory 230.

[0154] 7、at least two Path Delays; due to the physical distribution dispersion of the different blocks of the second memory 230, longer physical wires are needed to connect the blocks, thus there will be path delays between the different blocks after the second target data required by the memory access request is read from the second memory 230. After the at least two Path Delays, the second target data can be sent to the Data Select.

[0155] 8、at least two Data Selects; the at least two Data Selects are used to indicate the selection of the second target data currently output from the different blocks of the second memory 230. Since the number of the blocks in the second memory 230 is large, the number of the Data Selects set in this embodiment is also large, which is set as at least two Data Selects. Figure 15 It is shown that two Data Selects are set, which are a first Data Select (Data Select 1) and a second arbitration operation level (Data Select 2). It can be understood that the number of the Data Selects corresponding to the second memory 230 can also be set according to actual technical needs and the number of the blocks, and it is only required that the number of the Data Selects corresponding to the first memory 220 is less than the number of the Data Selects corresponding to the second memory 230.

[0156] 9、Register Out; Memory Out is used to indicate the output of the second target data.

[0157] It should be noted that since the memory access request can be used to indicate the read operation or the write operation, in the case that the memory access request is used to request to access the second memory 230 and is used to indicate the write operation, the memory access timing corresponding to the memory access request is 1-5 in the above memory access timing. In the case that the memory access request is used to request to access the second memory 230 and is used to indicate the read operation, the memory access timing corresponding to the memory access request is 1-9 in the above memory access timing.

[0158] In this embodiment, the memory access request when accessing the second memory 230 is listed, and from the above memory access timing, it can be seen that, relative to the first memory 220, because the arbitration level in the memory access timing corresponding to the second memory 230 is more and there is a path delay, the access speed of the second memory 230 is slower and the access delay is larger. Through this embodiment, it can be further proved that in the case of preferentially allocating each memory block in the first memory 220 when allocating memory blocks, the data processing efficiency can be significantly improved. Moreover, by automatically transferring the data in the second memory 230 to the first memory 220, the data processing efficiency can be further improved.

[0159] Next, the overall architecture and processing mode of the memory device are described.

[0160] Connection relationship Figure 16 is a schematic diagram of the architecture of the memory device provided by an exemplary embodiment of the present application. The memory device 200 includes a memory block allocation unit 210 (Memory Allocate), a first memory 220 (Close Memory), a second memory 230 (Far Memory), a free list register 240 (Freelist), a memory block release unit 250 (Memory Free), a request splitting unit 310 (Burst To Single), a dispatch unit 320 (Disp), a first arbitration unit 330 (Close Memory Arbiter) corresponding to the first memory 220, a second arbitration unit 340 (Far Memory Arbiter) corresponding to the second memory 230, a data buffer 350 (Data Buffer), and a multiplexer 360 (MUX). The request splitting unit 310, the dispatch unit 320, the first arbitration unit 330, the second arbitration unit 340, the data buffer 350, and the multiplexer 360 can be collectively referred to as a read-write unit 300.

[0161] The memory block allocation unit 210 and the memory block release unit 250 are distributed in parallel in the memory device 200. The memory block allocation unit 210 is connected to the free list register 240, and the memory block release unit 250 is connected to the free list register 240. The request splitting unit 310 is connected to the dispatch unit 320, the dispatch unit 320 is connected to the first arbitration unit 330, the first arbitration unit 330 is connected to the first memory 220, the dispatch unit 320 is also connected to the second arbitration unit 340, and the second arbitration unit 340 is connected to the second memory 230. The first arbitration unit 330 and the second arbitration unit 340 are each connected to the multiplexer 360, and the multiplexer 360 is connected to the data buffer 350.

[0162] In some examples, the memory device 200 can also be referred to as a Close Far Memory system.

[0163] The first memory 220, also referred to as a Close Memory system, has a small storage capacity but a fast access speed, usually several clock cycles. The small storage capacity of the first memory 220 mainly manifests in two aspects: 1) a small number of banks; and 2) a small bank depth of each bank. Figure 16 The first memory 220 is exemplified by taking an example of including 4 banks. It should be noted that the first memory 220 can be placed close to the processor in the chip to further improve the access speed of the first memory 220.

[0164] The second memory 230, also referred to as a Far Memory system, has a large storage capacity but a slow access speed, usually tens of clock cycles. The small storage capacity of the second memory 230 mainly manifests in two aspects: 1) a large number of banks; and 2) a large bank depth of each bank. Figure 16 The second memory 230 is exemplified by taking an example of including 6 banks.

[0165] • Encoding mode Referring to Figure 6 the encoding mode of the first memory 220 and the second memory 230. For example, the memory device 200 has M memory blocks, the first memory 220 includes N memory blocks, the N memory blocks correspond to addresses 0 to N-1, the second memory 230 includes M-N memory blocks, the M-N memory blocks correspond to addresses N to M-1, M is greater than N, M and N are integers, and M and N are greater than 0. Wherein, the memory address corresponding to each memory block can be a number, which can be encoded from 0, and the memory addresses corresponding to the M memory blocks of the memory device 200 are 0 to M-1.

[0166] • Data processing mode Referring to Figure 8 the memory block allocation mode. The white area indicates that the memory block corresponding to the memory address is not occupied, and the filled area indicates that the memory block corresponding to the memory address is occupied. Figure 8 The schematic of the memory addresses 0 to 15 is shown, and referring to Figure 8 (a) in FIG. 1, the memory addresses 0-1 and 7-11 correspond to the occupied memory blocks, and the memory addresses 2-6 and 12-15 correspond to the unoccupied memory blocks.

[0167] The memory block allocation unit 210 receives a memory block allocation request 511 (Space_req) sent by the processor. This request 511 requests the allocation of a 2-byte memory block. The memory block allocation unit 210 searches from the low address 0 to the high address 15, finding the first consecutive address segment that meets the allocation conditions. This consecutive address segment is 2-3. Based on the consecutive address segment 2-3, the starting address of the 2-byte memory block is determined to be 2, and its length is 2. This starting address and length are sent to the processor, and the corresponding position in the free list register 240 is marked as 1. After allocation, the 2 bytes of data can be written into the free memory block corresponding to the consecutive address segment 2-3. (Continue to refer to...) Figure 8 As shown in (b), after writing, the memory blocks corresponding to memory addresses 0-3 and 7-11 are occupied, while the memory blocks corresponding to memory addresses 4-6 and 12-15 are not occupied. This memory block allocation method can ensure that each memory block in the first memory 220 is allocated preferentially.

[0168] refer to Figure 11 The diagram shows how memory blocks are released. White areas indicate that the memory block corresponding to that memory address is not occupied, while filled areas indicate that the memory block corresponding to that memory address is occupied. Figure 11 This diagram illustrates memory addresses 0 to 15. (See reference...) Figure 11 As shown in (a), the memory blocks corresponding to memory addresses 0-3 and 7-11 are occupied, while the memory blocks corresponding to memory addresses 4-6 and 12-15 are not occupied.

[0169] The memory block release unit 250 receives a memory block release request 512 (Memory Free_req) sent by the processor. This request 512 requests the release of a 2-byte memory block, indicating a starting address of 2 and a length of 2. The memory block release unit 250 then releases the memory block corresponding to the consecutive address segment 2-3 and marks its corresponding position in the free list register 240 as 0. After release, it continues to refer to... Figure 11 As shown in (b), the memory blocks corresponding to memory addresses 0-1 and 7-11 are occupied, while the memory blocks corresponding to memory addresses 2-6 and 12-15 are not occupied.

[0170] The memory access request 520 (Memory_req) is used to request at least one of a read operation or a write operation to be performed on at least one memory block in the first memory 220, and / or, to request at least one of a read operation or a write operation to be performed on at least one memory block in the second memory 230. Generally, the memory access request 520 sent by the processor is a burst request, which contains a plurality of sub-requests carrying consecutive addresses. The request splitting unit 310 is configured to receive the memory access request 520 sent by the processor, split the memory access request 520 into a plurality of sub-access requests, and send the plurality of sub-access requests to the dispatch unit 320 based on the memory addresses carried by the plurality of sub-access requests.

[0171] In a case where the memory access request 520 is used to request a write operation to be performed on at least one memory block in the first memory 220, the dispatch unit 320 is configured to send the plurality of sub-access requests of the memory access request 520 to the first arbitration unit 330; the first arbitration unit 330 is configured to arbitrate the plurality of sub-access requests, and send the arbitrated sub-access request to the first memory 220, so as to write first data carried by the sub-access request into at least one memory block in the first memory 220 based on the memory address carried by the sub-access request.

[0172] In a case where the memory access request 520 is used to request a read operation to be performed on at least one memory block in the first memory 220, the dispatch unit 320 is configured to send the plurality of sub-access requests of the memory access request 520 to the first arbitration unit 330; the first arbitration unit 330 is configured to arbitrate the plurality of sub-access requests, and send the arbitrated sub-access request to the first memory 220, so as to read first target data requested to be read by the sub-access request from the first memory 220 based on the memory address and the first target length carried by the sub-access request. Next, the first arbitration unit 330 is configured to send the first target data to the multiplexer 360, and the multiplexer 360 is configured to send the first target data to the data buffer 350, and the data buffer 350 is configured to output the first target data, i.e., output the memory response data 530 (Memory_resp).

[0173] In a case where the memory access request 520 is used to request a write operation to be performed on at least one memory block in the second memory 230, the dispatch unit 320 is configured to send the plurality of sub-access requests of the memory access request 520 to the second arbitration unit 340; the second arbitration unit 340 is configured to arbitrate the plurality of sub-access requests, and send the arbitrated sub-access request to the second memory 230, so as to write second data carried by the sub-access request into at least one memory block in the second memory 230 based on the memory address carried by the sub-access request.

[0174] In a case where the memory access request 520 is used to request to perform a read operation on at least one storage block in the second memory 230, the dispatch unit 320 is configured to send a plurality of sub-access requests of the memory access request 520 to the second arbitration unit 340; the second arbitration unit 340 is configured to arbitrate the plurality of sub-access requests, and send the arbitrated sub-access request to the second memory 230, so as to read second target data requested to be read by the sub-access request from the second memory 230 based on a memory address and a second target length carried by the sub-access request. Next, the second arbitration unit 340 is configured to send the second target data to the multiplexer 360, and the multiplexer 360 is configured to send the second target data to the data buffer 350, and the data buffer 350 is configured to output the second target data, i.e., output the memory response data 530 (Memory_resp).

[0175] In summary, the storage device provided by the embodiments of the present application, the memory addresses of the storage device are obtained by encoding each storage block in the first memory and then encoding each storage block in the second memory in a unified encoding manner, which effectively reduces the programming burden of the programmer and improves the programming efficiency. When allocating storage blocks, the storage block allocation unit can automatically allocate each storage block in the first memory in priority, so that the programmer does not need to manually allocate storage blocks, and the storage block allocation efficiency can be significantly improved. Further, since the access speed of the first memory is greater than that of the second memory, by performing storage block allocation in the order from the low address to the high address, each storage block in the first memory can be allocated in priority, and in a case where data is subsequently stored in the first memory, the processor of the chip can directly obtain the corresponding data from the first memory, and the data acquisition speed is fast. Compared with the manner in which data needs to be frequently moved between each level of the storage hierarchy in the related art, the data acquisition efficiency can be improved, which is beneficial to improving the data processing efficiency, thereby improving the overall performance and processing efficiency of the storage device. In addition, when the storage device provided by the embodiments of the present application is applied to actual hardware products, for example, applied to chips, boards, computer equipment, the overall performance and data processing efficiency of the hardware products can be effectively improved, and the competitiveness of the hardware products can be improved.

[0176] Figure 17 is a flowchart of a processing method of a storage device provided by an exemplary embodiment of the present application.

[0177] Reference Figure 3As shown, the memory device 200 includes a read-write unit 300, a first memory 220 and a second memory 230 connected to the read-write unit 300 respectively, the access speed of the first memory 220 is greater than that of the second memory 230, and the memory addresses of the memory device 200 are obtained by encoding each storage block in the first memory 220 and then encoding each storage block in the second memory 230 in a unified encoding manner. In some embodiments, the method can be performed by the memory device 200, specifically by the read-write unit 300 in the memory device 200, and can specifically include step 540: Step 540, the read-write unit 300 performs at least one of a read operation and a write operation on at least one storage block in the first memory 220 and the second memory 230 based on the memory address.

[0178] In some embodiments, the memory device 200 has M storage blocks; the first memory 220 includes N storage blocks, and the corresponding memory addresses of the N storage blocks are 0th to N-1th addresses; the second memory 230 includes M-N storage blocks, and the corresponding memory addresses of the M-N storage blocks are Nth to M-1th addresses; wherein M is greater than N, M and N are integers, and M and N are greater than 0.

[0179] To sum up, the processing method of the memory device provided by the embodiments of the present application, the memory addresses of the memory device are obtained by encoding each storage block in the first memory and then encoding each storage block in the second memory in a unified encoding manner, which effectively reduces the programming burden of programmers and improves the programming efficiency. The first memory and the second memory of the memory device are connected to the read-write unit respectively, and at least one of a read operation and a write operation can be performed on at least one storage block in the first memory and the second memory based on the memory address through the read-write unit, so that the first memory and the second memory can be read and written respectively. Compared with the way of reading and writing the memory in the related art according to the storage hierarchy, the read-write efficiency of the first memory and the second memory is improved, and the overall read-write efficiency of the memory device is improved. Compared with the way of frequently moving data between the storage hierarchies in the related art, the data processing efficiency is improved, and the overall operation efficiency of the memory device is improved.

[0180] In some embodiments, with reference to Figure 7 As shown, the memory device 200 further includes a storage block allocation unit 210, and the method further includes steps 550, 560 and 570: Step 550, the storage block allocation unit 210 receives a storage block allocation request sent by a processor, and the storage block allocation request is used to request to allocate a storage block of a first storage capacity in the memory device 200; At step 560, the storage block allocation unit 210 allocates the storage block of the first storage capacity based on the memory address in the order from the low-bit address to the high-bit address. At step 570, the storage block allocation unit 210 sends the first address and the first length corresponding to the storage block of the first storage capacity to the processor.

[0181] In some embodiments, the step 560 can be implemented as step 562 and step 564: At step 562, the storage block allocation unit 210 finds the free storage block not occupied based on the memory address in the order from the low-bit address to the high-bit address. At step 564, the storage block allocation unit 210 determines the first address and the first length corresponding to the storage block of the first storage capacity from the free storage block to allocate the storage block of the first storage capacity.

[0182] In some embodiments, the step 564 is implemented as step 5641: At step 5641, the storage block allocation unit 210 further determines the first continuous address segment meeting the allocation condition from the memory address corresponding to the free storage block based on the number of the storage blocks corresponding to the first storage capacity; determines the first address and the first length corresponding to the storage block of the first storage capacity based on the continuous address segment; wherein the continuous address segment refers to the address segment corresponding to at least two free storage blocks in sequence, and the allocation condition includes the number of the free storage blocks corresponding to the continuous address segment, which is equal to the number of the storage blocks corresponding to the first storage capacity.

[0183] In some embodiments, referring to Figure 9 As shown in the figure, the storage device 200 further includes the free list register 240 connected with the storage block allocation unit 210, the free list register 240 is used to record the memory address and the occupation of each storage block in the first memory 220 and each storage block in the second memory 230, and the method further includes step 5642: At step 5642, the storage block allocation unit 210 further marks the corresponding position of the storage block of the first storage capacity in the free list register 240 as the first value; wherein the first value is used to represent that the storage block is occupied.

[0184] In some embodiments, referring to Figure 10 As shown in the figure, the storage device 200 further includes the storage block release unit 250 distributed in parallel with the storage block allocation unit 210; then after the step 570, or, after the step 5642, the method further includes step 580: At step 580, the storage block releasing unit 250 receives the storage block releasing request sent by the processor, the storage block releasing request is used to request releasing the second storage capacity of the storage block in the memory device 200, and indicates the second address and the second length of the second storage capacity of the storage block; and the second storage capacity of the storage block is released based on the second address and the second length.

[0185] In some embodiments, the storage block releasing unit 250 is connected with the free list memory 240. After step 580, the method further comprises step 590: At step 590, the storage block releasing unit 250 further marks the corresponding position of the second storage capacity of the storage block in the free list register 240 as a second value; wherein the second value is used to represent that the storage block is not occupied.

[0186] In some embodiments, the method can further comprise step 620: At step 620, the storage block allocating unit 210 further transfers the target transfer data into at least one storage block in the first memory 220 based on the storage capacity of the target transfer data in the second memory 230 and the memory address of the memory device.

[0187] In some embodiments, step 620 is specifically implemented as step 622: At step 622, the storage block allocating unit 210 searches the unoccupied free storage block in the order from the low address to the high address based on the memory address of the memory device 200; and determines the storage block allocated to the target transfer data from the free storage block based on the number of storage blocks corresponding to the storage capacity of the target transfer data, so as to transfer the target transfer data into at least one storage block in the first memory 220.

[0188] In some embodiments, referring to Figure 12 As shown in the figure, the read-write unit 300 in the memory device 200 comprises a request splitting unit 310, a dispatching unit 320, a first arbitration unit 330 corresponding to the first memory 220, a second arbitration unit 340 corresponding to the second memory 230, the request splitting unit 310 is connected with the dispatching unit 320, the dispatching unit 320 is connected with the first arbitration unit 330, the first arbitration unit 330 is connected with the first memory 220, the dispatching unit 320 is further connected with the second arbitration unit 340, and the second arbitration unit 340 is connected with the second memory 230; the method can further comprise step 630, step 640, step 650 and step 660: At step 630, the request splitting unit 310 receives the memory access request sent by the processor, splits the memory access request into a plurality of sub-access requests, and sends the plurality of sub-access requests to the dispatching unit 320 based on the memory address carried by each of the plurality of sub-access requests; At step 640, the dispatch unit 320 sends first-type sub-access requests in the plurality of sub-access requests to the first arbitration unit 330, and sends second-type sub-access requests in the plurality of sub-access requests to the second arbitration unit 340, the first-type sub-access requests being used to request at least one of a read operation and a write operation to be performed on at least one memory block in the first memory 220, and the second-type sub-access requests being used to request at least one of a read operation and a write operation to be performed on at least one memory block in the second memory 230. At step 650, the first arbitration unit 330 arbitrates the first-type sub-access requests, and sends the arbitrated first-type sub-access requests to the first memory 220 to perform at least one of a read operation and a write operation on at least one memory block in the first memory 220 based on a memory address carried by the first-type sub-access requests. At step 660, the second arbitration unit 340 arbitrates the second-type sub-access requests, and sends the arbitrated second-type sub-access requests to the second memory 230 to perform at least one of a read operation and a write operation on at least one memory block in the second memory 230 based on a memory address carried by the second-type sub-access requests.

[0189] In some embodiments, the memory access request is used to indicate a write operation, the first-type sub-access requests are used to indicate that first data is to be written into at least one memory block in the first memory 220, and the first-type sub-access requests further carry the first data, and the second-type sub-access requests are used to indicate that second data is to be written into at least one memory block in the second memory 230, and the second-type sub-access requests further carry the second data. For example, step 650 is implemented as step 652, and step 660 is implemented as step 662: At step 652, the first arbitration unit 330 arbitrates the first-type sub-access requests, and sends the arbitrated first-type sub-access requests to the first memory 220 to write the first data into at least one memory block in the first memory 220 based on a memory address carried by the first-type sub-access requests. At step 662, the second arbitration unit 340 arbitrates the second-type sub-access requests, and sends the arbitrated second-type sub-access requests to the second memory 230 to write the second data into at least one memory block in the second memory 230 based on a memory address carried by the second-type sub-access requests.

[0190] In some embodiments, with reference to Figure 13 As shown, the read-write unit 300 further includes a multiplexer 360 and a data buffer 350, and the first arbitration unit 330 and the second arbitration unit 340 are each further connected with the multiplexer 360, and the multiplexer 360 is connected with the data buffer 350.

[0191] In some embodiments, the memory access request is used to indicate a read operation, the first type of sub-access request is used to request reading the first target data from at least one storage block in the first memory 220, the first type of sub-access request further carries a first target length of the first target data, and the second type of sub-access request is used to indicate reading the second target data from at least one storage block in the second memory 230, the second type of sub-access request further carries a second target length of the second target data. For example, the step 650 is implemented as the step 654, the step 660 is implemented as the step 664, and the method further includes the steps 670 and 680: The step 654 is that the first arbitration unit 330 arbitrates the first type of sub-access request, sends the arbitrated first type of sub-access request to the first memory 220, reads the first target data from at least one storage block in the first memory 220 based on the memory address and the first target length carried by the first type of sub-access request, and sends the first target data to the multiplexer 360. The step 664 is that the second arbitration unit 340 arbitrates the second type of sub-access request, sends the arbitrated second type of sub-access request to the second memory 230, reads the second target data from at least one storage block in the second memory 230 based on the memory address and the second target length carried by the second type of sub-access request, and sends the second target data to the multiplexer 360. The step 670 is that the multiplexer 360 selects the target data from the first target data and the second target data, and sends the target data to the data buffer 350. The step 680 is that the data buffer 350 sequentially outputs the target data corresponding to the plurality of sub-access requests in the order of the plurality of sub-access requests in the memory access request.

[0192] In some embodiments, the memory access request is used to request accessing the first memory 220, and the memory access timing corresponding to the memory access request sequentially includes all or part of the following levels: 1. An input register level, which is used to indicate registering the memory access request; 2. An arbitration operation level, which is used to indicate arbitrating the memory access request; 3. A memory access request level, which is used to request accessing the first memory 220; 4. A memory access level, which is used to indicate accessing the first memory 220; 5. A memory output data register level, which is used to indicate registering the first target data read from different blocks of the first memory 220; 6、data selection stage; the data selection stage is configured to indicate selection of the first target data from different tiles of the first memory 220; 7、register output stage; the register output stage is configured to indicate output of the first target data.

[0193] In some embodiments, the memory access request is configured to request access to the second memory 230, and the memory access request corresponds to a memory access timing sequence including all or part of the following stages: 1、input register stage; the input register stage is configured to indicate registration of the memory access request; 2、at least two arbitration operation stages; the at least two arbitration operation stages are configured to indicate arbitration of the memory access request; 3、at least two path delays; the at least two path delays are configured to represent delays in accessing the second memory 230; 4、memory access request stage; the memory access request stage is configured to request access to the second memory 230; 5、memory access stage; the memory access stage is configured to indicate access to the second memory 230; 6、memory output data register stage; the memory output data register stage is configured to indicate registration of the second target data read from different tiles of the second memory 230; 7、at least two path delays; 8、at least two data selection stages; the at least two data selection stages are configured to indicate selection of the second target data from different tiles of the second memory 230; 9、register output stage; the register output stage is configured to indicate output of the second target data.

[0194] It should be noted that the units of the processing method of the memory device correspond to the steps, and the details and beneficial effects thereof can refer to the related embodiments of the memory device described above, and will not be described here.

[0195] Figure 18 is a schematic diagram of a chip provided by an exemplary embodiment of the present application. In the exemplary embodiment, the present application further provides a chip 400, which includes a processor 410 and a memory device 200. Optionally, the processor 410 can send at least one of a memory block allocation request, a memory block release request, and a memory access request to the memory device 200. The memory device 200 can refer to the detailed description of the memory device 200 in the foregoing embodiments, and will not be described here.

[0196] In some embodiments, in the chip 400, the first memory 220 of the memory device 200 can be placed close to the processor 410 to further improve the access speed of the first memory 220. Close means that the physical wire length between the interface of the first memory 220 and the interface of the processor 410 is less than a length threshold, or the first physical wire length between the interface of the first memory 220 and the interface of the processor 410 is less than the second physical wire length between the interface of the second memory 230 and the interface of the processor 410. For the specific connection mode of the physical wire between the processor 410 and the memory device 200 and the physical wire inside the memory device 200, the present embodiment does not make any limitation, as long as the corresponding function can be realized.

[0197] As an example, taking the application of the chip 400 in the field of image processing technology as an example, the chip 400 needs to process image data. In some examples, the image data can be from the computer device where the chip 400 is located. During the process of processing the image data by the chip 400, the processor 410 sends a memory block allocation request to the memory device 200, the memory block allocation request is used to request to allocate a memory block with a first storage capacity, the first storage capacity is determined based on the size of the currently processed image data; the memory block allocation unit 210 in the memory device 200 is used to receive the memory block allocation request, allocate a memory block with a first storage capacity based on the memory address in the order from the low address to the high address, and send the first address and the first length corresponding to the memory block with the first storage capacity to the processor. In the case that the memory block in the first memory 220 in the memory device 200 is temporarily occupied, the memory block allocation unit 210 is used to allocate the memory block in the second memory 230 to store the currently processed image data. After the memory block release unit 250 releases the memory block in the first memory 220, the memory block allocation unit 210 can also be used to transfer the currently processed image data in the second memory 230 to the first memory 220 based on the storage capacity of the currently processed image data in the second memory 230 and the memory address of the memory device 200.

[0198] Figure 19 is a schematic diagram of a board card provided by an example embodiment of the present application. In the example embodiment, the present embodiment further provides a board card 600, which comprises a processor 610 and a memory device 200. Optionally, the processor 610 can send at least one of a memory block allocation request, a memory block release request, and a memory access request to the memory device 200. The memory device 200 can refer to the detailed description of the memory device 200 in the foregoing embodiments, which will not be described herein again.

[0199] In some embodiments, the board card can also be referred to as a server board card. The board card is a kind of printed circuit board (PCB) which is made with a pin core and can be inserted into a slot of a mainboard of a server to control the operation of hardware, such as a display, a capture card and other hardware devices. After a driver or a computer program is installed in the board card, the board card can realize corresponding functions. The driver or the computer program can be installed in the processor 610, and the processor 610 controls the operation of the driver or the computer program, and in combination with the storage device 200, the corresponding functions of the board card 600 are realized.

[0200] In some embodiments, the embodiments of the present application further provide a computer device, which includes the storage device 200, or the computer device includes the chip 400, or the computer device includes the board card 600. Optionally, in the case where the computer device includes the chip 400, the computer device can be realized as a terminal, and the terminal 120 shown in FIG. 1 is referred to. Figure 1 In the case where the computer device includes the board card 600, the computer device can be realized as a server, and the server 140 shown in FIG. 1 is referred to. Figure 1

[0201] Optionally, the embodiments of the present application further provide a computer device, which includes a processor and a storage device, and the storage device stores a computer program; and the processor is used to execute the computer program in the storage device to realize the processing method of the storage device provided by each method embodiment.

[0202] For example, Figure 20 is a structural block diagram of a computer device 1000 provided by an exemplary embodiment of the present application. Optionally, the computer device 1000 is a server 1000.

[0203] Generally, the server 1000 includes a processor 1001 and a storage device 1002.

[0204] ​The processor 1001 can include one or more processing cores, such as a 4-core processor, an 8-core processor, and the like. The processor 1001 can be implemented in at least one of a hardware form of a digital signal processing (DSP), a field-programmable gate array (FPGA), a programmable logic array (PLA), and the like. The processor 1001 can also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processing unit (CPU), and the coprocessor being a low-power processor for processing data in a standby state. In some embodiments, the processor 1001 can be integrated with a graphics processor (GPU) that is responsible for rendering and drawing content required to be displayed by a display screen. In some embodiments, the processor 1001 can further include an artificial intelligence (AI) processor for processing computing operations related to machine learning.

[0205] The storage device 1002 can include one or more computer-readable storage media that can be non-transitory. The first memory and the second memory in the storage device 1002 can also be a high-speed random access memory, and a non-volatile memory such as one or more disk storage devices, flash storage devices. In some embodiments, the non-transitory computer-readable storage medium in the storage device 1002 is used to store at least one instruction for being executed by the processor 1001 to implement the processing method of the storage device provided by the method embodiments in the present application.

[0206] In some embodiments, the server 1000 can also optionally include an input interface 1003 and an output interface 1004. The processor 1001, the storage device 1002, and the input interface 1003 and the output interface 1004 can be connected through a bus or a signal line. Each peripheral device can be connected to the input interface 1003 and the output interface 1004 through a bus, a signal line, or a circuit board. The input interface 1003 and the output interface 1004 can be used to connect at least one input / output (I / O) related peripheral device to the processor 1001 and the storage device 1002. In some embodiments, the processor 1001, the storage device 1002, and the input interface 1003 and the output interface 1004 are integrated on the same chip or circuit board; in some other embodiments, any one or both of the processor 1001, the storage device 1002, and the input interface 1003 and the output interface 1004 can be implemented on a separate chip or circuit board, and the embodiments of the present application are not limited in this regard.

[0207] For example, Figure 21 is a structural block diagram of a computer device 2000 provided by an exemplary embodiment of the present application. Optionally, the computer device 2000 is a terminal 2000.

[0208] The computer device 2000 can be a portable mobile terminal, which is also referred to as a mobile terminal in the present embodiment. For example, the computer device 2000 can be a smart phone, a tablet computer, an MP3 (Moving Picture Experts Group Audio Layer III) player, or an MP4 (Moving Picture Experts Group Audio Layer IV) player. The computer device 2000 can also be referred to as a user equipment, a portable terminal, or other names.

[0209] Generally, the computer device 2000 includes a processor 2001 and a storage device 2002.

[0210] Processor 2001 may include one or more processing cores, such as a quad-core processor, an octa-core processor, etc. Processor 2001 may be implemented using at least one hardware form selected from DSP (Digital Signal Processing), FPGA (Field Programmable Gate Array), and PLA (Programmable Logic Array). Processor 2001 may also include a main processor and a coprocessor. The main processor, also known as a CPU (Central Processing Unit), is used to process data in the wake-up state; the coprocessor is a low-power processor used to process data in the standby state. In some embodiments, processor 2001 may integrate a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the screen. In some embodiments, processor 2001 may also include an AI (Artificial Intelligence) processor, which is used to handle computational operations related to machine learning.

[0211] Storage device 2002 may include one or more computer-readable storage media, which may be tangible and non-transitory. Storage device 2002 may also include high-speed random access memory and non-volatile storage devices, such as one or more disk storage devices or flash memory devices. In some embodiments, the non-transitory computer-readable storage medium in storage device 2002 is used to store at least one instruction, which is executed by processor 2001 to implement the processing method of the storage device provided in the embodiments of this application.

[0212] In some embodiments, the computer device 2000 may optionally include a peripheral device interface 2003 and at least one peripheral device. Specifically, the peripheral device includes at least one of a radio frequency circuit 2004, a touch display screen 2005, a camera 2006, an audio circuit 2007, and a power supply 2008. The computer device 2000 also includes one or more sensors 2009. The one or more sensors 2009 include, but are not limited to, an accelerometer 2010, a gyroscope 2011, a pressure sensor 2012, an optical sensor 2013, and a proximity sensor 2014.

[0213] Those skilled in the art will understand that Figure 20 The structure shown does not constitute a limitation on the computer device 1000. Figure 21The structure shown in the figure does not constitute a limitation on the computer device 2000, and can include more or fewer components than shown, or combine certain components, or adopt a different arrangement of components.

[0214] In an example embodiment, the present application provides a chip, which includes programmable logic circuit and / or program instructions, and when the chip is running on a computer device, is used to implement the processing method of the storage device provided by the above method embodiments.

[0215] In an example embodiment, the present application provides a computer readable storage medium, which stores a computer program, and the computer program is loaded and executed by a processor to implement the processing method of the storage device provided by the above method embodiments.

[0216] In an example embodiment, the present application provides a computer program product or computer program, which includes computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the processor of the computer device is loaded and executed to implement the processing method of the storage device provided by the above method embodiments.

[0217] The above-mentioned serial numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0218] Those skilled in the art can understand that all or part of the steps of the above-mentioned embodiments can be completed by hardware, or by program instructing relevant hardware, and the program can be stored in a computer readable storage medium. The above-mentioned computer readable storage medium can be a read-only memory, a magnetic disk or an optical disk.

[0219] Those skilled in the art should realize that in one or more of the above examples, the functions described in the embodiments of the present application can be realized by hardware, software, firmware or any combination thereof. When realized by software, these functions can be stored in a computer readable medium or transmitted as one or more instructions or codes on a computer readable medium. The computer readable medium includes computer storage medium and communication medium, wherein the communication medium includes any medium that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general or special purpose computer.

[0220] The above is only an optional embodiment of the present application, and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A memory device, comprising: The memory device comprises a read-write unit, a first memory and a second memory connected to the read-write unit respectively; The access speed of the first memory is greater than that of the second memory; the memory addresses of the memory device are obtained by encoding each memory block in the first memory and then encoding each memory block in the second memory according to a unified encoding mode; The read-write unit is configured to perform at least one of a read operation and a write operation on at least one memory block in the first memory and the second memory based on the memory address.

2. The memory device of claim 1, wherein, The memory device has M memory blocks; The first memory comprises N memory blocks, and the corresponding memory addresses of the N memory blocks are addresses 0 to N-1; The second memory comprises M-N memory blocks, and the corresponding memory addresses of the M-N memory blocks are addresses N to M-1; Wherein, the M is greater than the N, the M, the N is an integer, the M, the N is greater than 0.

3. The memory device of claim 1 or 2, wherein, The memory device further comprises a memory block allocation unit; The memory block allocation unit is configured to receive a memory block allocation request sent by a processor, the memory block allocation request being used to request allocation of a first storage capacity of memory blocks in the memory device; According to the order from the low address to the high address, the first storage capacity of memory blocks is allocated based on the memory address; The first address and the first length corresponding to the first storage capacity of memory blocks are sent to the processor.

4. The memory device of claim 3, wherein The memory block allocation unit is configured to find an unoccupied idle memory block from the low address to the high address based on the memory address; The first address and the first length corresponding to the first storage capacity of memory blocks are determined from the idle memory block to allocate the first storage capacity of memory blocks.

5. The memory device of claim 4, wherein The memory block allocation unit is configured to determine a first continuous address segment meeting the allocation condition from the memory addresses corresponding to the idle memory blocks based on the number of memory blocks corresponding to the first storage capacity; The first address and the first length corresponding to the first storage capacity of memory blocks are determined based on the continuous address segment; Wherein, the continuous address segment refers to the address segments corresponding to at least two continuous idle memory blocks, and the allocation condition includes the number of idle memory blocks corresponding to the continuous address segment, which is equal to the number of memory blocks corresponding to the first storage capacity.

6. The memory device of any one of claims 1 to 5, wherein, The memory device further comprises an idle list register, the memory block allocation unit is connected to the idle list memory, and the idle list register is used to record the memory address and the occupation of each memory block in the first memory and each memory block in the second memory; The memory block allocation unit is further configured to mark the corresponding position of the first storage capacity of memory blocks in the idle list register as a first value; Wherein, the first value is used to represent that the memory block is occupied.

7. The memory device of any one of claims 1 to 6, wherein, The memory device further comprises a memory block release unit distributed in parallel with the memory block allocation unit; The memory block release unit is configured to receive a memory block release request sent by the processor, the memory block release request being used to request to release a second memory block in the second storage capacity of the memory device and indicate a second address and a second length of the second memory block; and release the second memory block in the second storage capacity based on the second address and the second length.

8. The memory device of claim 7, wherein, The memory block release unit is connected with the free list memory; The memory block release unit is further configured to mark a corresponding position of the second memory block in the free list register as a second value; The second value is used to represent that the memory block is not occupied.

9. The memory device of any one of claims 1 to 8, wherein, The read-write unit comprises a request splitting unit, a dispatching unit, a first arbitration unit corresponding to the first memory, and a second arbitration unit corresponding to the second memory; the request splitting unit is connected with the dispatching unit; the dispatching unit is connected with the first arbitration unit; the first arbitration unit is connected with the first memory; the dispatching unit is further connected with the second arbitration unit; and the second arbitration unit is connected with the second memory. The request splitting unit is configured to receive a memory access request sent by the processor, split the memory access request into a plurality of sub-access requests, and send the plurality of sub-access requests to the dispatching unit based on memory addresses carried by the plurality of sub-access requests respectively. The dispatching unit is configured to send a first type of sub-access request in the plurality of sub-access requests to the first arbitration unit and send a second type of sub-access request in the plurality of sub-access requests to the second arbitration unit; the first type of sub-access request is used to request to perform at least one of the read operation and the write operation on at least one memory block in the first memory; and the second type of sub-access request is used to request to perform at least one of the read operation and the write operation on at least one memory block in the second memory. The first arbitration unit is configured to arbitrate the first type of sub-access request and send an arbitrated first type of sub-access request to the first memory, so as to perform at least one of the read operation and the write operation on at least one memory block in the first memory based on a memory address carried by the first type of sub-access request. The second arbitration unit is configured to arbitrate the second type of sub-access request and send an arbitrated second type of sub-access request to the second memory, so as to perform at least one of the read operation and the write operation on at least one memory block in the second memory based on a memory address carried by the second type of sub-access request.

10. The memory device of claim 9, wherein, The memory access request is used for indicating the write operation, the first type sub-access request is used for indicating writing first data into at least one memory block in the first memory, and the first type sub-access request also carries the first data; the second type sub-access request is used for indicating writing second data into at least one memory block in the second memory, and the second type sub-access request also carries the second data; The first arbitration unit is configured to arbitrate the first type sub-access request, and send the arbitrated first type sub-access request to the first memory, so as to write the first data into at least one memory block in the first memory based on a memory address carried by the first type sub-access request; The second arbitration unit is configured to arbitrate the second type sub-access request, and send the arbitrated second type sub-access request to the second memory, so as to write the second data into at least one memory block in the second memory based on a memory address carried by the second type sub-access request.

11. The memory device of claim 9, wherein, The read-write unit further comprises a multiplexer and a data buffer, and the first arbitration unit and the second arbitration unit are connected with the multiplexer respectively, and the multiplexer is connected with the data buffer; The memory access request is used for indicating the read operation, the first type sub-access request is used for requesting to read first target data from at least one memory block in the first memory, and the first type sub-access request further carries a first target length of the first target data; and the second type sub-access request is used for indicating to read second target data from at least one memory block in the second memory, and the second type sub-access request further carries a second target length of the second target data; The first arbitration unit is configured to arbitrate the first type sub-access request, and send the arbitrated first type sub-access request to the first memory, so as to read the first target data from at least one memory block in the first memory based on a memory address carried by the first type sub-access request and the first target length, and send the first target data to the multiplexer; The second arbitration unit is configured to arbitrate the second type sub-access request, and send the arbitrated second type sub-access request to the second memory, so as to read the second target data from at least one memory block in the second memory based on a memory address carried by the second type sub-access request and the second target length, and send the second target data to the multiplexer; The multiplexer is configured to select target data from the first target data and the second target data, and send the target data to the data buffer; The data buffer is configured to sequentially output the target data corresponding to the plurality of sub-access requests in the order of the plurality of sub-access requests in the memory access request.

12. The memory device of any one of claims 9 to 11, wherein, The memory access request is used for requesting to access the first memory, and a memory access request corresponding to a memory access timing successively includes all or part of the following levels: An input register level, which is used for indicating to register the memory access request; An arbitration operation level, which is used for indicating to arbitrate the memory access request; A memory access request level, which is used for requesting to access the first memory; A memory access level, which is used for indicating to access the first memory; A memory output data register level, which is used for indicating to register the first target data read from different plate blocks of the first memory; A data selection level, which is used for indicating to select the first target data from different plate blocks of the first memory; A register output level; The memory output level is used for indicating to output the first target data.

13. The memory device of any one of claims 9 to 11, wherein, The memory access request is used for requesting to access the second memory, and a memory access request corresponding to a memory access timing successively includes all or part of the following levels: An input register level, which is used for indicating to register the memory access request; At least two arbitration operation levels, which are used for indicating to arbitrate the memory access request; At least two path delays, which are used for representing delays when accessing the second memory; A memory access request level, which is used for requesting to access the second memory; A memory access level, which is used for indicating to access the second memory; A memory output data register level, which is used for indicating to register the second target data read from different plate blocks of the second memory; The at least two path delays; At least two data selection levels, which are used for indicating to select the second target data from different plate blocks of the second memory; A register output level; The memory output level is used for indicating to output the second target data.

14. A chip, characterized by The chip comprises a processor and the memory device according to any one of claims 1 to 13.

15. A board card, characterized by The board card comprises the memory device according to any one of claims 1 to 13.

16. A computer device, comprising: The computer device comprises the memory device according to any one of claims 1 to 13, or the chip according to claim 14, or the board card according to claim 15.

17. A processing method of a memory device, characterized by, The memory device comprises a read-write unit, and a first memory and a second memory connected to the read-write unit respectively; The access speed of the first memory is greater than that of the second memory; the memory addresses of the memory device are obtained by encoding each storage block in the first memory and then encoding each storage block in the second memory according to a unified encoding mode; and the method comprises: The read-write unit performs at least one of a read operation and a write operation on at least one storage block in the first memory and the second memory based on the memory addresses.

18. The method of claim 17, wherein, The memory device has M storage blocks in common; The first memory includes N memory blocks, and corresponding memory addresses of the N memory blocks are 0th to N-1th addresses; The second memory includes M-N memory blocks, and corresponding memory addresses of the M-N memory blocks are Nth to M-1th addresses; Wherein, the M is greater than the N, the M and the N are integers, and the M and the N are greater than 0.

19. The method of claim 17 or 18, wherein, The memory device further includes a memory block allocation unit; and the method further includes: The memory block allocation unit receives a memory block allocation request sent by a processor, the memory block allocation request being used to request allocation of a first storage capacity of memory blocks in the memory device; allocates the memory blocks of the first storage capacity based on the memory addresses in an order from a low address to a high address; and sends a first address and a first length corresponding to the memory blocks of the first storage capacity to the processor.

20. The method of claim 19, wherein, The memory block allocation unit allocates the memory blocks of the first storage capacity based on the memory addresses in the order from the low address to the high address, and includes: The memory block allocation unit finds unoccupied free memory blocks based on the memory addresses in the order from the low address to the high address; determines the first address and the first length corresponding to the memory blocks of the first storage capacity from the free memory blocks to allocate the memory blocks of the first storage capacity.

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