Non-mask drive register dynamic cascade method and device based on bus broadcast

Abstract

The invention provides a non-mask drive register dynamic cascade method and device based on bus broadcast, and belongs to the technical field of processor architecture design. According to the non-mask drive register dynamic cascading method based on the bus broadcast, cascading configuration and instruction execution are completed in parallel in the instruction decoding period, assembly line refreshing is not needed, the real-time performance and the response speed of a system are greatly improved, a processor can complete switching of register configuration within extremely short time, and the system reliability is improved. The operation is immediately carried out, so that the delay of a plurality of clock cycles caused by pipeline refreshing in the traditional architecture is avoided; through dynamic recombination of the logic module, the processor can flexibly adjust the bit width and the number of the registers so as to adapt to different application requirements, and rapid switching and power consumption control are achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of processor architecture design, and particularly relates to a non-masked driving register dynamic cascading method and device based on bus broadcasting. BACKGROUND

[0002] Register cascading is to connect the outputs of multiple registers with the inputs of the next register, forming a longer register chain to store or process more data bits. Dynamic cascading can dynamically adjust the connection relationship and number of registers during system operation according to actual needs, realizing flexible configuration and expansion of register resources.

[0003] In different running stages, the cascading structure of the registers can be dynamically adjusted according to the task requirements, optimizing resource allocation and improving system performance and efficiency. When processing different types and lengths of signals, dynamic cascading registers can conveniently adjust the scale of data storage and processing to adapt to the requirements of various signal processing algorithms.

[0004] Some platforms rely on predicate register configuration register groups, which requires 3-5 cycles to flush the pipeline when switching. In task scenarios with high real-time requirements, such delays may affect the timely processing and response of tasks, resulting in certain limitations on the performance of the system. Some platforms use a mask matrix to select a register window, with a conflict rate as high as 35% when switching between multiple tasks. High conflict rate means that when multiple tasks are executed concurrently, the selection and access of the register window by different tasks are likely to conflict, which will cause resource competition between tasks and reduce the parallel processing capability and overall performance of the system. Some platforms use AVX-512 mask registers for register cascading schemes, with a switching delay of 4-6 cycles and complex mask configuration, inefficient interrupt processing. Longer switching delay will affect the rapid switching of tasks and the timely response of the system to interrupts, especially in scenarios that require frequent interrupt processing or task switching. Some platforms use extended instructions LSX / LASX for register cascading, with a switching delay of 5-8 cycles, static grouping and no support for dynamic reorganization. Longer switching delay will also negatively affect system performance, especially in scenarios that require rapid task switching or interrupt processing. The static grouping of the register organization method lacks flexibility and cannot be dynamically adjusted and optimized according to different application requirements and task characteristics. Some platforms use custom vector extension instructions for register cascading, with a switching delay of 3-7 cycles, high hardware resource occupancy and poor energy efficiency. Higher hardware resource occupancy means that a large amount of chip area, power consumption and other hardware resources are consumed when implementing register cascading and related functions, which not only increases the cost and power consumption of the chip, but also limits the integration and application scenarios of the chip.

[0005] In the above different platforms, some register cascade schemes need to flush the pipeline to ensure the correctness and consistency of data when performing dynamic bit width switching, which interrupts the execution of real-time tasks and makes the tasks unable to run continuously, thereby affecting the real-time performance and reliability of the system. The mask configuration process of some register cascade schemes itself involves a series of operations and controls, such as reading and writing of registers, updating of states, etc., which consumes additional power consumption. Therefore, how to provide a cascade scheme that can ensure the real-time performance of the system and has better power consumption is a problem to be solved. SUMMARY

[0006] The application provides a non-mask driven register dynamic cascade method and device based on bus broadcast, to solve the defects of poor real-time performance and stability of the cascade scheme in the prior art, and to realize fast switching to ensure real-time performance and control power consumption.

[0007] The application provides a non-mask driven register dynamic cascade method based on bus broadcast, comprising:

[0008] processing multiple cascade configuration requests by a bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm;

[0009] generating a register cascade chain by a dynamic reconfiguration logic module according to the decoding parameters of the multiple cascade configuration requests, using a combination logic composed of multiple logic gate circuits;

[0010] performing target instructions by a processor based on an instruction set architecture and an execution unit to automatically adapt the bit width of the current cascade configuration, and operating the cascade register chain, so that the cascade configuration is completed in parallel with instruction decoding and instruction execution.

[0011] According to the non-mask driven register dynamic cascade method based on bus broadcast provided by the application, before the bus arbiter receives the multiple cascade configuration requests, the method further comprises:

[0012] receiving a bus broadcast instruction by a processor, the bus broadcast instruction being used to indicate a starting register address and a target bit width;

[0013] parsing the operation code and parameters of the bus broadcast instruction by an instruction decoder to generate multiple cascade configuration requests;

[0014] triggering the bus arbiter to process the multiple cascade configuration requests by the instruction decoder.

[0015] According to the non-mask driven register dynamic cascade method based on bus broadcast provided by the application, the bus arbiter processes multiple cascade configuration requests to allocate bus bandwidth based on a hybrid arbitration algorithm, comprising:

[0016] determining allocation of bus bandwidth based on priority and timestamp of corresponding task of multi-path cascading configuration request by the bus arbiter;

[0017] allocating bypass channel resource to the task in case that the task is an urgent task.

[0018] According to the application, a bus broadcast-based non-masked driving register dynamic cascading method is provided, before the register cascading chain is generated by the combination logic composed of multiple logic gate circuits according to the decoding parameters of the multi-path cascading configuration request through the dynamic reorganization logic module, the method further comprises:

[0019] checking whether there is resource conflict between the current configuration and the historical record through the cascading state cache;

[0020] if there is conflict and the current configuration priority is lower, rolling back to the nearest compatible historical configuration stored in the cascading state cache.

[0021] According to the application, a bus broadcast-based non-masked driving register dynamic cascading method is provided, after the current configuration and the historical record are checked through the cascading state cache, the method further comprises:

[0022] if there is conflict and the current configuration priority is higher, forcibly covering the old configuration and saving the historical state to the cascading state cache.

[0023] According to the application, a bus broadcast-based non-masked driving register dynamic cascading method is provided, the method further comprises:

[0024] based on the least recently used strategy, storing the current cascading configuration into the cascading state cache.

[0025] According to the application, a bus broadcast-based non-masked driving register dynamic cascading method is provided, the register cascading chain comprises:

[0026] the register cascading chain is generated by mapping the physical register to the virtual wide-bit register through the dynamic reorganization logic to splice the physical register.

[0027] The application further provides a bus broadcast-based non-masked driving register dynamic cascading device, comprising:

[0028] the configuration module is configured to process the multi-path cascading configuration request through the bus arbiter to allocate the bus bandwidth based on the hybrid arbitration algorithm;

[0029] the generation module is configured to generate the register cascading chain according to the decoding parameters of the multi-path cascading configuration request through the dynamic reorganization logic module, and utilize the combination logic composed of multiple logic gate circuits.

[0030] The execution module is configured to execute the target instruction based on the instruction set architecture and the execution unit to automatically adapt the bit width of the current cascade configuration, and perform operation on the cascade register chain so that the cascade configuration is completed in parallel with the instruction decoding period and the instruction execution.

[0031] The application further provides an electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the bus broadcast-based non-masked driving register dynamic cascade method according to any one of the above when executing the program.

[0032] The application further provides a non-transitory computer readable storage medium having a computer program stored thereon, wherein the computer program is executable on a processor to implement the bus broadcast-based non-masked driving register dynamic cascade method according to any one of the above.

[0033] The application further provides a computer program product comprising a computer program, wherein the computer program is executable on a processor to implement the bus broadcast-based non-masked driving register dynamic cascade method according to any one of the above.

[0034] The bus broadcast-based non-masked driving register dynamic cascade method and device provided by the application can complete the cascade configuration in parallel with the instruction decoding period and the instruction execution, without pipeline flushing, greatly improving the real-time performance and response speed of the system, enabling the processor to complete the switching of the register configuration in a very short time and immediately engage in operation, avoiding the delay of multiple clock cycles caused by pipeline flushing in the traditional architecture; through the dynamic recombination logic module, the processor can flexibly adjust the bit width and quantity of the register to adapt to different application requirements, realize fast switching, and control power consumption. BRIEF DESCRIPTION OF DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the application or prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the application, and for those skilled in the art, other drawings can also be obtained without creative labor.

[0036] Figure 1 is one of the flowcharts of the bus broadcast-based non-masked driving register dynamic cascade method provided by the application;

[0037] Figure 2 is another flowchart of the bus broadcast-based non-masked driving register dynamic cascade method provided by the application;

[0038] Figure 3is a structural schematic diagram of a non-masked driving register dynamic cascading device based on bus broadcast provided by the application;

[0039] Figure 4 is a structural schematic diagram of an electronic device provided by the application. DETAILED DESCRIPTION

[0040] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions in the present application will be described clearly and completely below with reference to the drawings in the present application. Obviously, the described embodiments are some of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0041] The bus arbitration method and device based on bus broadcast will be described below. Figures 1-4 The bus arbitration method and device based on bus broadcast will be described below.

[0042] The bus arbitration method based on bus broadcast in the embodiment of the present application mainly includes steps 110, 120, 130 and 140.

[0043] Step 110: Process multiple cascading configuration requests through a bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm.

[0044] The bus arbiter mainly processes cascading configuration requests from multiple modules or tasks and reasonably allocates bus bandwidth. In a multi-task parallel processing environment, multiple tasks may request cascading configuration of registers at the same time, which requires the bus arbiter to efficiently coordinate these requests.

[0045] The bus arbiter can adopt a hybrid arbitration algorithm based on time stamp and task urgency. The time stamp is used to record the time when each cascading configuration request is sent, and the task urgency is a pre-set parameter used to identify the priority of the task. When multiple requests arrive at the same time, the bus arbiter first compares the urgency of the tasks, and the task with higher urgency will have priority to obtain the bus resource. If the task urgency is the same, the allocation is made according to the order of the time stamp, ensuring that the request sent first is processed first.

[0046] In addition, the bus arbiter supports multiple parallel requests, which can receive and process multiple different cascading configuration requests at the same time, greatly improving the parallel processing capability and efficiency of the system. For example, in a complex artificial intelligence reasoning task, different neural network layers may require different bit width operation support, and the bus arbiter can process these cascading configuration requests from different layers at the same time, ensuring the smooth operation of each layer.

[0047] At step 120, the dynamic reconfiguration logic module generates a register cascade chain using a combination of logic gates according to the decoding parameters of the multi-cascade configuration request.

[0048] The dynamic reconfiguration logic module is responsible for generating a register cascade chain using a combination of logic according to the decoding parameters of the multi-cascade configuration request. The combination of logic is a circuit composed of basic logic gates (such as AND gates, OR gates, NOT gates, etc.), whose output only depends on the current input.

[0049] When receiving the cascade configuration request, the dynamic reconfiguration logic module determines the range and number of physical registers that need to be spliced according to the decoding parameters in the request, such as the starting register address and the target bit width. Then, the outputs of these physical registers are connected together through a combination of logic circuits to form a continuous register cascade chain.

[0050] In some embodiments, generating a register cascade chain includes mapping physical registers to virtual wide-bit registers by dynamic reconfiguration logic to splice physical registers to generate a register cascade chain.

[0051] Physical registers are actual register units that a processor has, with a fixed bit width, such as 64-bit or 32-bit general-purpose registers. Virtual wide-bit registers are logical registers formed by splicing multiple physical registers, and their bit width can be an integer multiple of the bit width of physical registers, such as 128-bit, 256-bit, 512-bit, etc.

[0052] The dynamic reconfiguration logic connects the address and data lines of the physical registers through a certain mapping relationship to form the data path of the virtual wide-bit register. For example, to generate a 512-bit virtual wide-bit register, the dynamic reconfiguration logic will combine and expand the address lines and data lines of 8 consecutive 64-bit physical registers, so that the execution unit of the processor can read and write these 8 physical registers as a unified 512-bit register.

[0053] This mapping method can dynamically adjust the bit width and number of virtual wide-bit registers according to different application requirements, without the need for hardware modification of the physical register bank. This mapping method has good compatibility with existing processor instruction set architectures and software ecosystems. Software developers can use virtual wide-bit registers like ordinary registers without complex adaptation and modification. The mapping relationship achieved through hardware combination logic has low latency and high bandwidth characteristics, which can meet the needs of high-performance computing.

[0054] For example, if the target bit width is 512 bits and each physical register is 64 bits, the dynamic reconfiguration logic module will splice 8 consecutive physical registers to form a 512-bit register cascade chain.

[0055] The above process is completely based on hardware combination logic implementation, without software intervention, and can be completed in a very short time. Compared with the traditional method of configuring mask registers through software, the speed and efficiency of cascade configuration are greatly improved.

[0056] In step 130, the processor executes the target instruction based on the instruction set architecture and the execution unit to automatically adapt the bit width of the current cascade configuration, and performs operation on the cascade register chain, so that the cascade configuration is completed in parallel with instruction execution in the instruction decoding period.

[0057] After the generation of the register cascade chain, the processor automatically performs operation according to the bit width of the current cascade configuration when executing the target instruction. The automatic adaptation means that the instruction set architecture and the execution unit of the processor have been optimized for dynamic cascade registers.

[0058] For example, when executing a vector addition instruction, if the bit width of the current cascade configuration is 256 bits, the execution unit of the processor will automatically identify and perform addition operation on the data in the two 256-bit register cascade chains with a precision of 256 bits. This process does not require programmers to perform additional bit width adaptation operations when writing instructions, and the compiler can easily generate machine code compatible with dynamic cascade registers.

[0059] The cascade configuration is completed in parallel with instruction execution in the T2 (i.e., instruction decoding period) period, without pipeline flushing. In the traditional processor architecture, when the register configuration changes, the pipeline usually needs to be flushed to ensure that the subsequent instructions can be executed correctly. This process will cause a delay of several clock cycles, seriously affecting the performance of the system. However, through the bus broadcast protocol and dynamic reorganization logic designed by the present application, the cascade configuration can be performed in parallel with instruction execution in the T2 period of instruction execution. In the T1 period (instruction fetch period), the processor obtains the instruction; in the T2 period, the instruction decoder parses the instruction while the bus arbiter starts processing the cascade configuration request; in the T3 period, the dynamic reorganization logic module generates the register cascade chain, and the execution unit starts executing the instruction; in the T4 period, the instruction execution is completed. The whole process does not need to pause the pipeline for flushing, greatly improving the real-time performance and throughput of the system.

[0060] According to the bus broadcast-based non-masked driving register dynamic cascading method provided by the embodiment of the application, the cascading is configured to be completed in parallel with instruction decoding and instruction execution, without pipeline flushing, thereby greatly improving the real-time performance and response speed of the system, enabling the processor to complete the switching of register configuration in a very short time and immediately engage in operation, and avoiding the delay of multiple clock cycles caused by pipeline flushing in the traditional architecture; through the dynamic reconfiguration logic module, the processor can flexibly adjust the bit width and quantity of the registers to adapt to different application requirements, realize fast switching, and control power consumption.

[0061] In some embodiments, before receiving the multi-way cascading configuration request through the bus arbiter, the bus broadcast-based non-masked driving register dynamic cascading method of the embodiment of the application further includes: receiving, by the processor, a bus broadcast instruction, the bus broadcast instruction being used to indicate a starting register address and a target bit width; parsing, by the instruction decoder, the operation code and parameters of the bus broadcast instruction to generate the multi-way cascading configuration request; and triggering, by the instruction decoder, the bus arbiter to process the multi-way cascading configuration request.

[0062] The processor is a core component of a computer system and is responsible for executing various instructions and processing data. In the present application, the processor receives a bus broadcast instruction from other parts of the system or the outside, and the instruction is used to indicate a starting register address and a target bit width.

[0063] The bus broadcast instruction is a special instruction that is sent to multiple components or modules in the system through a bus. In a multi-core processor system, the bus broadcast instruction can be sent from a control core to all computing cores, or from an external system controller to the processor. This broadcasting method can quickly update multiple registers or register configurations of multiple cores at the same time, improving the configuration efficiency of the system.

[0064] The format of the bus broadcast instruction usually includes an operation code and a parameter field. The operation code specifies the type of the instruction, such as "HEBCAST" indicating a broadcast cascading configuration instruction. The parameter field contains key information such as the starting register address and the target bit width. For example, the instruction "HEBCAST R8, WIDTH = 512bit" indicates that a 512-bit wide register cascading chain is configured starting from register R8.

[0065] The instruction decoder is used to parse the received instruction and extract the operation code and parameters of the instruction. When parsing the bus broadcast instruction, the instruction decoder will identify the operation code "HEBCAST" and extract the starting register address "R8" and the target bit width "512bit" and other parameters.

[0066] Then, the instruction decoder generates a multi-path concatenation configuration request based on these parameters. A multi-path request refers to a set of requests targeting multiple physical registers or multiple concatenation configuration parameters. For example, to configure a 512-bit register concatenation chain, it may be necessary to request concatenation of 64 physical registers from R8 to R71 (assuming each physical register is 8 bits). The instruction decoder generates a request queue containing these register addresses and related configuration parameters and sends it to the bus arbiter for processing.

[0067] After generating the multi-path concatenation configuration request, the instruction decoder triggers the bus arbiter to start processing these requests. The triggering mechanism is usually achieved by setting a hardware signal or interrupt. When the bus arbiter receives the trigger signal, it suspends the current other processing tasks and prioritizes the processing of these concatenation configuration requests to ensure that the register configuration is updated in time and does not affect the execution of subsequent instructions.

[0068] In some implementations, the multi-path concatenation configuration request is processed by the bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm, including: determining the allocation of bus bandwidth by the bus arbiter based on the priority and timestamp of the task corresponding to the multi-path concatenation configuration request; in the case of an emergency task, allocating a bypass channel resource to the task.

[0069] After receiving the multi-path concatenation configuration request, the bus arbiter determines the allocation of bus bandwidth based on the priority and timestamp of the task corresponding to each request. As mentioned above, the priority is a pre-set parameter used to measure the importance and urgency of the task. For example, in a real-time control system, the priority of a control task is usually higher than that of a data processing task.

[0070] The timestamp is used to record the time when each concatenation configuration request is issued. When multiple requests have the same priority, the bus arbiter processes them according to the order of the timestamps to ensure that the request issued first is serviced first. This hybrid arbitration algorithm based on priority and timestamp ensures that high-priority tasks can quickly acquire resources, and ensures fairness among tasks with the same priority.

[0071] When a task is identified as an emergency task, the bus arbiter allocates a bypass channel resource to it. The bypass channel is a special bus resource that bypasses the regular bus allocation and arbitration mechanism, providing a fast and direct communication path for emergency tasks.

[0072] For example, in a graphics processing system, when a screen refresh task occurs, the task needs to be completed in a very short time to avoid screen tearing or freezing. The bus arbiter identifies it as an emergency task and allocates it a bypass channel resource, allowing it to bypass other tasks waiting for bus resources and directly configure the register cascade, thereby ensuring the timeliness of screen refresh.

[0073] The allocation of bypass channel resources is achieved through hardware circuits. Inside the bus arbiter, there is a bypass channel controller that, when detecting an emergency task request, activates the bypass channel to send the emergency task request directly to the dynamic reconfiguration logic module, while notifying other modules to suspend access to the regular bus until the emergency task configuration is complete.

[0074] The hybrid arbitration algorithm based on priority and timestamp, as well as the bypass channel support for emergency tasks, allows for a reasonable and efficient allocation of bus bandwidth. In a multi-task parallel processing environment, high-priority tasks and emergency tasks can obtain the required resources in a timely manner, ensuring efficient operation of the system.

[0075] In some embodiments, as shown in Figure 2 Before generating the register cascade chain using a combination of logic gates based on the decoding parameters of the multi-cascade configuration request by the dynamic reconfiguration logic module, the method further includes steps 210 and 220.

[0076] Step 210: Check if there is a resource conflict between the current configuration and the historical record through the cascade state cache;

[0077] Step 220: If there is a conflict and the current configuration has a low priority, roll back to the most recent compatible historical configuration, which is stored in the cascade state cache.

[0078] The cascade state cache can be used to store the last few cascade configuration information for quick query and comparison. It uses non-volatile memory unit (NVM) technology to ensure that the historical configuration information in the cache is not lost after system power failure or reset, especially in complex application scenarios that require frequent switching of cascade configurations.

[0079] The storage structure of the cascade state cache usually includes a configuration storage unit and a rollback controller. The configuration storage unit is used to save specific cascade configuration parameters such as starting register address, target bit width, and number of spliced registers. The rollback controller is responsible for managing cache access and rollback operations. For example, when a resource conflict is detected between the current configuration and the historical record, the rollback controller quickly recovers to a compatible historical state based on the historical configuration information in the cache.

[0080] Before generating the register concatenation chain, the dynamic reconfiguration logic module checks the current configuration against the history records in the concatenation state cache for resource conflicts. A resource conflict is a situation where the current concatenation configuration request overlaps or competes with a previously existing concatenation configuration in terms of register resource usage. For example, if a historical configuration has concatenated registers R8 to R15 into a 128-bit register concatenation chain, and the current request attempts to concatenate R12 to R20 into another 128-bit chain, there is a resource conflict because R12 to R15 are being occupied by both configurations.

[0081] If there is a conflict and the current configuration has a lower priority, the dynamic reconfiguration logic module rolls back to the most recent compatible historical configuration based on the history records in the concatenation state cache. The rollback operation includes restoring the original configuration state of the registers and undoing the connections and mappings related to the conflicting configuration. For example, if there is a 256-bit register concatenation chain (R0-R31) in a historical configuration, and the current request attempts to configure a conflicting 512-bit chain (R16-R63), but the current request has a lower priority, the system will roll back to the historical configuration and maintain the 256-bit configuration of R0-R31, thereby avoiding system errors caused by resource conflicts.

[0082] The combination of the concatenation state cache and the rollback controller provides a guarantee for the reliable operation of the system. In the event of a resource conflict or system error, the system can quickly recover to a historical compatible configuration, avoiding system crashes or data loss caused by configuration errors.

[0083] In some embodiments, after checking the current configuration against the history records in the concatenation state cache for resource conflicts, the non-masked driving register dynamic concatenation method based on bus broadcasting further includes: if there is a conflict and the current configuration has a higher priority, forcibly overriding the old configuration and saving the historical state to the concatenation state cache.

[0084] If there is a resource conflict but the current configuration has a higher priority, the dynamic reconfiguration logic module will forcibly override the old concatenation configuration. This means that it will undo the register concatenation relationship in the old configuration and establish a new register concatenation chain according to the parameters of the current configuration. At the same time, the old configuration state will be saved to the concatenation state cache for rollback or query when needed.

[0085] For example, in a multi-task processing system, a high-priority image processing task needs to configure a 512-bit register cascade chain, while a low-priority audio processing task in the current system is using part of the overlapping register resources for 128-bit operation. The dynamic reconfiguration logic module will forcibly overwrite the configuration of the old audio processing task, establish the 512-bit cascade chain required by the new image processing task, and save the old audio processing configuration to the cache. When the audio processing task regains the opportunity to execute, its register configuration can be restored through a rollback operation.

[0086] In some embodiments, the bus broadcast-based non-masked drive register dynamic cascade method further comprises: based on a least recently used strategy, storing the current cascade configuration into a cascade state cache.

[0087] Based on the least recently used strategy, the current cascade configuration is stored into the cascade state cache. The LRU strategy is a cache management algorithm that, according to historical usage records, preferentially retains the cascade configuration information that has been used recently, and eliminates historical configurations that have not been used for a long time. For example, the size of the cascade state cache is limited and can only store the last 4 cascade configurations. When a new configuration needs to be stored, the system will check the usage timestamps of the historical configurations in the cache, replace the historical configuration that has not been used for the longest time, and store the new configuration.

[0088] It can be understood that, in the present embodiment, the above operations help to reasonably utilize the limited space of the cascade state cache and improve the hit rate and efficiency of the cache. In actual applications, this method can ensure that the cascade configurations stored in the cache are the ones that are most likely to be used again, so that when the system needs to roll back or query historical configurations, the appropriate configuration information can be quickly found.

[0089] The traditional architecture needs to flush the pipeline when switching register configurations, which consumes a large amount of energy. The dynamic cascade method of zero pipeline flush eliminates this part of energy consumption. For example, in a 5G signal processing scenario with high real-time requirements, the reception and processing of signals need to be completed within strict time limits. The dynamic cascade method of the present invention can ensure that the signal processing instructions are executed immediately after obtaining the correct register configuration, thereby meeting the low-latency requirements of 5G signal processing. At the same time, the throughput of the processor is also significantly improved, because more instructions can be executed within a unit of time, and the overall performance of the system is optimized.

[0090] The emergency task is quickly configured through the bypass channel, avoiding repeated requests and energy waste caused by competing with other tasks for regular bus resources. Through the LRU strategy for managing the cache, the energy consumption caused by frequent configuration and rollback operations is reduced.

[0091] In addition, the idle state automatically closes the unused cascade channel, and the static power consumption is reduced. When the dynamic reconfiguration logic module detects that the register cascade chain is in an idle state, it will automatically cut off the power supply of the unused register or put it into a low-power mode. For example, in a 512-bit register cascade chain, if only the first 128 bits are being used, and the remaining 384 bits are in an idle state, the system will automatically turn off the power supply of the corresponding register part of the 384 bits, thereby significantly reducing the static power consumption.

[0092] In artificial intelligence inference tasks, different neural network layers may require different bit width operation support. For example, some convolutional layers may have higher performance requirements for low-precision operations of 8 bits or 16 bits, while fully connected layers may require high-precision operations of 32 bits or 64 bits. The dynamic cascade method of the present application can quickly configure the corresponding register cascade chain according to the requirements of the currently executed neural network layer, thereby providing each layer with the optimal operation environment.

[0093] When performing an 8-bit convolutional layer operation, the processor configures a 256-bit register cascade chain (composed of 32 8-bit physical registers) through bus broadcast instructions to achieve efficient vector operations. When switching to a 32-bit fully connected layer operation, the processor reconfigures a 128-bit cascade chain (composed of 4 32-bit physical registers) through another broadcast instruction. The entire process does not need to pause the pipeline and can be completed in a very short time, greatly improving the efficiency and performance of artificial intelligence inference.

[0094] In 5G signal processing tasks, 5G signal processing requires real-time processing of a large amount of data, including signal modulation and demodulation, encoding and decoding, beamforming, etc. These operations have very high requirements for the real-time performance and energy efficiency ratio of the processor.

[0095] In 5G base stations or terminal devices, the dynamic cascade method of the present application can be applied to the register management of the signal processing engine. For example, when performing large-scale MIMO (Multiple Input Multiple Output) signal processing, the processor needs to process the signal data of multiple antennas simultaneously. By dynamically cascading registers, the processor can flexibly configure the bit width and number of registers according to the processing requirements of each antenna signal, thereby achieving efficient parallel processing. At the same time, the characteristic of automatically closing the unused cascade channel in the idle state can reduce power consumption when the signal processing load is low, prolonging the battery life of the device.

[0096] The AVX-512 instruction set of the traditional x86 architecture requires a complex mask register configuration, and the programmer needs to manually write a complex instruction sequence to set the mask register, which not only increases the difficulty and workload of software development, but also easily introduces errors. The application realizes the automation of register cascading configuration through bus broadcast instructions and dynamic reorganization logic, greatly simplifying the software development process. When handling interrupts, the x86 architecture needs to save and restore a large amount of register state information, including mask registers, resulting in low interrupt processing efficiency. The cascading state cache and rollback mechanism of the application can quickly save the current configuration when an interrupt occurs and quickly restore it when the interrupt returns, thereby improving the efficiency of interrupt processing. The pipeline flush operation and complex mask configuration logic of the x86 architecture result in high power consumption. The application significantly reduces power consumption through zero pipeline flush and efficient dynamic reorganization logic, especially in scenarios where dynamic bit width switching is frequent, and the energy-saving effect is more obvious.

[0097] Some architecture extension instructions LSX / LASX use a static grouping register organization method, which cannot be dynamically adjusted according to different application requirements. The dynamic reorganization logic module of the application can flexibly map physical registers to virtual wide-bit registers, realizing dynamic reorganization of registers and improving the utilization and flexibility of register resources. The register switching delay of the traditional architecture is 5-8 cycles, while the cascading configuration of the application can be completed in T2 cycles, i.e. about 2 cycles (depending on the clock cycle design of the processor), greatly reducing the switching delay and improving the real-time performance of the system. The cascading state cache uses an LRU strategy-based management algorithm and a fast rollback mechanism, and the state recovery speed is 5 times faster than that of the traditional architecture. In application scenarios that require frequent switching of cascading configurations, this advantage can significantly improve the performance and efficiency of the system.

[0098] Some other architecture architecture custom vector extension instructions require more hardware resources when implementing register cascading, resulting in high hardware resource occupancy. The application reduces hardware resource occupancy by 40% through optimized dynamic reorganization logic and bypass channel design, which enables the processor to achieve high-performance register dynamic cascading function at a lower hardware cost. The energy efficiency of the traditional architecture is poor, mainly due to the high power consumption of its register cascading scheme. The application significantly improves the energy efficiency ratio through a series of energy-saving measures, such as automatically turning off unused cascading paths in idle state and reducing cascading switching power consumption. In high-performance computing and low-power application scenarios, it has greater advantages. The data path delay of the register cascading of the traditional architecture is 0.3ns, while the data path delay of the application is reduced to 0.05ns through optimized dynamic reorganization logic and hardware design, a reduction of 82%. This enables the processor to achieve higher performance and efficiency when performing high-frequency data access and operation.

[0099] The bus broadcast-based non-masked driving register dynamic cascading method of the application realizes efficient dynamic cascading configuration of registers through innovative hardware architecture and control strategy. Compared with the prior art, the application has significant advantages in energy efficiency, performance, resource management flexibility, etc., and is particularly suitable for artificial intelligence reasoning and 5G signal processing and other application scenarios with high requirements for real-time performance and energy efficiency.

[0100] The bus broadcast-based non-masked driving register dynamic cascading device provided by the application is described below. The bus broadcast-based non-masked driving register dynamic cascading device described below can be referred to each other corresponding to the bus broadcast-based non-masked driving register dynamic cascading method described above.

[0101] As shown in Figure 3 The bus broadcast-based non-masked driving register dynamic cascading device of the embodiment of the application mainly includes a configuration module 310, a generation module 320 and an execution module 330.

[0102] The configuration module 310 is configured to process multiple cascading configuration requests through a bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm;

[0103] The generation module 320 is configured to generate a register cascading chain by a combination logic composed of multiple logic gate circuits according to the decoding parameters of the multiple cascading configuration requests through a dynamic reconfiguration logic module;

[0104] The execution module 330 is configured to execute target instructions based on an instruction set architecture and an execution unit through a processor to automatically adapt the bit width of the current cascading configuration, and perform operations on the cascading register chain so that the cascading configuration is completed in parallel with instruction decoding and instruction execution.

[0105] According to the bus broadcast-based non-masked driving register dynamic cascading device provided by the embodiment of the application, the cascading configuration is completed in parallel with instruction decoding and instruction execution, without pipeline flushing, greatly improving the real-time performance and response speed of the system, so that the processor can complete the switching of register configuration in a very short time and immediately enter operation, avoiding the delay of multiple clock cycles caused by pipeline flushing in the traditional architecture. Through the dynamic reconfiguration logic module, the processor can flexibly adjust the bit width and number of registers to adapt to different application requirements, realize fast switching and control power consumption.

[0106] Figure 4 An example of an entity structure schematic diagram of an electronic device is shown in Figure 4As shown, the electronic device can include a processor 410, a communication interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communication interface 420, and the memory 430 can communicate with each other through the communication bus 440. The processor 410 can invoke the logic instructions in the memory 430 to execute the bus broadcast-based non-masked drive register dynamic cascading method, which includes: processing a multi-path cascading configuration request by a bus arbiter to allocate bus bandwidth; generating a register cascading chain by a dynamic recombination logic module according to the decoding parameters of the multi-path cascading configuration request; and executing a target instruction to automatically adapt the bit width of the current cascading configuration and operate the cascading register chain.

[0107] In addition, the logic instructions in the memory 430 described above can be implemented in the form of a software functional unit and sold or used as an independent product, which can be stored in a computer readable storage medium. Based on this understanding, the technical solutions of the present application or the part of the technical solutions that essentially contribute to the prior art can be embodied in the form of a software product, which is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in the various embodiments of the present application. The aforementioned storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various media that can store program codes.

[0108] On the other hand, the present application also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer readable storage medium, and the computer program can be executed by a processor to enable a computer to execute the bus broadcast-based non-masked drive register dynamic cascading method provided by the above-mentioned methods, which includes: processing a multi-path cascading configuration request by a bus arbiter to allocate bus bandwidth; generating a register cascading chain by a dynamic recombination logic module according to the decoding parameters of the multi-path cascading configuration request; and executing a target instruction to automatically adapt the bit width of the current cascading configuration and operate the cascading register chain.

[0109] In yet another aspect, the present application also provides a non-transitory computer readable storage medium having stored thereon a computer program, which, when executed by a processor, implements the bus broadcast based non-masked drive register dynamic cascading method provided by the above method, and the method comprises: processing a plurality of cascade configuration requests by a bus arbiter to allocate bus bandwidth; generating a register cascade chain by a dynamic reconfiguration logic module using combination logic according to the decoding parameters of the plurality of cascade configuration requests; and executing a target instruction to automatically adapt the bit width of the current cascade configuration and perform operation on the cascade register chain.

[0110] The device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, i.e., they may be located in one place or distributed on multiple network units. Part or all of the modules can be selected to achieve the purpose of the embodiment scheme according to actual needs. Those skilled in the art can understand and implement without creative labor.

[0111] From the above description of the embodiments, those skilled in the art can clearly understand that the embodiments can be realized by means of software plus necessary universal hardware platforms, and of course, can also be realized by hardware. Based on such understanding, the above technical solutions, essentially or in other words, the part that contributes to the prior art, can be embodied in the form of a software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute the methods described in each embodiment or some parts of the embodiments.

[0112] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A bus broadcast based unmasked drive register dynamic cascading method, characterized in that, The method comprises the following steps: handling multiple cascade configuration requests by a bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm; generating a register cascade chain by a dynamic reconfiguration logic module according to the decoding parameters of the multiple cascade configuration requests using a combination of logic gates; performing target instructions by a processor based on an instruction set architecture and an execution unit to automatically adapt the bit width of the current cascade configuration, and performing operations on the cascade register chain, so that the cascade configuration is completed in parallel with instruction decoding and instruction execution.

2. The bus broadcast based unmasked drive register dynamic cascading method according to claim 1, wherein, Before the bus arbiter receives the multiple cascade configuration requests, the method further comprises: receiving a bus broadcast instruction by a processor, the bus broadcast instruction being used to indicate a starting register address and a target bit width; parsing the opcode and parameters of the bus broadcast instruction by an instruction decoder to generate a multiple cascade configuration request; triggering the bus arbiter to handle the multiple cascade configuration request by the instruction decoder.

3. The bus broadcast based unmasked drive register dynamic cascading method according to claim 1, wherein, The bus arbiter handles the multiple cascade configuration requests to allocate bus bandwidth based on a hybrid arbitration algorithm, which comprises: determining the allocation of bus bandwidth by the bus arbiter based on the priority and timestamp of the task corresponding to the multiple cascade configuration request; allocating a bypass channel resource to the task in the case of an emergency task.

4. The bus broadcast based unmasked drive register dynamic cascading method of claim 1, wherein, Before the dynamic reconfiguration logic module generates a register cascade chain according to the decoding parameters of the multiple cascade configuration requests using a combination of logic gates, the method further comprises: checking whether there is a resource conflict between the current configuration and the historical record by a cascade state cache; if there is a conflict and the priority of the current configuration is low, rolling back to the most compatible historical configuration stored in the cascade state cache.

5. The bus broadcast based unmasked drive register dynamic cascading method according to claim 4, wherein, After the cascade state cache checks whether there is a resource conflict between the current configuration and the historical record, the method further comprises: if there is a conflict and the priority of the current configuration is higher, forcibly overriding the old configuration and saving the historical state to the cascade state cache.

6. The non-maskable driver register dynamic cascading method based on bus broadcast according to any one of claims 1 to 5, characterized in that, The method further comprises: storing the current cascade configuration into the cascade state cache based on the least recently used strategy.

7. The non-maskable driver register dynamic cascading method based on bus broadcast according to any one of claims 1 to 5, characterized in that, The generation of the register cascade chain comprises: mapping physical registers to virtual wide-bit registers by dynamic reconfiguration logic to splice physical registers to generate the register cascade chain.

8. A bus broadcast based unmasked drive register dynamic cascading apparatus, comprising: The method comprises the following steps: a configuration module for handling multiple cascade configuration requests by a bus arbiter to allocate bus bandwidth based on a hybrid arbitration algorithm; a generation module for generating a register cascade chain by a dynamic reconfiguration logic module according to the decoding parameters of the multiple cascade configuration requests using a combination of logic gates; an execution module for performing target instructions by a processor based on an instruction set architecture and an execution unit to automatically adapt the bit width of the current cascade configuration, and performing operations on the cascade register chain, so that the cascade configuration is completed in parallel with instruction decoding and instruction execution.

9. An electronic device comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, The processor implements the bus broadcast-based non-masked driving register dynamic cascade method according to any one of claims 1 to 7 when executing the program.

10. A non-transitory computer-readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by a processor, implements the method of dynamic cascading of unmasked driven registers based on bus broadcast according to any one of claims 1 to 7.

Images