Method, device, equipment, storage medium and program product for executing atomic operation

Abstract

The embodiment of the present disclosure discloses an atomic operation execution method, device, equipment, storage medium and program product, wherein the atomic operation execution method comprises: in response to a first execution request of a vector atomic operation, reading a first payload from one or more first registers in a load storage unit based on an extension size in the first execution request; the extension size is determined based on the number of vectors and the data type; and performing the vector atomic operation according to the first payload. In this way, the processing of the vector atomic operation can be realized, and the utilization rate of the pass bandwidth and the hardware resources is improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to, but is not limited to, the technical field of computer, and particularly relates to an execution method and device of atomic operation, equipment, storage medium and program product. BACKGROUND

[0002] Generally, graphics tasks are processed by programmable pipelines in a graphics processing unit (GPU). A load store unit (LSU) is an access port of memory, and in addition to providing load and store functions, control information parsing operations of global atomic operations are also one of the important functions of this module to support memory order.

[0003] However, the related memory access method only supports scalar atomic operations, and there is a problem of low hardware resource utilization. SUMMARY

[0004] Therefore, the embodiments of the present disclosure provide at least an execution method, device, equipment, storage medium and program product of atomic operation.

[0005] The technical solutions of the embodiments of the present disclosure are implemented as follows:

[0006] In one aspect, the embodiments of the present disclosure provide an execution method of atomic operation, which comprises: in response to a first execution request of a vector atomic operation, reading a first payload from one or more first registers in a load store unit based on an extension size in the first execution request; the extension size is determined based on the number of vectors and the data type; and performing the vector atomic operation according to the first payload.

[0007] In another aspect, the embodiments of the present disclosure provide an execution device of atomic operation, which comprises: a reading module, configured to read a first payload from one or more first registers in a load store unit based on an extension size in a first execution request of a vector atomic operation in response to the first execution request; the extension size is determined based on the number of vectors and the data type; and a processing module, configured to perform the vector atomic operation according to the first payload.

[0008] In still another aspect, the embodiments of the present disclosure provide a computer device, which comprises a memory and a processor, and the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps in the above method when executing the program.

[0009] In yet another aspect, the embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps in the above method.

[0010] In yet another aspect, an embodiment of the present disclosure provides a computer program, including computer readable code, when the computer readable code is run in a computer device, a processor in the computer device performs part or all steps of the above method.

[0011] In yet another aspect, an embodiment of the present disclosure provides a computer program product, the computer program product includes a non-transitory computer readable storage medium storing a computer program, when the computer program is read and executed by a computer, part or all steps of the above method are implemented.

[0012] In an embodiment of the present disclosure, since the data is stored in sequence and continuously into the registers in the load store unit when stored, the number of vectors can reflect the size of the data, therefore, according to the extension size determined by the number of vectors and the data type, the data (first payload) required when the vector atomic operation is executed can be read from one or more first registers in the load store unit, so that the vector atomic operation is executed according to the first payload, and the processing of the vector atomic operation is realized. The execution request of the vector atomic operation can be adapted on the instruction set of the scalar atomic operation, and the extension size of the vector atomic operation can reuse the bit field of the request size of the scalar atomic operation, so that the processing of the vector atomic operation is realized on the basis of the existing hardware resources, and the usage rate of the channel bandwidth and the hardware resources is improved.

[0013] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the technical solutions of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present disclosure and, together with the specification, serve to explain the technical solutions of the present disclosure.

[0015] Figure 1 Implementation flowchart of the atomic operation execution method provided by an embodiment of the present disclosure Figure 1

[0016] Figure 2 Implementation flowchart of the atomic operation execution method provided by an embodiment of the present disclosure Figure 2

[0017] Figure 3 Implementation flowchart of the atomic operation execution method provided by an embodiment of the present disclosure Figure 3

[0018] Figure 4 Implementation flowchart of the atomic operation execution method provided by an embodiment of the present disclosure Figure 4 ;​​​

[0019] Figure 5 An implementation flowchart of a no-return-value scalar atomic operation in an atomic operation execution method provided by an embodiment of the present disclosure is shown in FIG. 6;

[0020] Figure 6 An implementation flowchart of a vector atomic operation in an atomic operation execution method provided by an embodiment of the present disclosure is shown in FIG. 7;

[0021] Figure 7 An implementation diagram of aligning a virtual address in an atomic operation execution method provided by an embodiment of the present disclosure is shown in FIG. 8;

[0022] Figure 8 A pipeline diagram of an atomic operation execution method provided by an embodiment of the present disclosure is shown in FIG. 9;

[0023] Figure 9 A hardware structure diagram of an atomic operation execution method provided by an embodiment of the present disclosure is shown in FIG. 10;

[0024] Figure 10 A component structure diagram of an atomic operation execution device provided by an embodiment of the present disclosure is shown in FIG. 11;

[0025] Figure 11 A hardware entity diagram of a computer device provided by an embodiment of the present disclosure is shown in FIG. 12. DETAILED DESCRIPTION

[0026] In order to make the objectives, technical solutions and advantages of the present disclosure clearer, the technical solutions of the present disclosure are further described in detail below in combination with the drawings and embodiments, and the described embodiments should not be regarded as limiting the present disclosure, and all other embodiments obtained by those of ordinary skill in the art without making creative efforts fall within the scope of protection of the present disclosure.

[0027] In the following description, “some embodiments” are described, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict.

[0028] The terms “first / second / third” involved only distinguish similar objects, and do not represent a specific order of the objects, and it can be understood that “first / second / third” can interchange specific order or sequence as allowed, so that the embodiments of the present disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used in the description herein is for describing particular embodiments only and is not intended to be limiting of the disclosure.

[0030] In order to better understand the execution method of the atomic operation provided by the embodiments of the present disclosure, the solutions in the related art will be described first.

[0031] GPU has played an increasingly important role in graphics and general computing scenarios due to its high parallel processing characteristics. The special processing of graphics in GPU is usually placed in a fixed pipeline, and the general part is placed in a programmable pipeline. LSU, as the access to the memory, plays a crucial role in the programmable pipeline, providing load (Load) function or store (Store) function. Among them, the load function refers to loading the data stored in the memory to the storage unit (such as register) inside the programmable pipeline through the cache. The storage function refers to writing the data processed inside the programmable pipeline to the memory through the cache.

[0032] In addition, in order to support memory order, the control information parsing operation of global atomic is also one of the important functions of LSU. Generally, atomic operation needs to carry the operand (optional) participating in atomic operation, operation type and return operand (optional).

[0033] Combined with application requirements, atomic operation is subdivided into return scalar atomic operation (scalar atomic operation, and the instruction configures the return operand), non-return scalar atomic operation (scalar atomic operation, and the instruction defaults the return operand), return vector atomic operation (continuous address vector atomic operation, and the instruction configures the return operand), and non-return vector atomic operation (continuous address vector atomic operation, and the instruction defaults the return operand).

[0034] Here, the main behaviors in the related art are arranged in Table 1 below:

[0035] Table 1

[0036]

[0037] In order to simplify the hardware logic overhead, it is necessary to ensure that the data type of the operand meets the alignment requirement. In the related art, the user perceives the alignment of the data type through the compilation software, and the following is the execution request of the aligned atomic operation.

[0038] At least the following technical problems exist in the related art: 1. Only scalar atomic operations are supported, and there is a poor adaptability problem; 2. There is a problem of waste of hardware resources in the return path of the return scalar atomic operation; 3. The user needs to ensure address alignment through compiled software, and there is a problem of relatively cumbersome operation.

[0039] To this end, an embodiment of the present disclosure provides an atomic operation execution method, which can be executed by a processor of a computer device. The computer device can be a server, a notebook computer, a tablet computer, a desktop computer, a smart television, a set-top box, a mobile device (such as a mobile phone, a portable video player, a personal digital assistant, a dedicated messaging device, a portable game device), and the like. As shown in the figure, the method comprises at least one of the following steps 101 to step 102: Figure 1

[0040] Step 101, in response to a first execution request of a vector atomic operation, reading a first payload from one or more first registers in a load store unit based on an extension size in the first execution request; the extension size is determined based on the number of vectors and the data type.

[0041] The first execution request refers to the execution request / command of the vector atomic operation currently being processed. The extension size is used to represent the number of vectors (i.e. the data size) and the data type corresponding to the vector atomic operation, and the main purpose is to read the payload required when the vector atomic operation is executed. In some embodiments, the extension size can be the product of the number of vectors and the size of the data type. The data type is used to represent whether there is a return value for the corresponding atomic operation.

[0042] The load store unit is used to read data in the memory and transmit it to the designated register for use by the processing module; it is also used to write the executed data in the register to the memory to achieve long-term storage of data. The first register refers to one or more registers that store data required when the vector atomic operation is executed. The first payload refers to the data required when the vector atomic operation is executed. In some embodiments, the first payload can include but is not limited to: the operand corresponding to the vector atomic operation, and the control data and verification data required to execute the vector atomic operation, etc.

[0043] In some embodiments, if a single register cannot meet the data storage requirements of the vector atomic operation, the data needs to be stored continuously in multiple registers when storing the payload; in this way, the payload of the vector atomic operation can be read from the continuous multiple registers according to the extension size of the vector atomic operation.

[0044] ​In some embodiments, the first execution request can carry a start address corresponding to the vector atomic operation, so that the first register storing data corresponding to the vector atomic operation can be located according to the start address, and then the payload (first payload) of the vector atomic operation can be read from the continuous multiple registers according to the extension size.

[0045] In some embodiments, the first execution request can carry an address identifier corresponding to the vector atomic operation, so that the first register storing data corresponding to the vector atomic operation can be located according to the address identifier, and then the payload (first payload) of the vector atomic operation can be read from the continuous multiple registers according to the extension size.

[0046] Step 102, performing the vector atomic operation according to the first payload.

[0047] In some embodiments, the vector atomic operation can be performed on the memory according to the first payload.

[0048] In the embodiments of the present disclosure, since the data is stored in sequence and continuously into the registers in the load storage unit when stored, the number of vectors can represent the size of the data, and therefore, the data (first payload) required for the execution of the vector atomic operation can be read from one or more first registers in the load storage unit according to the extension size determined by the number of vectors and the data type, so that the vector atomic operation is executed according to the first payload, and the processing of the vector atomic operation is realized. The execution request of the vector atomic operation can be adapted on the instruction set of the scalar atomic operation, and the extension size of the vector atomic operation can reuse the bit field of the request size of the scalar atomic operation, so that the processing of the vector atomic operation is realized on the basis of the existing hardware resources, and the usage rate of the channel bandwidth and the hardware resources is improved.

[0049] In some embodiments, before the execution of "reading the first payload from one or more first registers in the load storage unit according to the extension size in the first execution request" in step 101, the atomic operation execution method provided by the embodiments of the present disclosure further includes steps 103 to 104 as follows:

[0050] Step 103, determining the range of the memory address to be updated by the vector atomic operation based on the start address and the extension size in the first execution request.

[0051] In some embodiments, the specific implementation of step 103 can include: taking the address range from the start address to the start address plus the extension size as the range of the memory address to be updated by the atomic operation.

[0052] Step 104, in the case that the range of memory addresses is a non-aligned virtual address, performing alignment processing on the range of memory addresses.

[0053] In some embodiments, the specific implementation of "performing alignment processing on the range of memory addresses" can include: determining whether the range of memory addresses is a processable address according to the virtual address corresponding to the range of memory addresses and the data type of the vector atomic operation; in the case that the range of memory addresses is a processable address, performing alignment processing on the range of memory addresses according to the data type of the atomic operation.

[0054] In a feasible implementation, the calculation formula of the processable address can be: virtual address % data type of atomic operation == 0. If the range of memory addresses corresponding to the atomic operation satisfies the above formula, the range of memory addresses is left shifted according to the data type of the atomic operation to obtain an aligned virtual address.

[0055] Based on the above technical solution, before reading the payload, the range of memory addresses to be updated by the vector atomic operation is determined based on the start address and the extension size in the first execution request, and in the case that the range of memory addresses is a non-aligned virtual address, alignment processing is performed on the range of memory addresses, so that the effectiveness of subsequent data reading can be improved, and normal execution of the atomic operation is ensured.

[0056] In some embodiments, "reading a first payload from one or more first registers in the load store unit based on the extension size in the first execution request" in step 101 can be implemented by the following steps 1011 to step 1014:

[0057] Step 1011, determining the register resource allocated to the vector atomic operation.

[0058] In some embodiments, the register resource allocated to the vector atomic operation can be determined based on the resource requirement or operation complexity of the vector atomic operation. The resource requirement can be pre-set, and specifically can be set according to the historical execution of the vector atomic operation.

[0059] Step 1012, determining the boundary of the write-back register corresponding to the vector atomic operation based on the operand corresponding to the vector atomic operation and the extension size; the boundary of the write-back register at least includes an upper boundary and a lower boundary.

[0060] In a possible implementation, the specific implementation of determining the upper boundary of the write-back register corresponding to the vector atomic operation based on the operand corresponding to the vector atomic operation and the extension size can include: determining the upper boundary of the write-back register according to the operand corresponding to the vector atomic operation; and adding the operand corresponding to the vector atomic operation and the extension size to obtain the lower boundary of the write-back register.

[0061] In step 1013, in a case where it is determined that there is no write-back out-of-bound of the vector atomic operation based on the boundary of the write-back register and the register resource, a first payload is read from one or more first registers in the load-store unit based on the extension size.

[0062] In a possible implementation, the specific implementation of determining whether there is write-back out-of-bound of the vector atomic operation based on the boundary of the write-back register and the register resource can include: in a case where the register resource does not match the boundary of the write-back register, determining that there is write-back out-of-bound of the atomic operation; and in a case where the register resource matches the boundary of the write-back register, determining that there is no write-back out-of-bound of the atomic operation.

[0063] The register resource does not match the boundary of the write-back register, which means that the register resource does not match at least one of the upper and lower boundaries of the write-back register. The register resource matches the boundary of the write-back register, which means that the register resource matches both the upper and lower boundaries of the write-back register.

[0064] For example, if the currently accessible registers of the program are 32, the starting address of the write-back register is 30, and the extension size is 4 registers, the required range of the write-back register is 30, 31, 32, and 33 in turn. At this time, the accessible range is exceeded, and therefore it is considered that there is a write-back out-of-bound. If the extension size is 2 registers, the required range of the write-back register is 30 and 31, and at this time, there is no write-back out-of-bound.

[0065] In some embodiments, in a case where the range of the memory address is not a processable address and / or the vector atomic operation has write-back out-of-bound, it is determined that the first execution request has an exception, and / or prompt information representing the exception of the first execution request is sent.

[0066] In some embodiments, the first execution request has an exception at least includes one of the following: the range of the memory address is not within the range of processable addresses, the vector atomic operation has write-back out-of-bound, the range of the memory address is not within the range of processable addresses and the vector atomic operation has write-back out-of-bound.

[0067] When the atomic operation exists the write back out-of-bound condition, it is determined that the execution request of the atomic operation is an abnormal request, the execution request of the atomic operation is directly discarded, the configuration corresponding to the execution request is released, and an exception is reported for the user to query through software.

[0068] Based on the above technical solution, in the case that it is determined that the vector atomic operation does not exist the write back out-of-bound condition based on the write back register boundary and the register resource, the first payload is read, and the effectiveness of data reading can be further improved.

[0069] In some embodiments, the execution method of the atomic operation provided by the embodiments of the present disclosure further includes steps 105 to 106:

[0070] Step 105, determining first return control information based on a first bit field in the first execution request, the first bit field being used to represent whether the destination operand corresponding to the vector atomic operation is empty.

[0071] The first bit field is empty, indicating that the destination operand corresponding to the vector atomic operation is empty, which means that there is no need to return a value; the first bit field is not empty, indicating that the destination operand corresponding to the vector atomic operation is not empty, which means that there is a need to return a value. The first return control information is used to represent whether the operand corresponding to the vector atomic operation is written back to the programmable pipeline in the load store unit.

[0072] The destination operand is where the result of the atomic operation is stored after execution. In most cases, the destination operand is a memory address or a register, and the result of the operation will be written to this location. The source operand is the input data that the atomic operation needs to read. The source operand can be a fixed numerical value, or a value in a memory address or a register.

[0073] In some embodiments, the first return control information can be added on the link between the load store unit and the atomic operation execution unit based on the first bit field in the first execution request; in this way, the atomic operation execution unit can determine whether the vector atomic operation needs a return value according to the first return control information.

[0074] In some embodiments, the target bit in the bypass information passed from the load store unit to the atomic operation execution unit can be used as the first return control information. The target bit can be a bit that is not currently used, or a bit that is currently used but has a value that is not used. For example, if the bypass information includes a cache control bit, the cache control bit contains two bits, and 00, 01, and 10 have been used, then 11 can be used as the first return control information. When the cache control bit is 11, it indicates that the operand corresponding to the vector atomic operation is to be written back to the programmable pipeline in the load store unit. When the cache control bit is other values, it indicates that the operand corresponding to the vector atomic operation is not to be written back to the programmable pipeline in the load store unit.

[0075] In some embodiments, the first return control information can be passed to the atomic operation execution unit independently of the bypass information, or as part of the bypass information.

[0076] Step 106: When the first return control information indicates that the operand corresponding to the vector atomic operation is to be written back to the programmable pipeline in the load store unit, the operand corresponding to the vector atomic operation is written back to the programmable pipeline after the vector atomic operation is executed.

[0077] In some embodiments, when the first return control information indicates that the operand corresponding to the vector atomic operation is to be written back to the programmable pipeline in the load store unit, the operand is transmitted to the designated position of the programmable pipeline in the load store unit through the cache.

[0078] In some embodiments, when the first return control information indicates that the operand corresponding to the vector atomic operation is not to be written back to the programmable pipeline in the load store unit, the register resource in the programmable pipeline is released when the request is transmitted to the downstream module.

[0079] Based on the above technical solution, the first return control information that can be passed to the atomic operation execution unit is determined based on the first bit field indicating whether the destination operand corresponding to the vector atomic operation is empty, so that the atomic operation execution unit can know whether the operand corresponding to the vector atomic operation is to be written back to the programmable pipeline after execution based on the first return control information, the operand is returned on demand, and the waste of bandwidth of the return path of the atomic operation with no return value is reduced.

[0080] In some embodiments, the above step 105 can be implemented by the following steps 1051 to 1052:

[0081] Step 1051, in the case that the bit in the bypass information in the control signal transmitted by the load store unit to the cache at each level is in the first state value, defining the bit in the first state value as the first return control information; the first state value represents that the corresponding bit is not defined.

[0082] The bit in the first state value refers to the bit that is not defined. In some embodiments, the state value of the bit is 0 (the first state value), indicating that the bit is not defined; the state value of the bit is 1, indicating that the bit is defined.

[0083] The bypass information is used to indicate whether the normal cache operation process needs to be bypassed and data access is directly performed on the memory or other storage levels. In some embodiments, the bypass information can include, but is not limited to, an identifier indicating that the current operation needs to bypass the cache, an address mapping relationship, a request type, and a cache hit condition, etc.

[0084] Step 1052, determining the identifier value of the first return control information based on the first bit field.

[0085] In some embodiments, the specific implementation of step 1052 can include: in the case that the first bit field is a first identifier value, configuring the first return control information as a third identifier value; the first identifier value represents that the destination operand corresponding to the vector atomic operation is empty, and the third identifier value represents that the operand corresponding to the vector atomic operation is not written back to the programmable pipeline; in the case that the first bit field is a second identifier value, configuring the first return control information as a fourth identifier value; the second identifier value represents that the destination operand corresponding to the vector atomic operation is not empty, and the fourth identifier value represents that the operand corresponding to the vector atomic operation is written back to the programmable pipeline.

[0086] For example, the first identifier value can be null, and the second identifier value can be 1; the third identifier value can be 0, and the fourth identifier value can be 1. In this case, in the case that the first bit field is null, the first return control information is configured as 0; in the case that the first bit field is 1, the first return control information is configured as 1.

[0087] Based on the above technical solution, the undefined bit in the bypass information transmitted by the load store unit to the cache at each level is used as the first return control information, which can improve the utilization rate of the pass bandwidth between the load store unit and the cache at each level.

[0088] The embodiment of the present disclosure provides an execution method of an atomic operation, which can be executed by a processor of a computer device. As shown in the method includes at least one of the following steps 201 to step 202: Figure 2 The embodiment of the present disclosure provides an execution method of an atomic operation, which can be executed by a processor of a computer device. As shown in the method includes at least one of the following steps 201 to step 202: Figure 2

[0089] Step 201, in response to a second execution request of an atomic operation, determining a type of the atomic operation and second return control information based on a bit field in the second execution request.

[0090] The type of the atomic operation at least includes a vector atomic operation and a scalar atomic operation; and the second return control information represents whether to write back an operand corresponding to the atomic operation to a programmable pipeline in the load store unit.

[0091] The atomic operation is divided into a vector atomic operation and a scalar atomic operation according to whether the operand has a direction; the vector atomic operation includes a returnless vector atomic operation and a return vector atomic operation, and the scalar atomic operation includes a returnless scalar atomic operation and a return scalar atomic operation. The atomic operation is divided into a return atomic operation and a returnless atomic operation according to whether a return value is needed; the return atomic operation includes a return scalar atomic operation and a return vector atomic operation, and the returnless atomic operation includes a returnless scalar atomic operation and a returnless vector atomic operation.

[0092] The second execution request refers to an execution request / command of the atomic operation currently being processed. Characters in the execution request can be defined as different bit fields according to business needs. For example, the execution request can include but is not limited to a bit field representing a memory size to be accessed, a bit field for storing an operand, a bit field representing a type of the atomic operation, and the like.

[0093] For partitioned return atomic operations and returnless atomic operations, the embodiment of the present disclosure adds return control information in the entire link from the LSU to the atomic operation execution, so as to return the source operand on demand after the atomic operation is executed, and reduce the waste of the path bandwidth.

[0094] In some embodiments, the type of the atomic operation can be determined according to a bit field representing the type of the atomic operation in the first execution request, or according to a bit field representing a memory size to be accessed in the first execution request.

[0095] In some embodiments, the return control information can be determined according to a bit field representing whether a return value is needed in the first execution request.

[0096] Specifically, when the bit field representing whether a return value is needed is empty, the return control information that does not need to write back the operand corresponding to the atomic operation to the programmable pipeline is added; and when the bit field representing whether a return value is needed is not empty, the return control information that needs to write back the operand corresponding to the atomic operation to the programmable pipeline is added.

[0097] It should be noted that, in order to be compatible with scalar atomic operations and vector atomic operations, the embodiments of the present disclosure multiplex the bit field of Load and Store to represent the size of the memory to be accessed (request size). Specifically, when sending an execution request of a scalar atomic operation, the specific value of the bit field of the request size is an unextended size determined based on the number of bits of the scalar; when sending an execution request of a vector atomic operation, the specific value of the bit field of the request size is an extended size determined based on the number of vectors and the data type. In this way, the instruction set is adapted to be compatible with the execution requests of different atomic operations, and the type of atomic operation and the request size corresponding to different types of atomic operations are embodied through the bit field of the request size.

[0098] Step 202, based on the type of the atomic operation and the second return control information, executing the atomic operation.

[0099] In some embodiments, the specific implementation of step 202 can include: in the case where the second return control information represents that the operand corresponding to the atomic operation does not need to be written back to the programmable pipeline, executing the atomic operation on the memory based on the type of the atomic operation; in the case where the return control information represents that the operand corresponding to the atomic operation needs to be written back to the programmable pipeline, executing the atomic operation on the memory based on the type of the atomic operation and writing the operand corresponding to the atomic operation back to the programmable pipeline.

[0100] In the embodiments of the present disclosure, in order to enable the execution request of the atomic operation to be compatible with different types of atomic operations, the instruction set is adapted, and the bit field of the request size is multiplexed so that the bit field of the request size has different values under different types of atomic operations; in this way, not only the type of the atomic operation can be embodied, but also the request size corresponding to different types of atomic operations can be embodied. In order to partition atomic operations with return and atomic operations without return, return control information is added in the entire link from the LSU to the execution of the atomic operation, so that the source operand is returned on demand after the execution of the atomic operation, so as to optimize the return path of the atomic operation without return value and reduce the waste of path bandwidth. In this way, not only scalar atomic operations can be supported, but also vector atomic operations can be supported, and the adaptability is high; and by optimizing the return path of the atomic operation without return value, the waste of path bandwidth and hardware bandwidth can be reduced.

[0101] The embodiments of the present disclosure provide an atomic operation execution method, which can be executed by a processor of a computer device. As shown in Figure 3 The method includes at least one of the following steps 301 to 303:

[0102] Step 301, in response to a second execution request of an atomic operation, determining the type of the atomic operation based on a second bit field in the second execution request.

[0103] The second bit field represents a bit number of an operand corresponding to the atomic operation. The type of the atomic operation includes a vector atomic operation and a scalar atomic operation. The second return control information represents whether the operand corresponding to the atomic operation is written back to a programmable pipeline in a load storage unit.

[0104] The second bit field refers to a bit field of a request size. The second bit field stores an unexpanded size under a scalar atomic operation, and the unexpanded size is a bit number of a scalar. The second bit field stores an expanded size under a vector atomic operation, and the expanded size is determined based on a number of vectors and a data type. Specifically, the expanded size is a product of the number of vectors and a size based on the data type.

[0105] The expanded size is greater than the unexpanded size, and the number of bits required for storage of the expanded size is also greater than the number of bits required for storage of the unexpanded size. Therefore, the type of the atomic operation can be distinguished by a specific value in the bit field of the request size and / or the number of bits used.

[0106] In some embodiments, a specific implementation of the step 301 of "determining the type of the atomic operation based on the second bit field in the second execution request" can include: determining whether the second bit field is an expanded size based on a first sub-bit field and a second sub-bit field in the second bit field; the first sub-bit field represents a data type size, and the second sub-bit field represents a data bit width to be updated by the atomic operation; in the case that the second bit field is the expanded size, determining that the type of the atomic operation is a vector atomic operation; the expanded size is determined based on a number of vectors and a data type; in the case that the second bit field is an unexpanded size, determining that the type of the atomic operation is a scalar atomic operation; the unexpanded size is determined based on a bit number of a scalar.

[0107] In some embodiments, a specific implementation of "determining whether the second bit field is an expanded size based on a first sub-bit field and a second sub-bit field in the second bit field" can include: determining a multiple relationship between the first sub-bit field and the second sub-bit field; in the case that the multiple relationship is 2 0 , determining that the second bit field is an unexpanded size; in the case that the multiple relationship is 2 n , determining that the second bit field is an expanded size; n is a positive integer.

[0108] The step 302 of determining the second return control information based on a third bit field in the second execution request.

[0109] The third bit field represents whether a destination operand corresponding to the atomic operation is empty.

[0110] The third bit field is empty, indicating that a return value is not required; and the third bit field is not empty, indicating that a return value is required.

[0111] In some embodiments, the implementation of step 302 can include: in the case that there is an undefined bit in the bypass information in the control signal passed by the load-store unit to the cache, defining the undefined bit as second return control information; configuring the identification value of the second return control information based on a third field in the second execution request.

[0112] The bypass information in the control signal passed by the load-store unit to the cache can represent the type of the atomic operation.

[0113] In some embodiments, the implementation of "configuring the identification value of the second return control information based on a third field in the second execution request" can include: in the case that the third field is a first identification value, configuring the second return control information as a third identification value; the first identification value represents that the destination operand corresponding to the atomic operation is empty, and the third identification value represents that the operand corresponding to the atomic operation is not written back to the programmable pipeline; in the case that the third field is a second identification value, configuring the second return control information as a fourth identification value; the second identification represents that the destination operand corresponding to the atomic operation is not empty, and the fourth identification value represents that the operand corresponding to the atomic operation is written back to the programmable pipeline.

[0114] For example, the first identification value can be null, and the second identification value can be 1; the third identification value can be 0, and the fourth identification value can be 1. In this case, in the case that the third field is null, the second return control information is configured as 0; in the case that the third field is 1, the second return control information is configured as 1.

[0115] In some embodiments, the return control information is configured together with the type of the atomic operation, which can improve the utilization of resources and reduce the waste of the bandwidth of the path between the LSU and the atomic operation execution module; if the resource waste is not considered, the return control information can be configured separately.

[0116] Step 303, based on the type of the atomic operation and the second return control information, executing the atomic operation.

[0117] In some embodiments, in the case that the type of the atomic operation is a scalar atomic operation, step 303 can be implemented by steps 3031 to 3032 as follows:

[0118] Step 3031, in the case that the type of the atomic operation is the scalar atomic operation, reading a second payload from one or more second registers in the load-store unit based on an unextended size in the second execution request; the unextended size is determined based on the number of bits of the scalar.

[0119] Here, the second payload refers to a payload of the scalar atomic operation. The second register refers to a register storing data required by the scalar atomic operation when executed.

[0120] Step 3032, performing the scalar atomic operation on the memory according to the second payload and the second return control information.

[0121] Here, the second payload includes an operand corresponding to the scalar atomic operation, and other information required for executing the scalar atomic operation, etc.

[0122] In some embodiments, the specific implementation of step 3032 can include: in the case where the second return control information is the third identification value, performing the scalar atomic operation on the memory according to the second payload, and releasing resources in the programmable pipeline; in the case where the second return control information is the fourth identification value, performing the scalar atomic operation on the memory according to the second payload, and writing back the operand corresponding to the scalar atomic operation to the programmable pipeline.

[0123] For example, if an execution request of a scalar atomic operation is received, first, the LSU configures the return control information according to a bit field (third bit field) in the execution request indicating whether a return value is required; then, the LSU reads the payload from the load store unit according to the unextended size in the execution request, and transmits the scalar atomic operation, the return control information, and the payload to the memory through the caches; next, the scalar atomic operation is performed on the memory according to the payload, and if the return control information is 0, the register resources in the programmable pipeline are released when the request is transmitted to the downstream module; if the return control information is 1, the operand is transmitted to the specified position of the programmable pipeline in the load store unit through the caches after the scalar atomic operation is executed.

[0124] It should be noted that the scalar atomic operation, the main improvement of the embodiment of the present disclosure is that the return on demand is realized according to the return control information, the return path power consumption of the non-return scalar atomic operation is avoided, and the return path bandwidth is released.

[0125] In some embodiments, when the type of the atomic operation is a vector atomic operation, step 303 can be implemented by steps 3033 to 3034 as follows:

[0126] Step 3033, in the case where the type of the atomic operation is a vector atomic operation, reading a third payload from the load store unit based on the extended size in the second execution request; the extended size is determined based on the number of vectors and the data type.

[0127] Here, step 3033 corresponds to the aforementioned step 101, and the specific implementation of the aforementioned step 101 can be referred to during implementation.

[0128] The third payload refers to the payload of the vector atomic operation. The difference between the third payload and the first payload is that the third payload is the payload of the vector atomic operation corresponding to the second execution request, while the first payload is the payload of the vector atomic operation corresponding to the first execution request.

[0129] To ensure compatibility with vector atomic operations, in addition to adapting the instruction set, in vector scenarios, the payload also needs to be read from the register of the loading memory unit according to the extended size.

[0130] Step 3034: Perform the atomic operation in memory based on the third payload and the second return control information.

[0131] Here, step 3034 corresponds to the aforementioned step 102, and the specific implementation of the aforementioned step 102 can be referred to during implementation.

[0132] For example, if an execution request for a vector atomic operation is received, firstly, the LSU configures return control information based on the bit field (third bit field) in the execution request indicating whether a return value is required; then, the LSU reads the payload from the load storage unit according to the extended size in the execution request, and transfers the scalar atomic operation, return control information, and payload to memory (video memory) through various levels of cache; next, the vector atomic operation is performed in memory based on the payload. If the return control information is 0, the register resources in the programmable pipeline are released when the request is passed to the downstream module; if the return control information is 1, after the vector atomic operation is completed, the operands are transferred through the various levels of cache to the specified location in the programmable pipeline of the load transfer unit.

[0133] It should be noted that vector atomic operations have a higher risk of going out of bounds because they operate on multiple data units; while scalar atomic operations have an extremely low probability of going out of bounds because they operate on a single object and have a clearly defined address range. Therefore, the embodiments of this disclosure describe in detail the out-of-bounds situation of vector atomic operations. In implementation, the out-of-bounds situation of scalar atomic operations can also be analyzed and handled by referring to the out-of-bounds operation of vector atomic operations.

[0134] This disclosure provides a method for performing atomic operations, such as... Figure 4 As shown, the method includes at least one of the following steps 401 to 403:

[0135] Step 401: In the case of multiple first execution requests of the vector atomic operations with consecutive addresses, the multiple first execution requests are concatenated based on the starting address and extension size of the multiple first execution requests to obtain a third execution request.

[0136] The second execution request refers to an execution request of a plurality of address-continuous vector atomic operations.

[0137] In step 402, an extended size of the third execution request is determined based on a quantity of a vector corresponding to the third execution request and a data type.

[0138] In step 403, the corresponding vector atomic operation is executed based on the extended size of the third execution request.

[0139] It should be noted that the LSU in the related art does not contain a request merging function. In the embodiment of the present disclosure, the external interface of the LSU is multiplexed, and an adjacent address merging unit is added between the LSU and the cache at each level. The product of the number of elements in the vector and the size of the data type of the vector is taken as a new request size, and this does not cause an increase in external interface resources.

[0140] In the embodiment of the present disclosure, by adding return control information, on-demand return can be realized. When there is no return, the register resources corresponding to the atomic operation are directly released, which can reduce the power consumption of the return path, and reduce the waste of register resources and the bandwidth of the return path. To be compatible with vector atomic operations, the instruction set is adapted to the hardware logic, the reading path of the effective load of the storage request is multiplexed, and the adjacent address merging unit is configured. The same downstream is used for processing the vector atomic operation as the scalar atomic operation, which can improve the utilization rate of hardware resources such as interfaces and paths. When a non-aligned virtual address is received, the non-aligned virtual address is aligned downward, which can reduce the situation that the module executing the atomic operation downstream is deadlocked due to receiving non-conventional input.

[0141] The following describes the application of the atomic operation execution method provided by the embodiment of the present disclosure in an actual scenario.

[0142] The atomic operation execution method provided by the embodiment of the present disclosure is also expected to solve at least one of the following three problems: 1. The return path bandwidth is wasted in optimizing the variable atomic operation without a return value; 2. Support for vector atomic operations; 3. Aligning non-aligned virtual addresses downward and actively reporting exceptions when a non-aligned problem occurs.

[0143] The specific scheme of the atomic operation execution method provided by the embodiment of the present disclosure is as follows:

[0144] For the case that the return path bandwidth is wasted in optimizing the variable atomic operation without a return value, the embodiment of the present disclosure solves this problem by adding return control information, as shown in the following Table 2:

[0145] Table 2

[0146]

[0147] An exemplary setting of return control information of the return path is shown in Table 3 as follows:

[0148] Table 3

[0149]

[0150] As shown in Figure 5 , the related art returns the original value stored at the specified address before the execution of the atomic operation to the programmable pipeline after the execution of the scalar atomic operation without return, but does not write back, resulting in a waste of return path bandwidth. The embodiment of the present disclosure adds return control information, does not return the original value after the execution of the scalar atomic operation without return, and directly releases the register resource corresponding to the scalar atomic operation without return. In this way, the return path power consumption can be reduced, and the waste of register resources and return path bandwidth can be reduced.

[0151] To be compatible with global vector atomic operations, an exemplary modification scheme is shown in Table 4 as follows:

[0152] Table 4

[0153]

[0154] As shown in Figure 6 , the specific scheme of the vector atomic operation can include: the LSU reads the payload (operand) from the load store unit according to the extended size in the execution request after receiving the execution request of the vector atomic operation, and sends the atomic operation, the extended size and the payload to the adjacent address merging unit; the adjacent address merging unit judges whether there is other request adjacent to the memory address of the current vector atomic operation, if there is other request adjacent to the memory address of the current vector atomic operation, the request is merged, and the corresponding vector atomic operation of the merged request is processed through the cache and the memory; if there is no other request adjacent to the memory address of the current vector atomic operation, the current vector atomic operation is processed through the cache and the memory; and the original value is returned on demand after the execution of the vector atomic operation.

[0155] To provide a friendly global atomic operation experience for users and avoid the downstream atomic operation execution module from being deadlocked due to receiving non-conventional input, the LSU of the embodiment of the present disclosure performs down alignment on the memory virtual address when receiving the atomic operation using the non-aligned memory virtual address, and reports an exception, so as to facilitate the user to query through software.

[0156] As shown in Figure 7As shown in the formula: (virtual address % data type of atomic operation) == 0, it is judged whether the memory address corresponding to the atomic operation is a processable address, if the memory address corresponding to the atomic operation is a processable address, the memory address corresponding to the atomic operation is left shifted according to the data type of the atomic operation to obtain an aligned virtual address; if the memory address corresponding to the atomic operation is not a processable address, an exception is reported.

[0157] Embodiments of the present disclosure take a five-stage pipeline as an example to describe the execution method of the atomic operation provided by the embodiments of the present disclosure.

[0158] As shown in the formula: (virtual address % data type of atomic operation) == 0, it is judged whether the memory address corresponding to the atomic operation is a processable address, if the memory address corresponding to the atomic operation is a processable address, the memory address corresponding to the atomic operation is left shifted according to the data type of the atomic operation to obtain an aligned virtual address; if the memory address corresponding to the atomic operation is not a processable address, an exception is reported. Figure 8 As shown in the formula: (virtual address % data type of atomic operation) == 0, it is judged whether the memory address corresponding to the atomic operation is a processable address, if the memory address corresponding to the atomic operation is a processable address, the memory address corresponding to the atomic operation is left shifted according to the data type of the atomic operation to obtain an aligned virtual address; if the memory address corresponding to the atomic operation is not a processable address, an exception is reported.

[0159] As shown in the formula: (virtual address % data type of atomic operation) == 0, it is judged whether the memory address corresponding to the atomic operation is a processable address, if the memory address corresponding to the atomic operation is a processable address, the memory address corresponding to the atomic operation is left shifted according to the data type of the atomic operation to obtain an aligned virtual address; if the memory address corresponding to the atomic operation is not a processable address, an exception is reported. Figure 9 As shown in the formula: (virtual address % data type of atomic operation) == 0, it is judged whether the memory address corresponding to the atomic operation is a processable address, if the memory address corresponding to the atomic operation is a processable address, the memory address corresponding to the atomic operation is left shifted according to the data type of the atomic operation to obtain an aligned virtual address; if the memory address corresponding to the atomic operation is not a processable address, an exception is reported.

[0160] It should be noted that the optimization of the non-return atomic operation mainly reflects in the return control information, and the LSU only configures the return control information to be sent to the downstream according to whether the destination operand is empty. The change of the vector atomic operation will affect the data amount of the input and output through the return control information; the address alignment and the exception reporting need to be performed after the address calculation. The embodiments of the present disclosure need to cooperate with the adjacent address merging unit, and higher processing performance can be achieved.

[0161] The embodiments of the present disclosure are based on the global atomic operation scene, and solve the technical problems in the related art by adding return control information, optimizing the return-free path, and address preprocessing. Specifically:

[0162] 1. Control information adjustment of the global atomic operation without return value: reduce the power consumption of the return path and release the bandwidth of the return path at the cost of increasing 1 bit of control information;

[0163] 2. Support global vector atomic operation: reuse the control information of the load and store request to improve the utilization rate of the interface control information;

[0164] 3. Virtual address alignment preprocessing, and timely report of exceptions when the non-alignment problem occurs, so that the user can query through software, and effectively avoid the situation that the downstream module executing the atomic operation is deadlocked due to receiving non-conventional input.

[0165] The technical points of the embodiments of the present disclosure are exemplified in Table 5 as follows:

[0166] Table 5

[0167]

[0168] The technical effects that can be achieved by the embodiments of the present disclosure include but are not limited to those shown in Table 6 as follows:

[0169] Table 6

[0170]

[0171] Based on the foregoing embodiments, the present disclosure provides an atomic operation execution device, which includes various units and modules included in the units, and can be implemented by a processor in a computer device. Of course, it can also be implemented by a specific logic circuit. In the implementation process, the processor can be a central processing unit (CPU), a microprocessor unit (MPU), a digital signal processor (DSP), or a field programmable gate array (FPGA).

[0172] Figure 10 The composition structure diagram of the atomic operation execution device provided by the embodiments of the present disclosure is shown in FIG. 1, which includes a reading module 1010 and a processing module 1020. Figure 10

[0173] ​The read module 1010 is configured to, in response to a first execution request of a vector atomic operation, read a first payload from one or more first registers in a load storage unit based on an extended size in the first execution request; the extended size is determined based on the number and data type of the vector.

[0174] The processing module 1020 is used to perform the vector atomic operation according to the first payload.

[0175] In some embodiments, the processing module 1020 is further configured to: determine first return control information based on the first bit field in the first execution request; the first bit field is used to characterize whether the destination operand corresponding to the vector atomic operation is empty; and when the first return control information characterizes writing the operand corresponding to the vector atomic operation back to the programmable pipeline in the load memory unit, write the operand corresponding to the vector atomic operation back to the programmable pipeline after the vector atomic operation is executed.

[0176] In some embodiments, the processing module 1020 is further configured to: define the bit in the first state value as the first return control information when there is a bit in the bypass information of the control signal passed by the loading storage unit to each level of cache; the first state value indicates that the corresponding bit is not defined; and determine the identifier value of the first return control information based on the first bit field.

[0177] In some embodiments, the processing module 1020 is further configured to: configure the first return control information to a third identifier value when the first field is a first identifier value; the first identifier value indicates that the destination operand corresponding to the vector atomic operation is empty, and the third identifier value indicates that the operand corresponding to the vector atomic operation is not written back to the programmable pipeline; and configure the first return control information to a fourth identifier value when the first field is a second identifier value; the second identifier value indicates that the destination operand corresponding to the vector atomic operation is not empty, and the fourth identifier value indicates that the operand corresponding to the vector atomic operation is written back to the programmable pipeline.

[0178] In some embodiments, the processing module 1020 is further configured to: in response to a second execution request of an atomic operation, determine the type of the atomic operation and second return control information based on the bit fields in the second execution request; the type of the atomic operation includes at least: vector atomic operation and scalar atomic operation; the second return control information indicates whether to write the operand corresponding to the atomic operation back to the programmable pipeline; and execute the atomic operation based on the type of the atomic operation and the second return control information.

[0179] In some embodiments, the processing module 1020 is further configured to determine the type of the atomic operation based on a second bit field in the second execution request; the second bit field represents a bit number of an operand corresponding to the atomic operation; and determine the second return control information based on a third bit field in the second execution request; the third bit field represents whether a destination operand corresponding to the atomic operation is empty.

[0180] In some embodiments, the processing module 1020 is further configured to, in a case where it is determined that the second bit field is of an extended size based on a first sub-bit field and a second sub-bit field in the second bit field, determine that the type of the atomic operation is the vector atomic operation; the first sub-bit field indicates a data type size, and the second sub-bit field indicates a data bit width to be updated by the atomic operation; and in a case where it is determined that the second bit field is of an unextended size based on the first sub-bit field and the second sub-bit field in the second bit field, determine that the type of the atomic operation is the scalar atomic operation; the unextended size is determined based on a bit number of a scalar.

[0181] In some embodiments, the processing module 1020 is further configured to, in a case where a multiple relationship between the first sub-bit field and the second sub-bit field is 20, the second bit field is of the unextended size; and in a case where the multiple relationship between the first sub-bit field and the second sub-bit field is 2n, the second bit field is of the extended size; n is a positive integer.

[0182] In some embodiments, the reading module 1010 is further configured to, in a case where the type of the atomic operation is the scalar atomic operation, read a second payload from one or more second registers in the load-store unit based on an unextended size in the second execution request; the unextended size is determined based on a bit number of a scalar; and the processing module 1020 is further configured to perform the scalar atomic operation on the memory according to the second payload and the second return control information.

[0183] In some embodiments, the processing module 1020 is further configured to, in a case where the second return control information is a third identification value, perform the scalar atomic operation on the memory according to the second payload and release resources in the programmable pipeline; and in a case where the second return control information is a fourth identification value, perform the scalar atomic operation on the memory according to the second payload and write back an operand corresponding to the scalar atomic operation to the programmable pipeline.

[0184] In some embodiments, the processing module 1020 is further configured to: determine a range of memory addresses to be updated by the vector atomic operation based on the start address and the extension size in the first execution request; and perform alignment processing on the range of memory addresses in a case where the range of memory addresses is a non-aligned virtual address.

[0185] In some embodiments, the processing module 1020 is further configured to: determine whether the range of memory addresses is a processable address according to a virtual address corresponding to the range of memory addresses and a data type of the vector atomic operation; and perform alignment processing on the range of memory addresses according to the data type of the vector atomic operation in a case where the range of memory addresses is a processable address.

[0186] In some embodiments, the reading module 1010 is further configured to: determine a register resource allocated to the vector atomic operation; determine a boundary of a write-back register corresponding to the vector atomic operation based on an operand corresponding to the vector atomic operation and the extension size; the boundary of the write-back register at least includes an upper boundary and a lower boundary; and read a first payload from one or more first registers in the load-store unit based on the extension size in a case where it is determined that there is no write-back out-of-bound of the vector atomic operation based on the boundary of the write-back register and the register resource.

[0187] In some embodiments, the processing module 1020 is further configured to: determine that there is an exception in the first execution request in a case where the range of memory addresses is not a processable address and / or there is write-back out-of-bound of the vector atomic operation, and / or send prompt information representing the exception of the first execution request.

[0188] In some embodiments, the processing module 1020 is further configured to: splice a plurality of first execution requests of the vector atomic operation in a case where there are a plurality of first execution requests of the vector atomic operation that are continuous in address, to obtain a third execution request based on start addresses and extension sizes of the plurality of first execution requests; determine an extension size of the third execution request based on a number and a data type of vectors corresponding to the third execution request; and execute the corresponding vector atomic operation based on the extension size of the third execution request.

[0189] The above device embodiments are similar to the descriptions of the above method embodiments, and have similar beneficial effects to the method embodiments. In some embodiments, the device provided by the embodiments of the present disclosure has functions or includes modules that can be used to execute the methods described in the above method embodiments. For technical details of the device embodiments of the present disclosure that are not disclosed, please refer to the description of the method embodiments of the present disclosure.

[0190] It should be noted that, in the embodiments of the present disclosure, if the execution method of the atomic operation is implemented in the form of a software function module and is sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure can be embodied in the form of a software product in essence or the part that contributes to the related art, which is stored in a storage medium, includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present disclosure. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ReadOnly Memory, ROM), a magnetic disk or an optical disk, and various media that can store program codes. Thus, the embodiments of the present disclosure are not limited to any specific hardware, software or firmware, or any combination of hardware, software, firmware.

[0191] The embodiments of the present disclosure provide a computer device, including a memory and a processor, the memory stores a computer program capable of running on the processor, and the processor implements part or all of the steps of the above method when executing the program.

[0192] The embodiments of the present disclosure provide a computer readable storage medium, which stores a computer program, and the computer program is executed by a processor to implement part or all of the steps of the above method. The computer readable storage medium can be transitory or non-transitory.

[0193] The embodiments of the present disclosure provide a computer program, which includes computer readable code, and when the computer readable code runs in a computer device, a processor in the computer device executes part or all of the steps of the above method.

[0194] The embodiments of the present disclosure provide a computer program product, which includes a non-transitory computer readable storage medium storing a computer program, and when the computer program is read and executed by a computer, part or all of the steps of the above method are implemented. The computer program product can be specifically implemented by hardware, software or a combination thereof. In some embodiments, the computer program product is specifically embodied as a computer storage medium, and in other embodiments, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0195] It should be noted that the above description of the various embodiments tends to emphasize differences between the various embodiments, and the same or similar elements can be mutually referred to. The above description of the device, storage medium, computer program and computer program product embodiments is similar to the description of the method embodiments, and has similar beneficial effects as the method embodiments. For technical details of the device, storage medium, computer program and computer program product embodiments of the present disclosure, please refer to the description of the method embodiments of the present disclosure.

[0196] It should be noted that, Figure 11 A hardware entity diagram of a computer device in the embodiments of the present disclosure is shown in FIG. 11, which includes a processor 1101, a communication interface 1102 and a memory 1103, wherein: Figure 11 The processor 1101 generally controls the overall operation of the computer device 1100.

[0197] The processor 1101 generally controls the overall operation of the computer device 1100.

[0198] The communication interface 1102 can enable the computer device to communicate with other terminals or servers through a network.

[0199] The memory 1103 is configured to store instructions and applications executable by the processor 1101, and can also cache data to be processed by the processor 1101 and modules in the computer device 1100 (for example, image data, audio data, voice communication data and video communication data) to be processed or having been processed, which can be implemented by FLASH or Random Access Memory (RAM). The processor 1101, the communication interface 1102 and the memory 1103 can transmit data through the bus 1104.

[0200] It should be understood that the "one embodiment" or "an embodiment" mentioned throughout the specification means that the specific features, structures or characteristics related to the embodiment are included in one or more embodiments of the present disclosure. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present disclosure, the size of the sequence number of each step / process does not mean the execution order, and the execution order of each step / process should be determined by its function and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure. The above sequence number of the embodiments of the present disclosure is only for description, and does not represent the advantages and disadvantages of the embodiments.

[0201] It should be noted that, in the present document, the terms "comprising", "containing" or any other similar term are intended to encompass non-exclusive inclusion, such that processes, methods, articles, or apparatuses that comprise a list of elements are not limited to those elements, but can also include other elements not expressly listed, or also include elements inherent in such processes, methods, articles, or apparatuses. Without further limitation, an element defined by the phrase "comprising a" does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0202] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are merely illustrative, for example, the division of the units is only a logical function division, and actual implementation can have another division manner, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the coupling or direct coupling or communication connection between the various components shown or discussed can be through some interface, indirect coupling or communication connection between devices or units, which can be electrical, mechanical or other forms.

[0203] The units described above as separate components can or can not be physically separate, and the components shown as units can or can not be physical units; they can be located in one place or distributed on multiple network units; and some or all of the units can be selected according to actual needs to achieve the purpose of the embodiment.

[0204] In addition, each functional unit in each embodiment of the present disclosure can be integrated into one processing unit, or each unit can be a separate unit, or two or more units can be integrated into one unit; the integrated unit can be realized in the form of hardware or in the form of hardware plus software functional unit.

[0205] Those of ordinary skill in the art can understand that all or part of the steps of the above method embodiments can be completed by program instruction related hardware, and the aforementioned program can be stored in a computer readable storage medium, and the program executes the steps of the above method embodiments when executed; and the aforementioned storage medium includes: mobile storage device, read only memory (Read Only Memory, ROM), magnetic disc or optical disc, and various storage medium that can store program codes.

[0206] Alternatively, the above-mentioned integrated units of the present disclosure, if implemented in the form of software function modules and sold or used as independent products, can also be stored in a computer-readable storage medium. Based on such understanding, the technical solutions of the present disclosure can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to make a computer device (which can be a personal computer, a server, or a network device, etc.) execute all or part of the methods described in the various embodiments of the present disclosure. The aforementioned storage medium includes: mobile storage devices, ROM, magnetic disks or optical disks, and various media that can store program codes.

[0207] The above is only an embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure.

Claims

1. A method for performing atomic operations, characterized in that, The method for performing the atomic operation includes: In response to a first execution request for a vector atomic operation, a first payload is read from one or more first registers in a load memory unit based on an extended size in the first execution request; the extended size is determined based on the number and data type of the vectors; the atomic operation is divided into vector atomic operations and scalar atomic operations according to whether the operands have direction; the extended size is used to characterize the number and data type of the vectors corresponding to the vector atomic operation; the first payload refers to the data required by the vector atomic operation during execution. The vector atomic operation is performed based on the first payload.

2. The method for performing atomic operations according to claim 1, characterized in that, The method for performing the atomic operation further includes: Based on the first bit field in the first execution request, the first return control information is determined; the first bit field is used to characterize whether the destination operand corresponding to the vector atomic operation is empty; When the first return control information indicates that the operands corresponding to the vector atomic operation are written back to the programmable pipeline in the load memory unit, the operands corresponding to the vector atomic operation are written back to the programmable pipeline after the vector atomic operation is executed.

3. The method for performing atomic operations according to claim 2, characterized in that, The step of determining the first return control information based on the first field in the first execution request includes: If there is a bit in the bypass information of the control signal passed from the loading memory unit to each level of cache that is in a first state value, the bit in the first state value is defined as the first return control information; the first state value indicates that the corresponding bit is not defined. Based on the first bit field, determine the identifier value of the first returned control information.

4. The method for performing atomic operations according to claim 3, characterized in that, Determining the identifier value of the first returned control information based on the first bit field includes: When the first field is a first identifier value, the first returned control information is configured to a third identifier value; the first identifier value indicates that the destination operand corresponding to the vector atomic operation is empty, and the third identifier value indicates that the operand corresponding to the vector atomic operation is not written back to the programmable pipeline; When the first field is the second identifier value, the first returned control information is configured as the fourth identifier value; the second identifier value indicates that the destination operand corresponding to the vector atomic operation is not empty, and the fourth identifier value indicates that the operand corresponding to the vector atomic operation is written back to the programmable pipeline.

5. The method for performing atomic operations according to any one of claims 1 to 4, characterized in that, The method for performing the atomic operation further includes: In response to a second execution request for an atomic operation, the type of the atomic operation and second return control information are determined based on the bit fields in the second execution request; the type of the atomic operation includes at least: vector atomic operations and scalar atomic operations; the second return control information indicates whether to write the operands corresponding to the atomic operation back to the programmable pipeline in the load memory unit; The atomic operation is executed based on the type of the atomic operation and the second return control information.

6. The method for performing atomic operations according to claim 5, characterized in that, The step of determining the type of the atomic operation and the second return control information based on the bit fields in the second execution request includes: The type of the atomic operation is determined based on the second bit field in the second execution request; the second bit field represents the number of bits in the operand corresponding to the atomic operation. Based on the third bit field in the second execution request, the second return control information is determined; the third bit field indicates whether the destination operand corresponding to the atomic operation is empty.

7. The method for performing atomic operations according to claim 6, characterized in that, Determining the type of the atomic operation based on the second bit field in the second execution request includes: If the second bit field is determined to be an extended size based on the first and second sub-bit fields in the second bit field, the type of the atomic operation is determined to be the vector atomic operation; the first sub-bit field represents the data type size, and the second sub-bit field represents the data bit width to be updated by the atomic operation; If the second bit field is determined to be of unextended size based on the first and second sub-bit fields in the second bit field, the type of the atomic operation is determined to be the scalar atomic operation; the unextended size is determined based on the number of bits in the scalar.

8. The method for performing atomic operations according to claim 7, characterized in that, The multiple relationship between the first subdomain and the second subdomain is 2. 0 In this case, the second bit field is of unextended size; The multiple relationship between the first subdomain and the second subdomain is 2. n In the case of n, the second bit field is an extended size; n is a positive integer.

9. The method for performing atomic operations according to claim 5, characterized in that, The execution of the atomic operation based on the type of the atomic operation and the second return control information includes: In the case that the type of the atomic operation is the scalar atomic operation, the second payload is read from one or more second registers in the load memory unit based on the unexpanded size in the second execution request; the unexpanded size is determined based on the number of bits of the scalar. The scalar atomic operation is performed in memory based on the second payload and the second return control information.

10. The method for performing atomic operations according to claim 9, characterized in that, The step of performing the scalar atomic operation in memory based on the second payload and the second return control information includes: If the second returned control information is the third identifier value, the scalar atomic operation is performed in memory according to the second payload, and the resources in the programmable pipeline are released; When the second return control information is the fourth identifier value, the scalar atomic operation is executed in memory according to the second payload, and the operands corresponding to the scalar atomic operation are written back to the programmable pipeline.

11. The method for performing atomic operations according to any one of claims 1 to 4, characterized in that, Before reading the first payload from one or more first registers in the load storage unit based on the extended size in the first execution request, the method for executing the atomic operation further includes: Based on the starting address and extended size in the first execution request, determine the range of memory addresses to be updated by the vector atomic operation; If the range of memory addresses is an unaligned virtual address, the range of memory addresses is aligned.

12. The method for performing atomic operations according to claim 11, characterized in that, The alignment process for the range of memory addresses includes: Based on the virtual address corresponding to the range of memory addresses and the data type of the vector atomic operation, determine whether the range of memory addresses is a processable address; When the range of memory addresses is a processable address, the range of memory addresses is aligned according to the data type of the vector atomic operation.

13. The method for performing atomic operations according to any one of claims 1 to 4, characterized in that, The step of reading the first payload from one or more first registers in the load storage unit based on the extended size in the first execution request includes: Determine the register resources allocated to the vector atomic operations; Based on the operands corresponding to the vector atomic operation and the expansion size, the boundary of the write-back register corresponding to the vector atomic operation is determined; the boundary of the write-back register includes at least an upper boundary and a lower boundary. If it is determined, based on the boundaries of the write-back register and the register resources, that there is no write-back out-of-bounds in the vector atomic operation, the first payload is read from one or more first registers in the load memory unit based on the extended size.

14. The method for performing atomic operations according to claim 12, characterized in that, The method for performing the atomic operation further includes: If the range of the memory address is not a processable address, and / or the vector atomic operation has a write-back out-of-bounds condition, determine that the first execution request is abnormal, and / or send a prompt message indicating that the first execution request is abnormal.

15. The method for performing atomic operations according to any one of claims 1 to 4, characterized in that, The method for performing the atomic operation further includes: In the case of multiple first execution requests of the vector atomic operations with consecutive addresses, the multiple first execution requests are concatenated based on the starting address and extension size of the multiple first execution requests to obtain a third execution request; Based on the number and data type of the vectors corresponding to the third execution request, determine the expansion size of the third execution request; Based on the expanded size of the third execution request, the corresponding vector atomic operation is executed.

16. An execution device for atomic operations, characterized in that, The means of performing the atomic operation includes: A read module is configured to, in response to a first execution request of a vector atomic operation, read a first payload from one or more first registers in a load storage unit based on an extended size in the first execution request; the extended size is determined based on the number and data type of the vectors; the atomic operations are divided into vector atomic operations and scalar atomic operations according to whether the operands have direction; the extended size is used to characterize the number and data type of the vectors corresponding to the vector atomic operation; the first payload refers to the data required by the vector atomic operation during execution. The processing module is configured to perform the vector atomic operation based on the first payload.

17. A computer device comprising a memory and a processor, the memory storing a computer program executable on the processor, characterized in that, When the processor executes the program, it implements the steps of the method according to any one of claims 1 to 15.

18. A computer-readable storage medium having a computer program stored thereon, characterized in that, When executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 15.

19. A computer program product, characterized in that, The computer program product includes a non-transitory computer-readable storage medium storing a computer program that, when read and executed by a computer, implements the steps of the method according to any one of claims 1 to 15.

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