SRAM refreshing fault-tolerant structure and method for RISC-V processor system

Abstract

The invention discloses an SRAM (Static Random Access Memory) refreshing fault-tolerant structure and method for an RISC-V (Reduced Instruction Set Computer-View) processor system, aiming at the fetch / write-back characteristic of a processor, through a time-sharing multiplexing on-chip single-port SRAM, a variable-time-length timing refreshing strategy, a variable target refreshing address selection strategy and an EDAC (Error Detection And Detection Algorithm are adopted, and through an arbitration control mechanism, the refreshing fault-tolerant structure and method for the RISC-V processor system are realized. And performing data refreshing on the target area of the on-chip SRAM to realize fault-tolerant reinforcement. Using indications generated by the processor access control unit, conflicts between processor fetch / write back and SRAM refresh are avoided with an SRAM access arbitration mechanism. When the SRAM is idle, data error correction and error detection are carried out on the SRAM through time division multiplexing of the on-chip single-port SRAM, the data after error correction are written back, and the fault-tolerant capability of the system is improved. And the capability of resisting single event upset and single event transient behavior of the space processor system is effectively improved from the structural design.

Description

TECHNICAL FIELD

[0001] The application belongs to the field of hardware circuit design, and relates to an SRAM refresh fault-tolerant structure and method for a RISC-V processor system. BACKGROUND

[0002] Currently, for space anti-radiation processor chips, single event upset and transient behavior under space radiation environment can cause in-chip SRAM data to be flipped, resulting in problems such as processor instruction fetch operation exception, thereby reducing the fault-tolerant capability and reliability of the processor system.

[0003] The prior art 'SRAM safe storage system and method for automatically verifying data' CN112908394B mainly detects whether the safety of the SRAM block meets the standard, and when the standard is not met, the data is migrated to a backup block to achieve the purpose of replacement through the backup block, and does not involve SRAM refresh technology. The paper 'Research on SEU-resistant design of general bus controller' provides a chip-level SEU-resistant design method and redundancy coding technology for a general bus controller. The paper 'FPGA embedded multi-bit-width SRAM reinforcement design and implementation' proposes a reinforcement method suitable for FPGA multi-bit-width BRAM, which does not provide a refresh fault-tolerant control technology for processor coordination of in-chip SRAM.

[0004] For the Load (instruction fetch) / Store (write back) characteristics of the RISC-V processor system, how to implement in-chip SRAM refresh to improve system fault-tolerant capability, through retrieval of relevant literature and patents, no method has been found to solve the problem. SUMMARY

[0005] The application aims to solve the problem in the prior art that the instruction fetch / write back characteristics of the RISC-V processor system cannot implement in-chip SRAM refresh to improve system fault-tolerant capability, and provides an SRAM refresh fault-tolerant structure and method for a RISC-V processor system.

[0006] To achieve the above-mentioned purpose, the application adopts the following technical solutions:

[0007] The application provides an SRAM refresh fault-tolerant structure for a RISC-V processor system, which comprises a RISC-V processor unit, a processor access control unit, a refresh access control unit and an SRAM unit.

[0008] The RISC-V processor unit and the processor access control unit interact to implement Load / Store operations of the processor.

[0009] The processor access control unit interacts with the SRAM unit to convert the access initiated by the RISC-V processor unit to initiate read and write access to the SRAM unit; at the same time, the processor access control unit generates a core_busy indication to refresh the access control unit to complete the arbitration between the processor Load / Store and SRAM refresh using the core_busy indication;

[0010] The refresh access control unit is used to implement refresh control of the SRAM unit.

[0011] The SRAM unit is used to store data and EDAC check codes.

[0012] Preferably, the processor access control unit includes a fetch unit, an EDAC decoding unit, an EDAC encoding unit, and a write-back unit.

[0013] The fetch unit converts the processor Load to read access control of the SRAM to implement reading of data from the SRAM; the EDAC decoding unit performs EDAC error detection and correction on the read data, corrects the error bits when a single-bit error occurs, and rewrites the corrected data to the original data address of the SRAM; the EDAC encoding unit generates EDAC encoding for the write-back data and writes the data and the EDAC encoding to the target address of the SRAM; and the write-back unit converts the processor write-back to write access control of the SRAM to implement writing of data to the SRAM.

[0014] Preferably, the processor access control / refresh access control generates access address A[X:2], data D[31:0], EDAC check code PARITY[7:0], chip select CEN, read enable OEN, data SRAM write enable WEN, and EDAC SRAM write enable WEN_E, and interconnects the data SRAM and the EDAC SRAM of the SRAM unit according to the corresponding relationship.

[0015] Preferably, X in the access address A[X:2] is an adjustable parameter, which is determined according to the SRAM capacity selected by the system.

[0016] Preferably, the core_busy indication generated by the processor access control unit adopts an SRAM access arbitration mechanism; when the core_busy indication is valid, the refresh access control unit suspends work; and when the core_busy indication is invalid, the refresh access control unit continues to work to implement time-sharing multiplexing of the single-port SRAM in the chip.

[0017] Preferably, the refresh access control unit includes a refresh start unit, a refresh read unit, a refresh check unit, a refresh write unit, and a refresh timing unit.

[0018] The refresh starting unit is used for configuring refresh starting and ending addresses, configuring refresh enabling, and starting refresh function; the refresh reading unit is used for generating control of SRAM reading access, and realizing reading data access to the SRAM; the refresh checking unit is used for performing EDAC error detection and correction on the data read by the refresh reading unit through the DEAC decoding unit; the refresh writing unit is used for generating control of SRAM writing access, realizing re-writing of the data corrected by the refresh reading unit into the original data address of the SRAM, and jumping to the refresh starting unit after writing is completed or jumping to the refresh timing unit after the last writing is completed; and the refresh timing unit is used for timing the interval time between two refreshes according to the time parameters configured by timing, and after timing is completed, the next round of refresh is started, so as to realize the function of cyclic automatic refresh.

[0019] Preferably, the refresh checking unit performs EDAC error detection and correction on the data read by the refresh reading unit through the DEAC decoding unit, and specifically:

[0020] When single-bit error occurs in error detection, the error bit is corrected, and the refresh writing unit is jumped to; when error detection is correct, the refresh timing unit is directly jumped to.

[0021] Preferably, the refresh checking unit performs EDAC error detection and correction on the data read by the refresh reading unit through the DEAC decoding unit, and specifically:

[0022] When error detection is correct or multi-bit error occurs in error detection, the multi-bit error data and the corresponding SRAM address are recorded in the register, and the refresh starting unit is jumped to, and the register is queried through the RISC-V processor unit to obtain the multi-bit error data and address information.

[0023] Preferably, the refresh checking unit performs EDAC error detection and correction on the data read by the refresh reading unit through the DEAC decoding unit, and specifically:

[0024] When the last checking is completed, when multi-bit error occurs in error detection, the multi-bit error data and the corresponding SRAM address are recorded in the register, and the refresh timing unit is jumped to.

[0025] The method for the SRAM refresh fault-tolerant structure of the RISC-V processor system provided in the application comprises the following steps:

[0026] The RISC-V processor unit accesses the processor access control unit and the SRAM unit to interact, and initiates data reading and writing access to the SRAM unit;

[0027] The processor access control unit generates a core_busy indication signal representing the processor state;

[0028] The refresh access control unit receives the core_busy indication signal and performs arbitration between the processor Load / Store operation and the SRAM refresh operation based on the core_busy indication signal;

[0029] When the core_busy indication signal indicates that the processor unit is performing a Load / Store operation, the refresh access control unit suspends or delays the SRAM refresh operation and prioritizes the processor Load / Store operation;

[0030] When the core_busy indication signal indicates that the processor unit is not performing a Load / Store operation, the refresh access control unit performs the SRAM refresh operation;

[0031] During the execution of the SRAM refresh operation, the refresh access control unit synchronously refreshes the data and EDAC check code stored in the SRAM unit.

[0032] Compared with the prior art, the present application has the following beneficial effects:

[0033] The present application provides an SRAM refresh fault-tolerant structure for a RISC-V processor system, mainly aiming at the Load (instruction fetch) / Store (write back) characteristics of the RISC-V processor, by time-sharing multiplexing the on-chip single-port SRAM, taking the principle that the processor access priority is the highest, using a variable-length timing refresh strategy, a variable target refresh address selection strategy and an EDAC error correction and detection algorithm, through an arbitration control mechanism, the target area of the on-chip SRAM is refreshed to realize fault-tolerant reinforcement. The core_busy indication generated by the processor access control unit is used, and the SRAM access arbitration mechanism is used to avoid the conflict between the processor instruction fetch / write back and the SRAM refresh (read / write). When the SRAM is idle, the on-chip single-port SRAM is time-shared to correct and detect errors of the data in the SRAM, and the corrected data is written back to improve the system fault-tolerant capability. From the structural design, the ability of the space processor system to resist single event upset and single event transient behavior is effectively improved, and the chip reliability is improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0035] Figure 1 The RISC-V processor system SRAM refresh fault-tolerant structure of the present application is shown in the figure.

[0036] Figure 2 SRAM refresh fault-tolerant structure and SRAM interconnection diagram.

[0037] Wherein: 100-RISC-V processor unit, 200-processor access control unit, 300-refresh access control unit, 400-SRAM unit, 201-instruction fetch unit, 202-EDAC decoding unit, 203-EDAC encoding unit, 204-write back unit, 301-refresh initiation unit, 302-refresh read unit, 303-refresh check unit 303, 304-refresh write unit, 305-refresh timing unit. DETAILED DESCRIPTION

[0038] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0039] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but only represents selected embodiments of the present application. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative labor are within the scope of protection of the present application.

[0040] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0041] In the description of the embodiments of the present application, it should be noted that if the terms "upper", "lower", "horizontal", "inner" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" and the like are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0042] In addition, if the term "horizontal" appears, it does not mean that the component must be absolutely horizontal, but can be slightly inclined. For example, "horizontal" only means that its direction is relatively more horizontal than "vertical", and does not mean that the structure must be completely horizontal, but can be slightly inclined.

[0043] In the description of the embodiments of the present invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in the present invention according to the specific circumstances.

[0044] The present invention will now be described in further detail with reference to the accompanying drawings:

[0045] This invention proposes an SRAM refresh fault-tolerant structure for RISC-V processor systems, which mainly implements data refresh of on-chip SRAM, such as... Figure 1 As shown, it includes a RISC-V processor unit 100, a processor access control unit 200, a refresh access control unit 300, and an SRAM unit 400;

[0046] The RISC-V processor unit 100 interacts with the processor access control unit 200 to implement the processor's Load (fetch) / Store (write-back) operations. The processor access control unit 200 interacts with the SRAM unit 400 to translate accesses initiated by the RISC-V processor unit 100, thereby initiating read and write accesses to the SRAM unit 400. Simultaneously, the processor access control unit 200 generates a core_busy instruction, and the refresh access control unit 300 uses the core_busy instruction to complete arbitration between the processor Load / Store and SRAM refresh. The refresh access control unit 300 is used to implement refresh control of the SRAM unit 400. The SRAM unit 400 is used to store data and EDAC checksums.

[0047] The processor access control unit 200 includes an instruction fetch unit 201, an EDAC decoding unit 202, an EDAC encoding unit 203, and a write-back unit 204. The instruction fetch unit 201 converts the processor load into SRAM read access control, enabling data to be read from the SRAM. The EDAC decoding unit 202 performs EDAC error detection and correction on the read data. When a single-bit error is detected, the erroneous bit is corrected, and the corrected data is rewritten to the original data address in the SRAM. The EDAC encoding unit 203 generates EDAC encoding for the write-back data and writes the data and EDAC encoding together to the target address in the SRAM. The write-back unit 204 converts the processor write-back into SRAM write access control, enabling data to be written to the SRAM.

[0048] The SRAM refresh fault-tolerant structure and SRAM interconnection method of the present invention are as follows: Figure 2 As shown, the interconnection relationship between the RISC-V processor, processor / refresh access control, and SRAM is illustrated. The processor access control 200 and the refresh access control 300 generate access address A[X:2], data D[31:0], EDAC checksum PARITY[7:0], chip select CEN, read enable OEN, data SRAM write enable WEN, and EDAC SRAM write enable WEN_E, which are interconnected with the data SRAM and EDAC SRAM of SRAM cell 400 according to the corresponding relationship. X in access address A[X:2] is an adjustable parameter, which depends on the SRAM capacity selected by the system, further improving the portability of the present invention.

[0049] The core_busy indication generated by the processor access control unit 200 adopts the SRAM access arbitration mechanism. When the core_busy indication is valid, the refresh access control unit 300 suspends its work. When the core_busy indication is invalid, the refresh access control unit 300 continues to work, realizing time-division multiplexing of the on-chip single-port SRAM.

[0050] The refresh access control unit 300 includes a refresh start unit 301, a refresh read unit 302, a refresh verification unit 303, a refresh write unit 304, and a refresh timing unit 305. The refresh start unit 301 is used to configure the refresh start and end addresses, configure refresh enable, and start the refresh function. The refresh read unit 302 is used to generate SRAM read access control to realize read data access to SRAM. The refresh verification unit 303 performs EDAC error detection and correction on the data read by the refresh read unit 302 through the DEAC decoding unit. The refresh write unit 304 is used to generate SRAM write access control to realize the rewriting of the data corrected by the refresh read unit 302 into the original data address of SRAM. After the writing is completed, it jumps to the refresh start unit 301 or jumps to the refresh timing unit 305 after the last write is completed. The refresh timing unit 305 times the interval between two refreshes according to the time parameters configured in the timing configuration. After the timing is completed, the next round of refresh is started to realize the cyclic automatic refresh function.

[0051] The refresh verification unit 303 performs EDAC error detection and correction on the data read by the refresh read unit 302 through the DEAC decoding unit, specifically as follows:

[0052] When the error detection occurs single-bit error, the error bit is corrected, and the jump is made to the refresh write unit 304; when the error detection is correct, the jump is directly made to the refresh timing unit 305; when the error detection is correct or the error detection occurs multi-bit error, the multi-bit error data and the corresponding SRAM address are recorded in the register, and the jump is made to the refresh starting unit 301, the register is queried by the RISC-V processor unit 100, and the multi-bit error data and address information are obtained; when the last check is completed, when the error detection occurs multi-bit error, the multi-bit error data and the corresponding SRAM address are recorded in the register, and the jump is made to the refresh timing unit 305.

[0053] The four units are described in detail as follows:

[0054] 1) The RISC-V processor unit 100 realizes the Load (fetching) / Store (writing back) operation of the processor, initiates the read / write access to the SRAM, and the RISC-V processor unit 100 realizes the Load (fetching) / Store (writing back) operation of the processor, initiates the read / write access to the SRAM;

[0055] 2) The processor access control unit 200 is used for converting the access initiated by the RISC-V processor unit 100 and EDAC encoding the access data, finally realizing the access to the SRAM unit 400. At the same time, the processor access control unit 200 generates a core_busy indication, and the refresh access control unit 300 uses the core_busy indication to complete the arbitration between the processor Load (fetching) / Store (writing back) and the SRAM refresh (read / write);

[0056] 3) The processor access control unit 200 includes: the fetch (read) unit 201 used for converting the processor Load (fetching) into the read access control of the SRAM, realizing the reading of the data from the SRAM. The EDAC decoding 202 unit is used for EDAC error detection and correction of the read data, when the error detection occurs single-bit error, the error bit is corrected, and the corrected data is written into the original data address of the SRAM. The EDAC encoding unit 203 is used for generating EDAC encoding of the write back data, and writing the data and the EDAC encoding into the target address of the SRAM. The write back (write) unit 204 is used for converting the processor write back (write) into the write access control of the SRAM, realizing the writing of the data into the SRAM;

[0057] 4) The refresh access control unit 300 employs a variable-duration timed refresh strategy and a variable target refresh address selection strategy to control the refresh of the SRAM. Using the core_busy instruction generated by the processor access control unit 200, an SRAM access arbitration mechanism is employed to avoid conflicts between processor instruction fetch / write-back and SRAM refresh (read / write). When the core_busy instruction is valid, the refresh access control unit 300 pauses operation; when the core_busy instruction becomes invalid, the refresh access control unit 300 resumes operation, achieving time-division multiplexing of the on-chip single-port SRAM.

[0058] 5) The refresh access control unit 300 includes: a refresh start unit 301 for configuring the refresh start and end addresses, configuring refresh enable, and starting the refresh function; a refresh read unit 302 for generating SRAM read access control to realize read data access to SRAM; and a refresh verification unit 303 for performing EDAC error detection and correction on the data read from unit 302 through the DEAC decoding unit. When a single-bit error is detected, the erroneous bit is corrected, and the process jumps to unit 304. When the error detection is correct or a multi-bit error is detected, the multi-bit erroneous data and the corresponding SRAM address are recorded in a register, and the process jumps to unit 301. The register can be queried through unit 100 to obtain the multi-bit erroneous data and address information. When the last verification is completed (i.e., at the end address), if a multi-bit error is detected, the multi-bit erroneous data and the corresponding SRAM address are recorded in a register, and the process jumps to unit 305. If the error detection is correct, the process jumps directly to unit 305. The refresh write unit 304 is used to control SRAM write access, enabling the data corrected in unit 302 to be rewritten to the original SRAM data address. After the write is completed, it jumps to unit 301 or to unit 305 after the last write is completed. The refresh timing unit 305 times the interval between two refreshes according to the time parameters configured in the timing configuration. After the timing is completed, the next round of refresh is started, realizing the cyclic automatic refresh function.

[0059] 6) SRAM cell 400 is an on-chip SRAM memory used to store data and EDAC checksum.

[0060] In summary, based on the SRAM refresh fault-tolerant structure of the RISC-V processor system, and by adopting the SRAM refresh fault-tolerant structure and SRAM interconnection method, the SRAM refresh fault-tolerant structure and method of this invention can be obtained.

[0061] This invention proposes a method for an SRAM refresh fault-tolerant structure for a RISC-V processor system, comprising the following steps:

[0062] The RISC-V processor unit 100 accesses the processor access control unit 200 to interact with the SRAM unit 400, and initiates data read / write access to the SRAM unit;

[0063] The processor access control unit 200 generates a core_busy indication signal representing the processor state;

[0064] The refresh access control unit 300 receives the core_busy indication signal, and performs arbitration between the processor Load / Store operation and the SRAM refresh operation based on the core_busy indication signal;

[0065] When the core_busy indication signal indicates that the processor unit is performing a Load / Store operation, the refresh access control unit 300 suspends or delays the SRAM refresh operation, and prioritizes the processor Load / Store operation;

[0066] When the core_busy indication signal indicates that the processor unit is not performing a Load / Store operation, the refresh access control unit 300 performs the SRAM refresh operation;

[0067] During the execution of the SRAM refresh operation, the refresh access control unit 300 synchronously refreshes the data and EDAC check code stored in the SRAM unit 400.

[0068] The application has been applied to a space anti-radiation MCU chip, which uses the SRAM refresh fault-tolerant structure and method in the application, and the irradiation test results show that the fault-tolerant capability of the chip is significantly improved. The application is applicable to in-chip SRAM refresh fault tolerance based on a RISC-V processor, and can be applied by simply changing the structure for other processor systems, providing a solution for reliability design of anti-radiation processor products, and having strong universality.

[0069] 1) The application is based on a RISC-V processor system, and a in-chip SRAM refresh control structure is designed, which can perform data error correction and detection on the SRAM through time-sharing multiplexing of the in-chip single-port SRAM when the SRAM is idle, and write back the corrected data, thereby improving the system fault tolerance.

[0070] 2) The application realizes an SRAM access arbitration mechanism, which takes the highest priority of processor access as the principle, and ensures the conflict avoidance between the processor Load (instruction fetch) / Store (write back) and the SRAM refresh (read / write), thereby improving the system security.

[0071] 3) The application adopts a timing refresh strategy with variable length, which can meet the requirement of refresh frequency in different application scenarios, and has strong versatility.

[0072] 4) The application adopts a variable target refresh address selection strategy, which realizes partial refresh of the SRAM target area by configuring the refresh start and end addresses, and has strong application flexibility.

[0073] The above is only the preferred embodiment of the present application, and is not used to limit the present application. For those skilled in the art, the present application can have various modifications and changes. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. An SRAM refresh fault tolerance structure for a RISC-V processor system, the SRAM refresh fault tolerance structure comprising: The RISC-V processor unit (100), the processor access control unit (200), the refresh access control unit (300) and the SRAM unit (400) are included; The RISC-V processor unit (100) and the processor access control unit (200) interact to realize the Load / Store operation of the processor; The processor access control unit (200) interacts with the SRAM unit (400) to convert the access initiated by the RISC-V processor unit (100) to initiate the read / write access to the SRAM unit (400); at the same time, the processor access control unit (200) generates a core_busy indication, and the refresh access control unit (300) uses the core_busy indication to complete the arbitration between the processor Load / Store and the SRAM refresh; The refresh access control unit (300) is used to realize the refresh control of the SRAM unit (400); The SRAM unit (400) is used to store data and EDAC check codes.

2. The SRAM refresh fault tolerance structure for RISC-V processor system of claim 1, wherein, The processor access control unit (200) includes a fetch unit (201), an EDAC decoding unit (202), an EDAC encoding unit (203) and a write-back unit (204); The fetch unit (201) converts the processor Load into the read access control of the SRAM to realize the reading of data from the SRAM; the EDAC decoding unit (202) performs EDAC error detection and correction on the read data, corrects the error bits when a single-bit error occurs, and rewrites the corrected data to the original data address of the SRAM; the EDAC encoding unit (203) generates EDAC encoding for the write-back data, and writes the data and the EDAC encoding to the target address of the SRAM; the write-back unit (204) converts the processor write-back into the write access control of the SRAM to realize the writing of data to the SRAM.

3. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 1, wherein, The processor access control (200) / the refresh access control (300) generates access address A[X:2], data D[31:0], EDAC check code PARITY[7:0], chip selection CEN, read enable OEN, data SRAM write enable WEN and EDAC SRAM write enable WEN_E, and the data SRAM and the EDAC SRAM of the SRAM unit (400) are interconnected according to the corresponding relationship.

4. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 3, wherein, X in the access address A[X:2] is an adjustable parameter, which is determined according to the SRAM capacity selected by the system.

5. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 1, wherein, The core_busy indication generated by the processor access control unit (200) adopts the SRAM access arbitration mechanism; when the core_busy indication is valid, the refresh access control unit (300) suspends work; when the core_busy indication is invalid, the refresh access control unit (300) continues to work, realizing the time-sharing multiplexing of the single-port SRAM in the chip.

6. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 1, wherein, The refresh access control unit (300) comprises a refresh starting unit (301), a refresh reading unit (302), a refresh checking unit (303), a refresh writing unit (304) and a refresh timing unit (305); The refresh starting unit (301) is configured to configure refresh starting and ending addresses, configure refresh enabling, and start a refresh function; the refresh reading unit (302) is configured to generate control of SRAM read access and realize read data access to the SRAM; the refresh checking unit (303) is configured to perform EDAC error detection and correction on data read by the refresh reading unit (302) through a DEAC decoding unit; the refresh writing unit (304) is configured to generate control of SRAM write access and realize re-writing of corrected data of the refresh reading unit (302) into original data addresses of the SRAM, and after the writing is completed, jump to the refresh starting unit (301) or jump to the refresh timing unit (305) after the last write is completed; and the refresh timing unit (305) is configured to time interval time between two refreshes according to time parameters configured by timing, and after the timing is completed, start the next round of refresh to realize a cyclic automatic refresh function.

7. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 6, wherein, The refresh checking unit (303) performs EDAC error detection and correction on data read by the refresh reading unit (302) through a DEAC decoding unit, and specifically: When single-bit error detection occurs, correct the error bit and jump to the refresh writing unit (304); when the error detection is correct, directly jump to the refresh timing unit (305).

8. The SRAM refresh fault tolerance structure for RISC-V processor system of claim 6, wherein, The refresh checking unit (303) performs EDAC error detection and correction on data read by the refresh reading unit (302) through a DEAC decoding unit, and specifically: When the error detection is correct or multiple-bit error detection occurs, record the multiple-bit error data and the corresponding SRAM address in a register, and jump to the refresh starting unit (301), and query the register through the RISC-V processor unit (100) to obtain the multiple-bit error data and address information.

9. The SRAM refresh fault tolerance structure for RISC-V processor systems of claim 6, wherein, The refresh checking unit (303) performs EDAC error detection and correction on data read by the refresh reading unit (302) through a DEAC decoding unit, and specifically: When the last checking is completed, when multiple-bit error detection occurs, record the multiple-bit error data and the corresponding SRAM address in a register, and jump to the refresh timing unit (305).

10. The method for SRAM refresh fault tolerance structure for RISC-V processor system as claimed in any one of claims 1 to 9, wherein, The method comprises the following steps: The RISC-V processor unit (100) accesses the processor access control unit (200) and interacts with the SRAM unit (400) to initiate data read / write access to the SRAM unit; The processor access control unit (200) generates a core_busy indication signal representing a processor state; The refresh access control unit (300) receives the core_busy indication signal and performs arbitration between processor Load / Store operations and SRAM refresh operations based on the core_busy indication signal; When the core_busy indication signal indicates that the processor unit is performing Load / Store operations, the refresh access control unit (300) suspends or delays the SRAM refresh operation, and gives priority to the processor Load / Store operations; When the core_busy indication signal indicates that the processor unit is not performing Load / Store operations, the refresh access control unit (300) performs the SRAM refresh operation; During the execution of the SRAM refresh operation, the refresh access control unit (300) synchronously refreshes the data and EDAC check code stored in the SRAM unit (400).

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