Method for removing liner oxide layer
By combining chemical gas dry etching and DHF wet etching processes, the problem of step height difference caused by DHF etching was solved, achieving efficient removal of the pad oxide layer and improving device quality.
Patent Information
- Application Number
- CN202511066208.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-07
AI Technical Summary
In the existing technology, the DHF chemical etching process for removing the pad oxide layer has a high selectivity for different regions, resulting in a large difference in step height between the NMOS and PMOS regions, which affects device quality.
A combination of a first chemical gas dry etching process and a second DHF wet etching process is adopted. First, the chemical gas dry etching process removes part of the pad oxide layer, reducing the workload of the subsequent DHF wet etching process. The etching rate difference in different areas is adjusted to ensure that the step height difference is within a controllable range.
This effectively reduces the difference in oxide layer height between NMOS and PMOS regions, ensuring that the device quality and defect quantity meet requirements, and improving the effect of pad oxide layer removal.
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Figure CN120914098A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to a semiconductor integrated circuit manufacturing method, and in particular to a method for removing a pad oxide layer. BACKGROUND
[0002] In the prior art, after ion implantation (IMP) in a well (WELL) loop is completed, the pad oxide layer (Oxide) needs to be removed, and then a new oxide layer is grown as a gate oxide. The newly grown gate oxide is usually a thick (Thick) Gate Oxide, which can ensure the quality and thickness of the Gate Oxide. In the prior art, the pad oxide layer is removed by DHF etching.
[0003] Problems of the prior art:
[0004] The DHF chemical etching has a high selectivity to different regions when removing silicon oxide, which causes differences in the step height of different device regions. This is mainly due to the difference in doping elements between the NMOS and PMOS regions in the WELL loop, which causes the HARP Oxide properties of the surface shallow trench isolation to be different. Figures 1A-1C As shown in FIG. 1, a device structure in each step of the prior art method for removing the pad oxide layer is shown. The prior art method for removing the pad oxide layer includes the following steps:
[0005] As shown in FIG. 1, a device structure in each step of the prior art method for removing the pad oxide layer is shown. The prior art method for removing the pad oxide layer includes the following steps: Figure 1A As shown in FIG. 1, a device structure in each step of the prior art method for removing the pad oxide layer is shown. The prior art method for removing the pad oxide layer includes the following steps:
[0006] The shallow trench isolation 104 is formed in a shallow trench 102. Usually, an inner liner oxide layer 103 is also formed on the inner side surface of the shallow trench 102.
[0007] The semiconductor substrate 101 includes a silicon substrate.
[0008] The oxide layer of the shallow trench isolation 104 is grown by a HARP process.
[0009] The injection ions of the well injection process pass through the pad oxide layer 105; the well injection process includes N well injection process and P well injection process, the N well injection process forms N well in the first region 101a and also injects N type impurity in the shallow trench isolation 104 in the first region 101a, the P well injection process forms P well in the second region 101b and also injects P type impurity in the shallow trench isolation 104 in the second region 101b.
[0010] The first region 101a is the forming region of PMOS and the second region 101b is the forming region of NMOS. Figure 1A In the embodiment, the first region 101a and the second region 101b are located on two sides of the line AA respectively.
[0011] As shown in the figure, the etching process of the pad oxide layer 105 is removed by using DHF wet etching process. Figure 1B
[0012] Because the doped impurities in the shallow trench isolation 104 of the first region 101a and the second region 101b are different, the etching rate of the shallow trench isolation 104 of the first region 101a and the second region 101b by DHF wet etching is different, namely the etching loading is different, so the etching of the shallow trench isolation 104 of the first region 101a and the second region 101b has higher selectivity. Thus, after the DHF wet etching process is completed, the top surface of the shallow trench isolation 104 of the first region 101a and the second region 101b has larger height difference.
[0013] As shown in the figure, the first gate oxide layer 106 is formed on the surface of the semiconductor substrate 101. Figure 1C SUMMARY
[0014] The technical problem to be solved by the present application is to provide a pad oxide layer removing method, which can reduce the etching rate difference between the oxide layers with different doping, so as to ensure good removal of the oxide layer and make the height difference of the oxide layer of the shallow trench isolation in each region meet the requirements.
[0015] To solve the above technical problem, the pad oxide layer removing method provided by the present application includes the following steps:
[0016] A semiconductor substrate with shallow trench isolation is provided, a pad oxide layer is formed on the surface of the semiconductor substrate and a well implantation process is completed on the semiconductor substrate; the top surface of the shallow trench isolation is higher than the top surface of the pad oxide layer; the implantation ions of the well implantation process pass through the pad oxide layer; the well implantation process includes an N well implantation process and a P well implantation process, the N well implantation process forms an N well in a first region and N type impurities are also implanted in the shallow trench isolation in the first region, and the P well implantation process forms a P well in a second region and P type impurities are also implanted in the shallow trench isolation in the second region.
[0017] An etching process for removing the pad oxide layer is performed, including:
[0018] A first chemical gas dry etching process is performed to remove a partial thickness of the pad oxide layer, and the first chemical gas dry etching also causes loss of the oxide layer of the shallow trench isolation.
[0019] A second DHF wet etching process is performed to remove the remaining pad oxide layer; the etching rate difference of the oxide layer of the shallow trench isolation in the first region and the second region in the second DHF wet etching process is greater than the etching rate difference of the oxide layer of the shallow trench isolation in the first region and the second region in the first chemical gas dry etching process, and the etching rate difference of the oxide layer of the shallow trench isolation in the first region and the second region in the first chemical gas dry etching process is adjustable, so as to reduce the step difference of the top surface of the shallow trench isolation between the first region and the second region by the first chemical gas dry etching process.
[0020] Further improvement is that the semiconductor substrate includes a silicon substrate.
[0021] Further improvement is that the oxide layer of the shallow trench isolation is formed by a HARP process.
[0022] Further improvement is that the process gas of the first chemical gas dry etching process includes HF gas and NH3 gas.
[0023] Further improvement is that the first chemical gas dry etching process is implemented by a Certas etching machine.
[0024] Further improvement is that the thickness of the pad oxide layer is 4 nm to 15 nm; the total amount of etching of the oxide layer by the first chemical gas dry etching process and the second DHF wet etching process is greater than or equal to the thickness of the pad oxide layer.
[0025] Further improvement is that the etching time of the second DHF wet etching process is required to ensure the number of defects to meet the requirements.
[0026] Further improvement is that the etching time of the second DHF wet etching process is 60s-90s.
[0027] Further improvement is that the etching time of the first chemical gas dry etching process is required to ensure that the height difference of the oxide layer of the shallow trench isolation between the first region and the second region after the second DHF wet etching process is completed is less than the first required value.
[0028] Further improvement is that the first required value is 1nm.
[0029] Further improvement is that the etching time of the first chemical gas dry etching process is 20s-30s.
[0030] Further improvement is that the vacuum pressure of the first chemical gas dry etching process is 30mtorr.
[0031] Further improvement is that after removing the pad oxide layer, further comprising:
[0032] Forming a first gate oxide layer on the surface of the semiconductor substrate.
[0033] Further improvement is that the first region is the formation region of PMOS and the second region is the formation region of NMOS.
[0034] Further improvement is that before the first chemical gas dry etching process is performed, an annealing process for the N well and the P well is also completed.
[0035] In the present application, the first chemical gas dry etching process and the second DHF wet etching process are combined to remove the pad oxide layer. The etching rate of the pad oxide layer in different regions can be adjusted by the first chemical gas dry etching process, so that the etching rate difference of the pad oxide layer in different regions is small. The first chemical dry etching process is added before the second DHF wet etching process to remove part of the pad oxide layer. Therefore, the thickness of the pad oxide layer to be removed by the second DHF wet etching process is reduced, so that the height difference of the shallow trench isolation oxide layer in the first and second regions caused by the second DHF wet etching process can be reduced. At the same time, the second DHF wet etching process can ensure good cleaning of the surface of the semiconductor substrate, so that the number of defects can meet the requirements while the pad oxide layer is removed. Therefore, the present application can reduce the etching rate difference between the oxide layers with different doping, so that the height difference of the shallow trench isolation oxide layer in each region can meet the requirements while the oxide layer is removed and the number of defects meets the requirements. BRIEF DESCRIPTION OF DRAWINGS
[0036] The present application will be further described in detail below in combination with the drawings and specific embodiments:
[0037] Figures 1A-1C is a device structure schematic diagram in each step of the removal method of the existing pad oxide layer;
[0038] Figure 2 is a flowchart of the removal method of the pad oxide layer in the embodiment of the present application;
[0039] Figures 3A-3C is a device structure schematic diagram in each step of the removal method of the pad oxide layer in the embodiment of the present application. DETAILED DESCRIPTION
[0040] As shown in Figure 2 , it is a flowchart of the removal method of the pad oxide layer 205 in the embodiment of the present application; as shown in Figures 3A-3C , it is a device structure schematic diagram in each step of the removal method of the pad oxide layer 205 in the embodiment of the present application; the removal method of the pad oxide layer 205 in the embodiment of the present application comprises the following steps:
[0041] Step S101, as shown in Figure 3A , a semiconductor substrate 201 formed with a shallow trench isolation 204 is provided, a pad oxide layer 205 is formed on the surface of the semiconductor substrate 201, and a well implantation process is completed on the semiconductor substrate 201; the top surface of the shallow trench isolation 204 is higher than the top surface of the pad oxide layer 205.
[0042] The shallow trench isolation 204 is formed in the shallow trench 202. Generally, a liner oxide layer 203 is also formed on the inner side surface of the shallow trench 202.
[0043] In some embodiments, the semiconductor substrate 201 comprises a silicon substrate.
[0044] The oxide layer of the shallow trench isolation 204 is formed by a HARP process.
[0045] The implantation ions of the well implantation process pass through the liner oxide layer 205; the well implantation process comprises an N well implantation process and a P well implantation process, the N well implantation process forms an N well in the first region 201a and also implants N type impurities in the shallow trench isolation 204 in the first region 201a, and the P well implantation process forms a P well in the second region 201b and also implants P type impurities in the shallow trench isolation 204 in the second region 201b.
[0046] In some embodiments, the thickness of the liner oxide layer 205 is 4-15 nm.
[0047] In the embodiments of the present application, the first region 201a is a forming region of PMOS, and the second region 201b is a forming region of NMOS. Figure 3A In some embodiments, the first region 201a and the second region 201b are respectively located on the two sides of the line AA.
[0048] Further, the input / output (IO) device and the core device can be integrated on the semiconductor substrate 201 simultaneously. In the forming region of the IO device, the PMOS in the first region 201a is an IO PMOS, and the NMOS in the second region 201b is an IO NMOS. In the forming region of the core device, the PMOS in the first region 201a is a core PMOS, and the NMOS in the second region 201b is a core NMOS.
[0049] In the embodiments of the present application, an annealing process of the N well and the P well is also completed before the subsequent first chemical gas dry etching process.
[0050] Step S102, as shown in Figure 3B The etching process for removing the liner oxide layer 205 is performed, which comprises:
[0051] Step S102a, a first chemical gas dry etching process is performed to remove part of the thickness of the liner oxide layer 205, and the first chemical gas dry etching also causes loss of the oxide layer of the shallow trench isolation 204.
[0052] The first chemical gas dry etching process includes HF gas and NH3 gas.
[0053] Preferably, the first chemical gas dry etching process is implemented by a Certas etching machine. Generally, chemical gas dry etching implemented by a Certas etching machine is also called Certa etching.
[0054] In some embodiments, the etching time of the first chemical gas dry etching process is 20-30 seconds.
[0055] The vacuum pressure of the first chemical gas dry etching process is 30 mtorr.
[0056] In step S102b, a second DHF wet etching process is performed to remove the remaining pad oxide layer 205. The etching rate difference of the oxide layer of the shallow trench isolation 204 in the first region 201a and the second region 201b in the second DHF wet etching process is greater than the etching rate difference of the oxide layer of the shallow trench isolation 204 in the first region 201a and the second region 201b in the first chemical gas dry etching process, and the etching rate difference of the oxide layer of the shallow trench isolation 204 in the first region 201a and the second region 201b in the first chemical gas dry etching process is adjustable, so that the step difference of the top surface of the shallow trench isolation 204 between the first region 201a and the second region 201b is reduced by the first chemical gas dry etching process.
[0057] In the embodiments of the present application, the total etching amount of the oxide layer by the first chemical gas dry etching process and the second DHF wet etching process is greater than or equal to the thickness of the pad oxide layer 205.
[0058] The etching time of the second DHF wet etching process is required to ensure that the number of defects meets the requirements. In some embodiments, the etching time of the second DHF wet etching process is 60-90 seconds. That is, if only the first chemical gas dry etching process is used and the second DHF wet etching process is omitted, the problem of increased number of defects is likely to occur. Through experiments, it is found that when the second DHF wet etching process is 60-90 seconds, the embodiments of the present application can control the number of defects below the corresponding benchmark of the number of defects of the existing method.
[0059] In this embodiment of the invention, the etching time of the first chemical gas dry etching process is required to ensure that the height difference of the oxide layer of the shallow trench isolation 204 between the first region 201a and the second region 201b is less than a first required value after the second DHF wet etching process is completed. That is, compared with existing methods, in this embodiment of the invention, by employing the first chemical gas dry etching process, most of the thickness of the pad oxide layer 205 can be removed. Thus, the second DHF wet etching process only needs to meet the defect count requirement; this greatly reduces the time of the second DHF wet etching process, thereby significantly reducing the height difference of the shallow trench isolation 204 caused by different etching loads (i.e., different etching rates) in different regions during the second DHF wet etching process. Since the etching load of the first chemical gas dry etching process is adjustable for different regions, the height difference of the shallow trench isolation 204 in different regions can be minimized after the first chemical gas dry etching process is completed. Finally, after the first chemical gas dry etching process and the second DHF wet etching process are completed, the difference in oxide layer height between different regions of the shallow trench isolation 204 is less than the first required value.
[0060] In some embodiments, the first requirement value is 1 nm.
[0061] like Figure 3C As shown, in this embodiment of the invention, after removing the gasket oxide layer 205, the method further includes:
[0062] A first gate oxide layer 206 is formed on the surface of the semiconductor substrate 201. In some embodiments, the first gate oxide layer 206 is typically a thick gate oxide layer.
[0063] Next, the gate formation process is carried out.
[0064] Since the height difference of the shallow trench isolation 204 in each region is small after the gasket oxide layer 205 is removed in the embodiments of the present invention, the thickness and quality of the first gate oxide layer 206 can be well guaranteed.
[0065] In the embodiment of the present application, the first chemical gas dry etching process and the second DHF wet etching process are combined to remove the pad oxide layer 205. The etching rate of the first chemical gas dry etching process for different regions of different types of oxide layers, such as doped types, is adjustable, so that the etching rate difference of the oxide layers in different regions is small. The present application adds the first chemical dry etching process to remove part of the pad oxide layer 205 before the second DHF wet etching process. Thus, the thickness of the pad oxide layer 205 to be removed by the second DHF wet etching process is reduced, and the height difference of the oxide layer of the shallow trench isolation 204 in the first and second regions 201b caused by the second DHF wet etching process, i.e. the step difference, can be reduced. At the same time, the second DHF wet etching process can ensure good cleaning of the surface of the semiconductor substrate 201, so that the number of defects can meet the requirements while the pad oxide layer 205 is removed. Therefore, the embodiment of the present application can reduce the etching rate difference between the oxide layers with different doping, so that the height difference of the oxide layer of the shallow trench isolation 204 in each region can meet the requirements while the oxide layer is well removed and the number of defects meets the requirements.
[0066] The above has been described in detail through specific embodiments, but these do not constitute a limitation on the present application. Those skilled in the art can also make many modifications and improvements without departing from the principles of the present application, and these should also be considered as falling within the scope of protection of the present application.
Claims
1. A method for removing a pad oxide layer, characterized by, The method comprises the steps of: providing a semiconductor substrate formed with shallow trench isolation, forming a liner oxide layer on the surface of the semiconductor substrate and completing a well implantation process on the semiconductor substrate; the top surface of the shallow trench isolation is higher than the top surface of the liner oxide layer; the implantation ions of the well implantation process pass through the liner oxide layer; the well implantation process comprises an N well implantation process and a P well implantation process, the N well implantation process forms an N well in a first region and N type impurities are also implanted in the shallow trench isolation in the first region, and the P well implantation process forms a P well in a second region and P type impurities are also implanted in the shallow trench isolation in the second region; an etching process for removing the liner oxide layer is performed, comprising: a first chemical gas dry etching process is performed to remove part of the thickness of the liner oxide layer, and the first chemical gas dry etching also causes loss of the oxide layer of the shallow trench isolation; a second DHF wet etching process is performed to remove the remaining liner oxide layer; the etching rate difference of the oxide layer of the shallow trench isolation in the first region and the second region in the second DHF wet etching process is greater than that in the first chemical gas dry etching process, and the etching rate difference of the oxide layer of the shallow trench isolation in the first region and the second region in the first chemical gas dry etching process is adjustable, so as to reduce the step difference of the top surface of the shallow trench isolation between the first region and the second region by the first chemical gas dry etching process.
2. The method of claim 1, wherein: The semiconductor substrate comprises a silicon substrate.
3. The method of claim 2, wherein: The oxide layer of the shallow trench isolation is formed by a HARP process.
4. The method of claim 1, wherein: The process gas of the first chemical gas dry etching process comprises HF gas and NH3 gas.
5. The method of claim 4, wherein: The first chemical gas dry etching process is implemented by a Certas etching machine.
6. The method of claim 5, wherein: The thickness of the liner oxide layer is 4-15 nm; the total etching amount of the oxide layer by the first chemical gas dry etching process and the second DHF wet etching process is greater than or equal to the thickness of the liner oxide layer.
7. The method of claim 5, wherein: The etching time of the second DHF wet etching process is required to ensure that the number of defects meets the requirements.
8. The method of claim 7, wherein: The etching time of the second DHF wet etching process is 60-90 s.
9. The method of claim 5, wherein: The etching time of the first chemical gas dry etching process is required to ensure that the height difference of the oxide layer of the shallow trench isolation between the first region and the second region after the completion of the second DHF wet etching process is less than a first required value.
10. The method of claim 9, wherein: The first required value is 1 nm.
11. The method of claim 9, wherein: The etching time of the first chemical gas dry etching process is 20-30 s.
12. The method of claim 11, wherein: The vacuum pressure of the first chemical gas dry etching process is 30 mtorr.
13. The method of claim 1, wherein: After removing the liner oxide layer, the method further comprises: forming a first gate oxide layer on the surface of the semiconductor substrate.
14. The method of claim 1, wherein: The first region is a forming region of PMOS, and the second region is a forming region of NMOS.
15. The method of claim 1, wherein: Before the first chemical gas dry etching process is performed, an annealing process is also completed on the N well and the P well.