Power supply control circuit and chip

Abstract

According to the power supply control circuit and the chip provided by the invention, the dynamic latch is additionally arranged at the preceding stage of the comparator, the size of internal power supply voltage output by a power supply system is rapidly detected by utilizing the characteristic that the power consumption (at nA stage) of the dynamic latch is far lower than the power consumption (at muA stage) of the comparator, and the comparator is enabled or disabled to work according to a detection result, so that the power supply control circuit is realized. Especially when the voltage of the internal power supply is relatively high, the comparator is not turned on, so that the power consumption is further reduced, and the requirement of a product with lower standby power consumption can be met.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of integrated circuit technology, and in particular to a power control circuit and a chip. BACKGROUND

[0002] Low-Power design is particularly important in the field of information technology and electronic devices, which can significantly prolong the use time of the device. A conventional low-power design scheme in the prior art is to make the device or chip enter a standby mode (also known as "low-power mode") when the device or chip is not in use, thereby reducing the device power consumption to a very low running state. In the standby mode, the device or chip enters a sleep state, but still maintains the normal operation of part of the functions (such as clock or wake-up mechanism).

[0003] In order to reduce the standby power consumption of the device or chip, the standby power consumption of the power supply system of the device or chip can be reduced, and the following scheme is generally adopted: the power supply system is set to operate in an intermittent mode, that is, the power supply system operates for a period of time and is turned off for a period of time. During the period when the power supply system is turned off, the internal power supply voltage is provided to the internal circuit by the internal capacitor, thereby reducing the standby power consumption. However, during this period, the internal power supply voltage will decrease due to leakage, and therefore the power supply system is started to operate after a period of time to restore the internal power supply voltage to the target potential.

[0004] The above scheme generally uses a voltage detection circuit with a comparator to detect the change of the internal power supply voltage to determine whether to start the power supply system to operate. This scheme is simple and easy to implement, but the comparator will continuously operate and generate power consumption, which is difficult to meet the product demand for lower standby power consumption. SUMMARY

[0005] The purpose of the present application is to provide a power control circuit and a chip, which can detect the internal power supply voltage output by the power supply system more frequently at a lower power consumption, and realize more stable internal power supply voltage.

[0006] To achieve the above purpose, the present application provides a power control circuit for providing an internal power supply voltage to a chip, comprising a dynamic latch and a comparator coupled in sequence, the power consumption of the comparator when working is greater than the power consumption of the dynamic latch when working, and: The dynamic latch is coupled to a corresponding power supply system and is periodically enabled after the power supply system enters an intermittent operation mode, and detects whether the internal power supply voltage output by the power supply system is lower than a corresponding reference voltage after being enabled. If yes, the comparator is enabled, and if no, the comparator is disabled. The comparator is configured to compare the internal power supply voltage and the reference voltage in size after being enabled, and enable the power supply system to work when the internal power supply voltage is lower than the reference voltage, until the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage.

[0007] Optionally, the power supply control circuit further comprises a disable-enabling logic circuit coupled between the dynamic latch and the comparator, and configured to provide the output of the dynamic latch to the comparator after being delayed when the internal power supply voltage is lower than the reference voltage, so as to delay enabling the comparator, and after the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage, the disable-enabling logic circuit disables the comparator and / or resets the dynamic latch according to the output of the comparator which is flipped.

[0008] Optionally, the disable-enabling logic circuit comprises: a first delay logic circuit having an input end coupled to the output end of the dynamic latch and configured to perform delay logic processing on the output of the dynamic latch; a second delay logic circuit having an input end coupled to the output end of the comparator and configured to perform delay logic processing on the output of the comparator; wherein the delay time of the first delay logic circuit on the output of the dynamic latch is longer than the delay time of the second delay logic circuit on the output of the comparator.

[0009] Optionally, the disable-enabling logic circuit further comprises: a NAND logic circuit having a first input end coupled to the output end of the first delay logic circuit and a second input end coupled to the output end of the second delay logic circuit, and configured to perform NAND logic operation on the output of the first delay logic circuit and the output of the second delay logic circuit; a flip-flop having a first input end coupled to the output end of the NAND logic circuit and a second input end coupled to the output end of the first delay logic circuit, and configured to enable or disable the comparator according to the output of the NAND logic circuit and the output of the first delay logic circuit.

[0010] Optionally, the first delay logic circuit comprises a first inverter, a second inverter, a first NAND gate and a first delay circuit, the input end of the first inverter is coupled to the output end of the dynamic latch, the output end of the first inverter is coupled to the input end of the second inverter and the input end of the first delay circuit, the output end of the second inverter is coupled to the first input end of the first NAND gate, the output end of the first delay circuit is coupled to the second input end of the first NAND gate, and the output end of the first NAND gate is coupled to the first input end of the NAND logic circuit. And / or, the second delay logic circuit comprises a third inverter, a fourth inverter, a fifth inverter, a second NAND gate and a second delay circuit, an input end of the third inverter is coupled to an output end of the comparator, an output end of the third inverter is coupled to an input end of the fourth inverter and an input end of the second delay circuit, an output end of the fourth inverter is coupled to a first input end of the second NAND gate, an output end of the second delay circuit is coupled to a second input end of the second NAND gate, an output end of the second NAND gate is coupled to an input end of the fifth inverter, an output end of the fifth inverter is coupled to a second input end of the non-logic circuit.

[0011] Optionally, the dynamic latch comprises a first input transistor, a second input transistor and a pair of back-to-back cascaded inverters, a drain of the first input transistor is coupled to the reference voltage, a drain of the second input transistor is coupled to the internal supply voltage, a gate of the first input transistor and a gate of the second input transistor are both coupled to an inverted signal of a corresponding periodic enable signal, a source of the first input transistor and a source of the second input transistor are both coupled to the back-to-back cascaded inverters.

[0012] Optionally, the dynamic latch further comprises at least one of the following (1)~(4): (1) a tail transistor, a drain of the tail transistor is coupled to the back-to-back cascaded inverters, a source of the tail transistor is grounded, a gate of the tail transistor is coupled to the periodic enable signal; (2) a switch transistor, a drain of the switch transistor is coupled to the back-to-back cascaded inverters, a source of the switch transistor is coupled to a power supply, a gate of the switch transistor is coupled to an inverted signal of the periodic enable signal; (3) a first buffer, an input end of the first buffer is coupled to the back-to-back cascaded inverters and the source of the first input transistor; (4) a second buffer, an input end of the second buffer is coupled to the back-to-back cascaded inverters and the source of the second input transistor, an output end of the second buffer is coupled to an enable end of the comparator.

[0013] Optionally, the second buffer comprises a zeroth inverter and an OR gate, an input end of the zeroth inverter is coupled to the periodic enable signal, an output end of the zeroth inverter is coupled to a first input end of the OR gate, a second input end of the OR gate is coupled to the back-to-back cascaded inverters, an output end of the OR gate is coupled to the comparator.

[0014] Optionally, the power supply system has a power switch transistor, a gate of the power switch transistor is coupled to an output end of the comparator, a drain of the power switch transistor is coupled to or outputs the internal supply voltage; Alternatively, the power supply system comprises a linear voltage regulator, an enable terminal of the linear voltage regulator being coupled to an output terminal of the comparator, and an output terminal of the linear voltage regulator being coupled to or outputting the internal power supply voltage; Alternatively, the power supply system comprises a charge pump, a control terminal of the charge pump being coupled to an output terminal of the comparator, and an output terminal of the charge pump being coupled to or outputting the internal power supply voltage; Alternatively, the power supply system comprises a DC-DC converter, a control terminal of the DC-DC converter being coupled to an output terminal of the comparator, and an output terminal of the DC-DC converter being coupled to or outputting the internal power supply voltage.

[0015] Optionally, the power supply control circuit further comprises a pulse generator, the pulse generator being coupled to the dynamic latch and being configured to generate a periodic enable signal to periodically enable the dynamic latch.

[0016] Optionally, the power supply control circuit further comprises an oscillator, the oscillator being coupled to the pulse generator and being configured to provide a corresponding frequency signal to the pulse generator; the pulse generator is configured to count the frequency signal, and generate a pulse and restart counting each time the counting reaches a set value, to generate the periodic enable signal.

[0017] Optionally, the pulse generator and the oscillator are enabled when the power supply system enters the intermittent operation mode.

[0018] Based on the same inventive concept, the present application further provides a chip comprising a power supply system, a power consumption circuit coupled to an output terminal of the power supply system to receive an internal power supply voltage, and a power supply control circuit as described in the present application, and when the chip receives a low-power-consumption-mode-entering instruction and part or all of the devices in the power consumption circuit enter a corresponding low-power-consumption mode, the power supply system enters an intermittent operation mode.

[0019] Optionally, the chip is a memory chip, and the low-power-consumption mode is a semi-sleep mode, a deep sleep mode or a hybrid sleep mode of the memory chip.

[0020] Compared with the prior art, the technical scheme of the present application adds a dynamic latch in front of the comparator, and utilizes the feature that the power consumption of the dynamic latch (nA level) is much lower than the power consumption of the comparator (μA level) to quickly detect the size of the internal power supply voltage output by the power supply system, and enable or disable the operation of the comparator according to the detection result, especially when the internal power supply voltage is relatively high, the comparator is not turned on, and the power consumption is further reduced. BRIEF DESCRIPTION OF DRAWINGS

[0021] Those skilled in the art will understand that the drawings provided herein are for illustrative purposes and are not intended to limit the scope of the present application. Among other things, Figure 1 is a schematic diagram of an architecture of a voltage detection circuit with a comparator.

[0022] Figure 2 is a schematic diagram of an architecture of a power control circuit according to an embodiment of the present application.

[0023] Figure 3 is Figure 1 and Figure 2 is a schematic diagram of a comparison of signal timing in the circuits shown in

[0024] Figure 4 is a schematic diagram of an application example of a power control circuit according to an embodiment of the present application.

[0025] Figure 5 is a schematic diagram of another application example of a power control circuit according to an embodiment of the present application.

[0026] Figure 6 is a schematic diagram of yet another application example of a power control circuit according to an embodiment of the present application.

[0027] Figure 7 is a schematic diagram of still another application example of a power control circuit according to an embodiment of the present application.

[0028] Figure 8 is a schematic diagram of an example structure of a dynamic latch in a power control circuit according to an embodiment of the present application.

[0029] Figure 9 is a schematic diagram of another example structure of a dynamic latch in a power control circuit according to an embodiment of the present application.

[0030] Figure 10 is a schematic diagram of an example structure of a comparator in a power control circuit according to an embodiment of the present application.

[0031] Figure 11 is a schematic diagram of an architecture of a power control circuit according to another embodiment of the present application.

[0032] Figure 12 is Figure 11 is a schematic diagram of an example structure of an enable disable logic circuit in a power control circuit.

[0033] Figure 13 is Figure 11 is a schematic diagram of signal timing in a power control circuit.

[0034] Figure 14 is a schematic diagram of an architecture of a chip according to an embodiment of the present application. DETAILED DESCRIPTION

[0035] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon embodiments presented herein. Contrarily, the present embodiments are presented by way of example to enable a full and complete disclosure of the present application. Throughout the specification, like reference numerals will be used to denote like elements every where the use of "including", "containing", "having" and "involving" and variations thereof are intended to be equivalent and permit for items to be added to the described items without departing from the scope of the application. The terms "comprising", "comprise" and "when comprising" specify the presence of stated features, steps or components but do not preclude the presence or addition of one or more other features, steps, components, elements, or groups thereof. As used herein the term "and / or" includes any and all combinations of associated items.

[0036] Reference is made to Figure 1 A voltage detection circuit with a comparator generally consists of an oscillator 10, a pulse generator 11, and a comparator 12 coupled in sequence.

[0037] The oscillator 10 generates an internal frequency signal f, and the pulse generator 11 counts the internal frequency signal f and generates a pulse as an enable signal EN1 every time a set value is reached, to enable the comparator 12 to detect the state of the internal power supply voltage V int output by the power supply system 13. The comparator 12 has two functions: ① comparing the internal power supply voltage V int with a reference voltage Vref, and ② enabling or disabling the power supply system 13.

[0038] Reference is made to Figure 1 and Figure 3The system (or chip) in which the voltage detection circuit and the power supply system 13 are located will enter a low-power mode (the internal power consumption circuit is silent) after receiving a corresponding low-power entry instruction, and will generate a low-power mode signal PDEN (also referred to as "pulling high" or "enabling" PDEN), and then the power supply system 13 will enter a discontinuous operation mode. In the initial stage, the power supply system 13 is temporarily turned off. In further embodiments, the oscillator 10 and the pulse generator 11 in the voltage detection circuit will also start to work according to the low-power mode signal PDEN. In other embodiments, the oscillator 10 and the pulse generator 11 in the voltage detection circuit can always work without the low-power mode signal PDEN enabling the work. When the pulse generator 11 periodically generates a pulse EN1, the comparator enabling signal EN1 is generated based on the EN1 signal and in combination with the required comparator working state to enable the comparator 12. After the comparator 12 is enabled, the internal power supply voltage V_int and the reference voltage Vref are compared. If V_int < Vref, it indicates that V_int is pulled below Vref by the internal leakage of the system, and the output of the comparator 12 is valid (for example, low level) to enable the power supply system 13 to work, and V_int is charged to Vref or above Vref. If V_int > Vref, the output of the comparator 12 is invalid (for example, EN2 changes from low level to high level), and the power supply system 13 remains closed and silent.

[0039] The disadvantage of the voltage detection circuit is that when V_int is high, the comparator 12 will still work at a relatively high frequency, but the power supply system 13 does not need to charge V_int, which will generate additional power consumption and make it difficult to further reduce the system power consumption.

[0040] Based on this, the technical scheme of the present application increases a dynamic latch in front of the comparator, uses the feature that the power consumption of the dynamic latch (nA level) is much lower than the power consumption of the comparator (μA level), quickly detects the size of the internal power supply voltage output by the power supply system, and enables or disables the comparator according to the detection result. When the internal power supply voltage is relatively high, the comparator is not turned on, thereby further reducing the power consumption.

[0041] The technical scheme of the present application will be described in detail below with reference to the accompanying drawings. Figures 2 to 14

[0042] Please refer to Figure 2 ​An embodiment of the present application provides a power control circuit for providing internal power voltage V_int for a chip, which comprises a dynamic latch 14 and a comparator 12 coupled in sequence. The dynamic latch 14 is coupled with a corresponding power system 13 and is enabled periodically after the power system 13 enters a discontinuous working mode, and detects whether the internal power voltage V_int output by the power system 13 is lower than a corresponding reference voltage Vref after being enabled. If yes, the comparator 12 is enabled, and if no, the comparator 12 is disabled. The comparator 12 is used to compare the internal power voltage V_int and the reference voltage Vref in size after being enabled, so as to enable the power system 13 to work (i.e. the power system 13 is started and charges V_int) when the internal power voltage V_int is lower than the reference voltage Vref (i.e. V_int < Vref), until the power system 13 pulls up the internal power voltage V_int to be equal to or higher than the reference voltage Vref.

[0043] The dynamic latch 14 has the characteristics of small power consumption (e.g. nA level), high precision and fast response, and only enables the comparator 12 when V_int < Vref, and then the comparator 12 enables the power system 13 to charge V_int. After V_int meets the standard (i.e. V_int ≥ Vref), the output EN4 of the comparator 12 is reversed, and the power system 13 is disabled (i.e. the power system 13 is turned off), thereby Figure 1 compared with the voltage detection circuit shown in the prior art, the comparator 12 is not enabled when the internal power voltage V_int ≥ Vref, thereby reducing the power consumption of the comparator 12 during this period (the power consumption of the comparator 12 is generally in the order of μA), and the power consumption can be greatly saved.

[0044] It should be understood that in the present application, the power system 13 can enter the discontinuous working mode due to any suitable reason such as the system entering the low-power mode (i.e. the power system 13 can work for a period of time and be turned off for a period of time), and the power control circuit can enable the dynamic latch 14 periodically in any suitable manner after the power system 13 enters the discontinuous working mode. Moreover, the power system 13, the dynamic latch 14 and the comparator 12 can be implemented by any suitable circuit design respectively.

[0045] In an example, referring to Figure 2 The power control circuit further comprises a pulse generator 11, which is a front-stage circuit of the dynamic latch 14, and is coupled with the dynamic latch 14 and used to generate a periodic enable signal EN (the EN can be the same as the enable signal EN of the dynamic latch 14). Figure 1(The same as EN1 in the original text) to periodically enable dynamic latch 14.

[0046] Alternatively, please refer to Figure 2 The power control circuit also includes an oscillator 10, which is a pre-amplifier of the pulse generator 11. The output of the oscillator 10 is coupled to the input of the pulse generator 11 and provides a corresponding frequency signal f to the pulse generator 11. This frequency signal f is the internal timing unit of the power control circuit. The pulse generator 11 counts the period of the frequency signal f, and generates a pulse each time the count reaches a set value and restarts the counting to generate a periodic enable signal EN. When EN is high, the dynamic latch 14 is enabled; when EN is low, the dynamic latch 14 is disabled.

[0047] Please combine Figure 2 and Figure 3 , Figure 14 In one example, the power control circuit and the system (or chip) containing power system 13 enter a low-power mode after receiving the corresponding low-power entry command Standby. The power-consuming circuit 2 within this system enters a silent state (i.e., a state with very low power consumption) and generates a low-power mode signal PDEN (e.g., PDEN "pull high" or "enable") to provide to power system 13. This low-power mode signal PDEN can cause power system 13 to enter an intermittent operating mode, temporarily shutting it down. The specific timing sequence of the power control circuit in this example is as follows: Oscillator 10 and pulse generator 11 operate. Oscillator 10 outputs a frequency signal f, and pulse generator 11 counts the frequency signal f output by oscillator 10. Each time the count of the frequency signal f output by oscillator 10 by pulse generator 11 reaches a set value, a pulse is generated, and the counting restarts. Thus, pulse generator 11 can generate a periodic enable signal EN according to the frequency signal f to periodically enable dynamic latch 14. In one embodiment, the low-power mode signal PDEN is provided not only to the power system 13, but also to the oscillator 10 and pulse generator 11 in the power control circuit. Therefore, the low-power mode signal PDEN can not only enable the power system 13 to enter the intermittent operation mode, but also enable pulse generator 11 and oscillator 10 to start working. That is to say, when the power system 13 is controlled by PDEN to enter the intermittent operation mode, pulse generator 11 and oscillator 10 are also synchronously enabled by PDEN. At this time, the chip is in low-power mode, and pulse generator 11 and oscillator 10 continue to work in the low-power mode of the chip. In another embodiment, the pulse generator 11 and the oscillator 10 may also be uncoupled from the PDEN, thereby operating continuously in both the normal operating mode and the low power mode of the chip.

[0048] The dynamic latch 14 is periodically enabled by the periodic enable signal EN output by the pulse generator 11, and only when V_int < Vref is detected, the valid enable signal EN3 (for example, EN3 changes from low to high) is output, thereby enabling the comparator 12; When the comparator 12 compares V_int < Vref after being enabled, the valid enable signal EN4 (for example, EN4 changes from high to low) is output, thereby enabling the power supply system 13 to charge V_int until V_int ≥ Vref, and EN4 flips to disable the power supply system 13, so that the power supply system 13 is turned off.

[0049] Comparison Figure 3 It can be found that EN3 is low during V_int ≥ Vref, so that the comparator 12 does not work, and EN1 flips multiple times during V_int ≥ Vref, so that the comparator 12 works intermittently. Therefore, the technical solution of the present example can save the power consumption of the comparator 12 during V_int ≥ Vref.

[0050] In an example, please refer to Figure 4 The power supply system 13 has a power switch tube Power mos, the gate of the power switch tube Power mos is coupled to the output end of the comparator 12, the drain of the power switch tube Power mos outputs the internal power supply voltage V_int, and the source is coupled to the corresponding power supply vdd. When the comparator 12 compares V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, which turns on the power switch tube Power mos, and the power supply vdd charges V_int.

[0051] In an example, please refer to Figure 5 The power supply system 13 includes a linear voltage regulator LDO, the enable end of the linear voltage regulator LDO is coupled to the output end of the comparator 12, and the output end of the linear voltage regulator LDO outputs the internal power supply voltage V_int. When the comparator 12 compares V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, which enables the linear voltage regulator LDO to work, and the linear voltage regulator LDO charges V_int.

[0052] In an example, please refer to Figure 6 The power supply system 13 includes a DC converter (i.e. Figure 6The control terminal of the DC-DC converter is coupled to the output terminal of the comparator 12, and the output terminal of the DC-DC converter outputs the internal power supply voltage V_int. When the comparator 12 compares V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, enabling the DC-DC converter to work, and the DC-DC converter charges V_int.

[0053] In an example, referring to Figure 7 The control terminal of the charge pump is coupled to the output terminal of the comparator 12, and the output terminal of the charge pump outputs the internal power supply voltage V_int. When the comparator 12 compares V_int < Vref, the enable signal EN4 output by the comparator 12 is valid, enabling the charge pump to work, and the charge pump charges V_int.

[0054] In an example, referring to Figure 8 The dynamic latch 14 includes a first input transistor N3, a second input transistor N4, and a pair of back-to-back cascade inverters including PMOS transistors P1 and P2 and NMOS transistors N1 and N2.

[0055] P1 and N1 constitute one of the inverters in the back-to-back cascade inverters, P2 and N2 constitute the other inverter in the back-to-back cascade inverters, the drain of P1, the drain of N1, the gate of P2, the gate of N2, and the source of N3 are coupled to each other and form an output node a of the back-to-back cascade inverters, the drain of P2, the drain of N2, the gate of P1, the gate of N1, and the source of N4 are coupled to each other and form an output node b of the back-to-back cascade inverters, the source of P1 and the source of P2 are coupled, and the source of N1 and the source of N2 are coupled. The drain of N3 is coupled to the reference voltage Vref, the drain of N4 is coupled to the internal power supply voltage V_int, and the gate of N3 and the gate of N4 are both coupled to the inverted signal ENB of the periodic enable signal EN.

[0056] Optionally, the dynamic latch 14 further includes at least one of the following (1)~(4): (1) a tail current transistor N0, the drain of N0 is coupled to the source of N1 and the source of N2, the source of N0 is grounded, and the gate of N0 is coupled to the periodic enable signal EN.

[0057] (2) a switch transistor P0, the drain of P0 is coupled to the source of P1 and the source of P2, the source of P0 is coupled to the power supply vdd, and the gate of P0 is coupled to the inverted signal ENB of the periodic enable signal EN.

[0058] (3) a first buffer bufferl, an input of the first buffer bufferl is coupled to the output node a of the back-to-back cascaded inverters, and an output of the first buffer bufferl is Out-. The first buffer bufferl can buffer the signal of the output node a, reduce the internal mismatch of the dynamic latch 14, and improve the performance of the dynamic latch 14.

[0059] (4) a second buffer buffer2, an input of the second buffer buffer2 is coupled to the output node b of the back-to-back cascaded inverters, and an output of the second buffer buffer2 is Out+ for outputting an enable signal EN3 and coupled to the enable end of the comparator 12. The second buffer buffer2 can buffer the signal of the output node b, reduce the internal mismatch of the dynamic latch 14, and improve the performance of the dynamic latch 14.

[0060] The first buffer bufferl and the second buffer buffer2 can be implemented by any suitable circuit design. For example, please refer to Figure 9 The second buffer buffer2 includes a zeroth inverter INV0 and an OR gate OR0, an input of the zeroth inverter INV0 is coupled to the periodic enable signal EN, an output of the zeroth inverter INV0 is coupled to a first input of the OR gate OR0, a second input of the OR gate OR0 is coupled to the output node b of the back-to-back cascaded inverters, and an output of the OR gate OR0 is the output of the second buffer buffer2 and coupled to the enable end of the comparator 12.

[0061] In an example, please refer to Figure 10 The comparator 12 includes a tail current bias circuit 121, a differential input circuit 122, and a load circuit 123. The differential input circuit 122 is used to input and compare V_int and Vref. The tail current bias circuit 121 is coupled to the dynamic latch 14 and the differential input circuit 122, and provides a tail current to the differential input circuit 122 after being enabled by the dynamic latch 14. The load circuit 123 is coupled to the differential input circuit 122, and is used to convert and output the output of the differential input circuit 122. The tail current bias circuit 121, the differential input circuit 122, and the load circuit 123 can be implemented by any suitable circuit design.

[0062] For example, the tail current bias circuit 121 includes tail current transistors T3 and T4 in series. The gate of the tail current transistor T3 is coupled to the output of the dynamic latch 14, the source of the tail current transistor T3 is coupled to the drain of the tail current transistor T4, the drain of the tail current transistor T3 is coupled to the differential input circuit 122, and the tail current transistor T3 is turned on or off under the control of the enable signal EN3 outputted by the dynamic latch 14. The gate of the tail current transistor T4 is coupled to the bias signal bias, the source of the tail current transistor T4 is grounded, and the tail current transistor T4 converts the bias signal bias into a tail current and provides the tail current to the differential input circuit 122 when the tail current transistor T3 is turned on. Both T3 and T4 can be NMOS.

[0063] For another example, the differential input circuit 122 includes differential input pair transistors T1 and T2. Both T1 and T2 can be PMOS, and the gate of T1 is coupled to the reference voltage Vref. The gate of T2 is coupled to the output of the power system 13 to receive the internal power voltage V_int outputted by the power system 13. The drain of T1 and the drain of T2 are coupled to the drain of T3, and the source of T1 and the source of T2 are both coupled to the load circuit 123.

[0064] For still another example, the load circuit 123 includes a cross-coupled pair of transistors Q3 and Q4, a current mirror circuit, and a buffer buffer3. The current mirror circuit includes switching transistors Q1, Q2, Q6, Q5, T5-T8, Q1-Q6 can be PMOS, and T5-T8 can be NMOS. The gate of Q1, the drain and gate of Q2, the drain of Q3, and the gate of Q4 are coupled to each other and to the differential input circuit 122 (e.g., the source of T1). The gate of Q6, the drain and gate of Q5, the drain of Q4, and the gate of Q3 are coupled to each other and to the differential input circuit 122 (e.g., the source of T2). The sources of Q1-Q6 are all coupled to the power supply vdd. The drain of Q1 is coupled to the drain and gate of T5 and the gate of T7, the source of T5 is coupled to the drain and gate of T6 and the gate of T8, the sources of T6 and T8 are both grounded, the drain of T8 is coupled to the source of T7, the drain of T7 is coupled to the drain of Q6 and the input of the buffer buffer3, and the output of the buffer buffer3 is coupled to the control or enable end of the power system 13.

[0065] Please refer to Figure 11 Another embodiment of the present application also provides a power control circuit, which is used in a power system and includes a dynamic latch, a differential input circuit, a tail current bias circuit, and a load circuit. Figure 2Based on the embodiment shown, a disable-enabling logic circuit 15 is further added, which is coupled between the dynamic latch 14 and the comparator 12, and is used to delay the output of the dynamic latch 14 and provide it to the comparator 12 when the internal power supply voltage V_int output by the power supply system 13 is lower than the reference voltage Vref, so as to delay the enablement of the comparator 12, and after the power supply system 13 pulls up the internal power supply voltage V_int to be equal to or higher than the reference voltage Vref, disable the comparator 12 according to the output DISEN of the comparator 12 (which is the inverted EN4, indicating that the power supply is in place), so as to turn off the charging activity of the power supply system 13 to V_int this time, and prepare for the next detection of V_int.

[0066] The disable-enabling logic circuit 15 can be implemented by any suitable circuit design.

[0067] Please refer to Figure 12 In an example, the disable-enabling logic circuit 15 includes a first delay logic circuit 151 and a second delay logic circuit 152. In another example, the disable-enabling logic circuit 15 includes the first delay logic circuit 151, the second delay logic circuit 152, a NAND logic circuit NAND0 and a flip-flop 153.

[0068] The input end of the first delay logic circuit 151 is coupled to the output end Out+ of the dynamic latch 14, so as to access the enablement signal EN3 output by the dynamic latch 14 and perform delay logic processing on the enablement signal EN3.

[0069] The input end of the second delay logic circuit 152 is coupled to the output end of the comparator 12, so as to access the output DISEN of the comparator 12 (i.e. the inverted enablement signal EN4 output by the comparator 12) and perform delay logic processing on the output DISEN.

[0070] The delay time of the first delay logic circuit 151 on the output EN3 of the dynamic latch 14 is longer than the delay time of the second delay logic circuit 152 on the output DISEN of the comparator 12, so as to ensure the establishment of the comparator 12 and avoid the problem that the comparator 12 may be turned off during the establishment of the comparator 12.

[0071] One input end of the NAND logic circuit NAND0 is coupled to the output end of the first delay logic circuit 151, and the other input end is coupled to the output end of the second delay logic circuit 152, and is used to perform NAND logic operation on the output of the first delay logic circuit 151 and the output of the second delay logic circuit 152.

[0072] An input of the flip-flop 153 is coupled to an output of the NAND0 logic circuit, and another input is coupled to an output of the first delay logic circuit 151, and is used to enable or disable the comparator 12 according to the output of the NAND0 logic circuit and the output of the first delay logic circuit 151.

[0073] Figure 13 The timing diagram of the power control circuit of this embodiment is shown in FIG. 4. Please refer to the timing diagram of the power control circuit of this embodiment shown in FIG. 4, which is described as follows: Figure 9 Figure 12 Figure 13 The timing diagram of the power control circuit of this embodiment is shown in FIG. 4. Please refer to the timing diagram of the power control circuit of this embodiment shown in FIG. 4, which is described as follows: When the enable signal EN changes from low to high, the dynamic latch 14 is enabled by the EN, and starts to detect whether V_int is less than Vref; When the dynamic latch 14 detects that V_int < Vref, the EN3 output by the dynamic latch 14 changes from low to high; The first delay logic circuit 151 delays the EN3 by Delay1, and outputs the delayed enable signal EN3' through the NAND0 logic circuit and the flip-flop 153; The comparator 12 is enabled when the EN3' changes from low to high (i.e. enabled by the rising edge of the EN3'), and outputs the valid enable signal EN4 to enable the power system 13 to charge V_int; After V_int reaches the target potential (which can be any suitable value greater than or equal to Vref, at which time the power system 13 charges V_int to the target potential), the output EN4 of the comparator 12 flips (at this time, the output EN4 of the comparator 12 is denoted as DISEN); The second delay logic circuit 152 delays the DISEN (i.e. the flipped EN4) by Delay2 (wherein Delay2 < Delay1), and provides the input of the comparator 12 through the NAND0 logic circuit and the flip-flop 153 to pull the EN3' low (i.e. from high to low), thereby disabling the comparator 12.

[0074] The first delay logic circuit 151, the second delay logic circuit 152, the NAND0 logic circuit and the flip-flop 153 can all be designed with any suitable specific circuit.

[0075] As an example, please refer to Figure 12 ​​The first delay logic circuit 151 comprises a first inverter INV1, a second inverter INV2, a first NAND gate NAND1 and a first delay circuit (for the sake of understanding, its delay is marked as Delay1), the input of the first inverter INV1 is coupled to the output Out+ of the dynamic latch 14, the output of the first inverter INV1 is coupled to the input of the second inverter INV2 and the input of the first delay circuit Delay1, the output of the second inverter INV2 is coupled to the first input of the first NAND gate NAND1, the output of the first delay circuit Delay1 is coupled to the second input of the first NAND gate NAND1, the output of the first NAND gate NAND1 is coupled to the first input of the NAND0 logic circuit.

[0076] As an example, refer to Figure 12 The second delay logic circuit 152 comprises a third inverter INV3, a fourth inverter INV4, a fifth inverter INV5, a second NAND gate NAND2 and a second delay circuit (for the sake of understanding, its delay is marked as Delay2), the input of the third inverter INV3 is coupled to the output of the comparator 12, the output of the third inverter INV3 is coupled to the input of the fourth inverter INV4 and the input of the second delay circuit Delay2, the output of the fourth inverter INV4 is coupled to the first input of the second NAND gate NAND2, the output of the second delay circuit Delay2 is coupled to the second input of the second NAND gate NAND2, the output of the second NAND gate NAND2 is coupled to the input of the fifth inverter INV5, the output of the fifth inverter INV5 is coupled to the second input of the NAND0 logic circuit.

[0077] As an example, refer to Figure 12 The flip-flop 153 comprises a third NAND gate NAND3 and a fourth NAND gate NAND4, the first input of the third NAND gate NAND3 is coupled to the output of the NAND0 logic circuit, the second input of the third NAND gate NAND3 is coupled to the output of the fourth NAND gate NAND4 and the enable end of the comparator 12, the output of the third NAND gate NAND3 is coupled to the first input of the fourth NAND gate NAND4, the second input of the fourth NAND gate NAND4 is coupled to the output of the first delay logic circuit 151.

[0078] In an example, the EN3' can be further provided to the reset end of the dynamic latch 14, when the EN3' changes from high to low, the dynamic latch 14 can be reset by the falling edge of the EN3', so as to prepare for the next detection of V_int.

[0079] In another example, a NOR logic circuit (not shown) can be added between the pulse generator 11 and the dynamic latch 14, an input of the NOR logic circuit is coupled with the DISEN (i.e. the inverted EN4), another input of the NOR logic circuit is coupled with the EN output by the pulse generator 11, and the output of the NOR logic circuit is coupled with the dynamic latch 14, thereby the DISEN (i.e. the inverted EN4) is further provided to the dynamic latch 14, and the dynamic latch 14 is reset by the inverted EN4 (i.e. the DISEN) when the power system 13 is charged to the position (i.e. the EN4 is changed from high to low), so as to be ready for the next detection of the V_int. In this example, the falling edge of the EN3' can be aligned with the reset time of the dynamic latch 14.

[0080] It should be understood that the dynamic latch 14 can also be reset in other suitable manners, which are not limited in the present application.

[0081] The power control circuit of the present application can be applied in a chip inside any suitable electronic device such as a mobile phone, a smart voice device, a GPS receiver, a wearable device, etc., so as to reduce the power consumption of the electronic device.

[0082] Based on this, please refer to Figure 14 , an embodiment of the present application further provides a chip, which comprises a power system 13, a power consumption circuit 2 coupled with the output of the power system 13, and a power control circuit 1 (which can be designed in the embodiment structure shown in Figure 2 or Figure 11 ) as described in the present application, and when the chip receives a corresponding low-power entry instruction Standby, the chip enters a low-power mode, part or all of the devices in the power consumption circuit 2 (which can include the internal control logic of the chip) inside the chip enter a silent state (i.e. a state with very small power consumption), and generate a low-power mode signal PDEN, so that the power system 13 enters an intermittent working mode.

[0083] Optionally, the chip is a memory chip such as a PSRAM (Pseudo Static Random Access Memory) chip or a DRAM dynamic random memory chip or a Flash memory chip, which, when receiving a low-power entry instruction Standby (such as a half-sleep mode entry command, a hybrid sleep entry command, a deep power-down (DPD) entry command, which can be sent to the memory chip by a corresponding memory control module), after the read / write operation is completed, will enter a low-power (Standby) mode according to the low-power entry instruction, and make most of the internal circuits (such as the power-consuming circuit 2) enter a silent state to reduce unnecessary power consumption and increase the use time of the electronic device using the memory chip. The low-power mode can be a half-sleep mode (half sleep mode, a kind of low-power mode in which part of the power supply is turned off) of the memory chip, or a hybrid sleep mode, or a deep sleep (deep power down) mode (which has lower power consumption than the half-sleep mode), and when most of the circuits of the memory chip (such as the power-consuming circuit 2) enter the low-power mode, the low-power mode signal PDEN is enabled to the power supply system 13.

[0084] In summary, the power control circuit of the present application adds a dynamic latch in the front stage of the comparator, which has the characteristics that the power consumption of the dynamic latch (nA level) is much lower than that of the comparator (μA level), and can quickly detect the size of the internal power supply voltage output by the power supply system, and enable or disable the operation of the comparator according to the detection result. Especially when the internal power supply voltage is relatively high, the comparator can be kept off, thereby further reducing the power consumption, and the method is simple and easy to implement. The chip of the present application can achieve lower standby power consumption by using the power control circuit of the present application.

[0085] The above description is only a description of the preferred embodiments of the present application, and does not limit the scope of the present application. Any modification or modification made by a person skilled in the art based on the above disclosure is within the protection scope of the technical solution of the present application.

Claims

1. A power control circuit for providing an internal power supply voltage to a chip, characterized by The power consumption of the comparator in operation is greater than the power consumption of the dynamic latch in operation, and The dynamic latch is coupled to a corresponding power supply system and is periodically enabled after the power supply system enters a discontinuous operation mode, and detects whether the internal power supply voltage output by the power supply system is lower than a corresponding reference voltage after being enabled, and if so, enables the comparator, and if not, disables the comparator; The comparator is used to compare the sizes of the internal power supply voltage and the reference voltage after being enabled, to enable the power supply system to operate when the internal power supply voltage is lower than the reference voltage, until the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage.

2. The power control circuit of claim 1, wherein, The power control circuit further includes a disable logic circuit coupled between the dynamic latch and the comparator, and used to provide the output of the dynamic latch to the comparator after being delayed when the internal power supply voltage is lower than the reference voltage, to delay the enablement of the comparator, and after the power supply system pulls up the internal power supply voltage to be equal to or higher than the reference voltage, the disable logic circuit disables the comparator and / or resets the dynamic latch according to the output of the comparator that has flipped.

3. The power control circuit of claim 2, wherein, The disable logic circuit includes: a first delay logic circuit, the input end of which is coupled to the output end of the dynamic latch, and used to perform delay logic processing on the output of the dynamic latch; a second delay logic circuit, the input end of which is coupled to the output end of the comparator, and used to perform delay logic processing on the output of the comparator; The delay time of the first delay logic circuit on the output of the dynamic latch is longer than the delay time of the second delay logic circuit on the output of the comparator.

4. The power control circuit of claim 3, wherein, The disable logic circuit further includes: a NAND logic circuit, one input end of which is coupled to the output end of the first delay logic circuit, and the other input end of which is coupled to the output end of the second delay logic circuit, and used to perform NAND logic operation on the output of the first delay logic circuit and the output of the second delay logic circuit; a flip-flop, one input end of which is coupled to the output end of the NAND logic circuit, and the other input end of which is coupled to the output end of the first delay logic circuit, and used to enable or disable the comparator according to the output of the NAND logic circuit and the output of the first delay logic circuit.

5. The power control circuit of claim 4, wherein, The first delay logic circuit includes a first inverter, a second inverter, a first NAND gate and a first delay circuit, the input end of the first inverter is coupled to the output end of the dynamic latch, the output end of the first inverter is coupled to the input end of the second inverter and the input end of the first delay circuit, the output end of the second inverter is coupled to the first input end of the first NAND gate, the output end of the first delay circuit is coupled to the second input end of the first NAND gate, and the output end of the first NAND gate is coupled to the first input end of the NAND logic circuit. And / or, the second delay logic circuit comprises a third inverter, a fourth inverter, a fifth inverter, a second NAND gate and a second delay circuit, the input end of the third inverter is coupled to the output end of the comparator, the output end of the third inverter is coupled to the input end of the fourth inverter and the input end of the second delay circuit, the output end of the fourth inverter is coupled to the first input end of the second NAND gate, the output end of the second delay circuit is coupled to the second input end of the second NAND gate, the output end of the second NAND gate is coupled to the input end of the fifth inverter, and the output end of the fifth inverter is coupled to the second input end of the non-logic circuit.

6. The power control circuit of claim 1, wherein, The dynamic latch comprises a first input tube, a second input tube and a pair of back-to-back cascade inverters, the drain of the first input tube is coupled to the reference voltage, the drain of the second input tube is coupled to the internal power supply voltage, the gate of the first input tube and the gate of the second input tube are both coupled to the inverted signal of the corresponding periodic enable signal, and the source of the first input tube and the source of the second input tube are both coupled to the back-to-back cascade inverters.

7. The power control circuit of claim 6, wherein, The dynamic latch further comprises at least one of the following (1)~(4): (1) a tail current tube, the drain of the tail current tube is coupled to the back-to-back cascade inverters, the source of the tail current tube is grounded, and the gate of the tail current tube is coupled to the periodic enable signal; (2) a switch tube, the drain of the switch tube is coupled to the back-to-back cascade inverters, the source of the switch tube is coupled to the power supply, and the gate of the switch tube is coupled to the inverted signal of the periodic enable signal; (3) a first buffer, the input end of the first buffer is coupled to the back-to-back cascade inverters and the source of the first input tube; (4) a second buffer, the input end of the second buffer is coupled to the back-to-back cascade inverters and the source of the second input tube, and the output end of the second buffer is coupled to the enable end of the comparator.

8. The power control circuit of claim 7, wherein, The second buffer comprises a zeroth inverter and an OR gate, the input end of the zeroth inverter is coupled to the periodic enable signal, the output end of the zeroth inverter is coupled to the first input end of the OR gate, the second input end of the OR gate is coupled to the back-to-back cascade inverters, and the output end of the OR gate is coupled to the comparator.

9. The power control circuit of claim 1, wherein, The power supply system has a power switch tube, the gate of the power switch tube is coupled to the output end of the comparator, and the drain of the power switch tube outputs or is coupled to the internal power supply voltage; Or, the power supply system comprises a linear voltage regulator, the enable end of the linear voltage regulator is coupled to the output end of the comparator, and the output end of the linear voltage regulator outputs or is coupled to the internal power supply voltage; Or, the power supply system comprises a charge pump, the control end of the charge pump is coupled to the output end of the comparator, and the output end of the charge pump is coupled to or outputs the internal power supply voltage; Or, the power supply system comprises a DC converter, the control end of the DC converter is coupled to the output end of the comparator, and the output end of the DC converter is coupled to or outputs the internal power supply voltage.

10. The power control circuit of any one of claims 1-9, wherein, The power supply control circuit further comprises a pulse generator coupled to the dynamic latch and configured to generate a periodic enable signal to periodically enable the dynamic latch.

11. The power control circuit of claim 10, wherein, The power supply control circuit further comprises an oscillator coupled to the pulse generator and configured to provide a corresponding frequency signal to the pulse generator; the pulse generator is configured to count the frequency signal and generate a pulse and restart counting each time the count reaches a set value to generate the periodic enable signal.

12. The power control circuit of claim 11, wherein, The pulse generator and the oscillator are enabled when the power supply system enters the intermittent operation mode.

13. A chip, characterized by The chip is a memory chip, and the low-power consumption mode is a semi-sleep mode, a deep sleep mode, or a hybrid sleep mode of the memory chip.

14. The chip of claim 13, wherein, The chip is a memory chip, and the low-power consumption mode is a semi-sleep mode, a deep sleep mode, or a hybrid sleep mode of the memory chip.

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