Inversion system with symmetrical clamping structure and inversion control method

Abstract

The invention relates to the technical field of inverters, in particular to an inverter system with a symmetrical clamping structure and an inverter control method. The central path loop controls a capacitor charging and discharging path and provides direct current to multi-level alternating current conversion, and the control driving loop comprises a sampling receiving module and an adjusting output module; the sampling receiving module obtains a signal according to the central path loop, and provides adjustable current and voltage values to the adjusting output module; the adjusting output module receives the signal, provides error adjustment and generates a current given value; and comparing, adjusting and generating a modulation signal, and outputting a seven-level sine wave. According to the voltage and current double closed loop and SPWM control, a complex dynamic voltage balance algorithm is not needed, the complexity and development difficulty of control logic are reduced, an extra booster circuit or an independent direct-current power supply is not needed, three-time voltage gain can be achieved, the waveform of the output voltage is closer to sine waves, dependence on a filter is reduced, and the power consumption is reduced. The multi-level inverter is superior to a traditional multi-level inverter in the aspects of cost, performance, control complexity, expansibility and the like.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of inverters, and in particular to an inverter system with symmetrical clamping structure and an inverter control method. BACKGROUND

[0002] The mainstream technology in the current energy storage inverter field includes multi-level topology structures such as cascaded H-bridge (CHB), neutral point clamped (NPC) and flying capacitor (FC), which realize voltage boosting and harmonic suppression through multi-stage series connection, diode clamping or capacitor balancing. However, these traditional schemes have significant shortcomings.

[0003] The above traditional schemes require a large number of switching devices, clamping diodes and capacitors, for example, a seven-level NPC inverter requires 12 switches, 6 diodes and 6 capacitors, resulting in a large system size, high cost, and complex drive circuit and control logic; secondly, the voltage gain of the traditional topology is generally low (usually ≤1.5 times), if high-voltage output is required, it depends on multi-stage voltage boosting circuit or independent DC power supply, which not only reduces the efficiency, but also limits the applicability of high-voltage scenarios; in addition, NPC and FC technologies require complex dynamic voltage balancing control algorithms, which require high controller performance and are prone to voltage fluctuation problems when the load changes suddenly.

[0004] Therefore, there is a need for an inverter system with symmetrical clamping structure and an inverter control method that can effectively optimize the topology structure and capacitor series superposition strategy, achieve 3 times voltage gain, use voltage and current double closed loop control and sinusoidal pulse width modulation (SPWM), output seven-level waveform with low harmonic content and close to sine wave, and significantly improve the economy, scalability and engineering applicability without complex control algorithm to meet the existing environmental needs. SUMMARY

[0005] The purpose of this section is to summarize some aspects of the embodiments of the present application and briefly introduce some preferred embodiments. Some simplifications or omissions may be made in this section and the abstract and title of the specification to avoid obscuring the purpose of this section, abstract and title, and such simplifications or omissions cannot be used to limit the scope of the present application.

[0006] In view of the above prior art, the system of the traditional scheme has a large size, high cost, and complex drive circuit and control logic, depends on multi-stage voltage boosting circuit or independent DC power supply, has low efficiency, poor applicability in high-voltage scenarios, high requirements for controller performance, and is prone to voltage fluctuation problems when the load changes suddenly.

[0007] Therefore, the technical problem to be solved by the present application is to design a symmetric clamping structure inverter system and an inverter control method capable of effectively optimizing the topology and the capacitor series superposition strategy, reducing the number and cost of components, and outputting a seven-level waveform with low harmonic content and close to a sine wave, without the need for a complex control algorithm to meet the needs of the existing environment.

[0008] To solve the above technical problems, the present application provides the following technical solutions: a symmetric clamping structure inverter system, comprising,

[0009] A central path loop controls the charging and discharging path of the capacitor, provides direct current to the multi-level alternating current conversion, and the signal enters the control driving loop;

[0010] The control driving loop includes a sampling receiving module and an adjustment output module;

[0011] The sampling receiving module obtains signals from the central path loop and provides adjustable current and voltage values to the adjustment output module;

[0012] The adjustment output module receives the sampling receiving module signal to provide error adjustment and generates a current set value; compares the adjustment to generate a modulation signal and outputs a seven-level sine wave.

[0013] As an improvement of the present application,

[0014] The central path loop includes a charging and discharging control module, a filter module, and a switch switching group;

[0015] The charging and discharging control module is provided with a clamping capacitor group and a diode group, both of which are in series superposition, and the charging and discharging control module is connected to the switch switching group at both ends;

[0016] One end of the filter module is connected to the switch switching group, and the other end is connected to the voltage output end;

[0017] The sampling receiving module includes a current sampling unit and a voltage sampling unit;

[0018] The adjustment output module includes a current regulator, a voltage regulator, and an SPWM modulation unit;

[0019] The voltage sampling unit is connected to the voltage regulator, and the output end of the voltage regulator is connected to the current regulator;

[0020] The current regulator generates a modulation signal to enter the SPWM modulation unit for conversion.

[0021] An inverter control method, comprising,

[0022] The sampling conditioning, the control driving loop detects the output voltage Vo and the sampling current;

[0023] Error adjustment, Vo is compared with reference value (Vref), and the given value of current is generated by voltage regulator adjustment; and then compared with sampling current, and the modulation signal is generated by proportional adjustment;

[0024] SPWM generation, the modulation signal is converted into 8-way PWM, and the switch switching group is driven to switch on and off, and seven modes are generated, and a seven-level sine wave is output.

[0025] As an improvement of the present application,

[0026] In the SPWM generation mode 1 process,

[0027] S3, S6 and S7 in the switch switching group are turned on, D1, D2 and D3 in the charge and discharge control module are turned on, and the remaining switches and diodes are turned off;

[0028] The DC input voltage source Vin charges C1, C2 and C3 in the charge and discharge control module;

[0029] The sum of the voltages of C1 and C2 in series is Vin, the voltage of C3 is Vin, and the output voltage Vo=0;

[0030] The output voltage Vo corresponds to the signal finally passing through the SPWM modulation unit, which is used for generating mode 2.

[0031] As an improvement of the present application,

[0032] In the SPWM generation mode 2 process,

[0033] S2, S3, S5 and S8 in the switch switching group are turned on, D1 and D4 in the charge and discharge control module are turned on, and the remaining switches and diodes are turned off;

[0034] The DC input voltage source Vin charges C1 and C4 in the charge and discharge control module;

[0035] The voltage of C1 is Vin, the voltage of C4 is Vin, and the output voltage Vo=Vin;

[0036] The output voltage Vo corresponds to the signal finally passing through the SPWM modulation unit, which is used for generating mode 3.

[0037] As an improvement of the present application,

[0038] In the SPWM generation mode 3 process,

[0039] S2, S3, S6 and S8 in the switch switching group are turned on, D1 in the charge and discharge control module is turned on, and the remaining switches and diodes are turned off;

[0040] The DC input voltage source Vin is connected in series with C4, and the output voltage Vo=2Vin;

[0041] The output voltage Vo corresponding signal is finally modulated by the SPWM modulation unit to generate mode 4.

[0042] As an improvement of the present application,

[0043] In the SPWM generation mode 4 process,

[0044] The switches S1, S3, S6 and S8 in the switching group are turned on, and the rest of the switches and diodes are turned off.

[0045] The DC input voltage source Vin is connected in series with C1 and C4, and the output voltage Vo = 3Vin.

[0046] The output voltage Vo corresponding signal is finally modulated by the SPWM modulation unit to generate mode 5.

[0047] As an improvement of the present application,

[0048] In the SPWM generation mode 5 process,

[0049] The switches S1, S4 and S6 in the switching group are turned on, and the rest of the switches and diodes are turned off.

[0050] The DC input voltage source Vin is connected in series with C2 and C3.

[0051] The voltage of C2 is Vin, and the voltage of C3 is Vin, and the output voltage Vo = -Vin.

[0052] The output voltage Vo corresponding signal is finally modulated by the SPWM modulation unit to generate mode 6.

[0053] As an improvement of the present application,

[0054] In the SPWM generation mode 7 process,

[0055] The switches S2, S4, S5 and S7 in the switching group are turned on, and the rest of the switches and diodes are turned off.

[0056] The DC input voltage source Vin is connected in series with C2 and C3, and the output voltage Vo = -3Vin.

[0057] The application has the advantages that low cost and low complexity bring high economy, voltage and current double closed loop + SPWM control, without complex dynamic voltage balance algorithm, reducing the complexity and development difficulty of control logic, without additional voltage boosting circuit or independent DC power supply, 3 times voltage gain can be realized, seven-level output, combined with SPWM modulation, the output voltage waveform is closer to sine wave, the harmonic content is significantly reduced, the dependence on filter is reduced, the scheme is superior to the traditional multi-level inverter in cost, performance, control complexity and expansibility, and is especially suitable for energy storage and new energy application scenarios requiring high voltage gain, low harmonic and high reliability. BRIEF DESCRIPTION OF DRAWINGS

[0058] In order to more clearly illustrate the technical solutions of the embodiments of the application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the application, and other drawings can be obtained by those skilled in the art without creative labor. Among them:

[0059] Figure 1 It is the architecture planning diagram of the inverter system with symmetrical clamping structure in the application.

[0060] Figure 2 It is the mute mode 1 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0061] Figure 3 It is the mute mode 2 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0062] Figure 4 It is the mute mode 3 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0063] Figure 5 It is the mute mode 4 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0064] Figure 6 It is the mute mode 5 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0065] Figure 7 It is the mute mode 6 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0066] Figure 8 It is the mute mode 7 operation diagram of the inverter system with symmetrical clamping structure in the application.

[0067] Figure 9 It is the seven-level waveform diagram of the inverter system with symmetrical clamping structure in the application.

[0068] Figure 10The schematic diagram of the sampling and rectification circuit in the symmetrical clamping structure inverter system of the application.

[0069] Figure 11 The principle flow chart in the symmetrical clamping structure inverter system of the application. DETAILED DESCRIPTION

[0070] In order to make the above-mentioned purposes, features and advantages of the application more obvious and easy to understand, the specific embodiments of the application will be described in detail below with reference to the accompanying drawings.

[0071] Embodiment 1

[0072] Reference Figure 1 The embodiment provides a symmetrical clamping structure inverter system.

[0073] The central path loop 1 is a symmetrical clamping type seven-level inverter main circuit, and a complete set of switching device groups, clamping capacitor groups, clamping diode groups and filtering modules required by the complete set of processes are installed and arranged in the central path loop 1. In the present scheme, the switching device group includes 8 power switching tubes S1-S8, adopts IGBT or MOSFET, is symmetrically distributed according to the upper and lower bridge arms, and realizes seven-level voltage output through logic control.

[0074] The clamping capacitor group is composed of 4 capacitors (C1-C4), and through the series superposition strategy (such as C1+C2 or C3+C4), the gain of 3 times of the direct current input voltage (Vin) can be realized without additional boost circuit; the clamping diode group includes 4 fast recovery diodes (D1-D4), which are used to provide a voltage clamping path when switching to prevent capacitor overvoltage; the filtering module is composed of inductors (L1, L2) and an output capacitor C0 to form an LC filter, which suppresses high-frequency harmonics and ensures smooth output voltage waveform.

[0075] The central path loop 1 controls the charging and discharging path of the capacitor, can realize the conversion from direct current to multi-level alternating current, and the finally generated output voltage signal Vo can enter the control driving loop 2.

[0076] The control driving loop 2 includes a sampling receiving module 21 and an adjusting output module 22, the sampling receiving module 21 collects the inverter output voltage Vo in real time, and converts it into a processable feedback signal through the adjusting output module 22. The adjusting output module 22 includes a voltage outer loop regulator (PI controller) and a current inner loop regulator, which respectively adjust and process the voltage collected signal and the current collected signal. The SPWM modulation unit generates a modulation signal finally through the signal given by the adjusting output module 22, and outputs the required seven-level sine wave on site.

[0077] The scheme solves the problems of traditional multi-level inverters, such as many devices, low gain and complex control, by combining hardware topology optimization and control algorithm.

[0078] Embodiment 2

[0079] With reference to Figure 1 , this embodiment is based on the previous embodiment, and different from the previous embodiment is that:

[0080] The central path loop 1 is further divided into a charge-discharge control module 11, a filter module 12 and a switch switching group 13. The charge-discharge control module 11 is provided with a clamping capacitor group and a diode group. The clamping capacitor group is composed of four capacitors (C1-C4). Through the series superposition strategy (such as C1+C2 or C3+C4), a gain of three times of the direct current input voltage (Vin) can be achieved without an additional voltage boosting circuit. The diode group includes four fast recovery diodes (D1-D4) connected between the capacitor nodes and the switch tubes. A low impedance freewheeling path is provided during switch switching to prevent capacitor overvoltage and ensure one-way energy flow to avoid reverse current impact.

[0081] The switch switching group 13 is composed of eight power switch tubes S1-S8 and is divided into upper and lower bridge arms, each arm having four switch tubes. Seven-level switching is achieved through complementary conduction logic. The filter module 12 is responsible for the optimization of the output waveform. The filter module 12 includes two filter inductors (L1, L2) for suppressing high-frequency switching noise, and an output capacitor C o The filter module 12 is connected to the switch switching group 13 at one end and to the voltage output end at the other end.

[0082] The sampling receiving module 21 includes a current sampling unit 211 and a voltage sampling unit 212 to achieve real-time signal acquisition. The adjustment output module 22 is a double-closed-loop control core. The voltage regulator 222 is a PI controller with an input of voltage error (Vref-V o ) and an output of current given value (Iref). The current regulator 221 converts the current error (Iref-IL) into a modulation amplitude value. The signal finally enters the SPWM modulation unit 223 for conversion and is introduced into the central path loop 1.

[0083] The central path loop 1 controls the switch switching group 13 to adjust according to the output signal of the SPWM modulation unit 223, constantly switches the required conduction and blocking switches, and finally outputs a seven-level sine wave.

[0084] Embodiment 3

[0085] With reference to Figures 1-11 , this embodiment is based on the previous embodiment, and different from the previous embodiment is that:

[0086] The control drive circuit 2 first samples the initial state of the central path circuit 1, and first sets the reference voltage Vref, which is used for error comparison with the output voltage Vo. The voltage regulator 222 receives and adjusts this signal, and generates a given value of the current inner loop. The current regulator 221 compares this with the sampling current given by the current sampling unit 211, and calculates the error value.

[0087] The signal finally enters the SPWM modulation unit 223 for conversion, and the modulation signal is converted into an 8-way PWM, which is input to the central path circuit 1, to drive the on-off of the switch switching group 13, to generate a new mode 1, which is then sampled and detected by the control drive circuit 2, and so on, to generate seven modes, to output a seven-level sine wave.

[0088] In the SPWM generation mode 1 process, S3, S6, and S7 in the switch switching group 13 are turned on, D1, D2, and D3 in the charge-discharge control module 11 are turned on, the remaining switches and diodes are turned off, and the DC input voltage source Vin charges C1, C2, and C3 in the charge-discharge control module 11. The sum of the voltages of C1 and C2 in series is Vin, the voltage of C3 is Vin, the output end voltage Vo = 0, and the output end voltage Vo corresponds to the signal finally passing through the SPWM modulation unit 223, to generate mode 2.

[0089] In the SPWM generation mode 2 process, S2, S3, S5, and S8 in the switch switching group 13 are turned on, D1 and D4 in the charge-discharge control module 11 are turned on, the remaining switches and diodes are turned off, and the DC input voltage source Vin charges C1 and C4 in the charge-discharge control module 11. The voltage of C1 is Vin, the voltage of C4 is Vin, the output end voltage Vo = Vin, and the output end voltage Vo corresponds to the signal finally passing through the SPWM modulation unit 223, to generate mode 3.

[0090] In the SPWM generation mode 3 process, S2, S3, S6, and S8 in the switch switching group 13 are turned on, D1 in the charge-discharge control module 11 is turned on, the remaining switches and diodes are turned off, and the DC input voltage source Vin is connected in series with C4, and the output end voltage Vo = 2Vin, and the output end voltage Vo corresponds to the signal finally passing through the SPWM modulation unit 223, to generate mode 4.

[0091] In the SPWM generation mode 4 process, S1, S3, S6, and S8 in the switch switching group 13 are turned on, the remaining switches and diodes are turned off, and the DC input voltage source Vin is connected in series with C1 and C4, and the output end voltage Vo = 3Vin, and the output end voltage Vo corresponds to the signal finally passing through the SPWM modulation unit 223, to generate mode 5.

[0092] In the SPWM generating mode 5, S1, S4, S6 in the switch group 13 are turned on, D2, D3 in the charge-discharge control module 11 are turned on, the rest of the switch tubes and diodes are cut off, the DC input voltage source Vin charges C2, C3 in the charge-discharge control module 11, the voltage of C2 is Vin, the voltage of C3 is Vin, the output voltage Vo=-Vin, and the output voltage Vo corresponds to the signal finally generated by the SPWM modulation unit 223 for generating mode 6.

[0093] In the SPWM generating mode 6, S1, S4, S5, S7 in the switch group 13 are turned on, D2 in the charge-discharge control module 11 is turned on, the rest of the switch tubes and diodes are cut off, the DC input voltage source Vin charges C2 in the charge-discharge control module 11, the voltage of C2 is Vin, the DC input voltage source Vin is connected in series with C3, the output voltage Vo=-2Vin, and the output voltage Vo corresponds to the signal finally generated by the SPWM modulation unit 223 for generating mode 7.

[0094] In the SPWM generating mode 7, S2, S4, S5, S7 in the switch group 13 are turned on, the rest of the switch tubes and diodes are cut off, the DC input voltage source Vin is connected in series with C2, C3, and the output voltage Vo=-3Vin. After the above seven modes are generated, a 7-level voltage waveform is obtained.

[0095] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or replaced equivalently without departing from the spirit and scope of the present application, and all of them should be covered in the scope of the claims of the present application.

Claims

1. An inverter system of a symmetrical clamping structure, characterized by: The central path loop (1) controls the charging and discharging path of the capacitor, provides a direct current to the multi-level alternating current conversion, and the signal enters the control drive loop (2); The control drive loop (2) includes a sampling receiving module (21) and an adjustment output module (22); The sampling receiving module (21) obtains signals from the central path loop (1) to provide adjustable current and voltage values into the adjustment output module (22); The adjustment output module (22) receives the signal of the sampling receiving module (21) to provide error adjustment, generates a current set value, compares the adjustment to generate a modulation signal, and outputs a seven-level sine wave.

2. The symmetrical clamping structure inverter system according to claim 1, wherein: The central path loop (1) includes a charging and discharging control module (11), a filter module (12), and a switch switching group (13); The charging and discharging control module (11) is provided with a clamping capacitor group and a diode group, both of which are connected in series; the charging and discharging control module (11) is connected to the switch switching group (13) at both ends; The filter module (12) is connected to the switch switching group (13) at one end and connected to the voltage output end at the other end; The sampling receiving module (21) includes a current sampling unit (211) and a voltage sampling unit (212); The adjustment output module (22) includes a current regulator (221), a voltage regulator (222), and an SPWM modulation unit (223); The voltage sampling unit (212) is connected to the voltage regulator (222), and the output end of the voltage regulator (222) is connected to the current regulator (221); The current regulator (221) generates a modulation signal into the SPWM modulation unit (223) for conversion. The symmetrical clamping structure inverter system according to claim 2, and 3. An inverter control method characterized by comprising: The sampling conditioning detects the output voltage Vo and the sampling current of the control drive loop (2); Error adjustment: Vo is compared with the reference value (Vref), and the current set value is generated through the voltage regulator (222) adjustment; Then compared with the sampling current, the modulation signal is generated through proportional adjustment; SPWM generation: the modulation signal is converted into 8-way PWM, which drives the switch switching group (13) to switch on and off, generates seven modes, and outputs a seven-level sine wave.

4. The inverter control method according to claim 3, wherein: In the SPWM generation mode 1 process, S3, S6, and S7 in the switch switching group (13) are turned on, D1, D2, and D3 in the charging and discharging control module (11) are turned on, and the rest of the switches and diodes are turned off; The DC input voltage source Vin charges C1, C2, and C3 in the charging and discharging control module (11); The sum of the voltages of C1 and C2 in series is Vin, and the voltage of C3 is Vin, and the output end voltage Vo = 0; The output end voltage Vo corresponds to the signal finally used for generating mode 2 through the SPWM modulation unit (223).

5. The inverter control method according to claim 3, wherein: In the SPWM generation mode 2 process, S2, S3, S5, and S8 in the switch switching group (13) are turned on, D1 and D4 in the charging and discharging control module (11) are turned on, and the rest of the switches and diodes are turned off; ​ DC input voltage source Vin charges C1, C4 in charge-discharge control module (11); C1 voltage is Vin, C4 voltage is Vin, output voltage Vo = Vin; Output voltage Vo corresponding signal is finally through SPWM modulation unit (223) for generating mode 3.

6. The inverter control method according to claim 3, characterized in that: In the SPWM generation mode 3 process, S2, S3, S6, S8 in switch switching group (13) are turned on, D1 in charge-discharge control module (11) is turned on, and the rest of the switches and diodes are turned off; DC input voltage source Vin is connected in series with C4, and output voltage Vo = 2Vin; Output voltage Vo corresponding signal is finally through SPWM modulation unit (223) for generating mode 4.

7. The inverter control method according to claim 3, characterized in that: In the SPWM generation mode 4 process, S1, S3, S6, S8 in switch switching group (13) are turned on, and the rest of the switches and diodes are turned off; DC input voltage source Vin is connected in series with C1, C4, and output voltage Vo = 3Vin; Output voltage Vo corresponding signal is finally through SPWM modulation unit (223) for generating mode 5.

8. The inverter control method according to claim 3, characterized in that: In the SPWM generation mode 5 process, S1, S4, S6 in switch switching group (13) are turned on, D2, D3 in charge-discharge control module (11) are turned on, and the rest of the switches and diodes are turned off; DC input voltage source Vin charges C2, C3 in charge-discharge control module (11); C2 voltage is Vin, C3 voltage is Vin, and output voltage Vo = -Vin; Output voltage Vo corresponding signal is finally through SPWM modulation unit (223) for generating mode 6.

9. The inverter control method according to any one of claims 3, characterized in that: In the SPWM generation mode 6 process, S1, S4, S5, S7 in switch switching group (13) are turned on, D2 in charge-discharge control module (11) is turned on, and the rest of the switches and diodes are turned off; DC input voltage source Vin charges C2 in charge-discharge control module (11), and C2 voltage is Vin; DC input voltage source Vin is connected in series with C3, and output voltage Vo = -2Vin; Output voltage Vo corresponding signal is finally through SPWM modulation unit (223) for generating mode 7.

10. The inverter control method according to any one of claims 4-9, characterized in that: In the SPWM generation mode 7 process, S2, S4, S5, S7 in switch switching group (13) are turned on, and the rest of the switches and diodes are turned off; DC input voltage source Vin is connected in series with C2, C3, and output voltage Vo = -3Vin.

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