Multi-bit event image sensing system based on low throughput

Abstract

The invention discloses a multi-bit event image sensing system based on low throughput. The image sensing system comprises an optical receiver, a switched capacitor amplifier, a dual-threshold comparator, a programmable delay module and a multi-bit reading circuit, the strong ON / OFF event is directly input into the multi-bit reading circuit, and the weak ON / OFF event is input into the programmable delay module; the programmable delay module delays a triggered weak event for a period of time and outputs a corresponding delay event signal to the input end of the multi-bit readout circuit; the multi-bit reading circuit converts an input event pulse into a row request and a three-bit output signal to be connected with a rear-end circuit, and outputs a reset signal to the switched capacitor amplifier after event triggering is completed; through multi-threshold comparison and a trigger delay mechanism of the programmable delay module, texture details of a reconstructed image are improved, meanwhile, the number of events in a scene with violent light intensity change is remarkably reduced, and the system throughput is reduced.

Description

TECHNICAL FIELD

[0001] The application relates to the field of dynamic vision sensors, in particular to a low-throughput multi-bit event image sensing system. BACKGROUND

[0002] Image sensing systems are a great technological product of the new era, which is constantly updated and improved in the replacement of the era. At present, with the increasing demand for camera speed and image quality, the traditional frame-based image sensing system has been unable to meet the demand, its dynamic range is too small, and the periodic and full-range pixel information transmission brings great pressure to subsequent data processing, reducing the computing speed of the sensor and the quality of the image. The event image sensing system (EVS) is different from the traditional principle, which uses a differential capacitor amplifier to obtain data representing dynamic information within a certain time by combining biological vision and event-driven principles, and filters out static redundancy, thereby greatly reducing the data processing amount, and has the advantages of high dynamic range and high speed.

[0003] However, with the deepening of research, the single polarity event output of EVS only highlights the edge information of the reconstructed image, limits the texture features, causes the image details to be missing, and leads to the inability to identify and track objects; in addition, too many events generated under high light intensity also limit the time accuracy of reading out, and restrict the running speed. Therefore, the EVS camera has the problems of missing detail information and too much output data in complex scenes.

[0004] At present, the research on improving the quality of EVS reconstructed images mainly focuses on adding a set of circuits capable of outputting intensity information on the basis of the original EVS function, such as in-pixel gray scale conversion, time coding or direct output of intensity information. In recent years, research has been carried out based on the dynamic active pixel vision sensor (DAVIS) which combines the functions of traditional active pixel vision sensors and event image sensing systems, and the combination of event information and intensity information is continued under the progress of process conditions to optimize the image details and enrich the texture information. However, the above-mentioned ideas are often accompanied by the problem of mismatch and asynchronization of intensity information and event information, and require relatively complex readout circuits and high-cost processes to support. In addition, for the control of the number of events, a series of analysis and research shows that we can dynamically control it by changing the threshold, refractory period and signal bandwidth, but it is mostly at the method level and lacks circuit support.

[0005] Based on this, the application provides a multi-bit event image sensing system pixel structure based on a traditional event image sensing system. The design realizes the discrimination of event intensity through multi-threshold comparison and a programmable delay module, and can output intermediate intensity information, thereby improving the texture details of the reconstruction result. Meanwhile, in a complex scene with large light intensity changes, the introduction of the delay module greatly reduces the number of events and the throughput of the system. SUMMARY

[0006] The application provides a multi-bit event image sensing system pixel structure, which significantly reduces the number of events in a scene with large light intensity changes and reduces the throughput of the system through multi-threshold comparison and a programmable delay module trigger delay mechanism while improving the texture details of the reconstructed image. The application solves the problems of missing intermediate intensity, insufficient texture details and excessive event generation in complex scenes caused by the single-polarity event output of the traditional EVS pixel.

[0007] Based on the above problems, the application provides a multi-bit event image sensing system pixel structure, which retains the functions of the EVS light receiving stage and the switched-capacitor amplifier, changes the original reset mechanism by using a double-threshold comparator and a programmable delay module, reduces the throughput of the system, and further divides the event types through the discrimination of event intensity, thereby enriching the texture detail information of the reconstructed image.

[0008] The application adopts the following technical solutions:

[0009] A low-throughput multi-bit event image sensing system, the image sensing system comprising a light receiver, a switched-capacitor amplifier, a double-threshold comparator, a programmable delay module and a multi-bit readout circuit; wherein: the light receiver converts the logarithm of the light intensity signal into a photovoltage signal, and is connected to the input end of the switched-capacitor amplifier; the switched-capacitor amplifier amplifies the change amount of the photovoltage signal and outputs to the input end of the double-threshold comparator; the double-threshold comparator outputs strong ON / OFF events and weak ON / OFF events, wherein:

[0010] The strong ON / OFF events are directly input into the multi-bit readout circuit, and the weak ON / OFF events are input into the programmable delay module; the programmable delay module delays the triggered weak events for a period of time and outputs the corresponding delay event signal to the input end of the multi-bit readout circuit; the multi-bit readout circuit converts the input event pulse into a row request and a three-bit output signal connected to the back-end circuit, and outputs a reset signal to the switched-capacitor amplifier after the event trigger is completed.

[0011] Further, the double threshold comparator comprises four groups of the same comparator structure with current source load connected to the drain of PMOS, and the gates of the four PMOS are connected to the input voltage v diff ; wherein: the first PMOS and the input current i onw form a weak ON comparator; the second PMOS and the input current i ons form a strong ON comparator; the third PMOS and the input current i offw form a weak OFF comparator; the fourth PMOS and the input current i offs form a strong OFF comparator; wherein:

[0012] For the ON event, when the input voltage v diff falls to the low threshold onw , the first PMOS will flip first, generating an upward step v onw and maintaining, waiting for whether it can continue to fall to the high threshold ons before the delay ends, so that the second PMOS flips, and outputs the upward stepped v ons signal; similarly, for the OFF event, when the input voltage v diff rises to offw , the third PMOS will flip first, generating a downward step n offw and maintaining, waiting for whether it can continue to rise to offs before the delay ends, so that the fourth PMOS flips, and outputs the downward stepped n offs signal.

[0013] Further, the sizes of the first PMOS 31 and the third PMOS 32 are consistent, the sizes of the second PMOS 32 and the fourth PMOS 34 are consistent, and the sizes of the first PMOS 31 and the third PMOS 32 are half of the sizes of the second PMOS 32 and the fourth PMOS 34.

[0014] Further, the programmable delay module is composed of a programmable current bias unit outside the pixel and a delay unit inside the pixel.

[0015] Further, the programmable current bias unit is composed of a constant transconductance current reference circuit, a scaling circuit and a current adjustable circuit; the current adjustable circuit comprises a current input NMOS tube, a current input PMOS tube, a first replica PMOS tube, a second replica PMOS tube, a third replica PMOS tube, a fourth replica PMOS tube and a current output NMOS tube; the gate of the current input NMOS tube is connected with the constant transconductance current reference circuit; the drain thereof is connected with the drain of the current input PMOS tube; the gate of the current input PMOS tube is connected with the gates of the first replica PMOS tube, the second replica PMOS tube, the third replica PMOS tube and the fourth replica PMOS tube in series; the drain of the first replica PMOS tube is connected with the drain of the current output NMOS tube, the drain of the second replica PMOS tube is connected with the drain of the current output NMOS tube through a first switch, the drain of the third replica PMOS tube is connected with the drain of the current output NMOS tube through a second switch, the drain of the fourth replica PMOS tube is connected with the drain of the current output NMOS tube through a third switch; the drain of the current output NMOS tube is shorted with the gate thereof and connected with the scaling circuit; wherein:

[0016] When the constant transconductance current reference output circuit outputs a reference current i in The current then enters the current adjustable circuit through the current input NMOS tube and the current input PMOS tube, and when the control switch code value is changed <s3s2s1>When the switch code value is 0, the first switch, the second switch and the third switch are all open, so that the branch in which the first replica PMOS transistor is located is conducted, and then the output current i out =i in ; when the switch code value is 1, the first switch and the third switch are open, and the second switch is conducted, so that the branch in which the second replica PMOS transistor is located is conducted, and then the output current i <s3s2s1>When <001>, the first switch is closed, the second switch and the third switch are opened, the branch in which the first replica PMOS transistor and the second replica PMOS transistor are located is conducted, and then the output current i out =2i in ; … ; when the switch code value <s3s2s1>When <111>, the first switch, the second switch and the third switch are closed, the branch where the first replica PMOS, the second replica PMOS, the third replica PMOS and the fourth replica PMOS are located are all turned on, then the output current i out =8i in ; thus, the output current i out is controlled by the three-bit code value, and the switches S1, S2 and S3 perform 8-step fine adjustment on the output current i

[0017] The size of the first replica PMOS and the second replica PMOS is equal to the size of the current input PMOS, the size of the third replica PMOS is twice the size of the current input PMOS, and the size of the fourth replica PMOS is four times the size of the current input PMOS, so as to satisfy the replica input current i in and amplify it by ×1, ×1, ×2 and ×4 respectively.

[0018] Further, the delay unit in the pixel is composed of an OFF event conversion circuit and an ON event conversion circuit; the OFF event conversion circuit is composed of a delay NMOS and a controllable current source, and a first capacitor C1 is connected across the controllable current source; the ON event conversion circuit is composed of a delay PMOS and a controllable current source, and a second capacitor C2 is connected across the controllable current source.

[0019] Further, the multi-bit readout circuit includes a logic operation unit, an event output unit and a reset unit, wherein:

[0020] The logic operation unit includes an inverter, a NAND gate series circuit for processing ON events, and an inverter, an OR gate series circuit for processing OFF events. The series circuits are commonly connected to an OR gate, and output event signals to the event output module

[0021] The event output unit is composed of seven NMOS, including a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; wherein:

[0022] The sixth NMOS pipe receives the returned RA signal of the nRR signal, and the drain end of the sixth NMOS pipe is connected with the source end of the first NMOS pipe, the second NMOS pipe, the third NMOS pipe, the fourth NMOS pipe and the fifth NMOS pipe; the first NMOS pipe and the second NMOS pipe are connected in parallel, and the drain end of the first NMOS pipe and the second NMOS pipe outputs the intensity signal nSW; the third NMOS pipe and the fourth NMOS pipe are connected in parallel, and the drain end of the third NMOS pipe and the fourth NMOS pipe outputs the polarity signal nPOL; the transistor drain end outputs the event signal nEVE; wherein:

[0023] When the RA signal rises, the sixth NMOS pipe and the first control transistor are turned on, and the v A signal is set to low, and the gate end voltage of the fifth NMOS pipe, the first NMOS pipe / second NMOS pipe and the third NMOS pipe / fourth NMOS pipe is v eve , v ons / v offs and v ons / v onw , and after being turned on, it can be "or" operation with the returned RA signal to control the three-bit output signal: nEVE, nSW, nPOL, all of which are low effective; the three-bit signal is propagated through the column bus, and after the above signal transmission is completed, the high effective column response signal CA will be returned, the second control transistor is turned on, and the reset signal nrst is pulled to low level, and the reset is completed.

[0024] Beneficial effects

[0025] The design refines the event type by distinguishing the intensity of ON / OFF events, realizes the output of intermediate intensity events, and utilizes the programmable delay module to realize the delay trigger of events, reduces the system throughput, and reduces the pressure of the subsequent processing circuit under the condition of ensuring or even improving the image quality. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 It is a structure schematic diagram of a low-throughput multi-bit event image sensing system based on the application;

[0027] Figure 2 It is a double threshold comparator circuit diagram in a low-throughput multi-bit event image sensing system based on the application;

[0028] Figure 3 It is a programmable bias module circuit diagram in a low-throughput multi-bit event image sensing system based on the application;

[0029] Figure 4 It is a multi-bit readout circuit diagram in a low-throughput multi-bit event image sensing system based on the application;

[0030] Figure 5 is a true value table corresponding to three-bit output signals and event types in a throughput multi-bit event image sensing system based on the application;

[0031] Figure 6 is a readout signal timing diagram of a throughput multi-bit event image sensing system based on the application;

[0032] Figure 7 is a working timing diagram of a throughput multi-bit event image sensing system based on the application. DETAILED DESCRIPTION

[0033] The following will be combined with the accompanying Figure 1 The Figure 7 The technical solutions of the application will be described in detail.

[0034] Figure 1 A multi-bit event image sensing system pixel structure schematic diagram is given, including a light receiver 1, a switched-capacitor amplifier 2, a dual-threshold comparator 3, a programmable delay module 4, and a multi-bit readout circuit 5. Among them: the light receiving stage 1 and the switched-capacitor amplifier 2 are consistent with the traditional EVS structure. The light receiving stage 1 will convert the light intensity input signal into a photocurrent signal i ph , and then logarithmically convert it into a photovoltage signal v sf Input into the switched-capacitor amplifier 2. The switched-capacitor amplifier 2 adopts a simple two-tube amplifier stage and has two working modes. When the reset signal is low active, the circuit is in the reset state, and the output is maintained at the reset level; when the reset signal is high, the circuit enters the amplification state, differentially amplifies the input signal v sf , and outputs v diff which can represent the change of light intensity, connected to the dual-threshold comparator 3.

[0035] The dual-threshold comparator 3 works together with the programmable delay module 4 to generate event pulses with intensity and polarity information. When the change of v diff exceeds the low threshold, a weak event is generated, which will enter the programmable delay module 4 and at the same time be input into the multi-bit readout circuit 5 as a basis for polarity judgment, and will not be reset immediately. The programmable delay module 4 will perform slope conversion on the input weak event pulse and output a delayed weak event signal with a fixed delay. Before the end of the delay, if the change of v diff continues to increase until it exceeds the strong threshold, a strong event will be generated; otherwise, no strong event will be generated and the weak event will enter the next stage. After that, the delayed weak event and the strong event signal will be input into the multi-bit readout circuit 5, which will trigger and reset the event under the cooperation of logic operation and the response signal returned by the handshake protocol, send the output signal to the subsequent processing circuit, and return the reset signal to the switched-capacitor amplifier 2.

[0036] Figure 2 The internal details of the double threshold comparator 3 circuit are given. The circuit contains four groups of the same comparator structure with current source load connected to the PMOS tube drain, and the inputs of the four PMOS tubes are connected and serve as the input port of the module. Among them: the first PMOS tube 31 and the current source with input current i onw form a weak ON comparator; the second PMOS tube 32 and the current source with input current i ons form a strong ON comparator; the third PMOS tube 33 and the current source with input current i offw form a weak OFF comparator; and the fourth PMOS tube 34 and the current source with input current i offs form a strong OFF comparator. The currents i onw , i ons , i offw and i offs respectively provide bias for the branches where the first PMOS tube 31, the second PMOS tube 32, the third PMOS tube 33 and the fourth PMOS tube 34 are located, and the size is all in the order of nA, controlling the threshold size. The sizes of the first PMOS tube 31 and the third PMOS tube 32 are the same, the sizes of the second PMOS tube 32 and the fourth PMOS tube 34 are the same, and the sizes of the first PMOS tube 31 and the third PMOS tube 32 are half of the sizes of the second PMOS tube 32 and the fourth PMOS tube 34. For the ON event, when the input voltage v diff drops to the low threshold onw , the first PMOS tube 31 will first flip, generating an upward step v onw and maintaining, waiting to see if it can continue to drop to the high threshold ons and make the third PMOS tube 33 flip to output the v ons signal with an upward step. Similarly for the OFF event, when the input voltage v diff rises to offw , the second PMOS tube 32 will first flip, generating a downward step n offw and maintaining, waiting to see if it can continue to rise to offs and make the fourth PMOS tube 34 flip, outputting the n offs signal with a downward step. After the event occurs, the four comparator outputs will also return to the reset level under the action of the reset signal, that is, the event finally appears in the form of a pulse.

[0037] Figure 3 The programmable bias circuit and the internal details of the in-pixel delay module are given. The module consists of two parts, namely the programmable current bias unit outside the pixel and the delay unit inside the pixel. The programmable current bias adopts a constant transconductance current reference circuit G41, a scaling circuit G42 and a current adjustable circuit G43. Among them, the gate of the current input NMOS tube 41 in the current adjustable circuit G43 is connected with the output of the constant transconductance current reference G41, and the drain thereof is connected with the drain of the current input PMOS tube 42 to form a current input branch. The gate of the current input PMOS tube 42 is connected with the gates of the first, second, third and fourth replica PMOS tubes 43, 44, 45 and 46, and the sizes of the first and second replica PMOS tubes 43 and 44 are equal to that of the current input PMOS tube 42, the size of the third replica PMOS tube 45 is twice that of the current input PMOS tube 42, and the size of the fourth replica PMOS tube 46 is four times that of the current input PMOS tube 42, so as to meet the requirements of the replica input current i in and is amplified by ×1, ×1, ×2 and ×4 respectively. The drain of the first replica PMOS tube 43 is connected with the drain of the current output NMOS tube 47; the drain of the second replica PMOS tube 44 is connected with the drain of the current output NMOS tube 47 through the first switch S1, the drain of the third replica PMOS tube 45 is connected with the drain of the current output NMOS tube 47 through the second switch S2, and the drain of the fourth replica PMOS tube 46 is connected with the drain of the current output NMOS tube 47 through the third switch S3; the drain and the gate of the current output NMOS tube 47 are short-circuited, and are connected with the input of the scaling module. When the constant transconductance current reference circuit generates a fixed size reference current i in , the current enters the current adjustable circuit G43 through the current input branch, and when the control switch code value <s3s2s1>When the switch code value is 0, the first switch S1, the second switch S2 and the third switch S3 are all disconnected, the branch in which the first replica PMOS transistor 43 is located is turned on, and the output current i out =i in ; when the switch code value is 1, the first switch S1 is connected, the second switch S2 and the third switch S3 are disconnected, the branch in which the second replica PMOS transistor 44 is located is turned on, and the output current i <s3s2s1>When <001>, the first switch S1 is closed, the second switch S2 and the third switch S3 are opened, the branch where the first replica PMOS transistor 43 and the second replica PMOS transistor 44 are located is conducted, and then the output current i out = 2i in ; … ; when the switch code value <s3s2s1>When <111>, the first switch, the second switch, the third switch are closed, the first copy PMOS tube 43, the second copy PMOS tube 44, the third copy PMOS tube 45, the fourth copy PMOS tube 46 branch is all turned on, the output current i out =8i in Thus, the output current i out Can be controlled by three-bit code value switch S1, S2, S3 8 order step size fine tuning. The bias not only can provide current for the controllable current source in the pixel delay module, but also can supply all the bias current in the pixel, realize global dynamic adjustment.

[0038] For the delay unit in the pixel, in order to reduce the complexity of the circuit and the pixel area, the unit adopts the principle of capacitor current charging and discharging to convert the input signal into step to slope, which is divided into OFF event conversion circuit and ON event conversion circuit. Among them, the OFF event conversion circuit is composed of delay NMOS tube 48 and controllable current source G44, and the capacitor C1 is connected across the current source G44; the ON event conversion circuit is composed of delay PMOS tube 49 and controllable current source G45, and the capacitor C2 is connected across the current source G45. Taking the ON event as an example, when no event occurs, v onw Event is low, the delay PMOS tube 49 is turned on, and nv onw_delay Signal is pulled to high level; after v onw The step from low to high level occurs, the delay PMOS tube 49 is disconnected, and due to the capacitor characteristic, the voltage nv onw_delay On the C2 plate will not immediately decrease to low level but slowly discharge under the action of i refon , showing a slope type of decline, and the discharge time and voltage change are proportional. Thus, the conversion of step signal to slope signal can be realized through the interaction of current and capacitor, and the purpose of adjustable delay can be achieved by adjusting the current size.

[0039] Figure 4 The internal details of the multi-bit readout circuit are given, which is divided into logic operation module, event output module and reset module, and the event type is sorted out and the system is reset by combining the logic operation and the capacitor charging and discharging principle. Among them, the reset circuit uses the same structure as EVS, and the specific structure and signal flow process of the logic operation module and the event output module will be described below.

[0040] Logic operation unit: the logic operation module contains the inverter G51, NAND gate G52 series circuit for processing ON event and the inverter G53, OR gate G54 series circuit for processing OFF event. The above series circuits are commonly connected to OR gate G55, output event signal to event output module. Taking ON event as an example, input strong event v ons will first be inverted by inverter G51, output nv ons as the input of NAND gate G52. The other input of NAND gate G52 is the delayed weak ON event signal nv onw_delay output by programmable delay module 4. After logic operation, the output v on signal can represent the generation of ON event. The v on signal will be input to OR gate G55, and the v off signal representing the generation of OFF event will be input to OR gate G55, and the high effective event signal v eve will be obtained by AND operation. The signal can control the fifth NMOS tube 55 and the seventh NMOS tube 57 in the event output module to flip, and then control the row request signal nRR to be effective.

[0041] Event output unit: the module is composed of 7 NMOS, which sorts and outputs event information. Among them, the sixth NMOS tube 56 is responsible for receiving the RA signal returned after the nRR signal is sent out, and the drain end is connected with the source end of the first NMOS tube 51, the second NMOS tube 52, the third NMOS tube 53, the fourth NMOS tube 54 and the fifth NMOS tube 55. The first NMOS tube 51 and the second NMOS tube 52 are connected in parallel, and the drain end of the first NMOS tube 51 and the second NMOS tube 52 outputs the intensity signal nSW; the third NMOS tube 53 and the fourth NMOS tube 54 are connected in parallel, and the drain end of the third NMOS tube 53 and the fourth NMOS tube 54 outputs the polarity signal nPOL; the drain end of the fifth NMOS tube 55 outputs the event signal nEVE. The specific working process of the circuit is as follows: consistent with the handshake protocol of EVS, the nRR signal can represent the generation of event and the row coordinate, after the signal is effective, the subsequent circuit will process and return the high effective row response signal RA, and the system enters the sorting stage of event type. In this stage, the RA signal rises, controls the sixth NMOS tube 56 and the first control transistor 58 to be turned on, and sets the v A signal to low. The gate voltage of the fifth NMOS tube 55, the first NMOS tube 51 / second NMOS tube 52 and the third NMOS tube 53 / fourth NMOS tube 54 is v eve , v ons / v offs and v ons / v onw , and after being turned on, can perform OR operation with the returned RA signal to control three-bit output signals: nEVE, nSW, nPOL, all of which are low effective. The three-bit signals are propagated through a column bus, and can represent event generation, intensity, polarity and longitudinal coordinate, and their relationship with event types is shown in a truth table as follows. Figure 5 After the signal transmission is completed, a high effective column response signal CA will be returned, the second control transistor 59 is turned on, the reset signal nrst is pulled to low level, and the reset is completed. The post-reset signal will slowly rise to high level under the action of the current i refr and the capacitor C3, and the control system re-enters the amplification state.

[0042] Figure 5 A truth table of the three-bit output signals and event types is given. There are five event types: strong ON event, weak ON event, strong OFF event, weak OFF event and no event. The three-bit output signals are used to encode the event types in the application, and are all low effective signals. When the nEVE signal is high, it directly represents no event, and is independent of the last two signals.

[0043] Figure 6 A pixel readout signal timing diagram of the multi-bit event image sensor system is given. Two ON event triggering processes of different intensities are shown. Taking the first strong ON event triggering process as an example: according to the time sequence, when v diff drops to the weak ON threshold, v onw rises and maintains high level. Within a delay time T d , v diff continues to drop to the strong ON threshold, so that the strong ON event is generated, v ons rises, and then the ON event signal v on is effective, nRR is effective, which prompts the RA to return for a period of time, and the row handshake is completed. At this time, under the action of the RA and nRR, nEVE drops; at the same time, under the action of v ons , nSW drops; under the action of v ons / v onw , nPOL drops, and the output three-bit code value is "000", and the event triggering stage is completed. After the stage is completed, the column response signal CA is returned, so that nrst rapidly drops, and v onw , v ons signals drop, so that nSW and nPOL rise. The post v on , RR, nRR signals are reset in sequence, RR controls the nEVE signal to restore high level; the row response signal nRR controls the row response RA to reset, and the event signal nEVE signal controls the column response signal CA to reset. At this time, the complete event triggering and reset process is completed, and the event is waiting for nrst to re-rise to high level, and enters the triggering of the next round of events.

[0044] Figure 7 The pixel working timing diagram of the multi-bit event image sensor system is given. Four stages and four different event generation processes are shown in the diagram. First, the light receiving stage outputs a voltage v sf drops from a higher value and at a faster speed, and two strong OFF events are generated, and the three-bit output signal is "001"; then v sf remains at a lower voltage and does not change, and no event is generated at this time, and the output remains "111"; in the second stage v sf rises at a smaller amplitude and a slower speed, and only one weak ON event is generated, and the output is "010"; in the third stage v sf a small amplitude and low speed drop is generated, and a weak OFF event is generated at this time, and the output is "011"; in the last stage, v sf rises rapidly from a lower voltage to a higher voltage, and two strong ON events are generated, and the output signal is "000".

[0045] Figure 1 The pixel structure diagram of the multi-bit event image sensor system proposed in the application is given, which includes a light receiver 1, a switched-capacitor amplifier 2, a dual-threshold comparator 3, a programmable delay module 4, and a multi-bit readout circuit 5.

[0046] The light receiving stage 1 and the switched-capacitor amplifier 2 are consistent with the traditional EVS design. The light receiving stage 1 converts the light intensity signal into a photo-voltage signal and is connected to the input end of the switched-capacitor amplifier 2. The switched-capacitor amplifier 2 enters an amplification state under the control of a reset signal, captures the change amount of the input signal and amplifies it, and outputs to the input end of the dual-threshold comparator 3. The dual-threshold comparator 3 outputs strong ON / OFF events and weak ON / OFF events, wherein the strong ON / OFF events are directly input into the multi-bit readout circuit 5, and the weak ON / OFF events are input into the programmable delay module 4 (the weak ON event also enters the multi-bit readout circuit as an event polarity judgment basis). The programmable delay module 4 delays the triggered weak event for a period of time and outputs the corresponding delayed event signal, which is connected to the input end of the multi-bit readout circuit 5. The multi-bit readout circuit 5 includes the above five event inputs, which converts the input event pulses into a row request and a three-bit output signal through logical operation and a handshake protocol (a row and column response process in the data output process of the EVS structure), and is connected to the backend circuit and outputs a reset signal to the aforementioned switched-capacitor amplifier 5 after the event trigger is completed.

[0047] Although the present application has been described above with reference to specific embodiments, the above embodiments are merely illustrative and not restrictive, and many modifications and other embodiments of the present application can occur to those skilled in the art upon reading the foregoing description, which modifications and other embodiments fall within the scope of the present application.

Claims

1. A low-throughput multi-bit event image sensor system based on, characterized by: The image sensing system comprises a light receiver, a switched capacitor amplifier, a double threshold comparator, a programmable delay module and a multi-bit readout circuit; wherein: the light receiver converts a light intensity signal into a photo-voltage signal and is connected to an input end of the switched capacitor amplifier; the switched capacitor amplifier amplifies a variation of the photo-voltage signal and outputs to an input end of the double threshold comparator; the double threshold comparator outputs a strong ON / OFF event and a weak ON / OFF event; wherein: the strong ON / OFF event is directly input into the multi-bit readout circuit, and the weak ON / OFF event is input into the programmable delay module; the programmable delay module delays the triggered weak event for a period of time and outputs a corresponding delay event signal to an input end of the multi-bit readout circuit; the multi-bit readout circuit converts an input event pulse into a row request and a three-bit output signal connected to a back-end circuit and outputs a reset signal to the switched capacitor amplifier after the event triggering is completed.

2. A low-throughput multi-bit event image sensor system based on claim 1, characterized in that: The double threshold comparator comprises four groups of the same comparator structure with current source load connected to the PMOS tube drain, and the four PMOS tube gates are all connected with the input voltage v diff ; wherein: the first PMOS tube and the input current i onw form a weak ON comparator with the current source; the second PMOS tube and the input current i ons form a strong ON comparator with the current source; the third PMOS tube and the input current i offw form a weak OFF comparator with the current source; and the fourth PMOS tube and the input current i offs form a strong OFF comparator with the current source; wherein: For the ON event, when the input voltage v diff falls below the low threshold onw , the first PMOS will flip first, generating an upward step v onw and holding, waiting to see if it can continue to fall below the high threshold ons before the delay expires, causing the second PMOS to flip and output an upward stepped v ons signal. Similarly, for the OFF event, when the input voltage v diff rises above the high threshold offw , the third PMOS will flip first, generating a downward step n offw v and holding, waiting to see if it can continue to rise above the low threshold offs before the delay expires, causing the fourth PMOS to flip and output a downward stepped n offs v signal.

3. A low-throughput multi-bit event image sensor system based on claim 2, characterized in that: The first PMOS tube 31 and the third PMOS tube 32 have the same size, the second PMOS tube 32 and the fourth PMOS tube 34 have the same size, and the size of the first PMOS tube 31 and the third PMOS tube 32 is half of the size of the second PMOS tube 32 and the fourth PMOS tube 34.

4. A low-throughput multi-bit event image sensor system based on claim 1, characterized in that: The programmable delay module is composed of a programmable current bias unit outside the pixel and a delay unit inside the pixel.

5. A low-throughput multi-bit event image sensor system based on claim 4, characterized in that: The programmable current bias unit is composed of a constant transconductance current reference circuit, a scaling circuit and a current adjustable circuit; the current adjustable circuit comprises a current input NMOS tube, a current input PMOS tube, a first replica PMOS tube, a second replica PMOS tube, a third replica PMOS tube, a fourth replica PMOS tube and a current output NMOS tube; the gate of the current input NMOS tube is connected with the constant transconductance current reference circuit; the drain thereof is connected with the drain of the current input PMOS tube; the gate of the current input PMOS tube is connected in series with the gates of the first replica PMOS tube, the second replica PMOS tube, the third replica PMOS tube and the fourth replica PMOS tube; the drain of the first replica PMOS tube is connected with the drain of the current output NMOS tube, the drain of the second replica PMOS tube is connected with the drain of the current output NMOS tube through a first switch, the drain of the third replica PMOS tube is connected with the drain of the current output NMOS tube through a second switch, the drain of the fourth replica PMOS tube is connected with the drain of the current output NMOS tube through a third switch; the drain of the current output NMOS tube is short-circuited with its gate and connected with the scaling circuit; wherein: When the constant transconductance current reference output circuit reference current i in After that, the current enters the current regulating circuit through the current input NMOS tube and the current input PMOS tube, when the control switch code value <s3s2s1>When the switch code value is 0, the first switch, the second switch and the third switch are all open, so that the branch in which the first replica PMOS transistor is located is conducted, and then the output current i out =i in ; when the switch code value is 1, the first switch and the third switch are open, and the second switch is conducted, so that the branch in which the second replica PMOS transistor is located is conducted, and then the output current i <s3s2s1>When <001>, the first switch is closed, the second switch and the third switch are opened, the branch in which the first replica PMOS transistor and the second replica PMOS transistor are located is conducted, and then the output current i out =2i in ; … ; when the switch code value <s3s2s1>When <111>, the first switch, the second switch and the third switch are closed, so that the branch in which the first replica PMOS transistor, the second replica PMOS transistor, the third replica PMOS transistor and the fourth replica PMOS transistor are located is all turned on, and then the output current i out =8i in flows into the current output NMOS transistor; thus, the output current i out can be controlled by the three-bit code value to be finely adjusted in 8 steps by the switches S1, S2 and S3.

6. A low-throughput multi-bit event image sensor system based on claim 5, characterized in that: The sizes of the first and second replica PMOS transistors are equal to the size of the current input PMOS transistor, the size of the third replica PMOS transistor is twice the size of the current input PMOS transistor, and the size of the fourth replica PMOS transistor is four times the size of the current input PMOS transistor, so as to satisfy the replica input current i in and are amplified by ×1, ×1, ×2 and ×4, respectively.

7. A low-throughput multi-bit event image sensor system based on claim 4, characterized in that: The delay unit inside the pixel is composed of an OFF event conversion circuit and an ON event conversion circuit; the OFF event conversion circuit is composed of a delay NMOS tube and a controllable current source, and a first capacitor C1 is connected across the controllable current source; the ON event conversion circuit is composed of a delay PMOS tube and a controllable current source, and a second capacitor C2 is connected across the controllable current source.

8. A low-throughput multi-bit event image sensor system based on claim 1, characterized in that: The multi-bit readout circuit comprises a logic operation unit, an event output unit and a reset unit, wherein: The logic operation unit comprises an inverter for processing ON events, a NAND gate series circuit, an inverter for processing OFF events, and an OR gate series circuit. The series circuits are connected to an OR gate, which outputs an event signal to an event output module The event output unit is composed of seven NMOS, including a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, a fifth NMOS, a sixth NMOS and a seventh NMOS; wherein: The sixth NMOS receives the returned RA signal after the nRR signal is sent out, and the drain end of the sixth NMOS is connected with the source end of the first NMOS, the second NMOS, the third NMOS, the fourth NMOS, the fifth NMOS; the first NMOS and the second NMOS are connected in parallel, and the drain end of the first NMOS and the second NMOS outputs an intensity signal nSW; the third NMOS and the fourth NMOS are connected in parallel, and the drain end of the third NMOS and the fourth NMOS outputs a polarity signal nPOL; the transistor drain end outputs an event signal nEVE; wherein: The sixth NMOS receives the returned RA signal after the nRR signal is sent out, and the drain end of the sixth NMOS is connected with the source end of the first NMOS, the second NMOS, the third NMOS, the fourth NMOS, the fifth NMOS; the first NMOS and the second NMOS are connected in parallel, and the drain end of the first NMOS and the second NMOS outputs an intensity signal nSW; the third NMOS and the fourth NMOS are connected in parallel, and the drain end of the third NMOS and the fourth NMOS outputs a polarity signal nPOL; the transistor drain end outputs an event signal nEVE; wherein: The RA signal is raised, the sixth NMOS tube and the first control transistor are turned on, and v A The signal is set low, the gate voltage of the fifth NMOS tube, the first NMOS tube / second NMOS tube and the third NMOS tube / fourth NMOS tube is v eve , v ons / v offs and v ons / v onw After being turned on, it can be controlled together with the returned RA signal to perform "or" operation to control three-bit output signals: nEVE, nSW and nPOL, which are all low effective; the three-bit signals are propagated through the column bus, and after the above signal transmission is completed, the high effective column response signal CA will be returned, the second control transistor is turned on, the reset signal nrst is pulled to low level, and the reset is completed.

Images