Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. According to the display panel, the projection of an active pattern of a first output transistor on a substrate, the projection of a first-type low-potential signal line on the substrate and the projection of a first-type high-potential signal line on the substrate are located within the range of the projection of the first-type low-potential signal line on the substrate; therefore, the first-type low-potential signal line and the first-type high-potential signal line can shield the active pattern of the first output transistor, thereby preventing the first output transistor from being affected by illumination and causing electrical drift, improving the output stability of the gate drive circuit, and avoiding display abnormality.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display panel and a display device. BACKGROUND

[0002] With the development of display technology, the existing display device has higher and higher requirements for display effect. In order to improve the display effect, the existing display device will adopt LTPO (Low Temperature Polysilicon Oxide) pixel circuit, but the LTPO pixel driving circuit needs more GOA (Gate On Array, Gate on Array) circuit output signal, which will cause the power consumption of the display device to increase, in order to reduce the power consumption of the display device, CMOS (Complementary Metal Oxide Semiconductor, Complementary Metal Oxide Semiconductor) GOA circuit will be used to reduce the number of GOA circuit. But in the process of use, it is found that the output transistor is easy to be affected by light to cause electrical drift, which leads to unstable output signal and further leads to display abnormality.

[0003] Therefore, the existing display device has the technical problem that the output transistor is easy to be affected by light to cause electrical drift and further leads to display abnormality. SUMMARY

[0004] The embodiments of the present application provide a display panel and a display device to solve the technical problem that the existing display device has the technical problem that the output transistor is easy to be affected by light to cause electrical drift and further leads to display abnormality.

[0005] In order to achieve the above-mentioned purpose, according to the first aspect of the present application, a display panel is provided, which comprises a gate driving circuit, the gate driving circuit comprises a first output unit, the first output unit comprises a first output transistor and a second output transistor, a first electrode of the first output transistor is electrically connected with a first type low potential signal line, a first electrode of the second output transistor is electrically connected with a first type high potential signal line, a second electrode of the first output transistor and a second electrode of the second output transistor are connected with a first signal output end; the display panel comprises:

[0006] a substrate;

[0007] a semiconductor layer arranged on one side of the substrate, the semiconductor layer comprises an active pattern of the first output transistor;

[0008] Wherein, the projection of the active pattern of the first output transistor on the substrate is located within the projection range of the first type low potential signal line on the substrate and the first type high potential signal line on the substrate.

[0009] According to a second aspect of the present application, there is provided a display device comprising the display panel according to any one of the above embodiments.

[0010] The display panel and the display device provided by the embodiments of the present application can make the active pattern of the first output transistor be located in the projection range of the first low potential signal line and the first high potential signal line on the substrate by making the projection of the active pattern of the first output transistor on the substrate be located in the projection range of the first low potential signal line and the first high potential signal line on the substrate, so that the first low potential signal line and the first high potential signal line can shield the light for the active pattern of the first output transistor, avoid the electrical drift of the first output transistor caused by the light, improve the output stability of the gate drive circuit, and avoid display abnormalities.

[0011] Other features and advantages of the present application will be described in detail in the following detailed description of the embodiments. BRIEF DESCRIPTION OF DRAWINGS

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the embodiments will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can also be obtained by those skilled in the art without any creative effort on the basis of these drawings.

[0013] In order to more completely understand the present application and its advantages, the following will be described in conjunction with the drawings, wherein the same reference numerals in the following description represent the same parts.

[0014] Figure 1 A plan view of the display panel provided by the embodiments of the present application is shown.

[0015] Figure 2 A connection schematic diagram of the gate drive circuit and the pixel provided by the embodiments of the present application is shown.

[0016] Figure 3 A first cross-sectional schematic diagram of the display panel provided by the embodiments of the present application is shown.

[0017] Figure 4 A circuit diagram of the pixel drive circuit of the display panel provided by the embodiments of the present application is shown.

[0018] Figure 5 A circuit diagram of the first type of gate circuit and the second type of gate circuit of the gate drive circuit provided by the embodiments of the present application is shown.

[0019] Figure 6 A first type of layer stack diagram of each film layer of the setting area of the first output transistor of the display panel provided by the embodiments of the present application is shown.

[0020] Figure 7 is a cross-sectional view of a display panel in Figure 6 .

[0021] Figure 8 is a cross-sectional view of a display panel in Figure 6 .

[0022] Figure 9 is a cross-sectional view of a display panel in Figure 6 .

[0023] Figure 10 is a cross-sectional view of a display panel in Figure 6 .

[0024] Figure 11 is a cross-sectional view of a display panel in Figure 6 .

[0025] Figure 12 is a cross-sectional view of a display panel in Figure 6 .

[0026] Figure 13 is a cross-sectional view of a display panel in Figure 6 .

[0027] Figure 14 is a cross-sectional view of a display panel in Figure 6 .

[0028] Figure 15 is a cross-sectional view of a display panel in Figure 6 .

[0029] Figure 16 is a cross-sectional view of a display panel in Figure 6 .

[0030] Figure 17 is a cross-sectional view of a display panel in Figure 6 .

[0031] Figure 18 is a cross-sectional view of a display panel in Figure 6 .

[0032] Figure 19 is a second cross-sectional schematic view of a display panel provided by an embodiment of the present application.

[0033] Figure 20This is a second stacking diagram of the film layers in the setting area of ​​the first output transistor of the display panel provided in the embodiments of this application.

[0034] Figure 21 for Figure 20 An exploded view of the second gate layer of the display panel.

[0035] Figure 22 for Figure 20 An exploded view of the semiconductor layer of the display panel.

[0036] Figure 23 for Figure 20 An exploded view of the third gate layer of the display panel.

[0037] Figure 24 for Figure 20 An exploded view of the first source-drain layer of the display panel.

[0038] Figure 25 for Figure 20 An exploded view of the second source-drain layer of the display panel.

[0039] Figure 26 for Figure 20 An exploded view of the third source-drain layer of the display panel.

[0040] Figure 27 for Figure 20 An exploded view of the first via of the display panel.

[0041] Figure 28 for Figure 20 An exploded view of the second via of the display panel.

[0042] Figure 29 for Figure 20 An exploded view of the third via in the display panel.

[0043] Figure 30 for Figure 20 The stack-up diagram of the second gate layer and semiconductor layer of the display panel.

[0044] Figure 31 for Figure 20 The stack-up diagram of the second gate layer, semiconductor layer and third gate layer of the display panel.

[0045] Figure 32 for Figure 20 The stack-up diagram of the second gate layer, semiconductor layer, third gate layer and first via of the display panel.

[0046] Figure 33 for Figure 20A cross-sectional view of a display panel in the display device of FIG. 1.

[0047] Figure 34 A cross-sectional view of a display panel in the display device of FIG. 1. Figure 20 A cross-sectional view of a display panel in the display device of FIG. 1.

[0048] Figure 35 A cross-sectional view of a display panel in the display device of FIG. 1. Figure 20 A cross-sectional view of a display panel in the display device of FIG. 1.

[0049] Figure 36 A cross-sectional view of a display panel in the display device of FIG. 1. Figure 20 A cross-sectional view of a display panel in the display device of FIG. 1. DETAILED DESCRIPTION

[0050] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by a person skilled in the art without creative effort, fall within the protection scope of the present application.

[0051] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms “mounting”, “connection”, “connecting”, “electrically connecting”, “electrically connected” should be understood in a broad sense, for example, can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or electrically connected, or can be in communication with each other; can be directly connected, or indirectly connected through an intermediate medium; can be the communication between two elements or the interaction between two elements. For a person skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0052] In order to illustrate the principle of the technical problem of the present application, some comparative display devices are provided. It can be understood that these comparative display devices cannot be used as prior art in the embodiments of the present application. In order to reduce power consumption, the prior display devices will use CMOS GOA circuits to reduce the number of GOA circuits. Specifically, two CMOS GOA circuits are arranged in the first-stage GOA circuit on one side of the comparative display device. One CMOS GOA circuit outputs the scanning signals of the compensation transistors of two rows of pixels and the scanning signals of the switching transistors of the current row of pixels, and the other CMOS GOA circuit outputs the scanning signals of the initialization transistors of two rows of pixels and the scanning signals of the switching transistors of the next row of pixels. A metal oxide thin film transistor is arranged as an output transistor in each CMOS GOA circuit. However, in actual use, it is found that the output transistor is easily affected by external light to cause electrical drift, which leads to unstable scanning signals output by the CMOS GOA circuit, and further leads to abnormal display of the picture during display. Therefore, the prior display device has the technical problem that the output transistor is easily affected by light to cause electrical drift, which further leads to display abnormality.

[0053] The embodiments of the present application aim at the above technical problem and provide a display panel and a display device to solve the above technical problem.

[0054] As shown in Figure 1 The embodiments of the present application provide a display panel 1, which includes a display area 101 and a non-display area 102. The display area 101 is provided with a plurality of rows of pixels 13. Each pixel 13 includes a light emitting device LED and a pixel driving circuit 11 for driving the light emitting device LED. The non-display area 102 is provided with a plurality of stages of gate driving circuits 12. The gate driving circuits 12 can be arranged along a second direction Y. The gate driving circuits 12 are configured to output scanning signals to the pixel driving circuit 11.

[0055] Specifically, in the embodiments of the present application, the pixel 13 can be at least one of a red sub-pixel, a green sub-pixel and a blue sub-pixel. The light emitting colors of the red sub-pixel, the green sub-pixel and the blue sub-pixel are red, green and blue, respectively. It can be understood that each sub-pixel has a light emitting device LED and a pixel driving circuit 11 for driving the light emitting device LED.

[0056] Specifically, as shown in Figure 1As shown, the non-display area 102 can be disposed around the display area 101, but this embodiment is not limited to this. The non-display area 102 can be disposed on one side, two sides, or three sides of the display area 101, and the non-display area 102 can be bent to the back of the display area 101. The non-display area 102 may include an upper border area, a lower border area, a left border area, and a right border area. The gate driving circuit 12 can be disposed in the left border area and / or the right border area. The gate driving circuit 12 can be disposed along the first direction X on one side or both sides of the display area 101.

[0057] like Figure 3 As shown, as a specific structure of a display panel 1 in an embodiment of this application, the display panel 1 includes a substrate 201, a light-shielding layer 202, a buffer layer 203, a barrier layer 204, an active layer 205, a first gate insulating layer 206, a first gate layer 207, a second gate insulating layer 208, a second gate layer 209, a first interlayer insulating layer 210, a semiconductor layer 211, a third gate insulating layer 212, a third gate layer 213, a second interlayer insulating layer 214, a first source-drain layer 215, a first planarization layer 216, a second source-drain layer 217, and a light-emitting functional layer, which are arranged sequentially.

[0058] like Figure 19 As shown, as another specific structure of the display panel 1 in this application embodiment, the display panel 1 further includes a second planarization layer 218 and a third source-drain layer 219.

[0059] Specifically, the light-emitting functional layer may include a pixel electrode layer, a pixel definition layer, a light-emitting material layer, and a common electrode layer.

[0060] Specifically, the material of semiconductor layer 211 includes oxide semiconductor, specifically metal oxide, and more specifically indium gallium zinc oxide.

[0061] Specifically, the active layer 205 is made of silicon semiconductor, specifically low-temperature polycrystalline silicon.

[0062] Specifically, such as Figure 3 As shown, Figure 3 The illustration shows a buffer layer, a blocking layer, and a light-shielding layer, but the embodiments of this application are not limited to this, and one or more of these film layers may be removed.

[0063] like Figure 4 As shown, the pixel driving circuit 11 includes: a driving transistor T31, a switching transistor T32, a compensation transistor T33, a first initialization transistor T34, a first light-emitting transistor T35, a second light-emitting transistor T36, a second initialization transistor T37, and a third initialization transistor T38.

[0064] Specifically, such as Figure 4As shown, the gate of switching transistor T32 is connected to the second scan line Pscan1, the first electrode of switching transistor T32 is connected to the data signal line Data, the second electrode of switching transistor T32 is connected to the first electrode of driving transistor T31, the gate of compensation transistor T33 is connected to the first scan line Nscan1, the second electrode of compensation transistor T33 is connected to the second electrode of first initialization transistor T34, the first electrode of compensation transistor T33 is connected to the second electrode of driving transistor T31, the gate of first initialization transistor T34 is connected to the third scan line Nscan2, the first electrode of first initialization transistor T34 is connected to the first initialization line Vi1, the gate of first light-emitting transistor T35 is connected to the light-emitting control line EM, and the first electrode of first light-emitting transistor T35 is connected to the power supply high-potential signal line VDD. The second electrode of the light-emitting transistor T35 is connected to the first electrode of the driving transistor T31. The gate of the second light-emitting transistor T36 is connected to the light-emitting control line EM. The first electrode of the second light-emitting transistor T36 is connected to the second electrode of the driving transistor T31. The second electrode of the second light-emitting transistor T36 is connected to the light-emitting device LED. The gate of the second initialization transistor T37 is connected to the fourth scan line Pscan2. The first electrode of the second initialization transistor T37 is connected to the second initialization line Vi2. The second electrode of the second initialization transistor T37 is connected to the light-emitting device LED. The gate of the third initialization transistor T38 is connected to the fourth scan line Pscan2. The first electrode of the third initialization transistor T38 is connected to the third initialization line Vi3. The second electrode of the third initialization transistor T38 is connected to the first electrode of the driving transistor T31.

[0065] Specifically, such as Figure 4 As shown, the light-emitting device LED is connected to the low-potential power supply signal line VSS. The pixel driving circuit also includes a storage capacitor Cst and a boost capacitor Cboost. One end of the storage capacitor Cst is connected to the high-potential power supply signal line VDD, and the other end of the storage capacitor Cst is connected to the gate of the driving transistor T31. One end of the boost capacitor Cboost is connected to the gate of the switching transistor T32, and the other end of the boost capacitor Cboost is connected to the gate of the driving transistor T31.

[0066] Specifically, such as Figure 2As shown in the figure, as a specific structure of the display panel 1 in the embodiment of the present application, the gate drive circuit 12 includes a first type of gate circuit 121 and a second type of gate circuit 122, a first signal output end of the first type of gate circuit 121 in the current stage is connected with the gate of the compensation transistor T33 in the adjacent two rows of pixels 13, a second signal output end of the first type of gate circuit 121 in the current stage is connected with the gate of the switch transistor T32 of the current row of pixels 13, a first signal output end of the second type of gate circuit 122 in the current stage is electrically connected with the gate of the first initialization transistor T34 in the adjacent two rows of pixels 13, and a second signal output end of the second type of gate circuit 122 in the current stage is connected with the gate of the switch transistor T32 of the next row of pixels.

[0067] Specifically, as shown in the figure, Figure 2 As shown in the figure, as a specific structure of the display panel 1 in the embodiment of the present application, the gate drive circuit 12 further includes a third type of gate circuit 123 and a fourth type of gate circuit 124, a signal output end of the third type of gate circuit 123 is electrically connected with the gate of the first light-emitting transistor in the adjacent two rows of pixels 13, and a signal output end of the fourth type of gate circuit 124 is electrically connected with the gate of the second initialization transistor in the adjacent two rows of pixels 13.

[0068] Specifically, the drive transistor T31, the switch transistor T32, the first light-emitting transistor T35, the second light-emitting transistor T36, the second initialization transistor T37 and the third initialization transistor T38 are silicon semiconductor transistors, and the compensation transistor T33 and the first initialization transistor T34 are oxide semiconductor transistors.

[0069] Specifically, the drive transistor T31, the switch transistor T32, the first light-emitting transistor T35, the second light-emitting transistor T36, the second initialization transistor T37 and the third initialization transistor T38 are P-type transistors, and the compensation transistor T33 and the first initialization transistor T34 are N-type transistors.

[0070] Specifically, the oxide semiconductor transistor can be a metal oxide transistor, and the silicon semiconductor transistor can be a low-temperature polysilicon transistor.

[0071] As shown in the figure, Figures 1 to 36 As shown in the figure, the embodiment of the present application provides a display panel, which includes a gate drive circuit 12, the gate drive circuit 12 includes a first output unit 30, the first output unit 30 includes a first output transistor T10 and a second output transistor T9, a first electrode of the first output transistor T10 is electrically connected with a first type of low potential signal line NVGL, a first electrode of the second output transistor T9 is electrically connected with a first type of high potential signal line NVGH, and a second electrode of the first output transistor T10 and a second electrode of the second output transistor T9 are connected with a first signal output end Nout(n).

[0072] In some embodiments, as shown in Figures 1 to 36 The display panel 1 includes a substrate 201, a semiconductor layer 211 disposed on one side of the substrate 201, and an active pattern T10A of the first output transistor T10 included in the semiconductor layer 211. A projection of the active pattern T10A of the first output transistor T10 on the substrate 201 is located within a projection range of the first low-potential signal line NVGL and the first high-potential signal line NVGH on the substrate 201.

[0073] The display panel 1 provided by the embodiments of the present application can make the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 located within the projection range of the first low-potential signal line NVGL and the first high-potential signal line NVGH on the substrate 201, so that the first low-potential signal line NVGL and the first high-potential signal line NVGH can shield light for the active pattern T10A of the first output transistor T10, avoid the electrical drift of the first output transistor T10 caused by light, improve the output stability of the gate drive circuit, and avoid display abnormalities.

[0074] In some embodiments, as shown in Figures 1 to 36 The display panel 1 includes a plurality of rows of pixels 13, each pixel 13 including a light-emitting device LED and a pixel drive circuit 11 including a compensation transistor T33 and a first initialization transistor T34. The gate drive circuit 12 is disposed on at least one side of the pixel 13 along a first direction X. Each stage of the gate drive circuit 12 includes a first gate circuit 121 and a second gate circuit 122. The first gate circuit 121 and the second gate circuit 122 each include a first output unit 30. A first signal output end of the first gate circuit 121 is connected to the gate of the compensation transistor T33 of the pixel drive circuit 11 of adjacent two rows. A first signal output end of the second gate circuit 122 is connected to the first initialization transistor T34 of the pixel drive circuit 11 of adjacent two rows.

[0075] In at least one of the first gate circuit 121 and the second gate circuit 122, a projection of the active pattern of the first output transistor T10 on the substrate 201 is located within a projection range of the first low-potential signal line NVGL and the first high-potential signal line NVGH on the substrate 201.

[0076] Specifically, by making the first type of gate circuit 121 and the second type of gate circuit 122 include the first output unit 30, making the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 within the projection of the first type of low potential signal line NVGL and the projection of the first type of high potential signal line NVGH on the substrate 201 in at least one of the first type of gate circuit 121 and the second type of gate circuit 122, the first type of low potential signal line NVGL and the first type of high potential signal line NVGH can shield the active pattern T10A of the first output transistor T10 from light, so that the active pattern T10A of the first output transistor T10 is not affected by light, improving the electrical stability of the first output transistor T10, improving the output stability of at least one of the first type of gate circuit and the second type of gate circuit, and avoiding display abnormalities.

[0077] Specifically, the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 can be made within the projection of the first type of low potential signal line NVGL and the projection of the first type of high potential signal line NVGH on the substrate 201 in the first type of gate circuit 121, thereby improving the output stability of the first type of gate circuit and avoiding display abnormalities.

[0078] Specifically, the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 can be made within the projection of the first type of low potential signal line NVGL and the projection of the first type of high potential signal line NVGH on the substrate 201 in the second type of gate circuit 122, thereby improving the output stability of the first type of gate circuit and avoiding display abnormalities.

[0079] Specifically, the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 can be made within the projection of the first type of low potential signal line NVGL and the projection of the first type of high potential signal line NVGH on the substrate 201 in the first type of gate circuit 121 and the second type of gate circuit 122, thereby improving the output stability of the first type of gate circuit and avoiding display abnormalities.

[0080] Specifically, it can be understood that the first low potential signal line NVGL and the first high potential signal line NVGH are arranged in the arrangement region of the first gate circuit 121 and are also arranged in the arrangement region of the second gate circuit 122, so that the first low potential signal line NVGL and the first high potential signal line NVGH corresponding to the first gate circuit 121 can shield the active pattern of the first output transistor in the first gate circuit 121, and the first low potential signal line NVGL and the first high potential signal line NVGH corresponding to the second gate circuit 122 can shield the active pattern of the first output transistor in the second gate circuit 122.

[0081] Specifically, the specific design of the arrangement region of the first output transistor in the following embodiments is described, and this first output transistor is not limited to the first output transistor of the first gate circuit or the second gate circuit. It can be understood that the design of the arrangement region of the first output transistor in the first gate circuit and the second gate circuit can be referred to the above embodiments.

[0082] In some embodiments, as shown in FIG. 1B, the first low potential signal line NVGL includes a first low potential signal line VGL1 and a second low potential signal line VGL2, and the first high potential signal line NVGH includes a first high potential signal line VGH1 and a second high potential signal line VGH2. Figures 1 to 36 The projection of the active pattern T10A of the first output transistor T10 on the substrate 201 is located within the projection range of the first low potential signal line VGL1 on the substrate 201, the projection of the second low potential signal line VGL2 on the substrate 201, the projection of the first high potential signal line VGH1 on the substrate 201, and the projection of the second high potential signal line VGH2 on the substrate 201.

[0083] Specifically, the first low potential signal line VGL1 is electrically connected with the gate drive circuit of the odd row, the second low potential signal line VGL2 is electrically connected with the gate drive circuit of the even row, the first high potential signal line VGH1 is electrically connected with the gate drive circuit of the odd row, and the second high potential signal line VGH2 is electrically connected with the gate drive circuit of the even row.

[0084] Specifically, the first electrode of the first output transistor T10 of the first type of gate circuit 121 located in the odd-numbered row can be connected with the first low potential signal line VGL1, and the first electrode of the second output transistor T9 of the first type of gate circuit 121 located in the odd-numbered row can be connected with the first high potential signal line VGH1; the first electrode of the first output transistor T10 of the first type of gate circuit 121 located in the even-numbered row can be connected with the second low potential signal line VGL2, and the first electrode of the second output transistor T9 of the first type of gate circuit 121 located in the even-numbered row can be connected with the second high potential signal line VGH2.

[0085] Specifically, the first electrode of the first output transistor T10 of the second type of gate circuit 122 located in the odd-numbered row can be connected with the first low potential signal line VGL1, and the first electrode of the second output transistor T9 of the second type of gate circuit 122 located in the odd-numbered row can be connected with the first high potential signal line VGH1; the first electrode of the first output transistor T10 of the second type of gate circuit 122 located in the even-numbered row can be connected with the second low potential signal line VGL2, and the first electrode of the second output transistor T9 of the second type of gate circuit 122 located in the even-numbered row can be connected with the second high potential signal line VGH2.

[0086] In some embodiments, as shown in Figure 3 、 Figure 6 、 Figure 8 、 Figure 11 The active pattern T10A of the first output transistor T10 includes a first active part 211a, a second active part 211b, a third active part 211c, and a fourth active part 211d. The projection of the first active part 211a on the substrate 201 is located within the projection range of the first low potential signal line VGL1 on the substrate 201, the second active part 211b is located within the projection range of the second low potential signal line VGL2 on the substrate 201, the projection of the third active part 211c on the substrate 201 is located within the projection range of the first high potential signal line VGH1 on the substrate 201, and the projection of the fourth active part 211d on the substrate 201 is located within the projection range of the second high potential signal line VGH2 on the substrate 201. By locating the projections of the first active part 211a, the second active part 211b, the third active part 211c, and the fourth active part 211d on the substrate within the projection ranges of the first low potential signal line VGL1, the second low potential signal line VGL2, the first high potential signal line VGH1, and the second high potential signal line VGH2 on the substrate respectively, the light shielding of each active part can be performed, thereby improving the output stability of at least one of the first type of gate circuit and the second type of gate circuit and avoiding display abnormalities.

[0087] Specifically, as shown in Figure 6 ,Figure 8 As shown in FIG. 1, the active pattern T10A of the first output transistor T10 includes a plurality of active parts, and the plurality of active parts include a first active part 211a, a second active part 211b, a third active part 211c, and a fourth active part 211d.

[0088] Specifically, as shown in FIG. 1, compared with the width of each active part in the comparative display device, the plurality of active parts are combined into four active parts in the embodiment of the present application, and the positions and / or line widths of the active parts, the first low potential signal line VGL1, the second low potential signal line VGL2, the first high potential signal line VGH1, and the second high potential signal line VGH2 are adjusted, so that the first low potential signal line VGL1, the second low potential signal line VGL2, the first high potential signal line VGH1, and the second high potential signal line VGH2 can shade the active pattern of the first output transistor, avoid the active pattern of the first output transistor from being affected by light to cause the electrical property of the first output transistor to drift, improve the output stability of at least one of the first type of gate circuit and the second type of gate circuit, and avoid display abnormalities. Figure 6 Figure 8 Specifically, as shown in FIG. 1, compared with the width of each active part in the comparative display device, the plurality of active parts are combined into four active parts in the embodiment of the present application, and the positions and / or line widths of the active parts, the first low potential signal line VGL1, the second low potential signal line VGL2, the first high potential signal line VGH1, and the second high potential signal line VGH2 are adjusted, so that the first low potential signal line VGL1, the second low potential signal line VGL2, the first high potential signal line VGH1, and the second high potential signal line VGH2 can shade the active pattern of the first output transistor, avoid the active pattern of the first output transistor from being affected by light to cause the electrical property of the first output transistor to drift, improve the output stability of at least one of the first type of gate circuit and the second type of gate circuit, and avoid display abnormalities.

[0089] Specifically, when the active pattern is arranged, the aspect ratio of the active pattern can not be changed, the aspect ratio of the active pattern is not changed, and the electrical property of the first output transistor is better.

[0090] Specifically, it can be understood that each active part includes a plurality of sub-parts, and the plurality of sub-parts are arranged in sequence along the second direction Y.

[0091] In some embodiments, as shown in FIG. 1, the width L4 of the fourth active part 211d is greater than the width L1 of the first active part 211a, the width L4 of the fourth active part 211d is greater than the width L2 of the second active part 211b, and the width L4 of the fourth active part 211d is greater than the width L3 of the third active part. Figure 6 Figure 11 The width L8 of the second high potential signal line VGH2 is greater than the width L5 of the first low potential signal line VGL1, the width L8 of the second high potential signal line VGH2 is greater than the width L6 of the second low potential signal line VGL2, and the width L8 of the second high potential signal line VGH2 is greater than the width L7 of the first high potential signal line VGH1.

[0092] The width L8 of the second high potential signal line VGH2 is greater than the width L5 of the first low potential signal line VGL1, the width L8 of the second high potential signal line VGH2 is greater than the width L6 of the second low potential signal line VGL2, and the width L8 of the second high potential signal line VGH2 is greater than the width L7 of the first high potential signal line VGH1.

[0093] ​​Specifically, when setting the first active portion 211a, the second active portion 211b, the third active portion 211c, and the fourth active portion 211d, the width of the fourth active portion 211d can be greater than the widths of the first active portions 211a, 211b, and 211c. This ensures that the channel width of the active pattern of the first output transistor does not change, and the number of connection holes between the source and drain of the first output transistor and the active pattern of the first output transistor does not change. This results in minimal or no change in the electrical properties of the first output transistor. Correspondingly, the width of the second high-potential signal line VGH2 is greater than the widths of the first low-potential signal line VGL1, the second low-potential signal line VGL2, and the second high-potential signal line VGH2. This allows each signal line to shield each active portion of the first output transistor, preventing the electrical properties of the first output transistor from drifting due to light exposure. This improves the output stability of at least one of the first type of gate circuit and the second type of gate circuit, preventing display abnormalities.

[0094] In some embodiments, such as Figure 3 As shown, the display panel 1 further includes a first source-drain layer 215 and a second source-drain layer 217. The first source-drain layer 215 is disposed on the side of the semiconductor layer 211 away from the substrate 201; the second source-drain layer 217 is disposed on the side of the first source-drain layer 215 away from the semiconductor layer 211. The second source-drain layer 217 includes a first low-potential signal line VGL1, a second low-potential signal line VGL2, a first high-potential signal line VGH1, and a second high-potential signal line VGH2. By including the first low-potential signal line VGL1, the second low-potential signal line VGL2, the first high-potential signal line VGH1, and the second high-potential signal line VGH2 in the second source-drain layer, each signal line can shield the active pattern of the first output transistor from light, and each signal line will not occupy the space of the first source-drain layer, thus reducing the bezel size.

[0095] Specifically, such as Figure 5 As shown, one type of gate circuit 121 and the second type of gate circuit 122 are described. It should be understood that the first type of gate circuit 121 and the second type of gate circuit 122 in the embodiments of this application are not limited thereto.

[0096] like Figure 5 As shown, both the first type of gate circuit 121 and the second type of gate circuit 122 include a first control unit 10, a second control unit 20, a second output unit 40, a frequency division unit 50, an output control unit 60, a reset unit 70, a third control unit 801, a fourth control unit 802, and a switching unit 90.

[0097] The first control unit 10 is electrically connected with the first node K and is configured to control the signal of the first node K according to the corresponding start signal and the clock signal; the second control unit 20 is electrically connected with the first node K and is configured to control the signal of the internal node of the gate drive circuit of the current stage according to the signal of the first node K; the second output unit 40 is electrically connected with the second high potential signal line PVGH, the internal node of the gate drive circuit of the current stage, the third node Q, the first clock signal line CK and the second signal output end Pout(n) and is configured to control the signal of the second signal output end Pout(n) according to the signal of the third node Q, the signal of the internal node of the gate drive circuit of the current stage and the output signal of the first clock signal line CK;

[0098] The frequency division unit 50 includes a first frequency division unit 501 and a second frequency division unit 502; the first frequency division unit 501 is electrically connected with the first node K, the fourth node W and the internal node of the gate drive circuit of the current stage and is configured to control the signal transmission between the first node K and the fourth node W according to the signal of the internal node of the gate drive circuit of the current stage and the corresponding frequency division control signal; the second frequency division unit 502 is electrically connected with the first node K, the fifth node M and the internal node of the gate drive circuit of the current stage and is configured to control the signal transmission between the first node K and the fifth node M according to the signal of the internal node of the gate drive circuit of the current stage and the corresponding frequency division control signal;

[0099] The output control unit 60 is electrically connected with the second clock signal line XCK, the first node K and the internal node of the gate drive circuit of the current stage and is configured to control the signal of the first node K according to the signal of the internal node of the gate drive circuit of the current stage and the signal of the second clock signal line XCK; the reset unit 70 is electrically connected with the control signal line Control and the first node K and is configured to control the signal of the first node K according to the signal of the control signal line Control;

[0100] The third control unit 801 is electrically connected with the internal node of the gate drive circuit of the current stage and the fourth node W and is configured to control the signal of the fourth node W according to the signal of the internal node of the gate drive circuit of the current stage; the fourth control unit 802 is electrically connected with the internal node of the gate drive circuit of the current stage and the fifth node M and is configured to control the signal of the fifth node M according to the signal of the internal node of the gate drive circuit of the current stage; the switch unit 90 is electrically connected with the third node Q, the fifth node M and the switch signal line SC and is configured to control the signal transmission between the third node Q and the fifth node M according to the signal of the switch signal line SC; wherein the first output unit 30 is electrically connected with the first node K and the fourth node W.

[0101] Specifically, in the embodiments of this application, the internal nodes of the current-level gate driving circuit refer to the internal nodes of the first type of gate circuit and the internal nodes of the second type of gate circuit in the current-level gate driving circuit. It can be understood that, in the first type of gate circuit, the internal nodes of the current-level gate driving circuit refer to the internal nodes of the first type of gate circuit in the current-level gate driving circuit, and in the second type of gate circuit, the internal nodes of the current-level gate driving circuit refer to the internal nodes of the second type of gate circuit in the current-level gate driving circuit. Similarly, the meaning of the internal nodes of the previous-level gate driving circuit can be determined, which will not be repeated in the following embodiments.

[0102] Specifically, the start signal is the first start signal line STV1, the second start signal line STV2, or the signal of an internal node of the previous stage gate drive circuit. It can be understood that in the first type of gate circuit, the corresponding start signal is the first start signal line STV1 or the signal of an internal node of the first type of gate circuit of the previous stage gate drive circuit; in the second type of gate circuit, the corresponding start signal is the second start signal line STV2 or the signal of an internal node of the second type of gate circuit of the previous stage gate drive circuit.

[0103] In some embodiments, such as Figures 1 to 36 As shown, the gate of the first output transistor T10 is electrically connected to the first node K, and the gate of the second output transistor T9 is electrically connected to the fourth node W.

[0104] The second output unit 40 includes a third output transistor T6 and a fourth output transistor T7. The gate of the third output transistor T6 is electrically connected to the third node Q. The first electrode of the third output transistor T6 is electrically connected to the first type of clock signal line CK. The second electrode of the third output transistor T6 is electrically connected to the second electrode of the fourth output transistor T7. The second electrode of the third output transistor T6 is electrically connected to the second signal output terminal Pout(n). The gate of the fourth output transistor T7 is electrically connected to the internal node of the gate drive circuit of this stage. The first electrode of the fourth output transistor T7 is electrically connected to the second type of high potential signal line PVGH.

[0105] The display panel 1 further includes an active layer 205, which is disposed between the substrate 201 and the semiconductor layer 211. The active layer 205 is made of silicon semiconductor. The semiconductor layer 211 is made of oxide semiconductor. The active layer 205 includes an active pattern of the second output transistor T9, the third output transistor T6 and the fourth output transistor T7.

[0106] Specifically, since the active patterns of the second output transistor T9, the third output transistor T6, and the fourth output transistor T7 are all formed using an active layer 205, and the active layer is close to the substrate, and the gate shielding and other traces above the active layer will cause obstruction, making it difficult for light to reach the active layer; while the active pattern of the first output transistor T10 is formed using a semiconductor layer, which is far from the substrate and close to the light-emitting surface of the display panel, and the gate of the first output transistor T10 cannot completely shield the active pattern, making it easy for light to reach the active pattern of the first output transistor T10, resulting in the first output transistor... The performance of transistor T10 changes, so the projection of the active pattern T10A of the first output transistor T10 onto the substrate 201 can be located within the projection range of the first low-potential signal line NVGL onto the substrate 201 and the first high-potential signal line NVGH onto the substrate 201. This allows the first low-potential signal line NVGL and the first high-potential signal line NVGH to block the light from the active pattern T10A of the first output transistor T10, preventing the first output transistor T10 from being affected by light and causing electrical drift, improving the output stability of the gate drive circuit, and avoiding display abnormalities.

[0107] like Figure 5 As shown, both the first type of gate circuit 121 and the second type of gate circuit 122 include a first control unit 10. The first control unit includes a first control transistor T13 and a second control transistor T12. In the first type of gate circuit 121, the gates of the first control transistor T13 and the second control transistor T12 are connected to the first initial signal line STV1 or the internal node P(n-1) of the first type of gate circuit 121 in the previous stage gate driving circuit. In the second type of gate circuit 122, the gates of the first control transistor T13 and the second control transistor T12 are connected to the second initial signal line STV2 or the internal node P(n-1) of the second type of gate circuit 122 in the previous stage gate driving circuit. The first electrode of the first control transistor T13 and the first electrode of the second control transistor T12 are electrically connected to the first node K. The second electrode of the first control transistor T13 is connected to the second type low potential signal line PVGL, and the second electrode of the second control transistor T12 is connected to the second type high potential signal line PVGH.

[0108] Specifically, it is understandable that in Figure 5In the first stage gate drive circuit, the first type gate circuit 121 is electrically connected to the first start signal line STV1, and in other stage gate drive circuits, the first type gate circuit 121 is electrically connected to the internal node P(n-1) of the first type gate circuit 121 in the previous stage gate drive circuit, the second type gate circuit 122 in the first stage gate drive circuit is electrically connected to the second start signal line STV2, and the second type gate circuit 122 in other stage gate drive circuits is electrically connected to the internal node P(n-1) of the second type gate circuit 122 in the previous stage gate drive circuit.

[0109] Specifically, the first start signal line STV1 and the second start signal line STV2 have different time sequences.

[0110] Specifically, as shown in FIG. 1, the first control unit 10 further includes a ninth control transistor T2, a gate of the ninth control transistor T2 is connected to the second type clock signal line XCK, a first electrode of the ninth control transistor T2 is connected to the first node K, and a second electrode of the ninth control transistor T2, a first electrode of the first control transistor T13 and a first electrode of the second control transistor T12 are connected to the second node O. Figure 5

[0111] Specifically, as shown in FIG. 1, the first type gate circuit 121 and the second type gate circuit 122 each include a second control unit 20, the second control unit 20 includes a third control transistor T1 and a fourth control transistor T3, a gate of the third control transistor T1 and a gate of the fourth control transistor T3 are connected to the first node K, a first electrode of the third control transistor T1 and a first electrode of the fourth control transistor T3 are connected to the internal node P(n) of the first type gate circuit or the second type gate circuit of the current stage gate drive circuit, a second electrode of the third control transistor T1 is connected to the second type low potential signal line PVGL, and a second electrode of the fourth control transistor T3 is connected to the second type high potential signal line PVGH. Figure 5

[0112] Specifically, as shown in FIG. 1, the first type gate circuit 121 and the second type gate circuit 122 each include a first output unit 30, the first output unit 30 includes a first output transistor T10 and a second output transistor T9, a gate of the first output transistor T10 is connected to the first node K, a gate of the second output transistor T9 is electrically connected to the first node K, a second electrode of the first output transistor T10 and a second electrode of the second output transistor T9 are connected to the first signal output end Nout(n), a first electrode of the first output transistor T10 is connected to the first type low potential signal line NVGL, and a first electrode of the second output transistor T9 is connected to the first type high potential signal line NVGH. Figure 5 ​​​

[0113] Specifically, it can be understood that the first signal output terminal Nout(n) of the first type of gate circuit 121 is electrically connected to the gate of the compensation transistor T33 in the two adjacent rows of pixels 13, and the first signal output terminal Nout(n) of the second type of gate circuit 122 is electrically connected to the gate of the first initialization transistor T34 in the two adjacent rows of pixels 13.

[0114] Specifically, such as Figure 5 As shown, both the first type gate circuit 121 and the second type gate circuit 122 include a second output unit 40. The second output unit 40 includes a third output transistor T6, a fourth output transistor T7, and a first capacitor C1. The gate of the third output transistor T6 is connected to the third node Q. The first electrode of the third output transistor T6 is connected to the first type clock signal line CK. The second electrode of the third output transistor T6 is connected to the second electrode of the fourth output transistor T7. The second electrode of the third output transistor T6 is connected to the second signal output terminal Pout(n). The gate of the fourth output transistor T7 is connected to the internal node P(n) of the first type gate circuit or the second type gate circuit of this stage gate drive circuit. The first electrode of the fourth output transistor T7 is connected to the second type high potential signal line PVGH. The first plate of the first capacitor C1 is connected to the gate of the third output transistor T6. The second plate of the first capacitor C1 is connected to the second signal output terminal Pout(n).

[0115] Specifically, the second signal output terminal Pout(n) of the first type of gate circuit 121 is electrically connected to the gate of the switching transistor T32 of the current row pixel 13, and the second signal output terminal Pout(n) of the second type of gate circuit 122 is electrically connected to the gate of the switching transistor T32 of the next row pixel.

[0116] Specifically, such as Figure 5As shown in the figure, the first type gate circuit 121 and the second type gate circuit 122 both include a frequency division unit 50, the frequency division unit 50 includes a first frequency division unit 501 and a second frequency division unit 502, the first frequency division unit includes a first frequency division transistor T16, a second frequency division transistor T11 and a second capacitor C2, the gate of the first frequency division transistor T16 is connected with the internal node P(n) of the first type gate circuit or the second type gate circuit of the gate drive circuit of the current stage, the second electrode of the first frequency division transistor T16, the first plate of the second capacitor C2 and the gate of the second frequency division transistor T11 are connected, the first electrode of the first frequency division transistor T16 is connected with the second frequency signal line NLF, the first electrode of the second frequency division transistor T11 is connected with the second plate of the second capacitor C2 at the fourth node W, and the second electrode of the second frequency division transistor T11 is connected at the first node K; the second frequency division unit 502 includes a third frequency division transistor T20, a fourth frequency division transistor T19 and a third capacitor C3, the gate of the third frequency division transistor T20 is connected with the internal node P(n) of the first type gate circuit or the second type gate circuit of the gate drive circuit of the current stage, the first electrode of the third frequency division transistor T20, the first plate of the third capacitor C3 and the gate of the fourth frequency division transistor T19 are connected, the second electrode of the third frequency division transistor T20 is connected with the first frequency signal line PLF, the first electrode of the fourth frequency division transistor T19 is connected with the second plate of the third capacitor C3 at the fifth node M, and the second electrode of the fourth frequency division transistor T19 is connected at the first node K.

[0117] Specifically, as shown in the figure, Figure 5 the first type gate circuit 121 and the second type gate circuit 122 both include an output control unit 60, the output control unit 60 includes a first switch transistor T4, a second switch transistor T5 and a third switch transistor T14, the gate of the first switch transistor T4 is connected with the second type clock signal line XCK, the first electrode of the first switch transistor T4 is connected with the second electrode of the second switch transistor T5, the second electrode of the first switch transistor T4 is connected at the first node K, the gate of the second switch transistor T5 is connected with the gate of the third switch transistor T14, the first electrode of the third control transistor T1, the first electrode of the second switch transistor T5 is connected with the second type high potential signal line PVGH, the second electrode of the third switch transistor T14 is connected at the first node K, and the first electrode of the third switch transistor T14 is connected with the first type low potential signal line NVGL.

[0118] Specifically, as shown in the figure, Figure 5As shown in the figure, the first type of gate circuit 121 and the second type of gate circuit 122 both include a reset unit 70, the reset unit 70 includes a reset transistor T15, the gate of the reset transistor T15 is connected with a control signal line Control, the second electrode of the reset transistor T15 is connected with a first node K, and the first electrode of the reset transistor T15 is connected with a second type of high potential signal line PVGH.

[0119] Specifically, the control signal line can include a first control signal line and a second control signal line, the reset transistor T15 of the first type of gate circuit 121 is electrically connected with the first control signal line, the reset transistor T15 of the second type of gate circuit 122 is electrically connected with the second control signal line, and the timing of the first control signal line and the second control signal line can be the same or different.

[0120] Specifically, as shown in the figure, Figure 5 As shown in the figure, the first type of gate circuit 121 and the second type of gate circuit 122 both include a third control unit 801, the third control unit 801 includes a fifth control transistor T17 and a sixth control transistor T18, the gate of the fifth control transistor T17 is connected with a second type of clock signal line XCK, the second electrode of the fifth control transistor T17 and the second electrode of the sixth control transistor T18 are connected, the first electrode of the fifth control transistor T17 is electrically connected with the first node K, the gate of the sixth control transistor T18 is connected with the gate of the third switch transistor T14, and the first electrode of the sixth control transistor T18 is connected with a second type of high potential signal line PVGH.

[0121] Specifically, as shown in the figure, Figure 5 As shown in the figure, the first type of gate circuit 121 and the second type of gate circuit 122 both include a fourth control unit 802, the fourth control unit 802 includes a seventh control transistor T21 and an eighth control transistor T22, the gate of the seventh control transistor T21 is connected with a second type of clock signal line XCK, the second electrode of the seventh control transistor T21 and the second electrode of the eighth control transistor T22 are connected, the first electrode of the seventh control transistor T21 is electrically connected with the first node K, the gate of the eighth control transistor T22 is connected with the gate of the third switch transistor T14, and the first electrode of the eighth control transistor T22 is connected with a second type of high potential signal line PVGH.

[0122] Specifically, as shown in the figure, Figure 5As shown, the first type of gate circuit 121 and the second type of gate circuit 122 each include a switching unit 90, the switching unit 90 includes a fourth switching transistor T8, a gate of the fourth switching transistor T8 is connected to a switching signal line SC, the switching signal line SC is connected to an internal node P(n-2) of the upper two stages of the first type of gate circuit 121 or the upper two stages of the second type of gate circuit 122, a first electrode of the fourth switching transistor T8 is connected to a third node Q, and a second electrode of the fourth switching transistor T8 is connected to a fifth node M.

[0123] Specifically, the first control transistor T13, the third control transistor T1, the fifth control transistor T17, the seventh control transistor T21, the first switching transistor T4, the third switching transistor T14, and the first output transistor T10 can be oxide semiconductor transistors.

[0124] Specifically, the first control transistor T13, the third control transistor T1, the fifth control transistor T17, the seventh control transistor T21, the first switching transistor T4, the third switching transistor T14, and the first output transistor T10 can be N-type transistors.

[0125] Specifically, the second control transistor T12, the fourth control transistor T3, the sixth control transistor T18, the eighth control transistor T22, the ninth control transistor T2, the second switching transistor T5, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first frequency division transistor T16, the second frequency division transistor T11, the third frequency division transistor T20, the fourth frequency division transistor T19, the reset transistor T15, and the fourth switching transistor T8 can be silicon semiconductor transistors.

[0126] Specifically, the second control transistor T12, the fourth control transistor T3, the sixth control transistor T18, the eighth control transistor T22, the ninth control transistor T2, the second switching transistor T5, the second output transistor T9, the third output transistor T6, the fourth output transistor T7, the first frequency division transistor T16, the second frequency division transistor T11, the third frequency division transistor T20, the fourth frequency division transistor T19, the reset transistor T15, and the fourth switching transistor T8 can be P-type transistors.

[0127] Specifically, the first control transistor T13, the third control transistor T1, the fifth control transistor T17, the seventh control transistor T21, the first switching transistor T4, the third switching transistor T14, and the first output transistor T10 can be double-gate transistors, but the embodiments of the present application are not limited thereto, and they can be single-gate transistors.

[0128] Specifically, in the above embodiments, the first electrode of the transistor is the source and the second electrode is the drain; or in the above embodiments, the first electrode of the transistor is the drain and the second electrode is the source.

[0129] Specifically, such as Figures 6 to 18 As shown, the structure of each film layer in the setting area of ​​the first output transistor is explained.

[0130] like Figure 7 As shown, the second gate layer 209 includes the first gate T10Ga of the first output transistor T10; as Figure 8 As shown, the semiconductor layer 211 includes the active pattern T10A of the first output transistor T10; as Figure 9 As shown, the third gate layer 213 includes the second gate T10Gb of the first output transistor T10; as Figure 10 As shown, the first source-drain layer 215 includes the first electrode T10S of the first output transistor T10 and the second electrode T10D of the first output transistor T10; as Figure 11 As shown, the second source-drain layer 217 includes a first low-potential signal line VGL1, a second low-potential signal line VGL2, a first high-potential signal line VGH1, and a second high-potential signal line VGH2 arranged sequentially along the first direction X. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees.

[0131] Meanwhile, to illustrate the location of the vias that pass between different membrane layers, [the following is provided] Figures 12 to 13 ,like Figure 12 As shown, Figure 12 The location of the first via 311 is shown. The first via 311 refers to a via etched from the first source / drain layer to the semiconductor layer and the third gate layer. For example... Figure 13 As shown, Figure 13 The location of the second via 312 is shown. The second via 312 refers to the via etched from the second source-drain layer to the first source-drain layer, specifically the via of the first planarization layer.

[0132] Furthermore, to illustrate the relative positional relationships of the various film layers, the following are provided: Figures 14 to 18 Specifically, such as Figure 14 As shown, the relative positions of each structure can be seen when the second gate layer and semiconductor layer are stacked. Figure 15 As shown, the relative positions of the various structures when the second gate layer, semiconductor layer, and third gate layer are stacked can be observed. Figure 16 As shown, the relative positions of the various structures—the second gate layer, the semiconductor layer, the third gate layer, and the first via stack—can be observed. Figure 17As shown in FIG. 6, the relative positions of the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, and the second source-drain layer can be seen when they are arranged in a stack. Figure 18 As shown in FIG. 6, the relative positions of the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, and the second source-drain layer can be seen when they are arranged in a stack. Figure 6 As shown in FIG. 6, the relative positions of the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, and the second source-drain layer can be seen when they are arranged in a stack.

[0133] Specifically, in the embodiments of the present application, since some of the thin film transistors adopt double-gate design, when the first gate and the second gate of the thin film transistor are not distinguished, the gate of the thin film transistor refers to the two gates of the thin film transistor. For example, in some of the embodiments of the present application, the first output transistor T10 includes the first gate T10Ga and the second gate T10Gb, and when the gate of the first output transistor is connected with the gate of another transistor, it means that the first gate and the second gate of the first output transistor are both connected with the gate of the other transistor. Similarly, when other thin film transistors also include double gates, refer to the above description, and no further description is given here.

[0134] Specifically, in the circuit diagrams in the embodiments of the present application, in order to illustrate the connection relationship of each transistor, each transistor will have a gate, a first electrode and a second electrode, but in the actual design process, in order to reduce the occupied space of the transistor, the electrodes of some transistors will adopt the same structure to form, which can be understood as the electrodes of two transistors. Similarly, the structure of the electrodes of other transistors can be determined.

[0135] In some embodiments, as shown in FIG. 6, the first output transistor T10 includes the first gate T10Ga and the second gate T10Gb, and the second output transistor T20 includes the first gate T20Ga and the second gate T20Gb. Figure 19 、 Figure 20 、 Figure 25 、 Figure 26As shown, the display panel 1 further includes a first source-drain layer 215, a second source-drain layer 217 and a third source-drain layer 219. The first source-drain layer 215 is disposed on a side of the semiconductor layer 211 away from the substrate 201. The second source-drain layer 217 is disposed on a side of the first source-drain layer 215 away from the semiconductor layer 211. The second source-drain layer 217 includes a first portion VGL1a of the first low potential signal line VGL1, a first portion VGL2a of the second low potential signal line VGL2, a first portion VGH1a of the first high potential signal line VGH1 and a first portion VGH2a of the second high potential signal line VGH2. The third source-drain layer 219 is disposed on a side of the second source-drain layer 217 away from the first source-drain layer 215. The third source-drain layer 219 includes a second portion VGL1b of the first low potential signal line VGL1, a second portion VGL2b of the second low potential signal line VGL2, a second portion VGH1b of the first high potential signal line VGH1 and a second portion VGH2b of the second high potential signal line VGH2. The second portion VGL1b of the first low potential signal line VGL1, the second portion VGL2b of the second low potential signal line VGL2, the second portion VGH1b of the first high potential signal line VGH1 and the second portion VGH2b of the second high potential signal line VGH2 are respectively connected to the first portion VGL1a of the first low potential signal line VGL1, the first portion VGL2a of the second low potential signal line VGL2, the first portion VGH1a of the first high potential signal line VGH1 and the first portion VGH2a of the second high potential signal line VGH2.

[0136] The projection of the active pattern T10A of the first output transistor T10 on the substrate 201 is located within the projection of the first portion VGL1a of the first low potential signal line VGL1 on the substrate 201, the projection of the first portion VGL2a of the second low potential signal line VGL2 on the substrate 201, the projection of the first portion VGH1a of the first high potential signal line VGH1 on the substrate 201, the projection of the first portion VGH2a of the second high potential signal line VGH2 on the substrate 201, the projection of the second portion VGL1b of the first low potential signal line VGL1 on the substrate 201, the projection of the second portion VGL2b of the second low potential signal line VGL2 on the substrate 201, the projection of the second portion VGH1b of the first high potential signal line VGH1 on the substrate 201 and the projection of the second portion VGH2b of the second high potential signal line VGH2 on the substrate 201.

[0137] Specifically, by including two parts of the first low potential signal line, the second low potential signal line, the first high potential signal line and the second high potential signal line in the second source-drain layer and the third source-drain layer, the impedance of the first low potential signal line, the second low potential signal line, the first high potential signal line and the second high potential signal line can be reduced, and the two parts of the first low potential signal line, the second low potential signal line, the first high potential signal line and the second high potential signal line can cooperate to shield light for the active pattern, improve the electrical stability of the first output transistor T10, improve the output stability of at least one of the first type of gate circuit and the second type of gate circuit, and avoid display abnormalities.

[0138] In some embodiments, as shown in Figure 20 、 Figure 25 、 Figure 26 Specifically, the width H2 of the first part VGL2a of the second low potential signal line VGL2 is greater than the width H1 of the first part VGL1a of the first low potential signal line VGL1, and the width H6 of the second part VGL2b of the second low potential signal line VGL2 is less than the width H5 of the second part VGL1b of the first low potential signal line VGL1; the width H4 of the first part VGH2a of the second high potential signal line VGH2 is greater than the width H3 of the first part VGH1a of the first high potential signal line VGH1, and the width H8 of the second part VGH2b of the second high potential signal line VGH2 is less than the width H7 of the second part VGH1b of the first high potential signal line VGH1.

[0139] Specifically, the projection of the active pattern T10A of the first output transistor T10 on the substrate 201 is located within the projection of the second part VGL1b of the first low potential signal line VGL1 on the substrate 201, the projection of the first part VGL2a of the second low potential signal line VGL2 on the substrate 201, the projection of the second part VGH1b of the first high potential signal line VGH1 on the substrate 201, and the projection of the first part VGH2a of the second high potential signal line VGH2 on the substrate 201.

[0140] Specifically, as shown in Figure 25 、 Figure 26As shown in FIG. 1, it can be seen that the width H2 of the first part VGL2a of the second low potential signal line VGL2 is greater than the width H1 of the first part VGL1a of the first low potential signal line VGL1, and the width H6 of the second part VGL2b of the second low potential signal line VGL2 is less than the width H5 of the second part VGL1b of the first low potential signal line VGL1, so that the active pattern of the first output transistor is shaded by the second part VGL1b of the first low potential signal line VGL1 and the first part VGL2a of the second low potential signal line VGL2 without increasing additional space, and the frame of the display panel does not need to be enlarged.

[0141] Specifically, as shown in FIG. 1, Figure 25 , Figure 26 it can be seen that the width H4 of the first part VGH2a of the second high potential signal line VGH2 is greater than the width H3 of the first part VGH1a of the first high potential signal line VGH1, and the width H8 of the second part VGH2b of the second high potential signal line VGH2 is less than the width H7 of the second part VGH1b of the first high potential signal line VGH1, so that the active pattern of the first output transistor is shaded by the second part VGH1b of the first high potential signal line VGH1 and the first part VGH2a of the second high potential signal line VGH2 without increasing additional space, and the frame of the display panel does not need to be enlarged.

[0142] Specifically, as shown in FIG. 1, Figure 20 , Figure 25 it can be seen that there is a gap between the first part VGL1a of the first low potential signal line VGL1, the first part VGL2a of the second low potential signal line VGL2, the first part VGH1a of the first high potential signal line VGH1, and the first part VGH2a of the second high potential signal line VGH2, and the second part VGL1b of the first low potential signal line VGL1 and the second part VGH1b of the first high potential signal line VGH1 can shield each gap, so that each part of each signal line can be staggered to shade the active pattern of the first output transistor, and the frame of the display panel does not need to be enlarged.

[0143] In some embodiments, as shown in FIG. 1, Figure 26 , Figure 20 , Figure 22As shown, the projection of the first portion VGL2a of the second low potential signal line VGL2 on the substrate 201 overlaps with the projection of the second portion VGL1b of the first low potential signal line VGL1 on the substrate 201, and the projection of the first portion VGH2a of the second high potential signal line VGH2 on the substrate 201 overlaps with the projection of the second portion VGH1b of the first high potential signal line VGH1 on the substrate 201; wherein the projection of the first portion VGL2a of the second low potential signal line VGL2 on the substrate 201 is spaced apart from the projection of the second portion VGH1b of the first high potential signal line VGH1 on the substrate 201.

[0144] Specifically, by overlapping the projection of the first portion VGL2a of the second low potential signal line VGL2 on the substrate 201 with the projection of the second portion VGL1b of the first low potential signal line VGL1 on the substrate 201, the second portion VGL1b of the first low potential signal line VGL1 can shield the active part from light, and avoid increasing the frame, and by overlapping the projection of the first portion VGH2a of the second high potential signal line VGH2 on the substrate 201 with the projection of the second portion VGH1b of the first high potential signal line VGH1 on the substrate 201, the first portion VGH2a of the second high potential signal line VGH2 and the second portion VGH1b of the first high potential signal line VGH1 can shield the active part from light, and avoid increasing the frame.

[0145] Specifically, by spacing apart the projection of the first portion VGL2a of the second low potential signal line VGL2 on the substrate 201 from the projection of the second portion VGH1b of the first high potential signal line VGH1 on the substrate 201, interference between the second low potential signal line VGL2 and the first high potential signal line VGH1 is avoided, and the stability of the output signal of the gate drive circuit is improved.

[0146] In some embodiments, as Figure 25 , Figure 26 , Figures 20 to 36 , Figure 21As shown, the active pattern of the first output transistor includes a plurality of active portions 211e. The number of active portions 211e located within the projection range of the second portion VGL1b of the first low-potential signal line VGL1 on the substrate 201 and the first portion VGL2a of the second low-potential signal line VGL2 on the substrate 201 is less than the number of active portions 211e located within the projection range of the second portion VGH1b of the first high-potential signal line VGH1 on the substrate 201 and the first portion VGH2a of the second high-potential signal line VGH2 on the substrate 201.

[0147] Specifically, when setting the active pattern of the first output transistor, the active pattern of the first output transistor includes seven spaced active portions 211e. This allows three active portions 211e to be located within the projection range of the second portion VGL1b of the first low-potential signal line VGL1 on the substrate 201 and the first portion VGL2a of the second low-potential signal line VGL2 on the substrate 201. Four active portions 211e are located within the projection range of the second portion VGH1b of the first high-potential signal line VGH1 on the substrate 201 and the first portion VGH2a of the second high-potential signal line VGH2 on the substrate 201. This ensures that each signal line blocks light from the active pattern of the first output transistor, improving the electrical stability of the first output transistor T10, improving the output stability of at least one of the first and second type gate circuits, and preventing display abnormalities.

[0148] Specifically, such as Figure 22 As shown, the structure of each film layer in the setting area of ​​the first output transistor is explained.

[0149] like Figure 23 As shown, the second gate layer 209 includes the first gate T10Ga of the first output transistor T10; as Figure 24 As shown, the semiconductor layer 211 includes the active pattern T10A of the first output transistor T10; as Figure 25 As shown, the third gate layer 213 includes the second gate T10Gb of the first output transistor T10; as Figure 26 As shown, the first source-drain layer 215 includes the first electrode T10S of the first output transistor T10 and the second electrode T10D of the first output transistor T10; as Figures 27 to 29As shown, the second source-drain layer 217 includes a first portion VGL1a of a first low-potential signal line VGL1, a first portion VGL2a of a second low-potential signal line VGL2, a first portion VGH1a of a first high-potential signal line VGH1, and a first portion VGH2a of a second high-potential signal line VGH2, arranged sequentially along the first direction X. The angle between the first direction X and the second direction Y is greater than 0 and less than or equal to 90 degrees. Figure 27 As shown, the third source-drain layer 219 includes a second part VGL1b of a first low-potential signal line VGL1, a second part VGL2b of a second low-potential signal line VGL2, a second part VGH1b of a first high-potential signal line VGH1, and a second part VGH2b of a second high-potential signal line VGH2, which are sequentially arranged along the first direction X.

[0150] Meanwhile, to illustrate the location of the vias that pass between different membrane layers, [the following is provided] Figure 27 ,like Figure 28 As shown, Figure 28 The location of the first via 311 is shown. The first via 311 refers to a via etched from the first source / drain layer to the semiconductor layer and the third gate layer. For example... Figure 29 As shown, Figure 28 The location of the second via 312 is shown. The second via 312 refers to the via etched from the second source / drain layer to the first source / drain layer, specifically the via in the first planarization layer. Figures 30 to 36 As shown, Figure 30 The location of the third via 313 is shown. The third via 313 refers to the via etched from the third source-drain layer to the second source-drain layer, specifically the via of the second planarization layer.

[0151] Furthermore, to illustrate the relative positional relationships of the various film layers, the following are provided: Figure 31 Specifically, such as Figure 32 As shown, the relative positions of each structure can be seen when the second gate layer and semiconductor layer are stacked. Figure 33 As shown, the relative positions of the various structures when the second gate layer, semiconductor layer, and third gate layer are stacked can be observed. Figure 34 As shown, the relative positions of the various structures—the second gate layer, the semiconductor layer, the third gate layer, and the first via stack—can be observed. Figure 35 As shown, the relative positions of the various structures—the second gate layer, the semiconductor layer, the third gate layer, the first via, and the first source / drain layer—are visible when the layers are stacked. Figure 36 As shown, the relative positions of the various structures—the second gate layer, semiconductor layer, third gate layer, first via, first source / drain layer, and second via—are visible when the stack is configured. Figure 20As shown in FIG. 6, the relative positions of each structure can be seen when the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, the second via, and the second source-drain layer are stacked. ​ As shown in FIG. 6, the relative positions of each structure can be seen when the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, the second via, and the second source-drain layer are stacked. ​ As shown in FIG. 6, the relative positions of each structure can be seen when the second gate layer, the semiconductor layer, the third gate layer, the first via, the first source-drain layer, the second via, and the second source-drain layer are stacked.

[0152] Specifically, the drawings in the embodiments of the present application show the design of the setting area of the first output transistor in the first type of gate circuit and / or the second type of gate circuit in the gate drive circuit on one side of the display panel, and specifically, the design of the setting area of the first output transistor in the first type of gate circuit and / or the second type of gate circuit in the gate drive circuit on the left side of the display panel can be understood. When the gate drive circuit is provided on both sides of the display panel, the design of the setting area of the first output transistor in the gate drive circuit on the other side of the display panel can be symmetrical or identical to the design of the setting area of the first output transistor in the gate drive circuit on this side.

[0153] Specifically, the above embodiments respectively describe the display panel from various circuits, various film layers, various structures, and combinations thereof. It can be understood that when there is no conflict between the embodiments, the embodiments can be combined, for example, the material of the active layer 205 includes a silicon semiconductor material, and the material of the semiconductor layer 211 includes an oxide semiconductor.

[0154] Meanwhile, the present application provides a display device, which comprises the display panel according to any one of the above embodiments.

[0155] Specifically, the display device can further comprise a power supply and a driving board.

[0156] In the description of the present application, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first", "second" can explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0157] In the above embodiments, the description of each embodiment has its own emphasis, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments.

[0158] The embodiments, implementation manners and related technical features of the present application can be combined with each other without conflict.

[0159] The above is only a preferred embodiment of the present application, and does not limit the present application in any form. Any simple modification, equivalent change and modification made to the above embodiment according to the technical essence of the present application without departing from the technical solution content of the present application still falls within the scope of the technical solution of the present application.

Claims

1. A display panel, characterized by, The display panel comprises: a substrate; a semiconductor layer disposed on one side of the substrate, the semiconductor layer comprising an active pattern of the first output transistor; wherein a projection of the active pattern of the first output transistor on the substrate is located within a projection range of the first low-potential signal line on the substrate and a projection range of the first high-potential signal line on the substrate.

2. The display panel of claim 1, wherein, The first low-potential signal line comprises a first low-potential signal line and a second low-potential signal line, and the first high-potential signal line comprises a first high-potential signal line and a second high-potential signal line; wherein a projection of the active pattern of the first output transistor on the substrate is located within a projection range of the first low-potential signal line on the substrate, a projection range of the second low-potential signal line on the substrate, a projection range of the first high-potential signal line on the substrate, and a projection range of the second high-potential signal line on the substrate.

3. The display panel of claim 2, wherein, The active pattern of the first output transistor comprises a first active part, a second active part, a third active part, and a fourth active part, wherein a projection of the first active part on the substrate is located within a projection range of the first low-potential signal line on the substrate, the second active part is located within a projection range of the second low-potential signal line on the substrate, a projection of the third active part on the substrate is located within a projection range of the first high-potential signal line on the substrate, and a projection of the fourth active part on the substrate is located within a projection range of the second high-potential signal line on the substrate.

4. The display panel of claim 3, wherein, The width of the fourth active part is greater than the width of the first active part, the width of the fourth active part is greater than the width of the second active part, and the width of the fourth active part is greater than the width of the third active part. The width of the second high-potential signal line is greater than the width of the first low-potential signal line, the width of the second high-potential signal line is greater than the width of the second low-potential signal line, and the width of the second high-potential signal line is greater than the width of the first high-potential signal line.

5. The display panel of claim 3, wherein, The display panel further comprises: a first source-drain layer disposed on a side of the semiconductor layer away from the substrate; a second source-drain layer disposed on a side of the first source-drain layer away from the semiconductor layer, the second source-drain layer comprising the first low-potential signal line, the second low-potential signal line, the first high-potential signal line, and the second high-potential signal line.

6. The display panel of claim 2, wherein, The display panel further comprises: a first source-drain layer disposed on a side of the semiconductor layer away from the substrate; A second source-drain layer is disposed on a side of the first source-drain layer away from the semiconductor layer, and includes a first portion of the first low potential signal line, a first portion of the second low potential signal line, a first portion of the first high potential signal line, and a first portion of the second high potential signal line. A third source-drain layer is disposed on a side of the second source-drain layer away from the first source-drain layer, and includes a second portion of the first low potential signal line, a second portion of the second low potential signal line, a second portion of the first high potential signal line, and a second portion of the second high potential signal line. The second portion of the first low potential signal line, the second portion of the second low potential signal line, the second portion of the first high potential signal line, and the second portion of the second high potential signal line are connected to the first portion of the first low potential signal line, the first portion of the second low potential signal line, the first portion of the first high potential signal line, and the first portion of the second high potential signal line, respectively. The projection of the active pattern of the first output transistor on the substrate is located within the projection of the first portion of the first low potential signal line on the substrate, the projection of the first portion of the second low potential signal line on the substrate, the projection of the first portion of the first high potential signal line on the substrate, the projection of the first portion of the second high potential signal line on the substrate, the projection of the second portion of the first low potential signal line on the substrate, the projection of the second portion of the second low potential signal line on the substrate, the projection of the second portion of the first high potential signal line on the substrate, and the projection of the second portion of the second high potential signal line on the substrate.

7. The display panel of claim 6, wherein, The width of the first portion of the second low potential signal line is greater than the width of the first portion of the first low potential signal line, and the width of the second portion of the second low potential signal line is less than the width of the second portion of the first low potential signal line. The width of the first portion of the second high potential signal line is greater than the width of the first portion of the first high potential signal line, and the width of the second portion of the second high potential signal line is less than the width of the second portion of the first high potential signal line. The projection of the active pattern of the first output transistor on the substrate is located within the projection of the second portion of the first low potential signal line on the substrate, the projection of the first portion of the second low potential signal line on the substrate, the projection of the second portion of the first high potential signal line on the substrate, and the projection of the first portion of the second high potential signal line on the substrate.

8. The display panel of claim 7, wherein, The active pattern of the first output transistor includes a plurality of active portions. The number of the active portions located within the projection of the second portion of the first low potential signal line on the substrate and the projection of the first portion of the second low potential signal line on the substrate is less than the number of the active portions located within the projection of the second portion of the first high potential signal line on the substrate and the projection of the first portion of the second high potential signal line on the substrate.

9. The display panel of claim 7, wherein, A projection of the first portion of the second low potential signal line on the substrate overlaps with a projection of the second portion of the first low potential signal line on the substrate. A projection of the first portion of the second high potential signal line on the substrate overlaps with a projection of the second portion of the first high potential signal line on the substrate. The projection of the first portion of the second low potential signal line on the substrate is spaced apart from the projection of the second portion of the first high potential signal line on the substrate.

10. The display panel of any of claims 1 to 9, wherein, The display panel comprises: A plurality of rows of pixels, the pixels comprising light emitting devices and pixel driving circuits, the pixel driving circuits comprising compensation transistors and first initialization transistors; The gate driving circuit is arranged on at least one side of the pixels along a first direction, each stage of the gate driving circuit comprising a first type of gate circuit and a second type of gate circuit, the first type of gate circuit and the second type of gate circuit each comprising a first output unit, a first signal output end of the first type of gate circuit being connected to gates of the compensation transistors of adjacent two rows of the pixel driving circuits, a first signal output end of the second type of gate circuit being connected to first initialization transistors of adjacent two rows of the pixel driving circuits; In at least one of the first type of gate circuit and the second type of gate circuit, a projection of an active pattern of the first output transistor on the substrate is located within a projection range of the first type of low potential signal line on the substrate and a projection range of the first type of high potential signal line on the substrate.

11. The display panel of claim 10, wherein, The first type of gate circuit and the second type of gate circuit each comprise: A first control unit electrically connected to a first node and configured to control a signal of the first node according to a corresponding start signal and a clock signal; A second control unit electrically connected to the first node and configured to control a signal of an internal node of the gate driving circuit of the stage according to a signal of the first node; A second output unit electrically connected to a second type of high potential signal line, an internal node of the gate driving circuit of the stage, a third node, a first type of clock signal line, and a second signal output end, and configured to control a signal of the second signal output end according to a signal of the third node, a signal of the internal node of the gate driving circuit of the stage, and an output signal of the first type of clock signal line; A frequency division unit comprising a first frequency division unit and a second frequency division unit, the first frequency division unit being electrically connected to the first node, a fourth node, and the internal node of the gate driving circuit of the stage, and configured to control signal transmission between the first node and the fourth node according to a signal of the internal node of the gate driving circuit of the stage and a corresponding frequency division control signal; the second frequency division unit being electrically connected to the first node, a fifth node, and the internal node of the gate driving circuit of the stage, and configured to control signal transmission between the first node and the fifth node according to a signal of the internal node of the gate driving circuit of the stage and a corresponding frequency division control signal; The output control unit is electrically connected with the second clock signal line, the first node and an internal node of the gate drive circuit, and is configured to control the signal of the first node according to the signal of the internal node of the gate drive circuit and the signal of the second clock signal line; The reset unit is electrically connected with the control signal line and the first node, and is configured to control the signal of the first node according to the signal of the control signal line; The third control unit is electrically connected with the internal node of the gate drive circuit and the fourth node, and is configured to control the signal of the fourth node according to the signal of the internal node of the gate drive circuit; The fourth control unit is electrically connected with the internal node of the gate drive circuit and the fifth node, and is configured to control the signal of the fifth node according to the signal of the internal node of the gate drive circuit; The switch unit is electrically connected with the third node, the fifth node and a switch signal line, and is configured to control the signal transmission between the third node and the fifth node according to the signal of the switch signal line; The first output unit is electrically connected with the first node and the fourth node.

12. The display panel of claim 11, wherein, The gate of the first output transistor is electrically connected with the first node, and the gate of the second output transistor is electrically connected with the fourth node; The second output unit includes a third output transistor and a fourth output transistor, the gate of the third output transistor is electrically connected with the third node, the first electrode of the third output transistor is electrically connected with the first clock signal line, the second electrode of the third output transistor is electrically connected with the second electrode of the fourth output transistor, the second electrode of the third output transistor is electrically connected with the second signal output end, the gate of the fourth output transistor is electrically connected with the internal node of the gate drive circuit, and the first electrode of the fourth output transistor is electrically connected with the second high potential signal line. The display panel further includes an active layer, the active layer is arranged between the substrate and the semiconductor layer, the material of the active layer includes silicon semiconductor; the material of the semiconductor layer includes oxide semiconductor, and the active layer includes active patterns of the second output transistor, the third output transistor and the fourth output transistor.

13. A display device comprising: The display panel includes any one of the display panels according to claims 1 to 12.

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